From 73d328d80b3824dc9d1f917f73b2641c2c696020 Mon Sep 17 00:00:00 2001 From: Rishabh Joshi Date: Fri, 14 Oct 2016 19:10:07 +0530 Subject: [PATCH] Alternate implementation of register file --- Lab5/Lab51.v | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Lab5/Lab51.v b/Lab5/Lab51.v index 801e19f..cc5f362 100644 --- a/Lab5/Lab51.v +++ b/Lab5/Lab51.v @@ -174,4 +174,31 @@ module RegFile32(clk,reset,ReadReg1,ReadReg2,WriteData,WriteReg,RegWrite,ReadDat mux32_1 mux1(ReadData1,reg_pack,ReadReg1); mux32_1 mux2(ReadData2,reg_pack,ReadReg2); endmodule -// End of Exercise \ No newline at end of file +// End of Exercise + +// Alternate implementation of Register file +module RegFile(clk, reset, ReadReg1, ReadReg2, WriteData, WriteReg, RegWrite, ReadData1, ReadData2); + input clk, reset; + input [1:0] ReadReg1, ReadReg2; + input [31:0] WriteData; + input [1:0] WriteReg; + input RegWrite; + output [31:0] ReadData1, ReadData2; + + wire [31:0] q[0:3]; + wire [3:0] registertowrite; + wire [3:0] clkwrite; + + mux4_1 m1 (ReadData1, q[0], q[1], q[2], q[3], ReadReg1); + mux4_1 m2 (ReadData2, q[0], q[1], q[2], q[3], ReadReg2); + + decoder2_4 d1(registertowrite, WriteReg); + + genvar j; + generate for (j=0; j<4; j=j+1) begin :write_loop + assign clkwrite[j] = clk & RegWrite & registertowrite[j]; + reg_32bit r1(q[j], WriteData, clkwrite[j], reset); + end + endgenerate +endmodule +// End of alternate implementation