From 336fa8e5606d55c16e75e43e9c6b5e5c405a720d Mon Sep 17 00:00:00 2001
From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com>
Date: Thu, 30 Oct 2025 03:13:21 +0000
Subject: [PATCH 1/2] Initial plan


From a16311d8d3cfc0e0841b0e392be87226a0988305 Mon Sep 17 00:00:00 2001
From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com>
Date: Thu, 30 Oct 2025 03:20:10 +0000
Subject: [PATCH 2/2] Add optical AND and OR gate implementations with
 testbench

Co-authored-by: ewdlop <25368970+ewdlop@users.noreply.github.com>
---
 .../Basic Gates/optical_and_gate.v            | 27 +++++++++
 .../Basic Gates/optical_or_gate.v             | 27 +++++++++
 Test/optical_gates_testbench.v                | 55 +++++++++++++++++++
 3 files changed, 109 insertions(+)
 create mode 100644 3.Circuits/Combinational Logic/Basic Gates/optical_and_gate.v
 create mode 100644 3.Circuits/Combinational Logic/Basic Gates/optical_or_gate.v
 create mode 100644 Test/optical_gates_testbench.v

diff --git a/3.Circuits/Combinational Logic/Basic Gates/optical_and_gate.v b/3.Circuits/Combinational Logic/Basic Gates/optical_and_gate.v
new file mode 100644
index 0000000..9e6cafb
--- /dev/null
+++ b/3.Circuits/Combinational Logic/Basic Gates/optical_and_gate.v	
@@ -0,0 +1,27 @@
+// Optical AND Gate Implementation
+// 
+// This module simulates an optical AND gate using Verilog.
+// In optical computing, an AND gate can be implemented using:
+// - Nonlinear optical materials (e.g., MoS2, GaAs)
+// - Two input laser beams with binary encoding (0=no light, 1=light present)
+// - The output is light only when both inputs have light (logical AND)
+//
+// Physical Implementation:
+// - Input A and B are represented as optical signals (light intensity)
+// - The gate uses nonlinear optical effects where two beams interact
+// - Output light is produced only when both inputs are present
+// - This can be achieved through four-wave mixing or cross-phase modulation
+
+module optical_and_gate (
+    input wire A,  // Optical Input A (0=no light, 1=light)
+    input wire B,  // Optical Input B (0=no light, 1=light)
+    output wire Y  // Optical Output Y (0=no light, 1=light)
+);
+
+    // Logical AND operation: Y = A AND B
+    // In optical implementation:
+    // - Both beams must be present to generate output
+    // - Uses nonlinear optical interaction
+    assign Y = A & B;
+
+endmodule
diff --git a/3.Circuits/Combinational Logic/Basic Gates/optical_or_gate.v b/3.Circuits/Combinational Logic/Basic Gates/optical_or_gate.v
new file mode 100644
index 0000000..5b9c2b0
--- /dev/null
+++ b/3.Circuits/Combinational Logic/Basic Gates/optical_or_gate.v	
@@ -0,0 +1,27 @@
+// Optical OR Gate Implementation
+//
+// This module simulates an optical OR gate using Verilog.
+// In optical computing, an OR gate can be implemented using:
+// - Beam combiners or optical couplers
+// - Two input laser beams with binary encoding (0=no light, 1=light present)
+// - The output has light when either or both inputs have light (logical OR)
+//
+// Physical Implementation:
+// - Input A and B are represented as optical signals (light intensity)
+// - The gate uses passive optical coupling or beam splitting
+// - Output light is produced when at least one input is present
+// - Can be implemented with Y-branch waveguides or directional couplers
+
+module optical_or_gate (
+    input wire A,  // Optical Input A (0=no light, 1=light)
+    input wire B,  // Optical Input B (0=no light, 1=light)
+    output wire Y  // Optical Output Y (0=no light, 1=light)
+);
+
+    // Logical OR operation: Y = A OR B
+    // In optical implementation:
+    // - Either beam present generates output
+    // - Uses beam combiner or optical coupler
+    assign Y = A | B;
+
+endmodule
diff --git a/Test/optical_gates_testbench.v b/Test/optical_gates_testbench.v
new file mode 100644
index 0000000..7fe0d2f
--- /dev/null
+++ b/Test/optical_gates_testbench.v
@@ -0,0 +1,55 @@
+// Testbench for Optical Logic Gates
+//
+// This testbench verifies the functionality of optical AND and OR gates
+
+`timescale 1ns / 1ps
+
+module optical_gates_testbench;
+
+    // Inputs
+    reg A;
+    reg B;
+
+    // Outputs
+    wire Y_and;
+    wire Y_or;
+
+    // Instantiate the optical AND gate
+    optical_and_gate uut_and (
+        .A(A),
+        .B(B),
+        .Y(Y_and)
+    );
+
+    // Instantiate the optical OR gate
+    optical_or_gate uut_or (
+        .A(A),
+        .B(B),
+        .Y(Y_or)
+    );
+
+    initial begin
+        // Display header
+        $display("=========================================");
+        $display("Optical Logic Gates Test");
+        $display("=========================================");
+        $display("Time\tA\tB\t|\tAND\tOR");
+        $display("-----------------------------------------");
+
+        // Monitor signals
+        $monitor("%0t\t%b\t%b\t|\t%b\t%b", $time, A, B, Y_and, Y_or);
+
+        // Test all input combinations
+        A = 0; B = 0; #10;  // Both off
+        A = 0; B = 1; #10;  // Only B on
+        A = 1; B = 0; #10;  // Only A on
+        A = 1; B = 1; #10;  // Both on
+
+        $display("=========================================");
+        $display("Test completed successfully!");
+        $display("=========================================");
+        
+        $finish;
+    end
+
+endmodule