diff --git a/.codecheckignore b/.codecheckignore index c75a49e7bea..68ae6f66880 100644 --- a/.codecheckignore +++ b/.codecheckignore @@ -7,6 +7,7 @@ ^connectivity/drivers/emac ^connectivity/drivers/mbedtls ^connectivity/drivers/wifi/COMPONENT_WHD +^connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi ^connectivity/mbedtls ^features/frameworks ^connectivity/lwipstack/lwip diff --git a/.mergify.yml b/.mergify.yml index 0062487842b..0ba49f9437f 100644 --- a/.mergify.yml +++ b/.mergify.yml @@ -47,32 +47,36 @@ pull_request_rules: - check-failure=cmake-checks - check-failure=frozen-tools-check - "label!=mergify skip" + - "label!='needs: work'" actions: label: add: ['needs: work'] remove: ['needs: review', 'needs: CI'] - # From needs: review to needs: work - CI failure + # From needs: CI to needs: work - CI failure in jenkins pipeline - name: "label needs: work when Jenkins CI failed - pr head" conditions: - # Jenkins CI failing + # Jenkins CI failing, only pr head - check-failure~=continuous-integration/jenkins/pr-head - "label!=mergify skip" + - "label=needs: CI" + - -closed actions: label: add: ['needs: work'] - remove: ['needs: review','needs: CI'] + remove: ['needs: CI'] - # From needs: review to needs: work - CI failure + # From needs: CI to needs: work - CI failure - name: "label needs: work when Jenkins CI failed - any of the pipeline" conditions: # Jenkins CI failing - any of the pipeline - check-failure~=^jenkins-ci + - "label=needs: CI" - "label!=mergify skip" actions: label: add: ['needs: work'] - remove: ['needs: review', 'needs: CI'] + remove: ['needs: CI'] # From needs: review or needs: work to needs: CI. One approval means we should be good to start CI - name: "label needs: CI when at least one reviewers approval" diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 00000000000..2a1be7d6bc9 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,73 @@ +# Copyright (c) 2013-2019 Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the License); you may +# not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an AS IS BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +language: sh +os: linux +dist: focal + + +env: + global: + - deps_url="https://mbed-os-ci-public.s3-eu-west-1.amazonaws.com/jenkins-ci/deps" + - deps_dir="${HOME}/.cache/deps" + +cache: + pip: true + ccache: true + directories: + - ${HOME}/.cache/deps + +before_install: + - source tools/test/travis-ci/functions.sh + +addons: + apt: + sources: + - sourceline: 'deb https://apt.kitware.com/ubuntu/ focal main' + key_url: 'https://apt.kitware.com/keys/kitware-archive-latest.asc' + packages: + - cmake + - ninja-build + - gcovr + - libncursesw5 + - g++-7 + +matrix: + include: + + ### Mbed OS unittest ### + - &cmake-build-run-unittest + stage: "CMake" + name: "CMake unittest build" + env: NAME=cmake_unittest + install: + # Hide Travis-preinstalled CMake + # The Travis-preinstalled CMake is unfortunately not installed via apt, so we + # can't replace it with an apt-supplied version very easily. Additionally, we + # can't permit the Travis-preinstalled copy to survive, as the Travis default + # path lists the Travis CMake install location ahead of any place where apt + # would install CMake to. Instead of apt removing or upgrading to a new CMake + # version, we must instead delete the Travis copy of CMake. + - sudo rm -rf /usr/local/cmake* + script: + - echo ctest --build-and-test . build --build-generator Ninja --build-options -DBUILD_TESTING=ON -DCMAKE_BUILD_TYPE=Debug -DCOVERAGE=ON -DCMAKE_CXX_COMPILER=g++-7 -DCMAKE_C_COMPILER=gcc-7 --test-command ctest + - ctest --build-and-test . build --build-generator Ninja --build-options -DBUILD_TESTING=ON -DCMAKE_BUILD_TYPE=Debug -DCOVERAGE=ON -DCMAKE_CXX_COMPILER=g++-7 -DCMAKE_C_COMPILER=gcc-7 --test-command ctest + - gcovr --gcov-executable gcov-7 -r . ./build -s -x coverage.xml -e ".*\.h" --exclude-directories=$TRAVIS_BUILD_DIR/build/UNITTESTS --exclude-directories=$TRAVIS_BUILD_DIR/build/_deps + - ccache -s + - curl -Os https://uploader.codecov.io/latest/linux/codecov + - chmod +x codecov + - ./codecov -F unittests -f "coverage.xml" -t 57166f89-22b3-4949-9488-ddd3c78123fb + diff --git a/CMakeLists.txt b/CMakeLists.txt index 9536ccf0f32..b3fab59fc05 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -195,7 +195,9 @@ endif() if ("${CMAKE_GENERATOR}" MATCHES "Ninja") # known issue ARMClang and Ninja with response files for windows # https://gitlab.kitware.com/cmake/cmake/-/issues/21093 - if((CMAKE_HOST_SYSTEM_NAME MATCHES "Windows" AND NOT CMAKE_CXX_COMPILER_ID MATCHES "ARMClang")) + # This gets fixed in newer cmake version + # https://gitlab.kitware.com/cmake/cmake/-/merge_requests/6484 + if((CMAKE_HOST_SYSTEM_NAME MATCHES "Windows") AND ((${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.22.0") OR (NOT CMAKE_CXX_COMPILER_ID MATCHES "ARMClang"))) set(CMAKE_NINJA_FORCE_RESPONSE_FILE 1 CACHE INTERNAL "") endif() endif() diff --git a/UNITTESTS/CMakeLists.txt b/UNITTESTS/CMakeLists.txt index c194021a979..ce70ec40359 100644 --- a/UNITTESTS/CMakeLists.txt +++ b/UNITTESTS/CMakeLists.txt @@ -17,7 +17,7 @@ include(FetchContent) # Download and unpack googletest FetchContent_Declare(googletest GIT_REPOSITORY https://github.com/google/googletest.git - GIT_TAG master + GIT_TAG main ) FetchContent_MakeAvailable(googletest) diff --git a/codecov.yml b/codecov.yml new file mode 100644 index 00000000000..06cdb1b4980 --- /dev/null +++ b/codecov.yml @@ -0,0 +1,38 @@ +codecov: + require_ci_to_pass: yes + +coverage: + precision: 2 + round: down + range: "0...100" + status: + project: + default: + # basic + target: auto + threshold: 2% + base: auto + # advanced + branches: + - master + if_not_found: success + if_ci_failed: error + informational: true + only_pulls: false + +parsers: + gcov: + branch_detection: + conditional: yes + loop: yes + method: no + macro: no + +comment: + layout: "reach,diff,flags,files,footer" + behavior: default + require_changes: no + +ignore: + - "**/tests/**" + - "**/test/**" diff --git a/connectivity/CMakeLists.txt b/connectivity/CMakeLists.txt index dcf9b48c36d..1a3bfd41c47 100644 --- a/connectivity/CMakeLists.txt +++ b/connectivity/CMakeLists.txt @@ -24,7 +24,17 @@ add_library(mbed-nfc INTERFACE) add_library(mbed-ppp INTERFACE) add_library(mbed-wifi INTERFACE) -if(${CMAKE_CROSSCOMPILING}) +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + # Add these subdirectories for tests + add_subdirectory(cellular) + add_subdirectory(drivers) + add_subdirectory(FEATURE_BLE) + add_subdirectory(libraries) + add_subdirectory(lorawan) + add_subdirectory(mbedtls) + add_subdirectory(netsocket) + add_subdirectory(nfc) +else() # The directories below contain optional target libraries add_subdirectory(FEATURE_BLE EXCLUDE_FROM_ALL) add_subdirectory(cellular EXCLUDE_FROM_ALL) @@ -36,12 +46,4 @@ if(${CMAKE_CROSSCOMPILING}) add_subdirectory(nanostack EXCLUDE_FROM_ALL) add_subdirectory(netsocket EXCLUDE_FROM_ALL) add_subdirectory(nfc EXCLUDE_FROM_ALL) -else() - # Add these subdirectories for the Unit test - add_subdirectory(cellular) - add_subdirectory(lorawan) - add_subdirectory(netsocket) - add_subdirectory(mbedtls) - add_subdirectory(libraries) - add_subdirectory(FEATURE_BLE) endif() diff --git a/connectivity/FEATURE_BLE/CMakeLists.txt b/connectivity/FEATURE_BLE/CMakeLists.txt index 1e9da9185a7..fbd35db9afc 100644 --- a/connectivity/FEATURE_BLE/CMakeLists.txt +++ b/connectivity/FEATURE_BLE/CMakeLists.txt @@ -2,7 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) - add_subdirectory(tests/UNITTESTS) + if(NOT BUILD_GREENTEA_TESTS) + add_subdirectory(tests/UNITTESTS) + endif() endif() add_subdirectory(libraries) diff --git a/connectivity/cellular/include/cellular/framework/AT/AT_CellularStack.h b/connectivity/cellular/include/cellular/framework/AT/AT_CellularStack.h index 8fbb9e5100d..11308f87cda 100644 --- a/connectivity/cellular/include/cellular/framework/AT/AT_CellularStack.h +++ b/connectivity/cellular/include/cellular/framework/AT/AT_CellularStack.h @@ -88,21 +88,6 @@ class AT_CellularStack : public NetworkStack { virtual void socket_attach(nsapi_socket_t handle, void (*callback)(void *), void *data); - - nsapi_size_or_error_t socket_sendto_control(nsapi_socket_t handle, const SocketAddress &address, - const void *data, nsapi_size_t size, - nsapi_msghdr_t *control, nsapi_size_t control_size) override - { - return NSAPI_ERROR_UNSUPPORTED; - } - - nsapi_size_or_error_t socket_recvfrom_control(nsapi_socket_t handle, SocketAddress *address, - void *data, nsapi_size_t size, - nsapi_msghdr_t *control, nsapi_size_t control_size) override - { - return NSAPI_ERROR_UNSUPPORTED; - } - protected: class CellularSocket { public: diff --git a/connectivity/drivers/802.15.4_RF/atmel-rf-driver/CMakeLists.txt b/connectivity/drivers/802.15.4_RF/atmel-rf-driver/CMakeLists.txt index b716ca710c4..8184174715c 100644 --- a/connectivity/drivers/802.15.4_RF/atmel-rf-driver/CMakeLists.txt +++ b/connectivity/drivers/802.15.4_RF/atmel-rf-driver/CMakeLists.txt @@ -1,5 +1,20 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 +################################################################################# +## Copyright 2020-2021 Pelion. +## +## SPDX-License-Identifier: Apache-2.0 +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +################################################################################# target_include_directories(mbed-802.15.4-rf INTERFACE diff --git a/connectivity/drivers/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp b/connectivity/drivers/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp index 5aea0a7c229..42387c57f79 100644 --- a/connectivity/drivers/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp +++ b/connectivity/drivers/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp @@ -703,7 +703,8 @@ static void rf_handle_rx_done(void) rf_state = RF_IDLE; } if (rf_read_bbc_register(BBC_PC, rf_module) & FCSOK) { - if (!rf_read_rx_buffer(cur_rx_packet_len, rf_module)) { + uint16_t rx_packet_len = rf_read_rx_frame_length(rf_module); + if (!rf_read_rx_buffer(rx_packet_len, rf_module)) { uint8_t version = ((rx_buffer[1] & VERSION_FIELD_MASK) >> SHIFT_VERSION_FIELD); if (((rx_buffer[0] & MAC_FRAME_TYPE_MASK) == MAC_TYPE_ACK) && (version < MAC_FRAME_VERSION_2)) { rf_handle_ack(rx_buffer[2], rx_buffer[0] & MAC_DATA_PENDING); @@ -711,11 +712,11 @@ static void rf_handle_rx_done(void) int8_t rssi = (int8_t) rf_read_rf_register(RF_EDV, rf_module); // Cut CRC bytes if (mac_mode == IEEE_802_15_4_2011) { - cur_rx_packet_len -= 2; + rx_packet_len -= 2; } else { - cur_rx_packet_len -= 4; + rx_packet_len -= 4; } - device_driver.phy_rx_cb(rx_buffer, cur_rx_packet_len, 0xf0, rssi, rf_radio_driver_id); + device_driver.phy_rx_cb(rx_buffer, rx_packet_len, 0xf0, rssi, rf_radio_driver_id); // If auto ack used, must wait until RF returns to RF_TXPREP state if ((version != MAC_FRAME_VERSION_2) && (rx_buffer[0] & FC_AR)) { wait_us(100); diff --git a/connectivity/drivers/802.15.4_RF/mcr20a-rf-driver/CMakeLists.txt b/connectivity/drivers/802.15.4_RF/mcr20a-rf-driver/CMakeLists.txt index a29383253d0..420ec7d13c5 100644 --- a/connectivity/drivers/802.15.4_RF/mcr20a-rf-driver/CMakeLists.txt +++ b/connectivity/drivers/802.15.4_RF/mcr20a-rf-driver/CMakeLists.txt @@ -1,5 +1,20 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 +################################################################################# +## Copyright 2020-2021 Pelion. +## +## SPDX-License-Identifier: Apache-2.0 +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +################################################################################# target_include_directories(mbed-802.15.4-rf INTERFACE diff --git a/connectivity/drivers/802.15.4_RF/stm-s2lp-rf-driver/CMakeLists.txt b/connectivity/drivers/802.15.4_RF/stm-s2lp-rf-driver/CMakeLists.txt index d64ffa0134f..02bd7856c46 100644 --- a/connectivity/drivers/802.15.4_RF/stm-s2lp-rf-driver/CMakeLists.txt +++ b/connectivity/drivers/802.15.4_RF/stm-s2lp-rf-driver/CMakeLists.txt @@ -1,5 +1,20 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 +################################################################################# +## Copyright 2020-2021 Pelion. +## +## SPDX-License-Identifier: Apache-2.0 +## +## Licensed under the Apache License, Version 2.0 (the "License"); +## you may not use this file except in compliance with the License. +## You may obtain a copy of the License at +## +## http://www.apache.org/licenses/LICENSE-2.0 +## +## Unless required by applicable law or agreed to in writing, software +## distributed under the License is distributed on an "AS IS" BASIS, +## WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +## See the License for the specific language governing permissions and +## limitations under the License. +################################################################################# target_include_directories(mbed-802.15.4-rf INTERFACE diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp index 03339e74024..14e0ba20ce7 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp @@ -514,7 +514,7 @@ class TransportDriver : public CordioHCITransportDriver { } break; case INFO_STACK_TYPE_BLE_HCI: - if (MBED_ROM_SIZE > 0xE0000) { + if (MBED_ROM_SIZE > (((p_wireless_info->VersionMajor > 1) || (p_wireless_info->VersionMinor >= 12)) ? 0xE1000 : 0xE0000)) { error("Wrong MBED_ROM_SIZE with HCI FW\n"); } break; diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/stm32f7_eth_conf.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/stm32f7_eth_conf.c index 98655d74b83..ade0404c4c5 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/stm32f7_eth_conf.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32F7/stm32f7_eth_conf.c @@ -17,6 +17,8 @@ #include "stm32f7xx_hal.h" +#if defined ETH + void _eth_config_mac(ETH_HandleTypeDef *heth) { ETH_MACInitTypeDef macconf = { @@ -59,3 +61,5 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) (void) HAL_ETH_ConfigMAC(heth, &macconf); } + +#endif // defined ETH diff --git a/connectivity/drivers/lora/COMPONENT_SX126X/mbed_lib.json b/connectivity/drivers/lora/COMPONENT_SX126X/mbed_lib.json index 2cce26389e9..6fcdf16f05b 100644 --- a/connectivity/drivers/lora/COMPONENT_SX126X/mbed_lib.json +++ b/connectivity/drivers/lora/COMPONENT_SX126X/mbed_lib.json @@ -1,5 +1,6 @@ { "name": "SX126X-lora-driver", + "requires": ["lora"], "config": { "spi-frequency": { "help": "SPI frequency, Default: 16 MHz", diff --git a/connectivity/drivers/lora/COMPONENT_SX1272/mbed_lib.json b/connectivity/drivers/lora/COMPONENT_SX1272/mbed_lib.json index 7182de340aa..824c71ee964 100644 --- a/connectivity/drivers/lora/COMPONENT_SX1272/mbed_lib.json +++ b/connectivity/drivers/lora/COMPONENT_SX1272/mbed_lib.json @@ -1,5 +1,6 @@ { "name": "sx1272-lora-driver", + "requires": ["lora"], "config": { "spi-frequency": { "help": "SPI frequency, Default: 8 MHz", diff --git a/connectivity/drivers/lora/COMPONENT_SX1276/SX1276_LoRaRadio.cpp b/connectivity/drivers/lora/COMPONENT_SX1276/SX1276_LoRaRadio.cpp index fed23c721d7..af7600af8b0 100644 --- a/connectivity/drivers/lora/COMPONENT_SX1276/SX1276_LoRaRadio.cpp +++ b/connectivity/drivers/lora/COMPONENT_SX1276/SX1276_LoRaRadio.cpp @@ -35,7 +35,8 @@ SPDX-License-Identifier: BSD-3-Clause #include "sx1276Regs-LoRa.h" #include //rint - +#include +using namespace std::chrono_literals; using namespace rtos; using namespace mbed; @@ -210,6 +211,8 @@ SX1276_LoRaRadio::SX1276_LoRaRadio(PinName spi_mosi, if (tcxo != NC) { _tcxo = 1; + // TCXO startup time + ThisThread::sleep_for(5ms); } #ifdef MBED_CONF_RTOS_PRESENT @@ -288,9 +291,9 @@ void SX1276_LoRaRadio::radio_reset() { _reset_ctl.output(); _reset_ctl = 0; - ThisThread::sleep_for(2); + ThisThread::sleep_for(2ms); _reset_ctl.input(); - ThisThread::sleep_for(6); + ThisThread::sleep_for(6ms); } /** @@ -357,7 +360,7 @@ uint32_t SX1276_LoRaRadio::random(void) set_operation_mode(RF_OPMODE_RECEIVER); for (i = 0; i < 32; i++) { - ThisThread::sleep_for(1); + ThisThread::sleep_for(1ms); // Unfiltered RSSI value reading. Only takes the LSB value rnd |= ((uint32_t) read_register(REG_LR_RSSIWIDEBAND) & 0x01) << i; } @@ -805,7 +808,7 @@ void SX1276_LoRaRadio::send(uint8_t *buffer, uint8_t size) // FIFO operations can not take place in Sleep mode if ((read_register(REG_OPMODE) & ~RF_OPMODE_MASK) == RF_OPMODE_SLEEP) { standby(); - ThisThread::sleep_for(1); + ThisThread::sleep_for(1ms); } // write_to_register payload buffer write_fifo(buffer, size); @@ -1025,7 +1028,7 @@ bool SX1276_LoRaRadio::perform_carrier_sense(radio_modems_t modem, set_operation_mode(RF_OPMODE_RECEIVER); // hold on a bit, radio turn-around time - ThisThread::sleep_for(1); + ThisThread::sleep_for(1ms); Timer elapsed_time; elapsed_time.start(); @@ -1263,13 +1266,27 @@ void SX1276_LoRaRadio::read_fifo(uint8_t *buffer, uint8_t size) void SX1276_LoRaRadio::set_operation_mode(uint8_t mode) { if (mode == RF_OPMODE_SLEEP) { + write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode); set_low_power_mode(); + /* FIXME taken from set_modem, it reduces the power consumption + *from 300µA to 1.5µA */ + write_to_register(REG_DIOMAPPING1, 0x00); // sets DIO0-DI03 in default mode + write_to_register(REG_DIOMAPPING2, 0x30); // bits 4-5 are turned on i.e., + if (_rf_ctrls.tcxo != NC) { + ThisThread::sleep_for(1ms); + _tcxo = 0; + } } else { + if (_rf_ctrls.tcxo != NC) { + _tcxo = 1; + // TCXO startup time + ThisThread::sleep_for(5ms); + } set_low_power_mode(); + write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode); set_antenna_switch(mode); } - write_to_register(REG_OPMODE, (read_register(REG_OPMODE) & RF_OPMODE_MASK) | mode); } /** @@ -1327,14 +1344,14 @@ void SX1276_LoRaRadio::set_sx1276_variant_type() { if (_rf_ctrls.ant_switch != NC) { _ant_switch.input(); - ThisThread::sleep_for(1); + ThisThread::sleep_for(1ms); if (_ant_switch == 1) { radio_variant = SX1276MB1LAS; } else { radio_variant = SX1276MB1MAS; } _ant_switch.output(); - ThisThread::sleep_for(1); + ThisThread::sleep_for(1ms); } else { radio_variant = MBED_CONF_SX1276_LORA_DRIVER_RADIO_VARIANT; } @@ -2274,4 +2291,4 @@ void SX1276_LoRaRadio::handle_timeout_irq() #endif // DEVICE_SPI -// EOF +// EOF \ No newline at end of file diff --git a/connectivity/drivers/lora/COMPONENT_SX1276/mbed_lib.json b/connectivity/drivers/lora/COMPONENT_SX1276/mbed_lib.json index 0033945bece..82bbf8a02df 100644 --- a/connectivity/drivers/lora/COMPONENT_SX1276/mbed_lib.json +++ b/connectivity/drivers/lora/COMPONENT_SX1276/mbed_lib.json @@ -1,5 +1,6 @@ { "name": "sx1276-lora-driver", + "requires": ["lora"], "config": { "spi-frequency": { "help": "SPI frequency, Default: 8 MHz", diff --git a/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt b/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt index 35280ef154a..e8b564563f0 100644 --- a/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt +++ b/connectivity/drivers/lora/TARGET_STM32WL/CMakeLists.txt @@ -9,4 +9,5 @@ target_include_directories(mbed-lorawan target_sources(mbed-lorawan INTERFACE STM32WL_LoRaRadio.cpp + STM32WL_radio_driver.cpp ) diff --git a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp index 6a0327e380a..4962db7d70c 100644 --- a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp +++ b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp @@ -39,6 +39,16 @@ SPDX-License-Identifier: BSD-3-Clause #include "Timer.h" #include "STM32WL_LoRaRadio.h" +#ifndef DEBUG_STDIO +#define DEBUG_STDIO 0 +#endif + +#if DEBUG_STDIO +#define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0) +#else +#define DEBUG_PRINTF(...) {} +#endif + uint8_t regulator_mode = MBED_CONF_STM32WL_LORA_DRIVER_REGULATOR_MODE; uint8_t crystal_select = MBED_CONF_STM32WL_LORA_DRIVER_CRYSTAL_SELECT; @@ -136,7 +146,6 @@ STM32WL_LoRaRadio::STM32WL_LoRaRadio() STM32WL_LoRaRadio::~STM32WL_LoRaRadio() { - } /** @@ -270,7 +279,7 @@ void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef *subghzHandle) static void RadioIrqProcess() { radio_irq_masks_t irq_status; - + core_util_critical_section_enter(); irq_status = (radio_irq_masks_t)STM32WL_LoRaRadio::get_irq_status(); /* clear IRQs lines after recovering their status */ @@ -292,8 +301,10 @@ static void RadioIrqProcess() if ((irq_status & IRQ_RX_TX_TIMEOUT) == IRQ_RX_TX_TIMEOUT) { STM32WL_LoRaRadio::HAL_SUBGHZ_RxTxTimeoutCallback(); } + core_util_critical_section_exit(); } -/* ----- */ + + /* HAL_SUBGHz Callbacks definitions */ void STM32WL_LoRaRadio::HAL_SUBGHZ_TxCpltCallback(void) { @@ -352,7 +363,6 @@ void STM32WL_LoRaRadio::HAL_SUBGHZ_CADStatusCallback(void) } } - void STM32WL_LoRaRadio::HAL_SUBGHZ_RxTxTimeoutCallback(void) { if ((_radio_events->tx_timeout) && (_operating_mode == MODE_TX)) { @@ -373,14 +383,13 @@ void STM32WL_LoRaRadio::HAL_SUBGHZ_RxTxTimeoutCallback(void) } } -/* ----- */ -/* HAL_SUBGHz Callbacks definitions END */ /* STM32WL specific BSP Nucleo board functions */ void STM32WL_LoRaRadio::SUBGRF_SetSwitch(uint8_t paSelect, RFState_t rxtx) { RBI_Switch_TypeDef state = RBI_SWITCH_RX; + DEBUG_PRINTF("STM32WL_LoRaRadio::SUBGRF_SetSwitch %u %u\n", paSelect, rxtx); if (rxtx == RFSWITCH_TX) { if (paSelect == RFO_LP) { @@ -400,6 +409,7 @@ void STM32WL_LoRaRadio::SUBGRF_SetSwitch(uint8_t paSelect, RFState_t rxtx) uint8_t STM32WL_LoRaRadio::SUBGRF_SetRfTxPower(int8_t power) { + DEBUG_PRINTF("STM32WL_LoRaRadio::SUBGRF_SetRfTxPower %u\n", power); uint8_t paSelect = RFO_LP; int32_t TxConfig = board_rf_switch_config; @@ -434,6 +444,7 @@ uint8_t STM32WL_LoRaRadio::SUBGRF_SetRfTxPower(int8_t power) void STM32WL_LoRaRadio::SUBGRF_SetTxParams(uint8_t paSelect, int8_t power, radio_ramp_time_t rampTime) { uint8_t buf[2]; + DEBUG_PRINTF("STM32WL_LoRaRadio::SUBGRF_SetTxParams %u %u\n", paSelect, power); if (paSelect == RFO_LP) { if (power == 15) { @@ -496,6 +507,7 @@ void STM32WL_LoRaRadio::Radio_SMPS_Set(uint8_t level) void STM32WL_LoRaRadio::calibrate_image(uint32_t freq) { uint8_t cal_freq[2]; + DEBUG_PRINTF("STM32WL_LoRaRadio::calibrate_image %u\n", freq); if (freq > 900000000) { cal_freq[0] = 0xE1; @@ -521,6 +533,7 @@ void STM32WL_LoRaRadio::calibrate_image(uint32_t freq) void STM32WL_LoRaRadio::set_channel(uint32_t frequency) { + DEBUG_PRINTF("STM32WL_LoRaRadio::set_channel %u\n", frequency); #if MBED_CONF_STM32WL_LORA_DRIVER_SLEEP_MODE == 1 // At this point, we are not sure what is the Modem type, set both _mod_params.params.lora.operational_frequency = frequency; @@ -571,6 +584,7 @@ void STM32WL_LoRaRadio::standby(void) void STM32WL_LoRaRadio::SUBGRF_SetTcxoMode(radio_TCXO_ctrl_voltage_t voltage, uint32_t timeout) { + DEBUG_PRINTF("STM32WL_LoRaRadio::SUBGRF_SetTcxoMode %u\n", voltage); uint8_t buf[4]; buf[0] = voltage & 0x07; @@ -585,12 +599,16 @@ void STM32WL_LoRaRadio::init_radio(radio_events_t *events) { HAL_StatusTypeDef error_value; uint32_t vector = 0; - + DEBUG_PRINTF("STM32WL_LoRaRadio::init_radio\n"); _radio_events = events; _tx_timeout = 0; _rx_timeout = 0; + hsubghz.Init.BaudratePrescaler = 0; + hsubghz.ErrorCode = 0; + hsubghz.State = HAL_SUBGHZ_STATE_RESET; + //call to HAL_SUBGHZ_Init() for MSPInit and NVIC Radio_IRQ setting error_value = HAL_SUBGHZ_Init(&hsubghz); @@ -602,7 +620,6 @@ void STM32WL_LoRaRadio::init_radio(radio_events_t *events) SUBGRF_SetTxParams(RFO_LP, 0, RADIO_RAMP_200_US); sleep(); - } @@ -634,6 +651,7 @@ void STM32WL_LoRaRadio::cold_start_wakeup() void STM32WL_LoRaRadio::set_public_network(bool enable) { + DEBUG_PRINTF("STM32WL_LoRaRadio::set_public_network %u\n", enable); if (enable) { // Change LoRa modem SyncWord write_to_register(REG_LR_SYNCWORD, (LORA_MAC_PUBLIC_SYNCWORD >> 8) & 0xFF); @@ -680,12 +698,14 @@ uint32_t STM32WL_LoRaRadio::time_on_air(radio_modems_t modem, uint8_t pkt_len) } break; } + DEBUG_PRINTF("STM32WL_LoRaRadio::time_on_air %u %u => %u\n", modem, pkt_len, air_time); return air_time; } void STM32WL_LoRaRadio::radio_reset() { + DEBUG_PRINTF("STM32WL_LoRaRadio::radio_reset\n"); // give some time for automatic image calibration rtos::ThisThread::sleep_for(6ms); @@ -704,10 +724,12 @@ void STM32WL_LoRaRadio::wakeup() cold_start_wakeup(); #endif } + DEBUG_PRINTF("STM32WL_LoRaRadio::wakeup\n"); } void STM32WL_LoRaRadio::sleep(void) { + DEBUG_PRINTF("STM32WL_LoRaRadio::sleep\n"); #if MBED_CONF_STM32WL_LORA_DRIVER_SLEEP_MODE == 1 // cold start, power consumption 160 nA sleep_state = 0x00; @@ -739,25 +761,29 @@ uint32_t STM32WL_LoRaRadio::random(void) read_register(RANDOM_NUMBER_GENERATORBASEADDR, buf, 4); standby(); - return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3]; + uint32_t random_value = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3] ; + DEBUG_PRINTF("STM32WL_LoRaRadio::random %u\n", random_value); + return random_value; } void STM32WL_LoRaRadio::write_opmode_command(uint8_t cmd, uint8_t *buffer, uint16_t size) { HAL_StatusTypeDef error_value; + core_util_critical_section_enter(); error_value = HAL_SUBGHZ_ExecSetCmd(&hsubghz, (SUBGHZ_RadioSetCmd_t)cmd, buffer, size); MBED_ASSERT(error_value == HAL_OK); - + core_util_critical_section_exit(); } void STM32WL_LoRaRadio::read_opmode_command(uint8_t cmd, uint8_t *buffer, uint16_t size) { HAL_StatusTypeDef error_value; + core_util_critical_section_enter(); error_value = HAL_SUBGHZ_ExecGetCmd(&hsubghz, (SUBGHZ_RadioGetCmd_t)cmd, buffer, size); MBED_ASSERT(error_value == HAL_OK); - + core_util_critical_section_exit(); } void STM32WL_LoRaRadio::write_to_register(uint16_t addr, uint8_t data) @@ -813,6 +839,7 @@ void STM32WL_LoRaRadio::write_fifo(uint8_t *buffer, uint8_t size) void STM32WL_LoRaRadio::set_modem(uint8_t modem) { _active_modem = modem; + DEBUG_PRINTF("STM32WL_LoRaRadio::set_modem %u\n", modem); // setting modem type must happen in standby mode if (_operating_mode != MODE_STDBY_RC) { @@ -841,6 +868,10 @@ uint8_t STM32WL_LoRaRadio::get_fsk_bw_reg_val(uint32_t bandwidth) { uint8_t i; + if (bandwidth == 0) { + return 0x1F; + } + for (i = 0; i < (sizeof(fsk_bandwidths) / sizeof(fsk_bw_t)) - 1; i++) { if ((bandwidth >= fsk_bandwidths[i].bandwidth) && (bandwidth < fsk_bandwidths[i + 1].bandwidth)) { @@ -875,6 +906,7 @@ void STM32WL_LoRaRadio::set_tx_config(radio_modems_t modem, bool iq_inverted, uint32_t timeout) { + DEBUG_PRINTF("STM32WL_LoRaRadio::set_tx_config %u %u %u %u\n", modem, power, fdev, bandwidth); uint8_t modem_type = (uint8_t) modem; switch (modem_type) { @@ -966,6 +998,7 @@ void STM32WL_LoRaRadio::set_rx_config(radio_modems_t modem, uint8_t max_payload_len; (void) freq_hop_on; (void) hop_period; + DEBUG_PRINTF("STM32WL_LoRaRadio::set_rx_config %u %u %u %u\n", modem, bandwidth, datarate, coderate); if (rx_continuous) { _reception_mode = RECEPTION_MODE_CONTINUOUS; @@ -1089,6 +1122,7 @@ void STM32WL_LoRaRadio::configure_dio_irq(uint16_t irq_mask, uint16_t dio1_mask, void STM32WL_LoRaRadio::send(uint8_t *buffer, uint8_t size) { + DEBUG_PRINTF("STM32WL_LoRaRadio::send %u\n", size); set_tx_power(_tx_power); configure_dio_irq(IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT, @@ -1127,6 +1161,8 @@ void STM32WL_LoRaRadio::send(uint8_t *buffer, uint8_t size) void STM32WL_LoRaRadio::receive(void) { + DEBUG_PRINTF("STM32WL_LoRaRadio::receive\n"); + if (get_modem() == MODEM_LORA) { if (_reception_mode != RECEPTION_MODE_CONTINUOUS) { // Data-sheet Table 13-11: StopOnPreambParam @@ -1243,6 +1279,7 @@ void STM32WL_LoRaRadio::set_pa_config(uint8_t pa_DC, uint8_t hp_max, uint8_t device_type, uint8_t pa_LUT) { uint8_t buf[4]; + DEBUG_PRINTF("STM32WL_LoRaRadio::set_pa_config %u %u %u %u\n", pa_DC, hp_max, device_type, pa_LUT); buf[0] = pa_DC; buf[1] = hp_max; @@ -1253,6 +1290,7 @@ void STM32WL_LoRaRadio::set_pa_config(uint8_t pa_DC, uint8_t hp_max, void STM32WL_LoRaRadio::set_crc_seed(uint16_t seed) { + DEBUG_PRINTF("STM32WL_LoRaRadio::set_crc_seed\n"); if (_active_modem == MODEM_FSK) { uint8_t buf[2]; buf[0] = (uint8_t)((seed >> 8) & 0xFF); @@ -1263,6 +1301,7 @@ void STM32WL_LoRaRadio::set_crc_seed(uint16_t seed) void STM32WL_LoRaRadio::set_crc_polynomial(uint16_t polynomial) { + DEBUG_PRINTF("STM32WL_LoRaRadio::set_crc_polynomial\n"); if (_active_modem == MODEM_FSK) { uint8_t buf[2]; buf[0] = (uint8_t)((polynomial >> 8) & 0xFF); @@ -1273,6 +1312,7 @@ void STM32WL_LoRaRadio::set_crc_polynomial(uint16_t polynomial) void STM32WL_LoRaRadio::set_whitening_seed(uint16_t seed) { + DEBUG_PRINTF("STM32WL_LoRaRadio::set_whitening_seed\n"); if (_active_modem == MODEM_FSK) { uint8_t reg_value = read_register(REG_LR_WHITSEEDBASEADDR_MSB) & 0xFE; reg_value = ((seed >> 8) & 0x01) | reg_value; @@ -1286,6 +1326,7 @@ void STM32WL_LoRaRadio::set_packet_params(packet_params_t *packet_params) uint8_t n; uint8_t crc_val = 0; uint8_t buf[9] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + DEBUG_PRINTF("STM32WL_LoRaRadio::set_packet_params %u\n", packet_params->modem_type); // Check if required configuration corresponds to the stored packet type // If not, silently update radio packet type @@ -1363,6 +1404,7 @@ void STM32WL_LoRaRadio::set_buffer_base_addr(uint8_t tx_base_addr, uint8_t rx_ba uint8_t STM32WL_LoRaRadio::get_status(void) { + DEBUG_PRINTF("STM32WL_LoRaRadio::get_status\n"); switch (_operating_mode) { case MODE_TX: return RF_TX_RUNNING; @@ -1382,12 +1424,15 @@ int8_t STM32WL_LoRaRadio::get_rssi() read_opmode_command((uint8_t) RADIO_GET_RSSIINST, buf, 1); rssi = -buf[0] >> 1; + + DEBUG_PRINTF("STM32WL_LoRaRadio::get_rssi %d\n", rssi); return rssi; } void STM32WL_LoRaRadio::get_rx_buffer_status(uint8_t *payload_len, uint8_t *start_ptr) { + // DEBUG_PRINTF("STM32WL_LoRaRadio::get_rx_buffer_status\n"); uint8_t status[2]; read_opmode_command((uint8_t) RADIO_GET_RXBUFFERSTATUS, status, 2); @@ -1406,6 +1451,7 @@ void STM32WL_LoRaRadio::get_rx_buffer_status(uint8_t *payload_len, void STM32WL_LoRaRadio::get_packet_status(packet_status_t *pkt_status) { + // DEBUG_PRINTF("STM32WL_LoRaRadio::get_packet_status\n"); uint8_t status[3]; read_opmode_command((uint8_t) RADIO_GET_PACKETSTATUS, status, 3); @@ -1437,6 +1483,7 @@ void STM32WL_LoRaRadio::get_packet_status(packet_status_t *pkt_status) radio_error_t STM32WL_LoRaRadio::get_device_errors(void) { radio_error_t error; + DEBUG_PRINTF("STM32WL_LoRaRadio::get_device_errors\n"); read_opmode_command((uint8_t) RADIO_GET_ERROR, (uint8_t *)&error, 2); return error; @@ -1444,6 +1491,7 @@ radio_error_t STM32WL_LoRaRadio::get_device_errors(void) void STM32WL_LoRaRadio::clear_device_errors(void) { + DEBUG_PRINTF("STM32WL_LoRaRadio::clear_device_errors\n"); uint8_t buf[2] = {0x00, 0x00}; write_opmode_command((uint8_t) RADIO_CLR_ERROR, buf, 2); } diff --git a/connectivity/drivers/lora/TARGET_STM32WL/mbed_lib.json b/connectivity/drivers/lora/TARGET_STM32WL/mbed_lib.json index 3d3def03830..f1ebdd18dbb 100644 --- a/connectivity/drivers/lora/TARGET_STM32WL/mbed_lib.json +++ b/connectivity/drivers/lora/TARGET_STM32WL/mbed_lib.json @@ -1,5 +1,6 @@ { "name": "stm32wl-lora-driver", + "requires": ["lora"], "config": { "buffer-size": { "help": "Max. buffer size the radio can handle, Default: 255 B", diff --git a/connectivity/drivers/wifi/CMakeLists.txt b/connectivity/drivers/wifi/CMakeLists.txt index 6ca3b2f0923..78ecb7fa4ce 100644 --- a/connectivity/drivers/wifi/CMakeLists.txt +++ b/connectivity/drivers/wifi/CMakeLists.txt @@ -3,7 +3,11 @@ add_subdirectory(TARGET_WICED EXCLUDE_FROM_ALL) -add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM EXCLUDE_FROM_ALL) + +if("WHD" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL) +endif() add_subdirectory(esp8266-driver) diff --git a/connectivity/drivers/wifi/TARGET_STM/CMakeLists.txt b/connectivity/drivers/wifi/TARGET_STM/CMakeLists.txt new file mode 100644 index 00000000000..78d80df1a6f --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("EMW3080B" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_EMW3080B EXCLUDE_FROM_ALL) +endif() diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/CMakeLists.txt b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/CMakeLists.txt new file mode 100644 index 00000000000..830fdf088df --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(wifi-EMW3080B INTERFACE) + +target_include_directories(mbed-wifi + INTERFACE + . + mx_wifi + mx_wifi/core +) + +target_sources(mbed-wifi + INTERFACE + EMW3080BInterface.cpp + EMW3080B_EMAC.cpp + EMW3080B_UART.cpp + EMW3080B_SPI.cpp + mx_wifi_mbed_os.cpp + mx_wifi/mx_wifi.c + mx_wifi/core/checksumutils.c + mx_wifi/core/mx_wifi_hci.c + mx_wifi/core/mx_wifi_ipc.c + mx_wifi/core/mx_wifi_slip.c +) diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080BInterface.cpp b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080BInterface.cpp new file mode 100644 index 00000000000..c59407d7ffc --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080BInterface.cpp @@ -0,0 +1,367 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* Includes ------------------------------------------------------------------*/ +/* Private includes ----------------------------------------------------------*/ +#include "EMW3080BInterface.h" +#if MX_WIFI_USE_SPI +#include "EMW3080B_SPI.h" +#else +#include "EMW3080B_UART.h" +#endif + +#define DEBUG_SILENT 0 +#define DEBUG_WARNING 1 +#define DEBUG_INFO 2 +#define DEBUG_LOG 3 +#define DEFAULT_DEBUG DEBUG_SILENT + +static EMW3080BInterface *emw3080b_object; + +#if MX_WIFI_USE_SPI +static EMW3080B_SPI *emw3080b_protocol_context; +#else +static EMW3080B_UART *emw3080b_protocol_context; +#endif + +static bool deepsleep_locked = false; + +EMW3080BInterface::EMW3080BInterface(bool debug, + PinName mosi, + PinName miso, + PinName sclk, + PinName nss, + PinName notify, + PinName flow, + PinName reset, + PinName tx, + PinName rx, + EMAC &emac, + OnboardNetworkStack &stack + ) : EMACInterface(emac, stack), _ssid(""), _isConnected(false) +{ + emw3080b_object = this; +#if MX_WIFI_USE_SPI + emw3080b_protocol_context = new EMW3080B_SPI(debug, mosi, miso, sclk, nss, notify, flow, reset); +#else + emw3080b_protocol_context = new EMW3080B_UART(debug, tx, rx, reset); +#endif + + if (debug) { + _debug_level = DEBUG_LOG; + } else { + _debug_level = DEFAULT_DEBUG; + } + + probe(); +} + + + + +int8_t IO_Init_static(uint16_t mode) +{ + return emw3080b_protocol_context->IO_Init(mode); +} + +int8_t IO_DeInit_static(void) +{ + return emw3080b_protocol_context->IO_DeInit(); +} + +void IO_Delay_static(uint32_t delayms) +{ + return emw3080b_protocol_context->IO_Delay(delayms); +} + +uint16_t IO_Send_static(uint8_t *data, uint16_t len) +{ + return emw3080b_protocol_context->IO_Send(data, len); +} + +uint16_t IO_Receive_static(uint8_t *buffer, uint16_t buff_size) +{ + return emw3080b_protocol_context->IO_Receive(buffer, buff_size); +} + + + +MX_WIFIObject_t *wifi_obj_get(void) +{ + if (emw3080b_object) { + return &emw3080b_object->MxWifiObj; + } else { + error("MxWifiObj is not initialized"); + } +} + +void EMW3080BInterface::probe(void) +{ + + if (MX_WIFI_RegisterBusIO(&MxWifiObj, + IO_Init_static, + IO_DeInit_static, + IO_Delay_static, + IO_Send_static, + IO_Receive_static) != 0) { + debug_if(_debug_level >= DEBUG_LOG, "EMW3080BInterface : MX_WIFI_RegisterBusIO failed \n"); + return; + } + + + if (MX_WIFI_HardResetModule(&MxWifiObj)) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : MX_WIFI_HardResetModule failed \n"); + return ; + } + + /* wait for mxchip wifi reboot */ + rtos::ThisThread::sleep_for(800ms); + + if (MX_WIFI_Init(&MxWifiObj)) { + error("EMW3080BInterface : MX_WIFI_Init failed, you may have to update MXCHIP fimrware module to version 2.1.11\n"); + } + + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : Product name: %s\n", MxWifiObj.SysInfo.Product_Name); + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : Product ID: %s\n", MxWifiObj.SysInfo.Product_ID); + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : FW revision: %s\n", MxWifiObj.SysInfo.FW_Rev); + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : MAC %02x.%02x.%02x.%02x.%02x.%02x\n\n", MxWifiObj.SysInfo.MAC[0], MxWifiObj.SysInfo.MAC[1], MxWifiObj.SysInfo.MAC[2], MxWifiObj.SysInfo.MAC[3], MxWifiObj.SysInfo.MAC[4], MxWifiObj.SysInfo.MAC[5]); +} + +void EMW3080BInterface::release(void) +{ + return; +} + + +int EMW3080BInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) +{ + if ((ssid == NULL) || (strlen(ssid) == 0) || (strlen(ssid) > 32)) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : bad credential\n"); + return NSAPI_ERROR_PARAMETER; + } + + if (security != NSAPI_SECURITY_NONE) { + if ((pass == NULL) || (strcmp(pass, "") == 0) || (strlen(pass) > 63)) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : bad security\n"); + return NSAPI_ERROR_PARAMETER; + } + } + + _mutex.lock(); + memset(_ssid, 0, sizeof(_ssid)); + strncpy(_ssid, ssid, sizeof(_ssid)); + + memset(_pass, 0, sizeof(_pass)); + if (security != NSAPI_SECURITY_NONE) { + strncpy(_pass, pass, sizeof(_pass)); + } + _sec = nsapi_sec2emw_sec(security); + + _mutex.unlock(); + debug_if(_debug_level >= DEBUG_LOG, "EMW3080BInterface : set credential OK %s %s \n", _ssid, _pass); + return NSAPI_ERROR_OK; +} + +nsapi_error_t EMW3080BInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, + uint8_t channel) +{ + nsapi_error_t ret; + + if (channel != 0) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : connect bad channel value, only 0 is supported\n"); + ret = NSAPI_ERROR_UNSUPPORTED; + } else { + + _mutex.lock(); + nsapi_error_t credentials_status = set_credentials(ssid, pass, security); + _mutex.unlock(); + + if (credentials_status) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : connect unable to set credential\n"); + ret = credentials_status; + } else { + ret = connect(); + } + } + return ret; +} + + +nsapi_error_t EMW3080BInterface::connect() +{ + nsapi_error_t ret ; + _mutex.lock(); + + /* Disable deepsleep as wakeup latency is too high */ + if (!deepsleep_locked) { + deepsleep_locked = true; + sleep_manager_lock_deep_sleep(); + } + + MxWifiObj.NetSettings.DHCP_IsEnabled = true; + + if (_ssid[0] == '\0') { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : connect , ssid is missing\n"); + ret = NSAPI_ERROR_NO_SSID; + } else if (_isConnected) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : connect is already connected\n"); + ret = NSAPI_ERROR_IS_CONNECTED; + } else { + + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : connecting MX_WIFI\n"); + if (MX_WIFI_Connect( + &MxWifiObj, + _ssid, + _pass, + _sec)) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : Connect failed; wrong parameter ?\n"); + ret = NSAPI_ERROR_PARAMETER ; + } else { + // FIXME : MX_WIFI_Connect command needs to allocate a netbuffer to store the module answer (zero copy mechanism) + // potential issue is that netbuffer allocation is not ready because part of the EMAC class connect phase + + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : connecting EMAC\n"); + ret = EMACInterface::connect(); + /* EMAC is waiting for UP conection , UP means we join an hotspot and IP services running */ + if (ret == NSAPI_ERROR_OK || ret == NSAPI_ERROR_IS_CONNECTED) { + debug_if(_debug_level >= DEBUG_LOG, "EMW3080BInterface : Connected to emac! (using ssid %s , passw %s )\n", _ssid, _pass); + _isConnected = true; + ret = NSAPI_ERROR_OK; + } else { + + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : EMAC Fail to connect NSAPI_ERROR %d\n", ret); + (void) MX_WIFI_Disconnect(&MxWifiObj); + EMACInterface::disconnect(); + ret = NSAPI_ERROR_CONNECTION_TIMEOUT; + } + } + } + _mutex.unlock(); + + return ret; +} + +nsapi_error_t EMW3080BInterface::disconnect() +{ + nsapi_error_t ret ; + _mutex.lock(); + + if (_isConnected == false) { + ret = NSAPI_ERROR_NO_CONNECTION; + } else { + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : disconnecting MX_WIFI and EMAC\n"); + if (MX_WIFI_Disconnect(&MxWifiObj)) { + debug_if(_debug_level >= DEBUG_WARNING, "MXWIFI disconnect command failed\n"); + ret = NSAPI_ERROR_DEVICE_ERROR; + } else { + ret = NSAPI_ERROR_OK; + } + _isConnected = false; + EMACInterface::disconnect(); + } + + if (deepsleep_locked) { + deepsleep_locked = false; + sleep_manager_unlock_deep_sleep(); + } + + _mutex.unlock(); + return ret; +} + + +int8_t EMW3080BInterface::get_rssi() +{ + _mutex.lock(); + int8_t ret = 0; + if (_isConnected) { + uint32_t count; + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : Perform a scan for RSSI\n"); + + MX_WIFI_Scan(&MxWifiObj, MC_SCAN_ACTIVE, (char *)&_ssid[0], strlen(_ssid)); + count = MX_WIFI_Get_scan_result(&MxWifiObj, (uint8_t *) _ap_info, MAX_AP_COUNT); + if (count == 0) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : Get RSSI , scan did not find HotSpot %s\n", _ssid); + } else { + if (count > 1) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080BInterface : Get RSSI , scan find several HotSpot named %s, return strenght of first one\n", _ssid); + } + ret = _ap_info[0].rssi; + } + } + + _mutex.unlock(); + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : Get RSSI return %d\n", ret); + return ret; +} + + + +int EMW3080BInterface::scan(WiFiAccessPoint *res, unsigned int count) +{ + _mutex.lock(); + if (count == 0) { + return MAX_AP_COUNT; + } else { + if (count > MAX_AP_COUNT) { + count = MAX_AP_COUNT; + } + + MX_WIFI_Scan(&MxWifiObj, MC_SCAN_PASSIVE, NULL, 0); + count = MX_WIFI_Get_scan_result(&MxWifiObj, (uint8_t *) _ap_info, count); + debug_if(_debug_level >= DEBUG_INFO, "EMW3080BInterface : Scan find %d HotSpot\n", count); + + if (res != NULL) { + for (uint32_t i = 0; i < count ; i++) { + nsapi_wifi_ap_t ap; + debug_if(_debug_level >= DEBUG_LOG, "EMW3080BInterface : %" PRIu32 " SSID %s rssi %" PRIu32 "\n", i, _ap_info[i].ssid, _ap_info[i].rssi); + debug_if(_debug_level >= DEBUG_LOG, "EMW3080BInterface : BSSID %hhx:%hhx:%hhx:%hhx:%hhx:%hhx\n", _ap_info[i].bssid[0], _ap_info[i].bssid[1], _ap_info[i].bssid[2], _ap_info[i].bssid[3], _ap_info[i].bssid[4], _ap_info[i].bssid[5]); + + memcpy(ap.ssid, _ap_info[i].ssid, 33); + memcpy(ap.bssid, _ap_info[i].bssid, 6); + ap.security = emw_sec2nsapi_sec(_ap_info[i].security); + ap.rssi = _ap_info[i].rssi; + ap.channel = _ap_info[i].channel; + res[i] = WiFiAccessPoint(ap); + } + } + } + _mutex.unlock(); + return (int) count; +} + + +#if MBED_CONF_EMW3080B_PROVIDE_DEFAULT +WiFiInterface *WiFiInterface::get_default_instance() +{ + static EMW3080BInterface emw; + return &emw; +} +#endif /* MBED_CONF_EMW3080B_PROVIDE_DEFAULT */ + + +#if defined(MBED_CONF_NSAPI_PRESENT) +WiFiInterface *WiFiInterface::get_target_default_instance() +{ +#if (DEFAULT_DEBUG == DEBUG_LOG) + printf("get_target_default_instance\n"); +#endif /* MBED_CONF_NSAPI_PRESENT */ + static EMW3080BInterface wifi; + return &wifi; +} +#endif /* MBED_CONF_NSAPI_PRESENT */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080BInterface.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080BInterface.h new file mode 100644 index 00000000000..91f3057aa45 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080BInterface.h @@ -0,0 +1,207 @@ +/* EMW3080B implementation of NetworkInterfaceAPI + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMW3080B_INTERFACE_H +#define EMW3080B_INTERFACE_H + +#if defined(MBED_CONF_NSAPI_PRESENT) + +#include + +#include "mbed.h" +#include "mbed_debug.h" +#include "mx_wifi.h" +#include "netsocket/WiFiInterface.h" +#include "netsocket/EMACInterface.h" +#include "netsocket/OnboardNetworkStack.h" +#include "EMW3080B_EMAC.h" + + +/** EMW3080BInterface class + * Implementation of the NetworkStack for the EMW3080B + */ +class EMW3080BInterface : public WiFiInterface, public EMACInterface { +public: + EMW3080BInterface(bool debug = MBED_CONF_EMW3080B_WIFI_DEBUG, + PinName mosi = MBED_CONF_EMW3080B_WIFI_MOSI, + PinName miso = MBED_CONF_EMW3080B_WIFI_MISO, + PinName sclk = MBED_CONF_EMW3080B_WIFI_SCLK, + PinName nss = MBED_CONF_EMW3080B_WIFI_NSS, + PinName notify = MBED_CONF_EMW3080B_WIFI_NOTIFY, + PinName flow = MBED_CONF_EMW3080B_WIFI_FLOW, + PinName reset = MBED_CONF_EMW3080B_WIFI_RESET, + PinName tx = MBED_CONF_EMW3080B_WIFI_TX, + PinName rx = MBED_CONF_EMW3080B_WIFI_RX, + EMAC &emac = EMW3080B_EMAC::get_instance(), + OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance() + ); + + /** Start the interface + * + * Attempts to connect to a WiFi network. Requires ssid and passphrase to be set. + * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. + * + * @return 0 on success, negative error code on failure + */ + nsapi_error_t connect(); + + /** Start the interface + * + * Attempts to connect to a WiFi network. + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE) + * @param channel This parameter is not supported, setting it to anything else than 0 will result in NSAPI_ERROR_UNSUPPORTED + * @return 0 on success, or error code on failure + */ + nsapi_error_t connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0); + + /** Stop the interface + * @return 0 on success, negative on failure + */ + nsapi_error_t disconnect(); + + /** Set the WiFi network credentials + * + * @param ssid Name of the network to connect to + * @param pass Security passphrase to connect to the network + * @param security Type of encryption for connection + * (defaults to NSAPI_SECURITY_NONE) + * @return 0 on success, or error code on failure + */ + nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); + + /** Set the WiFi network channel - NOT SUPPORTED + * + * This function is not supported and will return NSAPI_ERROR_UNSUPPORTED + * + * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) + * @return Not supported, returns NSAPI_ERROR_UNSUPPORTED + */ + nsapi_error_t set_channel(uint8_t channel) + { + if (channel != 0) { + return NSAPI_ERROR_UNSUPPORTED; + } + + return 0; + } + + /** Gets the current radio signal strength for active connection + * + * @return Connection strength in dBm (negative value) + */ + int8_t get_rssi(); + + /** Scan for available networks + * + * This function will block. + * + * @param ap Pointer to allocated array to store discovered AP + * @param count Size of allocated @a res array, or 0 to only count available AP + * @param timeout Timeout in milliseconds; 0 for no timeout (Default: 0) + * @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error + * see @a nsapi_error + */ + int scan(WiFiAccessPoint *res, unsigned count); + + MX_WIFIObject_t MxWifiObj; + +private: + + nsapi_security_t emw_sec2nsapi_sec(mwifi_security_t sec) + { + nsapi_security_t sec_out; + + switch (sec) { + case MX_WIFI_SEC_NONE: + sec_out = NSAPI_SECURITY_NONE; + break; + case MX_WIFI_SEC_WEP: + sec_out = NSAPI_SECURITY_WEP; + break; + case MX_WIFI_SEC_WPA_AES: + case MX_WIFI_SEC_WPA_TKIP: + sec_out = NSAPI_SECURITY_WPA; + break; + case MX_WIFI_SEC_WPA2_AES: + case MX_WIFI_SEC_WPA2_TKIP: + case MX_WIFI_SEC_WPA2_MIXED: + sec_out = NSAPI_SECURITY_WPA2; + break; + case MX_WIFI_SEC_AUTO: + sec_out = NSAPI_SECURITY_WPA_WPA2; + break; + default: + sec_out = NSAPI_SECURITY_WPA_WPA2; + break; + + } + return sec_out; + } + + MX_WIFI_SecurityType_t nsapi_sec2emw_sec(nsapi_security_t sec) + { + MX_WIFI_SecurityType_t mx_sec; + + switch (sec) { + case NSAPI_SECURITY_NONE: + mx_sec = MX_WIFI_SEC_NONE; + break; + case NSAPI_SECURITY_WEP: + mx_sec = MX_WIFI_SEC_WEP; + break; + case NSAPI_SECURITY_WPA: + mx_sec = MX_WIFI_SEC_WPA_AES; + break; + case NSAPI_SECURITY_WPA2: + mx_sec = MX_WIFI_SEC_WPA2_AES; + break; + default: + mx_sec = MX_WIFI_SEC_AUTO; + break; + } + + return mx_sec; + } + + /* MXCHIP array size for SCAN is 2KB , so limits number of AP to 20 */ +#define MAX_AP_COUNT 20 + + + int8_t IO_Init(uint16_t mode); + int8_t IO_DeInit(void); + void IO_Delay(uint32_t delayms); + uint16_t IO_Send(uint8_t *data, uint16_t len); + uint16_t IO_Receive(uint8_t *buffer, uint16_t buff_size); + + void probe(void); + void release(void); + char _ssid[33]; /* The longest possible name (defined in 802.11) +1 for the \0 */ + char _pass[64]; /* The longest allowed passphrase + 1 */ + mwifi_ap_info_t _ap_info[MAX_AP_COUNT]; + MX_WIFI_SecurityType_t _sec; + volatile bool _isConnected; + Mutex _mutex; + + uint8_t _debug_level; +}; + +#endif /* MBED_CONF_NSAPI_PRESENT */ + +#endif /* EMW3080B_INTERFACE_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_EMAC.cpp b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_EMAC.cpp new file mode 100644 index 00000000000..4343351e0ea --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_EMAC.cpp @@ -0,0 +1,336 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "EMW3080B_EMAC.h" +#include "mx_wifi_ipc.h" + +#include "lwip/etharp.h" +#include "lwip/ethip6.h" + +#define DEBUG_SILENT 0 +#define DEBUG_WARNING 1 +#define DEBUG_INFO 2 +#define DEBUG_LOG 3 +#define DEFAULT_DEBUG DEBUG_SILENT + + +EMW3080B_EMAC::EMW3080B_EMAC() +{ + _debug_level = DEFAULT_DEBUG; +} + + +uint32_t EMW3080B_EMAC::get_mtu_size() const +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : get_mtu_size %d\n", MX_WIFI_MTU_SIZE); + return MX_WIFI_MTU_SIZE; +} + +uint32_t EMW3080B_EMAC::get_align_preference() const +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : get_align_preference 0\n"); + return 0; +} + +void EMW3080B_EMAC::add_multicast_group(const uint8_t *addr) +{ + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : add_multicast_group is not supported\n"); +} + +void EMW3080B_EMAC::remove_multicast_group(const uint8_t *addr) +{ + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : remove_multicast_group is not supported\n"); +} + +void EMW3080B_EMAC::set_all_multicast(bool all) +{ + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : set_all_multicast not supported\n"); + /* No-op at this stage */ +} + +void EMW3080B_EMAC::power_down() +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : power_down\n"); + +} + +bool EMW3080B_EMAC::power_up() +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : power_up\n"); + + return true; +} + + +bool EMW3080B_EMAC::get_hwaddr(uint8_t *addr) const +{ + bool ret; + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : get_hwaddr\n"); + + MX_WIFIObject_t *pMxWifiObj = wifi_obj_get(); + if (pMxWifiObj) { + addr[0] = pMxWifiObj->SysInfo.MAC[0]; + addr[1] = pMxWifiObj->SysInfo.MAC[1]; + addr[2] = pMxWifiObj->SysInfo.MAC[2]; + addr[3] = pMxWifiObj->SysInfo.MAC[3]; + addr[4] = pMxWifiObj->SysInfo.MAC[4]; + addr[5] = pMxWifiObj->SysInfo.MAC[5]; + ret = true; + } else { + ret = false; + } + return ret; +} + + +void EMW3080B_EMAC::set_hwaddr(const uint8_t *addr) +{ + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : set_hwaddr ignoring this command ,not possible to set MAC address for MXCHIP device\n"); +} + +uint8_t EMW3080B_EMAC::get_hwaddr_size() const +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : get_hwaddr_size %u\n", EMW3080B_HWADDR_SIZE); + return EMW3080B_HWADDR_SIZE; +} + + +static void emac_data_callback(mx_buf_t *buffer, void *user_args) +{ + /* to retrieve the C++ class */ + EMW3080B_EMAC emac = EMW3080B_EMAC::get_instance(); + emac.mx_wifi_netlink_input_callback(buffer); +} + +void EMW3080B_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : set_link_input_cb\n"); + if (MX_WIFI_STATUS_OK != MX_WIFI_Network_bypass_mode_set(wifi_obj_get(), 1, emac_data_callback, NULL)) { + error("EMW3080B_EMAC : can not set set_link_input_cb\n"); + } else { + _emac_input_data_cb = input_cb; + } +} + +extern "C" { + void emac_status_changed(uint8_t cate, uint8_t status, void *arg) + { + /* to retrieve the C++ class */ + EMW3080B_EMAC emac = EMW3080B_EMAC::get_instance(); + emac.mx_wifi_status_changed(cate, status, arg); + } +} + +void EMW3080B_EMAC::mx_wifi_status_changed(uint8_t cate, uint8_t status, void *arg) +{ + bool mx_wifi_driver_up; + if ((uint8_t)MC_STATION == cate) { + switch (status) { + case MWIFI_EVENT_STA_DOWN: + mx_wifi_driver_up = false; + break; + + case MWIFI_EVENT_STA_UP: + mx_wifi_driver_up = true; + break; + + default: + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : mx_wifi_status_changed get unknown Event from EMW3080B\n"); + mx_wifi_driver_up = false; + break; + } + + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : Interface is %s (calling)\n", mx_wifi_driver_up ? "UP" : "DOWN"); + if (_emac_link_state_cb) { + _emac_link_state_cb(mx_wifi_driver_up); + } + + } else if ((uint8_t)MC_SOFTAP == cate) { + switch (status) { + case MWIFI_EVENT_AP_DOWN: + break; + + case MWIFI_EVENT_AP_UP: + break; + + default: + break; + } + } else { + /* nothing */ + } +} + + + +void EMW3080B_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + _emac_link_state_cb = state_cb; + + + if (MX_WIFI_RegisterStatusCallback_if( + wifi_obj_get(), + emac_status_changed, + NULL /* void * arg */, + (mwifi_if_t)MC_STATION)) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : Fail to register callback\n"); + return ; + } + + +} + +EMACMemoryManager *emac3080b_global_memory_manager = NULL; + +void EMW3080B_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : set_memory_manager\n"); + _memory_manager = &mem_mngr; + emac3080b_global_memory_manager = &mem_mngr; + +} +#define EMW_PROTOCOL_HEADROOM sizeof(wifi_bypass_out_cparams_t) + +bool EMW3080B_EMAC::link_out(emac_mem_buf_t *buf) +{ + bool ret = true; + + emac_mem_buf_t *q; + uint32_t m = 0; + uint32_t len = 0; + int32_t mx_ret; + +#if MX_WIFI_TX_BUFFER_NO_COPY + for (q = buf; q != NULL; q = _memory_manager->get_next(q)) { + len += _memory_manager->get_len(q); + } + + mx_buf_t *net = mx_buf_alloc(len + EMW_PROTOCOL_HEADROOM); + if (net != NULL) { + MX_NET_BUFFER_HIDE_HEADER(net, EMW_PROTOCOL_HEADROOM); + MX_NET_BUFFER_SET_PAYLOAD_SIZE(net, len); + + uint8_t *payload = MX_NET_BUFFER_PAYLOAD(net); + for (q = buf; q != NULL; q = _memory_manager->get_next(q)) { + memcpy(payload, _memory_manager->get_ptr(q), _memory_manager->get_len(q)); + payload += _memory_manager->get_len(q); + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_EMAC : TX seg %" PRIu32 " %" PRIu32 " bytes\n", m, _memory_manager->get_len(q)); + m++; + } + + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_EMAC : %" PRIu32 " TX %" PRIu32 "\n", m, MX_NET_BUFFER_GET_PAYLOAD_SIZE(net)); + mx_ret = MX_WIFI_Network_bypass_netlink_output( + wifi_obj_get(), + MX_NET_BUFFER_PAYLOAD(net), + MX_NET_BUFFER_GET_PAYLOAD_SIZE(net), + STATION_IDX + ); + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_EMAC : TX done lust e zero %" PRIu32 "\n", mx_ret); + MX_NET_BUFFER_FREE(net); + if (mx_ret != MX_WIFI_STATUS_OK) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : link_out : failed to send buffer\n"); + ret = false; + } +#else + /* copy is managed internally */ + ret = MX_WIFI_Network_bypass_netlink_output( + wifi_obj_get(), + _memory_manager->get_ptr(q), + _memory_manager->get_len(q), + STATION_IDX + ); +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + } else + { + error("EMW3080B_EMAC : unable to allocate %" PRIu32 " bytes\n", len); + } + + _memory_manager->free(buf); + return ret; +} + +void EMW3080B_EMAC::get_ifname(char *name, uint8_t size) const +{ + debug_if(_debug_level >= DEBUG_INFO, "EMW3080B_EMAC : get_ifname\n"); + if (size > 0) { + strncpy(name, "st", size - 1); + name[size - 1] = '\0'; + } +} + +EMW3080B_EMAC &EMW3080B_EMAC::get_instance() +{ + static EMW3080B_EMAC emac; + return emac; +} + +void EMW3080B_EMAC::mx_wifi_netlink_input_callback(mx_buf_t *buffer) +{ + struct eth_hdr *ethernet_header; + uint16_t ethertype; + uint32_t len = 0U; + + if (buffer != NULL) { + len = MX_NET_BUFFER_GET_PAYLOAD_SIZE(buffer); + + if ((len > 0U) && (len <= (uint32_t) MX_WIFI_MTU_SIZE)) { + /* points to packet payload, which starts with an Ethernet header */ + ethernet_header = (struct eth_hdr *) MX_NET_BUFFER_PAYLOAD(buffer); + + ethertype = lwip_htons(ethernet_header->type); + switch (ethertype) { + case ETHTYPE_IP: + /* case ETHTYPE_IPV6: */ + case ETHTYPE_ARP: + /* PPPoE packet */ + case ETHTYPE_PPPOEDISC: + case ETHTYPE_PPPOE: { + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_EMAC : process input packet 0x%02x, len=%" PRIu32 "\n", ethertype, len); + emac_mem_buf_t *p, *q; + uint32_t index = 0; + p = _memory_manager->alloc_pool(len, 0); + if (p != NULL) { + uint8_t *src = (uint8_t *) ethernet_header; + uint32_t m = 0; + for (q = p; q != NULL; q = _memory_manager->get_next(q)) { + uint8_t *dest = (uint8_t *) _memory_manager->get_ptr(q); + memcpy(dest, &src[index], _memory_manager->get_len(q)); + index += _memory_manager->get_len(q); + + if (index >= len) { + break; + } + m++; + } + + + if (_emac_input_data_cb) { + _emac_input_data_cb(p); + } + } else { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_EMAC : fail to allocate emac_mem_buf_t %" PRIu32 " bytes\n", len); + } + } + break; + + default: + break; + } + } + MX_NET_BUFFER_FREE(buffer); + } +} diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_EMAC.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_EMAC.h new file mode 100644 index 00000000000..17f368366c5 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_EMAC.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EMW3080B_EMAC_H_ +#define EMW3080B_EMAC_H_ + +#include + +#include "mbed.h" +#include "mbed_debug.h" +#include "EMACInterface.h" +#include "WiFiInterface.h" +#include "mx_wifi.h" + +extern EMACMemoryManager *emac3080b_global_memory_manager ; + + +class EMW3080B_EMAC : public EMAC { +public: + EMW3080B_EMAC(); + + static EMW3080B_EMAC &get_instance(); + + /** + * Return maximum transmission unit + * + * @return MTU in bytes + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not + * align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ + virtual uint32_t get_align_preference() const; + + /** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Return interface-supplied HW address + * + * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size + * + * HW address need not be provided if this interface does not have its own HW + * address configuration; stack will choose address from central system + * configuration if the function returns false and does not write to addr. + * + * @param addr HW address for underlying interface + * @return true if HW address is available + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden, eg for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ + virtual bool power_up(); + + /** + * Deinitializes the HW + * + */ + virtual void power_down(); + + /** + * Sets a callback that needs to be called for packets received for that interface + * + * @param input_cb Function to be register as a callback + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that needs to be called on link status changes for given interface + * + * @param state_cb Function to be register as a callback + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Add device to a multicast group + * + * @param address A multicast group hardware address + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + + void mx_wifi_status_changed(uint8_t cate, uint8_t status, void *arg); + void mx_wifi_netlink_input_callback(mx_buf_t *buffer); + +#define EMW3080B_HWADDR_SIZE 6 + + emac_link_input_cb_t _emac_link_input_cb; /**< Callback for incoming data */ + emac_link_state_change_cb_t _emac_link_state_cb; + emac_link_input_cb_t _emac_input_data_cb; + EMACMemoryManager *_memory_manager; + uint8_t _mac_addr[EMW3080B_HWADDR_SIZE]; + + uint8_t _debug_level; +}; + +#endif /* EMW3080B_EMAC_H_ */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_SPI.cpp b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_SPI.cpp new file mode 100644 index 00000000000..459bb928b7c --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_SPI.cpp @@ -0,0 +1,409 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Includes ------------------------------------------------------------------*/ +/* Private includes ----------------------------------------------------------*/ +#include "EMW3080B_SPI.h" + +#define DEBUG_SILENT 0 +#define DEBUG_WARNING 1 +#define DEBUG_INFO 2 +#define DEBUG_LOG 3 +#define DEFAULT_DEBUG DEBUG_SILENT + +static EMW3080B_SPI *emw3080B_spi_object; + + +EMW3080B_SPI::EMW3080B_SPI(bool debug, + PinName mosi, + PinName miso, + PinName sclk, + PinName nss, + PinName notify, + PinName flow, + PinName reset + ): SPI(mosi, miso, sclk), _resetpin(reset), _nsspin(nss), _notifypin(notify), _flowpin(flow) +{ + if (debug) { + _debug_level = DEBUG_INFO; // too much real time impact with DEBUG_LOG + } else { + _debug_level = DEFAULT_DEBUG; + } + + _notify_irq = new InterruptIn(notify); + _flow_irq = new InterruptIn(flow); + + _notify_irq->rise(NULL); + _flow_irq->rise(NULL); + + emw3080B_spi_object = this; + /* MXWIFI supports 30 Mhz SPI clock but Mbed implementation is limitted to 5 Mhz */ + /* DMA implementation would be required to increase this supported frequency */ + SPI::frequency(5000000); + /* Phase 0 and One edge => mode 0 */ + SPI::format(8, 0); + + SPI::set_default_write_value(0); + + SEM_INIT(spi_transfer_done_sem, 1); +} + +int flow_rise_count = 0; +int notify_rise_count = 0; + +void EMW3080B_SPI::flow_rise() +{ + flow_rise_count++; + SEM_SIGNAL(spi_flow_rise_sem); +} + +void EMW3080B_SPI::notify_rise() +{ + notify_rise_count++; + if (SEM_SIGNAL(spi_txrx_sem) != SEM_OK) { + error("failed to signal spi_txrx_sem\n"); + } +} + + +#pragma pack(1) +typedef struct _spi_header { + uint8_t type; + uint16_t len; + uint16_t lenx; + uint8_t dummy[3]; +} spi_header_t; +#pragma pack() + + +/* Private define ------------------------------------------------------------*/ +/* SPI protocol */ +#define SPI_WRITE (0x0A) +#define SPI_READ (0x0B) +#define SPI_HEADER_SIZE (5) +#define SPI_DATA_SIZE (MX_WIFI_HCI_DATA_SIZE) + +#define SPI_WAITING_FLOW_HIGH_TIMEOUT (100) /* ms unit */ +#define SPI_MAX_TRANSMIT_DURATION (500) /* ms unit */ + + +/* SPI CS */ +#define MX_WIFI_SPI_CS_HIGH() _nsspin = 1 +#define MX_WIFI_SPI_CS_LOW() _nsspin = 0 + + + +/** + * @brief Initialize SPI + * @param None + * @retval None + */ +int8_t EMW3080B_SPI::IO_Init(uint16_t mode) +{ + int8_t ret = 0; + + if (MX_WIFI_RESET == mode) { + /* HW reset */ + MX_WIFI_SPI_CS_HIGH(); + + _resetpin = 0; + rtos::ThisThread::sleep_for(100ms); + _resetpin = 1; + rtos::ThisThread::sleep_for(1200ms); + } else { + ret = mx_wifi_spi_txrx_start(); + } + return ret; +} + + +/** + * @brief DeInitialize SPI + * @param None + * @retval None + */ +int8_t EMW3080B_SPI::IO_DeInit(void) +{ + mx_wifi_spi_txrx_stop(); + return 0; +} + +void EMW3080B_SPI::IO_Delay(uint32_t delayms) +{ + return; +} + +uint16_t EMW3080B_SPI::IO_Send(uint8_t *data, uint16_t len) +{ + if ((NULL == data) || (0 == len) || (len > SPI_DATA_SIZE)) { + return 0; + } + + spi_tx_data = data; + spi_tx_len = len; + + if (SEM_SIGNAL(spi_txrx_sem) != SEM_OK) { + /* Happen if received thread did not have a chance to run on time, need to increase priority */ + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : spi semaphore has been already notified\n"); + } + + return len; +} + + +uint16_t EMW3080B_SPI::IO_Receive(uint8_t *buffer, uint16_t buff_size) +{ + return 0U; +} + + +int8_t EMW3080B_SPI::wait_flow_high(uint32_t timeout) +{ + int8_t ret = 0; + + if (SEM_WAIT(spi_flow_rise_sem, timeout, NULL) != SEM_OK) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : wait_flow_high semaphore failed, timeout\n"); + ret = -1; + } + + return ret; +} + +int spi_handler_count = 0; +int spi_handler_event_value = 0; + +void EMW3080B_SPI::spi_handler(int event) +{ + spi_handler_count++; + spi_handler_event_value = event; + + SEM_SIGNAL(spi_transfer_done_sem); +} + + +int32_t EMW3080B_SPI::TransmitReceive(uint8_t *txdata, uint8_t *rxdata, uint32_t datalen, + uint32_t timeout) +{ + int32_t ret = 0; + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_SPI : Spi Tx Rx %" PRIu32 "\n", datalen); + SPI::transfer((const uint8_t *) txdata, (int) datalen, rxdata, (int) datalen, callback(this, &EMW3080B_SPI::spi_handler), SPI_EVENT_COMPLETE); + if (SEM_WAIT(spi_transfer_done_sem, timeout, NULL) != SEM_OK) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Timeout on TransmitReceive %d\n", spi_handler_count); + ret = -1; + } + + return ret; +} + + +int32_t EMW3080B_SPI::Transmit(uint8_t *txdata, uint32_t datalen, uint32_t timeout) +{ + int32_t ret = 0; + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_SPI : Spi Tx %" PRIu32 "\n", datalen); + SPI::transfer((const uint8_t *) txdata, (int) datalen, (uint8_t *)NULL, (int) datalen, callback(this, &EMW3080B_SPI::spi_handler), SPI_EVENT_COMPLETE); + if (SEM_WAIT(spi_transfer_done_sem, timeout, NULL) != SEM_OK) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Timeout on Transmit\n"); + ret = -1; + } + return ret; +} + +int32_t EMW3080B_SPI::Receive(uint8_t *rxdata, uint32_t datalen, uint32_t timeout) +{ + int32_t ret = 0; + debug_if(_debug_level >= DEBUG_LOG, "EMW3080B_SPI : Spi Rx %" PRIu32 "\n", datalen); + SPI::transfer((const uint8_t *) NULL, (int) datalen, rxdata, (int) datalen, callback(this, &EMW3080B_SPI::spi_handler), SPI_EVENT_COMPLETE); + if (SEM_WAIT(spi_transfer_done_sem, timeout, NULL) != SEM_OK) { + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Timeout on Receive\n"); + ret = -1; + } + return ret; +} + + +void EMW3080B_SPI::process_txrx_poll(uint32_t timeout) +{ + + spi_header_t mheader, sheader; + int32_t ret; + uint8_t *txdata; + uint8_t *p = NULL; + uint16_t datalen; + static mx_buf_t *netb = NULL; + bool first_miss = true; + + MX_WIFI_SPI_CS_HIGH(); + + while (netb == NULL) { + netb = MX_NET_BUFFER_ALLOC(MX_WIFI_BUFFER_SIZE); + if (netb == NULL) { + rtos::ThisThread::sleep_for(1ms); + if (true == first_miss) { + first_miss = false; + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Running Out of buffer for RX\n"); + } + } + } + + /* waiting for data to be sent or to be received */ + if (SEM_WAIT(spi_txrx_sem, timeout, NULL) == SEM_OK) { + if (spi_tx_data == NULL) { + if (_notifypin == 0) { + /* tx data null means no data to send , _flowpin low means no data to received */ + error("EMW3080B_SPI : Nothing to process but wake UP!!!\n"); + } + txdata = NULL; + mheader.len = 0; + } else { + mheader.len = spi_tx_len; + txdata = spi_tx_data; + } + + mheader.type = SPI_WRITE; + mheader.lenx = ~mheader.len; + mheader.dummy[0] = 0; + mheader.dummy[1] = 0; + mheader.dummy[2] = 0; + + MX_WIFI_SPI_CS_LOW(); + + /* wait EMW to be ready */ + if (wait_flow_high(SPI_WAITING_FLOW_HIGH_TIMEOUT) != 0) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : wait flow high timeout, notify_rise_count %d flow_rise_count %d flow is %d\n", notify_rise_count, flow_rise_count, (int)_flowpin); + } + + /* transmit only header part */ + sheader.type = 0; + sheader.len = 0; + + if (TransmitReceive((uint8_t *)&mheader, (uint8_t *)&sheader, sizeof(mheader), SPI_MAX_TRANSMIT_DURATION)) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Send mheader error\r\n"); + } + if (sheader.type != SPI_READ) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Invalid SPI type %02x\r\n", sheader.type); + } + if ((sheader.len ^ sheader.lenx) != 0xFFFF) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Invalid len %04x-%04x\r\n", sheader.len, sheader.lenx); + } + + /* send or received header must be not null */ + if ((sheader.len == 0) && (mheader.len == 0)) { + MX_WIFI_SPI_CS_HIGH(); + return; + } + + if ((sheader.len > SPI_DATA_SIZE) || (mheader.len > SPI_DATA_SIZE)) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : SPI length invalid: %d-%d\r\n", sheader.len, mheader.len); + } + + /* keep max length */ + if (mheader.len > sheader.len) { + datalen = mheader.len; + } else { + datalen = sheader.len; + } + + /* allocate a buffer */ + if (sheader.len > 0) { + /* get payload */ + p = MX_NET_BUFFER_PAYLOAD(netb); + } else { + p = NULL; + } + + /* flow must be high */ + + if (wait_flow_high(SPI_WAITING_FLOW_HIGH_TIMEOUT) != 0) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : timeout waiting for flow high after transfer !\r\n"); + } + + /* transmit and received */ + if (NULL != txdata) { + spi_tx_data = NULL; + spi_tx_len = 0; + if (NULL != p) { + ret = TransmitReceive(txdata, p, datalen, SPI_MAX_TRANSMIT_DURATION); + } else { + ret = Transmit(txdata, datalen, SPI_MAX_TRANSMIT_DURATION); + } + } else { + ret = Receive(p, datalen, SPI_MAX_TRANSMIT_DURATION); + } + + if (ret) { + MX_WIFI_SPI_CS_HIGH(); + debug_if(_debug_level >= DEBUG_WARNING, "EMW3080B_SPI : Transmit/Receive data timeout\r\n"); + } + + /* resize the input buffer and sent it back to processing thread */ + if (sheader.len > 0) { + MX_NET_BUFFER_SET_PAYLOAD_SIZE(netb, sheader.len); + mx_wifi_hci_input(netb); + netb = NULL; + + } + MX_WIFI_SPI_CS_HIGH(); + + } +} + +void mx_wifi_spi_txrx_task(void) +{ + while (1) { + emw3080B_spi_object->process_txrx_poll(WAIT_FOREVER); + } +} + +int8_t EMW3080B_SPI::mx_wifi_spi_txrx_start(void) +{ + int8_t ret = 0; + + SEM_INIT(spi_txrx_sem, 2); + SEM_INIT(spi_flow_rise_sem, 1); + SEM_INIT(spi_transfer_done_sem, 1); + _notify_irq->rise(callback(this, &EMW3080B_SPI::notify_rise)); + _flow_irq->rise(callback(this, &EMW3080B_SPI::flow_rise)); + + if (THREAD_OK == THREAD_INIT(MX_WIFI_TxRxThreadId, + mx_wifi_spi_txrx_task, NULL, + MX_WIFI_SPI_THREAD_STACK_SIZE, + MX_WIFI_SPI_THREAD_PRIORITY)) { + ret = 0; + } else { + ret = -1; + } + + return ret; +} + +int8_t EMW3080B_SPI::mx_wifi_spi_txrx_stop(void) +{ + + THREAD_DEINIT(MX_WIFI_TxRxThreadId); + _notify_irq->rise(NULL); + _flow_irq->rise(NULL); + SEM_DEINIT(spi_txrx_sem); + SEM_DEINIT(spi_flow_rise_sem); + SEM_DEINIT(spi_transfer_done_sem); + return 0; +} diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_SPI.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_SPI.h new file mode 100644 index 00000000000..f7c00fe1582 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_SPI.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Private includes ----------------------------------------------------------*/ +#include "mbed.h" +#include "mbed_debug.h" +#include "mbed_error.h" +#include "mx_wifi.h" +#include "core/mx_wifi_hci.h" + + + +class EMW3080B_SPI : public SPI { +public: + EMW3080B_SPI(bool debug = MBED_CONF_EMW3080B_WIFI_DEBUG, + PinName mosi = MBED_CONF_EMW3080B_WIFI_MOSI, + PinName miso = MBED_CONF_EMW3080B_WIFI_MISO, + PinName sclk = MBED_CONF_EMW3080B_WIFI_SCLK, + PinName nss = MBED_CONF_EMW3080B_WIFI_NSS, + PinName notify = MBED_CONF_EMW3080B_WIFI_NOTIFY, + PinName flow = MBED_CONF_EMW3080B_WIFI_FLOW, + PinName reset = MBED_CONF_EMW3080B_WIFI_RESET + ); + +private: + DigitalOut _resetpin; + DigitalOut _nsspin; + + DigitalIn _notifypin; + DigitalIn _flowpin; + + InterruptIn *_notify_irq; + InterruptIn *_flow_irq; + + void flow_rise(void); + void notify_rise(void); + int8_t wait_flow_high(uint32_t timeout); + + SEM_DECLARE(spi_txrx_sem); + SEM_DECLARE(spi_flow_rise_sem); + SEM_DECLARE(spi_transfer_done_sem); + + uint8_t *spi_tx_data = NULL; + uint16_t spi_tx_len = 0; + + int32_t TransmitReceive(uint8_t *txdata, uint8_t *rxdata, uint32_t datalen, uint32_t timeout); + int32_t Transmit(uint8_t *txdata, uint32_t datalen, uint32_t timeout); + int32_t Receive(uint8_t *rxdata, uint32_t datalen, uint32_t timeout); + void spi_handler(int event); + + int8_t mx_wifi_spi_txrx_start(void); + int8_t mx_wifi_spi_txrx_stop(void); + + THREAD_DECLARE(MX_WIFI_TxRxThreadId); + + +public: + + int8_t IO_Init(uint16_t mode); + int8_t IO_DeInit(void); + void IO_Delay(uint32_t delayms); + uint16_t IO_Send(uint8_t *data, uint16_t len); + uint16_t IO_Receive(uint8_t *buffer, uint16_t buff_size); + void process_txrx_poll(uint32_t timeout); + + uint8_t _debug_level; +}; diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_UART.cpp b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_UART.cpp new file mode 100644 index 00000000000..a91c30178a6 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_UART.cpp @@ -0,0 +1,144 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* Includes ------------------------------------------------------------------*/ +/* Private includes ----------------------------------------------------------*/ +#include "EMW3080B_UART.h" + +#define DEBUG_SILENT 0 +#define DEBUG_WARNING 1 +#define DEBUG_INFO 2 +#define DEBUG_LOG 3 +#define DEFAULT_DEBUG DEBUG_SILENT + +//#define DEBUG_UART_DATA 1 + +static EMW3080B_UART *emw3080b_uart_object; + + +EMW3080B_UART::EMW3080B_UART(bool debug, + PinName tx, + PinName rx, + PinName reset + ): BufferedSerial(tx, rx, 230400), _resetpin(reset) +{ + emw3080b_uart_object = this; + + if (debug) { + _debug_level = DEBUG_LOG; + } else { + _debug_level = DEFAULT_DEBUG; + } +} + +#if DEBUG_UART_DATA +void debug_print(char *prefix, uint8_t *data, uint16_t len); +void debug_print(char *prefix, uint8_t *data, uint16_t len) +{ + if (NULL != data) { + printf("%s[%d]:\n", prefix, len); + for (int32_t i = 0; i < len; i++) { + printf(" %02x", data[i]); + } + printf("\n"); + for (int32_t i = 0; i < len; i++) { + printf(" %c ", data[i]); + } + printf("\n"); + } +} +#else +#define debug_print(...) +#endif /* DEBUG_UART_DATA */ + + +void EMW3080B_UART::process_txrx_poll(void) +{ + uint8_t c; + ssize_t n; + mx_buf_t *nbuf = NULL; + + n = read(&c, 1); + if (n == 1) { + nbuf = slip_input_byte(c); + if (NULL != nbuf) { + debug_print("URX", MX_NET_BUFFER_PAYLOAD(nbuf), MX_NET_BUFFER_GET_PAYLOAD_SIZE(nbuf)); + mx_wifi_hci_input(nbuf); + } + } +} + + +void HWInterfaceReceivedPollTask(void) +{ + while (true) { + emw3080b_uart_object->process_txrx_poll(); + } +} + + + +int8_t EMW3080B_UART::IO_Init(uint16_t mode) +{ + int8_t rc = 0; + + if (MX_WIFI_RESET == mode) { + /* HW reset */ + _resetpin = 0; + rtos::ThisThread::sleep_for(100ms); + _resetpin = 1; + rtos::ThisThread::sleep_for(1200ms); + } else { + + if (THREAD_OK == THREAD_INIT(MX_WIFI_UARTRecvThreadId, + HWInterfaceReceivedPollTask, NULL, + MX_WIFI_UART_THREAD_STACK_SIZE, MX_WIFI_UART_THREAD_PRIORITY)) { + rc = MX_WIFI_STATUS_OK; + } else { + rc = MX_WIFI_STATUS_ERROR; + } + } + return rc; +} + + +int8_t EMW3080B_UART::IO_DeInit(void) +{ + int8_t rc = 0; + THREAD_DEINIT(MX_WIFI_UARTRecvThreadId); + return rc; +} + +void EMW3080B_UART::IO_Delay(uint32_t delayms) +{ + printf("%s %d\n", __FILE__, __LINE__); + return; +} + +uint16_t EMW3080B_UART::IO_Send(uint8_t *pdata, uint16_t len) +{ + uint16_t rc; + debug_print("UTX", pdata, len); + rc = write(pdata, len); + return rc; +} + +uint16_t EMW3080B_UART::IO_Receive(uint8_t *pdata, uint16_t request_len) +{ + return 0; +} diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_UART.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_UART.h new file mode 100644 index 00000000000..05d80f171ad --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/EMW3080B_UART.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) STMicroelectronics 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +/* Includes ------------------------------------------------------------------*/ +/* Private includes ----------------------------------------------------------*/ +#include "mbed.h" +#include "mbed_debug.h" +#include "mbed_error.h" +#include "mx_wifi.h" +#include "core/mx_wifi_hci.h" +#include "core/mx_wifi_slip.h" + + + +class EMW3080B_UART : public BufferedSerial { +public: + EMW3080B_UART(bool debug, + PinName tx, + PinName rx, + PinName reset + ); + +private: + DigitalOut _resetpin; + THREAD_DECLARE(MX_WIFI_UARTRecvThreadId); + + +public: + void process_txrx_poll(void); + + int8_t IO_Init(uint16_t mode); + int8_t IO_DeInit(void); + void IO_Delay(uint32_t delayms); + uint16_t IO_Send(uint8_t *data, uint16_t len); + uint16_t IO_Receive(uint8_t *buffer, uint16_t buff_size); + + uint8_t _debug_level; +}; diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/README.md b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/README.md new file mode 100644 index 00000000000..0241ce9d021 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/README.md @@ -0,0 +1,146 @@ +# EMW3080B WiFi driver for STM32 + +## License + +This software is licensed under terms that can be found in the [license](mx_wifi/LICENSE.md) file + + +## Currently supported platforms + +EMW3080B module is available + +- with an [ARDUINO extension board](https://www.seeedstudio.com/IOT-AT3080-IoT-development-board-p-4021.html) + +- with a ST Discovery kit for IoT node : [B-U585I-IOT02A](https://os.mbed.com/platforms/ST-Discovery-B-U585I-IOT02A/) + + +## Configuration + +B_U585I_IOT02A default configuration is enabled in [mbed_lib.json](mbed_lib.json) + +For Arduino shield, the UART interface is used. +See in mbed_lib.json, B_U585I_IOT02A__ARDUINO_SHIELD configuration example you need to add in your local mbed_app.json. + +``` + "YOUR_TARGET": { + "emw3080b.wifi-spi-interface": false, + "emw3080b.wifi-tx": "ARDUINO_UNO_D1", + "emw3080b.wifi-rx": "ARDUINO_UNO_D0", + "emw3080b.wifi-reset": "ARDUINO_UNO_D13", + "emw3080b.provide-default": true + }, +``` + +## Code Structure + +The Mbed EMW3080B driver relies on the [STM32 EMW3080B BSP driver](https://github.com/STMicroelectronics/STM32CubeU5/tree/main/Drivers/BSP/Components/mx_wifi) + +- COMPONENT_emw3080b/EMW3080BInterface.cpp : WiFiInterface class implementation (derived from EMACInterface ) +- COMPONENT_emw3080b/EMW3080B_EMAC.cpp : EMAC interface +- COMPONENT_emw3080b/EMW3080B_SPI.cpp : SPI communication protocol implementation +- COMPONENT_emw3080b/EMW3080B_UART.cpp : UART communication protocol implementation +- COMPONENT_emw3080b/mx_wifi/* : [STM32 EMW3080B BSP driver](https://github.com/STMicroelectronics/STM32CubeU5/tree/main/Drivers/BSP/Components/mx_wifi) + + +## Debug + +Some debug print on console can help to debug if necessary. + +Either update your mbed_app.json: +``` + "YOUR_TARGET": { + "emw3080b.wifi-debug": true + }, +``` + +Either update manually the different .cpp source files to choose the appropriate level of VERBOSITY. + +`#define DEFAULT_DEBUG DEBUG_SILENT` ==> choose DEBUG_WARNING/DEBUG_INFO/DEBUG_LOG + +NB: in file "EMW3080B_SPI.cpp", DEBUG_LOG may have side effect due to real time issue. + + +## Validation + +- netsocket tests: https://github.com/ARMmbed/mbed-os/tree/master/connectivity/netsocket/tests/TESTS/netsocket + +- network-wifi tests: https://github.com/ARMmbed/mbed-os/tree/master/connectivity/netsocket/tests/TESTS/network/wifi + + +## Open point + + +TODO: netbuffer allocator feedback to choose appropriate memory mngt (copy or not) and fix concern regarding potential race when starting EMACinterface. + +## Limitations + +Performance of SPI limitted to 5Mhz. + + +## Firmware version & firmware update + +The recommended firmware version is V2.1.11 + +NB: with older FW version, you could get an assert: +``` +++ MbedOS Error Info ++ +Error Status: 0x80FF0100 Code: 256 Module: 255 +Error Message: Fatal Run-time error +Location: 0x801CB73 +Error Value: 0xFFFFFFFE +Current Thread: lwip_tcpip Id: 0x20006058 Entry: 0x802064D StackSize: 0x4B0 StackMem: 0x20006698 SP: 0x20006ACC +For more info, visit: https://mbed.com/s/error?error=0x8003010D&tgt=B_U585I_IOT02A +-- MbedOS Error Info -- +EMW3080BInterface : MX_WIFI_Init failed, you may have to update MXCHIP fimrware module to version 2.1.11 +``` + +### How to get FW version ? + +Enable DEBUG_INFO in EMW3080BInterface.cpp + +``` +EMW3080BInterface : Product name: MXCHIP-WIFI +EMW3080BInterface : Product ID: EMW3080B +EMW3080BInterface : FW revision: V2.1.11 +``` + + +### How to upgrade FW for B_U585I_IOT02A ? + +Latest FW binary is provided in: + +https://www.st.com/en/development-tools/x-wifi-emw3080b.html#get-software + +Start TeraTerm (115200) + +Drag and drop `EMW3080updateV2.1.11RevC.bin` into `NOD_U585AI`drive + +You should get: +``` +################### Welcome to EMW3080 firmware update utility 1.0.0 for board RevB or RevC ################### + +STM32>Configured for MXchip embedded FW ST-EMW3080B_V2.1.11_SPI.OTA.BIN 0x8000234 / 546080 bytes +STM32>Don't forget to connect EMW3080 Boot to GND thanks to switch SW2 , move it to position "0" (instead of NC) to have boot loader running ! +STM32>Push user button (Blue) to flash EMW3080 device or enter command +STM32>MCU system clock 160 MHz , Uart Baud rate 921600 , Software emulated UART bit duration 173 cycles + + +" help" print this message +" boot" Boot EMW3080 (needed before using mx command) +" mx" mx [cmd] : send command to mxchip device (can not use cmd which require ymodem protocol) +" flash" flash mxchip firmware (same as pushing blue button) +" check" check mxchip firmware +STM32> +``` + +- on switch SW2 (with 2 white switches), move BOOT one (Id 1) from NC to O position +- press blue button (User B3) + +Wait till: +``` +STM32>Flash successfull, move back switch to original position, reset the device to get back to prompt +``` + +So: +- move switch back to postion NC +- Reset diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mbed_lib.json b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mbed_lib.json new file mode 100644 index 00000000000..c6238780cd1 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mbed_lib.json @@ -0,0 +1,73 @@ +{ + "name": "emw3080b", + "config": { + "wifi-spi-interface": { + "help": "SPI interface if true / UART interface if false", + "value": "NC" + }, + "wifi-miso": { + "help": "SPI-MISO connection to external device", + "value": "NC" + }, + "wifi-mosi": { + "help": "SPI-MOSI connection to external device", + "value": "NC" + }, + "wifi-sclk": { + "help": "SPI-CLOCK connection to external device", + "value": "NC" + }, + "wifi-nss": { + "help": "SPI chip select of external device", + "value": "NC" + }, + "wifi-notify": { + "help": "EMW3080B notify from externam device", + "value": "NC" + }, + "wifi-flow": { + "help": "EMW3080B flow from externam device", + "value": "NC" + }, + "wifi-reset": { + "help": "EMW3080B reset to external device", + "value": "NC" + }, + "wifi-tx": { + "help": "EMW3080B uart tx to external device", + "value": "NC" + }, + "wifi-rx": { + "help": "EMW3080B uart rx from external device", + "value": "NC" + }, + "wifi-debug": { + "help": "Defines whether logging is on or off", + "value": false + }, + "provide-default": { + "help": "Provide default WifiInterface. [true/false]", + "value": false + } + }, + "target_overrides": { + "B_U585I_IOT02A": { + "wifi-spi-interface": true, + "wifi-miso": "PD_3", + "wifi-mosi": "PD_4", + "wifi-sclk": "PD_1", + "wifi-nss": "PB_12", + "wifi-notify": "PD_14", + "wifi-flow": "PG_15", + "wifi-reset": "PF_15", + "provide-default": true + }, + "B_U585I_IOT02A__ARDUINO_SHIELD": { + "wifi-spi-interface": false, + "wifi-tx": "ARDUINO_UNO_D1", + "wifi-rx": "ARDUINO_UNO_D0", + "wifi-reset": "ARDUINO_UNO_D13", + "provide-default": true + } + } +} diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/LICENSE.md b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/LICENSE.md new file mode 100644 index 00000000000..1af52330787 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/LICENSE.md @@ -0,0 +1,80 @@ +SLA0044 Rev5/February 2018 + +## Software license agreement + +### __ULTIMATE LIBERTY SOFTWARE LICENSE AGREEMENT__ + +BY INSTALLING, COPYING, DOWNLOADING, ACCESSING OR OTHERWISE USING THIS SOFTWARE +OR ANY PART THEREOF (AND THE RELATED DOCUMENTATION) FROM STMICROELECTRONICS +INTERNATIONAL N.V, SWISS BRANCH AND/OR ITS AFFILIATED COMPANIES +(STMICROELECTRONICS), THE RECIPIENT, ON BEHALF OF HIMSELF OR HERSELF, OR ON +BEHALF OF ANY ENTITY BY WHICH SUCH RECIPIENT IS EMPLOYED AND/OR ENGAGED AGREES +TO BE BOUND BY THIS SOFTWARE LICENSE AGREEMENT. + +Under STMicroelectronics’ intellectual property rights, the redistribution, +reproduction and use in source and binary forms of the software or any part +thereof, with or without modification, are permitted provided that the following +conditions are met: + +1. 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THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS, WHICH ARE +DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT SHALL +STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +11. EXCEPT AS EXPRESSLY PERMITTED HEREUNDER, NO LICENSE OR OTHER RIGHTS, WHETHER +EXPRESS OR IMPLIED, ARE GRANTED UNDER ANY PATENT OR OTHER INTELLECTUAL PROPERTY +RIGHTS OF STMICROELECTRONICS OR ANY THIRD PARTY. diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/checksumutils.c b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/checksumutils.c new file mode 100644 index 00000000000..4af620d084c --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/checksumutils.c @@ -0,0 +1,266 @@ +/** + ****************************************************************************** + * @file checksum_utils.c + * @author MCD Application Team + * @brief Host driver checksum utils of MXCHIP Wi-Fi component. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include "stdio.h" +/*cstat +MISRAC2012-* */ + +#include "checksumutils.h" + +#ifdef CHECKSUM_DEBUG +#define DEBUG_LOG printf +#else +#define DEBUG_LOG +#endif /* CHECKSUM_DEBUG */ + +#ifdef USE_STM32L_CRC + +/* User-defined polynomial */ +#define CRC_POLYNOMIAL_16B 0x1021 /* X^16 + X^12 + X^5 + 1, CRC-CCITT generating polynomial */ + +/* User-defined CRC init value */ +/* As the CRC is 16-bit long, the init value is 16-bit long as well */ +#define CRC_INIT_VALUE 0x0000 /* 0x5AB */ + +#endif /* USE_STM32L_CRC */ + +static uint8_t UpdateCRC8(uint8_t crcIn, uint8_t byte); + +static uint8_t UpdateCRC8(uint8_t crcIn, uint8_t byte) +{ + uint8_t crc = crcIn; + uint8_t i; + + crc ^= byte; + + for (i = 0; i < (uint8_t)8; i++) + { + if ((crc & (uint8_t)0x01) > 0u) + { + crc = (crc >> 1) ^ (uint8_t)0x8C; + } + else + { + crc >>= 1; + } + } + return crc; +} + + +void CRC8_Init(CRC8_Context *inContext) +{ + inContext->crc = 0; +} + + +void CRC8_Update(CRC8_Context *inContext, const uint8_t *inSrc, size_t inLen) +{ + const uint8_t *src = (const uint8_t *) inSrc; + const uint8_t *srcEnd = &(src[inLen]); + while (src < srcEnd) + { + inContext->crc = UpdateCRC8(inContext->crc, *src); + src++; + } +} + + +void CRC8_Final(CRC8_Context *inContext, uint8_t *outResult) +{ + *outResult = inContext->crc & 0xffu; +} + + +/*************************************CRC16******************************************/ + +#ifdef USE_STM32L_CRC +/** + * @brief CRC16 init function + */ +int8_t HW_CRC16_Init(CRC_HandleTypeDef *CrcHandle) +{ + /****************************************************************************/ + /* */ + /* CRC peripheral initialization */ + /* */ + /****************************************************************************/ + + if (NULL == CrcHandle) + { + DEBUG_LOG("*** CRC16_Init: CrcHandle null error!\n"); + return -1; + } + + CrcHandle->Instance = CRC; + + /* The default polynomial is not used. The one to be used must be defined + in CrcHandle.Init.GeneratingPolynomial */ + CrcHandle->Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; + + /* Set the value of the generating polynomial. + The one used in that example is the 16-bit long CRC generating + polynomial X^16 + X^12 + X^5 + 1 */ + CrcHandle->Init.GeneratingPolynomial = CRC_POLYNOMIAL_16B; + + /* The user-defined generating polynomial yields a 16-bit long CRC */ + CrcHandle->Init.CRCLength = CRC_POLYLENGTH_16B; + + /* The default init value is not used */ + CrcHandle->Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_DISABLE; + + /* User init value is used instead */ + CrcHandle->Init.InitValue = CRC_INIT_VALUE; + + /* The input data are inverted by word */ + CrcHandle->Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; + /* The bit reversal is done on a full word basis. + + The input stream yielded by CRC16_DATA8[] is the sequence of + bytes 0x4D, 0x3C, 0x2B, 0x1A, 0xBE, 0x71, ... + meaning that the first word written in the CRC DR register is + 0x4D3C2B1A. + + Bit reversal done by the hardware on the full word leads to the actual + CRC processing of + 0x58D43CB2. + + Similarly, the second word written in the peripheral is 0xBE71C98A, leading to + the processing of 0x51938E7D after hardware input data reversal. + + Note that when the software writes less than a word in the peripheral (to minimize the + number of write accesses for a given number of bytes), the bit-reversal operation + is carried out only on the inputted data. + Therefore, the last written data is the last byte 0x5E, processed as 0x7A + by the hardware after bit-reversal to wrap-up the CRC computation. + + This means that the field InputDataInversionMode set to CRC_INPUTDATA_INVERSION_WORD + applied to {0x4D, 0x3C, 0x2B, 0x1A, 0xBE, 0x71, 0xC9, 0x8A, 0x5E} + yields the same result as InputDataInversionMode set to CRC_INPUTDATA_INVERSION_NONE + applied to {0x58, 0xD4, 0x3C, 0xB2, 0x51, 0x93, 0x8E, 0x7D, 0x7A}. + + */ + + /* The output data are inverted */ + CrcHandle->Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; + /* Output data reversal can only be done at bit level. + The expected CRC is 0x5043 after output data reversal, meaning + that the CRC before the reversal operation is 0xC20A. */ + + /* The input data are bytes (8-bit long data) */ + CrcHandle->InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; + + /* De-initialize the CRC peripheral */ + if (HAL_CRC_DeInit(CrcHandle) != HAL_OK) + { + /* Initialization Error */ + DEBUG_LOG("*** CRC16_Init: HAL_CRC_DeInit error!\n"); + return -1; + } + + /* Then, initialize the CRC handle */ + if (HAL_CRC_Init(CrcHandle) != HAL_OK) + { + /* Initialization Error */ + DEBUG_LOG("*** CRC16_Init: HAL_CRC_Init error!\n"); + return -1; + } + + return 0; /* init success */ +} + +int8_t HW_CRC16_Update(CRC_HandleTypeDef *CrcHandle, uint8_t *input_data, uint32_t input_len, uint16_t *crc16_out) +{ + /****************************************************************************/ + /* */ + /* CRC computation */ + /* */ + /****************************************************************************/ + + /* Used for storing CRC Value */ + __IO uint32_t uwCRCValue = 0; + + if (NULL == CrcHandle) + { + DEBUG_LOG("*** CRC16_Update: CrcHandle null error!\n"); + return -1; + } + + /* The 16-bit long CRC of the 9-byte buffer is computed. After peripheral initialization, + the CRC calculator is initialized with the user-defined value that is 0x5ABE. + + The computed CRC is stored in uint32_t uwCRCValue. The 16-bit long CRC is made of + uwCRCValue 16 LSB bits. */ + + uwCRCValue = HAL_CRC_Accumulate(CrcHandle, (uint32_t *)input_data, input_len); + *crc16_out = (uint16_t)(uwCRCValue & 0x0000FFFF); + + return 0; +} + +#else /* SOFTWARE CRC16 */ + +static uint16_t UpdateCRC16(uint16_t crcIn, uint8_t byte) +{ + uint32_t crc = crcIn; + uint32_t in = (uint32_t)byte | (uint32_t)0x100; + + do + { + crc <<= 1; + in <<= 1; + if ((in & (uint32_t)0x100) > 0u) + { + ++crc; + } + if ((crc & (uint32_t)0x10000) > 0u) + { + crc ^= (uint32_t)0x1021; + } + } while (!((in & (uint32_t)0x10000) > 0u)); + return (uint16_t)(crc & (uint32_t)0xffffu); +} + +void CRC16_Init(CRC16_Context *inContext) +{ + inContext->crc = 0; +} + + +void CRC16_Update(CRC16_Context *inContext, const uint8_t *inSrc, size_t inLen) +{ + const uint8_t *src = (const uint8_t *) inSrc; + const uint8_t *srcEnd = &(src[inLen]); + while (src < srcEnd) + { + inContext->crc = UpdateCRC16(inContext->crc, *src); + src++; + } +} + + +void CRC16_Final(CRC16_Context *inContext, uint16_t *outResult) +{ + inContext->crc = UpdateCRC16(inContext->crc, 0); + inContext->crc = UpdateCRC16(inContext->crc, 0); + *outResult = inContext->crc & 0xffffu; +} + +#endif /* USE_STM32L_CRC */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/checksumutils.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/checksumutils.h new file mode 100644 index 00000000000..62fc0ad6e3c --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/checksumutils.h @@ -0,0 +1,142 @@ +/** + ****************************************************************************** + * @file checksumutils.h + * @author MCD Application Team + * @brief Header for checksumutils.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef CHECKSUM_UTILS_H +#define CHECKSUM_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include +#include +/*cstat +MISRAC2012-* */ + + +/* NOTE: MUST ENABLE STM32L HARDWARE CRC periph before use this API +#define USE_STM32L_CRC + */ + +#ifdef USE_STM32L_CRC +/*cstat -MISRAC2012-* */ +#include "stm32l4xx_hal.h" +/*cstat +MISRAC2012-* */ +#endif /* USE_STM32L_CRC */ + + +/********************* CRC8 MXOS Check ************************************** + ******************CRC-8 XMODEM x8+x5+x4+1****************************** + ****************************************************************************/ + +typedef struct +{ + uint8_t crc; +} CRC8_Context; + +/** + * @brief initialize the CRC8 Context + * + * @param inContext holds CRC8 result + * + * @retval none + */ +void CRC8_Init(CRC8_Context *inContext); + + +/** + * @brief Calculate the CRC8 result + * + * @param inContext holds CRC8 result during calculation process + * @param inSrc input data + * @param inLen length of input data + * + * @retval none + */ +void CRC8_Update(CRC8_Context *inContext, const uint8_t *inSrc, size_t inLen); + + +/** + * @brief output CRC8 result + * + * @param inContext holds CRC8 result + * @param outResutl holds CRC8 final result + * + * @retval none + */ +void CRC8_Final(CRC8_Context *inContext, uint8_t *outResult); + + +/********************* CRC16 MXOS Check ************************************** + ******************CRC-16/XMODEM x16+x12+x5+1****************************** + ******************************************************************************/ + +#ifdef USE_STM32L_CRC + +int8_t HW_CRC16_Init(CRC_HandleTypeDef *CrcHandle); +int8_t HW_CRC16_Update(CRC_HandleTypeDef *CrcHandle, uint8_t *input_data, uint32_t input_len, uint16_t *crc16_out); + +#else + +typedef struct +{ + uint16_t crc; +} CRC16_Context; + +/** + * @brief initialize the CRC16 Context + * + * @param inContext holds CRC16 result + * + * @retval none + */ +void CRC16_Init(CRC16_Context *inContext); + + +/** + * @brief Calculate the CRC16 result + * + * @param inContext holds CRC16 result during calculation process + * @param inSrc input data + * @param inLen length of input data + * + * @retval none + */ +void CRC16_Update(CRC16_Context *inContext, const uint8_t *inSrc, size_t inLen); + + +/** + * @brief output CRC16 result + * + * @param inContext holds CRC16 result + * @param outResutl holds CRC16 final result + * + * @retval none + */ +void CRC16_Final(CRC16_Context *inContext, uint16_t *outResult); + +#endif /* USE_STM32L_CRC */ + + +#ifdef __cplusplus +} +#endif + +#endif /* CHECKSUM_UTILS_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_rtos_abs.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_rtos_abs.h new file mode 100644 index 00000000000..3c68e209d7a --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_rtos_abs.h @@ -0,0 +1,44 @@ +/** + ****************************************************************************** + * @file mx_rtos_abs.h + * @author MCD Application Team + * @brief Header for mx_wifi.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_RTOS_ABS_H +#define MX_RTOS_ABS_H +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "mx_wifi_conf.h" +#include "stdlib.h" +#include "stddef.h" + + +#if MX_WIFI_USE_CMSIS_OS + +#else + + +#endif /* MX_WIFI_USE_CMSIS_OS */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* MX_RTOS_ABS_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_hci.c b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_hci.c new file mode 100644 index 00000000000..69cbab1e0f0 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_hci.c @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file mx_wifi_hci.c + * @author MCD Application Team + * @brief Host driver HCI protocol of MXCHIP Wi-Fi component. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include "stdlib.h" +/*cstat +MISRAC2012-* */ +#include + +#include "mx_wifi_conf.h" +#include "mx_wifi_hci.h" +#include "mx_wifi_slip.h" +#include "checksumutils.h" + +#ifdef MX_WIFI_HCI_DEBUG +#define DEBUG_LOG(M, ...) printf((M), ##__VA_ARGS__) +#else +#define DEBUG_LOG(M, ...) +#endif /* MX_WIFI_HCI_DEBUG */ + +#define DEBUG_ERROR(M, ...) printf((M), ##__VA_ARGS__) + +/* Private defines -----------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ + +/* HCI low level function */ +static hci_send_func_t tcl_output = NULL; +/* HCI recv data queue */ +static FIFO_DECLARE(hci_pkt_fifo); + +static bool mx_wifi_hci_pkt_verify(uint8_t *data, uint16_t len); + + +/* Private functions ---------------------------------------------------------*/ +static bool mx_wifi_hci_pkt_verify(uint8_t *data, uint16_t len) +{ + /* here each uart slip frame or spi frame as a hci packet */ + return true; +} + + +/* Global functions ----------------------------------------------------------*/ +int32_t mx_wifi_hci_init(hci_send_func_t low_level_send) +{ + int32_t ret = 0; + + tcl_output = low_level_send; + + if (0 == ret) + { + FIFO_INIT(hci_pkt_fifo, MX_WIFI_MAX_RX_BUFFER_COUNT); + } + + return ret; +} + +int32_t mx_wifi_hci_deinit(void) +{ + FIFO_DEINIT(hci_pkt_fifo); + return 0; +} + +int32_t mx_wifi_hci_send(uint8_t *payload, uint16_t len) +{ + int32_t ret = 0; + uint16_t sent = 0; + +#if MX_WIFI_USE_SPI + sent = tcl_output(payload, len); + if (len != sent) + { + DEBUG_ERROR("tcl_output(spi) error sent=%d !\n", sent); + ret = -1; + } + else + { + ret = 0; + } +#else + uint8_t *slip_frame = NULL; + uint16_t slip_len = 0; + + slip_frame = slip_transfer(payload, len, &slip_len); + if ((NULL != slip_frame) && (slip_len > 0)) + { + sent = tcl_output(slip_frame, slip_len); + if (slip_len == sent) + { + ret = 0; + } + else + { + DEBUG_ERROR("tcl_output(uart) error sent=%d !\r\n", sent); + ret = -1; + } + + MX_WIFI_FREE(slip_frame); + slip_frame = NULL; + } + else + { + DEBUG_ERROR("create slip frame error!\r\n"); + ret = -2; + } +#endif /* MX_WIFI_USE_SPI */ + + return ret; +} + +void process_txrx_poll(uint32_t timeout); + +mx_buf_t *mx_wifi_hci_recv(uint32_t timeout) +{ + mx_buf_t *nbuf; + nbuf = (mx_buf_t*) FIFO_POP(hci_pkt_fifo, timeout, process_txrx_poll); + if (nbuf != NULL) + { + MX_STAT(out_fifo); + } + return nbuf; +} + +void mx_wifi_hci_free(mx_buf_t *nbuf) +{ + if (NULL != nbuf) + { + (void) MX_NET_BUFFER_FREE(nbuf); + } +} + + +/** + * @brief LOW LEVEL INTERFACE + */ +void mx_wifi_hci_input(mx_buf_t *netbuf) +{ + if (NULL != netbuf) + { + uint8_t *data = MX_NET_BUFFER_PAYLOAD(netbuf); + uint32_t len = MX_NET_BUFFER_GET_PAYLOAD_SIZE(netbuf); + + if ((NULL != data) && (len > 0)) + { + if (mx_wifi_hci_pkt_verify(data, len)) + { + if (FIFO_OK != FIFO_PUSH(hci_pkt_fifo, netbuf, WAIT_FOREVER, NULL)) + { + DEBUG_ERROR("push tcl input queue err!\n"); + MX_NET_BUFFER_FREE(netbuf); + } + else + { + DEBUG_LOG("\nhci input len %"PRIu32" nbuf : %p\n", len, netbuf); + MX_STAT(in_fifo); + } + } + else + { + DEBUG_LOG("input bad tcl pkt!\n"); + MX_NET_BUFFER_FREE(netbuf); + } + } + } +} + diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_hci.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_hci.h new file mode 100644 index 00000000000..1744587f4ed --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_hci.h @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file mx_wifi_hci.h + * @author MCD Application Team + * @brief Header for mx_wifi_hci.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_HCI_H +#define MX_WIFI_HCI_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include "stdint.h" +#include "string.h" +#include "stdbool.h" +#include "stdio.h" +/*cstat +MISRAC2012-* */ + +#include "mx_wifi_ipc.h" + +/** + * @brief CONFIGURATIONS + */ +/* #define MX_WIFI_HCI_DEBUG */ + +/** + * @brief HCI PACKET + */ +#define MX_WIFI_HCI_DATA_SIZE (MIPC_PKT_MAX_SIZE) + +/** + * @brief PROTOTYPES + */ +typedef struct _hci_pkt_s +{ + uint16_t len; + uint8_t *data; +} hci_pkt_t; + +typedef uint16_t (*hci_send_func_t)(uint8_t *data, uint16_t size); + +/** + * @brief API + */ +int32_t mx_wifi_hci_init(hci_send_func_t low_level_send); +int32_t mx_wifi_hci_send(uint8_t *payload, uint16_t len); +mx_buf_t *mx_wifi_hci_recv(uint32_t timeout); +void mx_wifi_hci_free(mx_buf_t *nbuf); +int32_t mx_wifi_hci_deinit(void); + +/** + * @brief LOW LEVEL INTERFACE + */ +void mx_wifi_hci_input(mx_buf_t *netbuf); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* MX_WIFI_HCI_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_ipc.c b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_ipc.c new file mode 100644 index 00000000000..03841475aa4 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_ipc.c @@ -0,0 +1,421 @@ +/** + ****************************************************************************** + * @file mx_wifi_ipc.c + * @author MCD Application Team + * @brief Host driver IPC protocol of MXCHIP Wi-Fi component. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include +#include +/*cstat +MISRAC2012-* */ + +#include + +#include "mx_wifi.h" +#include "mx_wifi_ipc.h" +#include "mx_wifi_hci.h" + + +#ifdef MX_WIFI_IPC_DEBUG +#define DEBUG_LOG(M, ...) printf((M), ##__VA_ARGS__) +#define DEBUG_ERROR(M, ...) printf((M), ##__VA_ARGS__) +#else +#define DEBUG_LOG(M, ...) +#define DEBUG_ERROR(M, ...) printf((M), ##__VA_ARGS__) +#endif /* MX_WIFI_IPC_DEBUG */ + +#define MIPC_REQ_LIST_SIZE (64) + +/** + * @brief IPC API event handlers + */ +typedef void (*event_callback_t)(mx_buf_t *mx_buff); +typedef struct _event_item_s +{ + uint16_t api_id; + void (*callback)(mx_buf_t *mx_buff); +} event_item_t; + +event_item_t event_table[3] = +{ + /* system */ + {MIPC_API_SYS_REBOOT_EVENT, mapi_reboot_event_callback}, + /* wifi */ + {MIPC_API_WIFI_STATUS_EVENT, mapi_wifi_status_event_callback}, + {MIPC_API_WIFI_BYPASS_INPUT_EVENT, mapi_wifi_netlink_input_callback}, +}; + +/** + * @brief IPC API request list + */ +typedef struct _mipc_req_s +{ + uint32_t req_id; + SEM_DECLARE(resp_flag); + uint16_t *rbuffer_size; /* in/out*/ + uint8_t *rbuffer; +} mipc_req_t; + + +static mipc_req_t pending_request; + +static uint32_t get_new_req_id(void); +static uint32_t mpic_get_req_id(uint8_t *buffer_in); +static uint16_t mpic_get_api_id(uint8_t *buffer_in); +static uint32_t mipc_event(mx_buf_t *netbuf); + +/* unique sequence number */ +static uint32_t get_new_req_id(void) +{ + static uint32_t id = 1; + return id++; +} + +static uint32_t mpic_get_req_id(uint8_t *buffer_in) +{ + return *((uint32_t *) & (buffer_in[MIPC_PKT_REQ_ID_OFFSET])); +} + +static uint16_t mpic_get_api_id(uint8_t *buffer_in) +{ + return *((uint16_t *) & (buffer_in[MIPC_PKT_API_ID_OFFSET])); +} + +static uint32_t mipc_event(mx_buf_t *netbuf) +{ + uint32_t req_id = MIPC_REQ_ID_NONE; + uint16_t api_id = MIPC_API_ID_NONE; + uint32_t i; + void (*callback)(mx_buf_t *mx_buff); + + if (NULL != netbuf) + { + uint8_t *buffer_in = MX_NET_BUFFER_PAYLOAD(netbuf); + uint32_t buffer_size = MX_NET_BUFFER_GET_PAYLOAD_SIZE(netbuf); + + if ((NULL != buffer_in) && (buffer_size >= MIPC_PKT_MIN_SIZE)) + { + req_id = mpic_get_req_id(buffer_in); + api_id = mpic_get_api_id(buffer_in); + DEBUG_LOG("req_id: 0x%08"PRIx32", api_id: 0x%04x\n", req_id, api_id); + if ((0 == (api_id & MIPC_API_EVENT_BASE)) && (MIPC_REQ_ID_NONE != req_id)) + { + /* cmd response must match pending req id */ + MX_ASSERT(pending_request.req_id == req_id); + { + + /* return params */ + if ((pending_request.rbuffer_size != NULL) && (*(pending_request.rbuffer_size) > 0) + && (NULL != pending_request.rbuffer)) + { + *(pending_request.rbuffer_size) = *(pending_request.rbuffer_size) < (buffer_size - MIPC_PKT_MIN_SIZE) ? \ + *(pending_request.rbuffer_size) : (buffer_size - MIPC_PKT_MIN_SIZE); + memcpy(pending_request.rbuffer, buffer_in + MIPC_PKT_PARAMS_OFFSET, *(pending_request.rbuffer_size)); + } + pending_request.req_id = 0xFFFFFFFF; + if (SEM_OK != SEM_SIGNAL(pending_request.resp_flag)) + { + DEBUG_ERROR("Failed to signal command response\n"); + while (1); + } + MX_STAT(cmd_get_answer); + mx_wifi_hci_free(netbuf); + } + } + else /* event callback */ + { + for (i = 0; i < sizeof(event_table) / sizeof(event_item_t); i++) + { + if (event_table[i].api_id == api_id) + { + callback = event_table[i].callback; + if (NULL != callback) + { + DEBUG_LOG("callback with %p\n", buffer_in); + callback(netbuf); + break; + } + } + } + if (i == sizeof(event_table) / sizeof(event_item_t)) + { + DEBUG_ERROR("unknown event: 0x%04x !\n", api_id); + mx_wifi_hci_free(netbuf); + } + } + } + else + { + DEBUG_LOG("unknown buffer content\n"); + mx_wifi_hci_free(netbuf); + } + } + return req_id; +} + +/******************************************************************************* + * IPC API implementations for mx_wifi over HCI + ******************************************************************************/ + +/** + * @brief mxchip ipc protocol init + * @param ipc_send low level send function + * @return int32_t status code + */ +int32_t mipc_init(mipc_send_func_t ipc_send) +{ + int32_t ret; + + pending_request.req_id = 0xFFFFFFFF; + SEM_INIT(pending_request.resp_flag, 1); + ret = mx_wifi_hci_init(ipc_send); + + return ret; +} + + +int32_t mipc_deinit(void) +{ + int32_t ret; + SEM_DEINIT(pending_request.resp_flag); + ret = mx_wifi_hci_deinit(); + + return ret; +} + + +int32_t mipc_request(uint16_t api_id, uint8_t *cparams, uint16_t cparams_size, + uint8_t *rbuffer, uint16_t *rbuffer_size, uint32_t timeout_ms) +{ + int32_t ret = MIPC_CODE_ERROR; + + uint8_t *cbuf; + uint8_t *pos; + uint16_t cbuf_size; + uint32_t req_id; + bool copy_buffer = true; + + LOCK(wifi_obj_get()->lockcmd); + if (cparams_size <= MX_WIFI_IPC_PAYLOAD_SIZE) + { + /* create cmd data */ + cbuf_size = sizeof(req_id) + sizeof(api_id) + cparams_size; + +#if MX_WIFI_TX_BUFFER_NO_COPY + if (api_id == MIPC_API_WIFI_BYPASS_OUT_CMD) + { + cbuf = cparams - sizeof(req_id) - sizeof(api_id); + copy_buffer = false; + } + else +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + { + cbuf = (uint8_t *)MX_WIFI_MALLOC(cbuf_size); + } + + if (NULL != cbuf) + { + /* get an uniq identifier */ + req_id = get_new_req_id(); + /* copy the protocol parameter to the head part of the buffer */ + pos = cbuf; + memcpy(pos, &req_id, sizeof(req_id)); + pos += sizeof(req_id); + memcpy(pos, &api_id, sizeof(api_id)); + pos += sizeof(api_id); + + if ((true == copy_buffer) && (cparams_size > 0)) + { + memcpy(pos, cparams, cparams_size); + } + + /* a single pending request due to LOCK usage on command */ + if (pending_request.req_id != 0xFFFFFFFF) + { + DEBUG_LOG("Error req_id must be 0xffffffff here %"PRIu32"\n", pending_request.req_id); + while (1); + } + pending_request.req_id = req_id; + pending_request.rbuffer = rbuffer; + pending_request.rbuffer_size = rbuffer_size; + /* static int iter=0; */ + /* printf("%d push %d\n",iter++,cbuf_size); */ + + /* send the command */ + DEBUG_LOG("cmd %"PRIu32"\n", req_id); + ret = mx_wifi_hci_send(cbuf, cbuf_size); + if (ret == 0) + { + /* wait for command answer */ + if (SEM_WAIT(pending_request.resp_flag, timeout_ms, mipc_poll) != SEM_OK) + { + DEBUG_ERROR("Error: command 0x%04x timeout(%"PRIu32" ms) waiting answer %"PRIu32"\n", + api_id, timeout_ms, pending_request.req_id); + pending_request.req_id = 0xFFFFFFFF; + ret = MIPC_CODE_ERROR; + } + + } + else + { + DEBUG_ERROR("Failed to send command to Hci\n"); + while (1); + } + DEBUG_LOG("done %"PRIu32"\n", req_id); + if (true == copy_buffer) + { + MX_WIFI_FREE(cbuf); + } + } + } + UNLOCK(wifi_obj_get()->lockcmd); + + return ret; +} + + +/** + * @brief mipc poll + * @param timeout_ms timeout in ms + * @return int32_t 0 if success, otherwise failed + */ +void mipc_poll(uint32_t timeout) +{ + mx_buf_t *nbuf; + + /* process the received data inside RX buffer */ + nbuf = mx_wifi_hci_recv(timeout); + if (NULL != nbuf) + { + uint32_t len = MX_NET_BUFFER_GET_PAYLOAD_SIZE(nbuf); + DEBUG_LOG("\nhci recv len %"PRIu32"\n", len); + if (len > 0) + { + mipc_event(nbuf); + } + else + { + MX_NET_BUFFER_FREE(nbuf); + } + } +} + + +int32_t mipc_echo(uint8_t *in, uint16_t in_len, uint8_t *out, uint16_t *out_len, + uint32_t timeout) +{ + int32_t ret = MIPC_CODE_ERROR; + + if ((NULL != in) && (NULL != out) && (NULL != out_len)) + { + ret = mipc_request(MIPC_API_SYS_ECHO_CMD, in, in_len, out, out_len, timeout); + if (MIPC_CODE_SUCCESS == ret) + { + ret = MIPC_CODE_SUCCESS; + } + else + { + *out_len = 0; + } + } + return ret; +} + +/******************************************************************************* + * IPC API event callbacks + ******************************************************************************/ + +/* system */ + +void mapi_reboot_event_callback(mx_buf_t *buff) +{ + if (buff != NULL) + { + mx_wifi_hci_free(buff); + } + DEBUG_LOG("\nEVENT: reboot done.\n"); +} + +/* wifi */ + +void mapi_wifi_status_event_callback(mx_buf_t *nbuf) +{ + uint8_t cate; + mwifi_status_t status; + mx_wifi_status_callback_t status_cb = NULL; + void *cb_args = NULL; + + if (NULL != nbuf) + { + uint8_t *payload = MX_NET_BUFFER_PAYLOAD(nbuf); + status = *((mwifi_status_t *)(payload + MIPC_PKT_PARAMS_OFFSET)); + DEBUG_LOG("\nEVENT: wifi status: %02x\r\n", status); + mx_wifi_hci_free(nbuf); + + switch (status) + { + case MWIFI_EVENT_STA_UP: + case MWIFI_EVENT_STA_DOWN: + case MWIFI_EVENT_STA_GOT_IP: + cate = MC_STATION; + status_cb = wifi_obj_get()->Runtime.status_cb[0]; + cb_args = wifi_obj_get()->Runtime.callback_arg[0]; + break; + + case MWIFI_EVENT_AP_UP: + case MWIFI_EVENT_AP_DOWN: + cate = MC_SOFTAP; + status_cb = wifi_obj_get()->Runtime.status_cb[0]; + cb_args = wifi_obj_get()->Runtime.callback_arg[0]; + break; + + default: + cate = MC_SOFTAP; + MX_ASSERT(false); + break; + } + + if (NULL != status_cb) + { + status_cb(cate, status, cb_args); + } + } +} + +void mapi_wifi_netlink_input_callback(mx_buf_t *nbuf) +{ + wifi_bypass_in_rparams_t *in_rprarams; + /* DEBUG_LOG("IP stack in %d\n",len); */ + if (NULL != nbuf) + { + uint8_t *buffer_in = MX_NET_BUFFER_PAYLOAD(nbuf); + MX_STAT(callback); + + in_rprarams = (wifi_bypass_in_rparams_t *)(buffer_in + MIPC_PKT_PARAMS_OFFSET); + MX_NET_BUFFER_HIDE_HEADER(nbuf, MIPC_PKT_PARAMS_OFFSET + sizeof(wifi_bypass_in_rparams_t)); + if ((NULL != wifi_obj_get()->Runtime.netlink_input_cb) && \ + (in_rprarams->tot_len > 0)) + { + wifi_obj_get()->Runtime.netlink_input_cb(nbuf, + wifi_obj_get()->Runtime.netlink_user_args); + } + else + { + MX_NET_BUFFER_FREE(nbuf); + } + } +} diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_ipc.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_ipc.h new file mode 100644 index 00000000000..310101a2c38 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_ipc.h @@ -0,0 +1,657 @@ +/** + ****************************************************************************** + * @file mx_wifi_ipc.h + * @author MCD Application Team + * @brief Header for mx_wifi_ipc.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_IPC_H +#define MX_WIFI_IPC_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include +#include +#include +#include +/*cstat +MISRAC2012-* */ + +#include "mx_wifi.h" + +/* Exported Constants --------------------------------------------------------*/ +/* #define MX_WIFI_IPC_DEBUG */ +#define MX_API_VERSION ("2.0.0") + +/** + * @brief IPC error code + */ +#define MIPC_CODE_SUCCESS (0) +#define MIPC_CODE_ERROR (-1) +#define MIPC_CODE_TIMEOUT (-2) +#define MIPC_CODE_NO_MEMORY (-3) + +/** + * @brief IPC packet + */ +/* + * |--------+--------+--------------------| + * | req_id | api_id | args (...) | + * |--------+--------+--------------------| + * | 4Bytes | 2Btyes | nBytes | + * |--------+--------+--------------------| + */ +#define MIPC_PKT_REQ_ID_OFFSET (0) +#define MIPC_PKT_REQ_ID_SIZE (4) +#define MIPC_PKT_API_ID_OFFSET (MIPC_PKT_REQ_ID_OFFSET + MIPC_PKT_REQ_ID_SIZE) +#define MIPC_PKT_API_ID_SIZE (2) +#define MIPC_PKT_PARAMS_OFFSET (MIPC_PKT_API_ID_OFFSET + MIPC_PKT_API_ID_SIZE) +#define MIPC_HEADER_SIZE (MIPC_PKT_REQ_ID_SIZE + MIPC_PKT_API_ID_SIZE) +#define MIPC_PKT_MIN_SIZE (MIPC_HEADER_SIZE) +#define MIPC_PKT_MAX_SIZE (MIPC_HEADER_SIZE + MX_WIFI_IPC_PAYLOAD_SIZE) + +/** + * @brief IPC api id + */ +#define MIPC_REQ_ID_NONE (0x00000000) +#define MIPC_API_ID_NONE (0x0000) +#define MIPC_API_CMD_BASE (MIPC_API_ID_NONE) +#define MIPC_API_EVENT_BASE (0x8000) + +/** + * API CMD + */ +/* system */ +#define MIPC_API_SYS_CMD_BASE (MIPC_API_CMD_BASE + 0x0000) +#define MIPC_API_SYS_ECHO_CMD (MIPC_API_SYS_CMD_BASE + 0x0001) +#define MIPC_API_SYS_REBOOT_CMD (MIPC_API_SYS_CMD_BASE + 0x0002) +#define MIPC_API_SYS_VERSION_CMD (MIPC_API_SYS_CMD_BASE + 0x0003) +#define MIPC_API_SYS_RESET_CMD (MIPC_API_SYS_CMD_BASE + 0x0004) + +/* wifi */ +#define MIPC_API_WIFI_CMD_BASE (MIPC_API_CMD_BASE + 0x0100) +#define MIPC_API_WIFI_GET_MAC_CMD (MIPC_API_WIFI_CMD_BASE + 0x0001) +#define MIPC_API_WIFI_SCAN_CMD (MIPC_API_WIFI_CMD_BASE + 0x0002) +#define MIPC_API_WIFI_CONNECT_CMD (MIPC_API_WIFI_CMD_BASE + 0x0003) +#define MIPC_API_WIFI_DISCONNECT_CMD (MIPC_API_WIFI_CMD_BASE + 0x0004) +#define MIPC_API_WIFI_SOFTAP_START_CMD (MIPC_API_WIFI_CMD_BASE + 0x0005) +#define MIPC_API_WIFI_SOFTAP_STOP_CMD (MIPC_API_WIFI_CMD_BASE + 0x0006) +#define MIPC_API_WIFI_GET_IP_CMD (MIPC_API_WIFI_CMD_BASE + 0x0007) +#define MIPC_API_WIFI_GET_LINKINFO_CMD (MIPC_API_WIFI_CMD_BASE + 0x0008) +#define MIPC_API_WIFI_PS_ON_CMD (MIPC_API_WIFI_CMD_BASE + 0x0009) +#define MIPC_API_WIFI_PS_OFF_CMD (MIPC_API_WIFI_CMD_BASE + 0x000a) +#define MIPC_API_WIFI_PING_CMD (MIPC_API_WIFI_CMD_BASE + 0x000b) +#define MIPC_API_WIFI_BYPASS_SET_CMD (MIPC_API_WIFI_CMD_BASE + 0x000c) +#define MIPC_API_WIFI_BYPASS_GET_CMD (MIPC_API_WIFI_CMD_BASE + 0x000d) +#define MIPC_API_WIFI_BYPASS_OUT_CMD (MIPC_API_WIFI_CMD_BASE + 0x000e) + +/* socket */ +#define MIPC_API_SOCKET_CMD_BASE (MIPC_API_CMD_BASE + 0x0200) +#define MIPC_API_SOCKET_CREATE_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0001) +#define MIPC_API_SOCKET_CONNECT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0002) +#define MIPC_API_SOCKET_SEND_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0003) +#define MIPC_API_SOCKET_SENDTO_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0004) +#define MIPC_API_SOCKET_RECV_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0005) +#define MIPC_API_SOCKET_RECVFROM_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0006) +#define MIPC_API_SOCKET_SHUTDOWN_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0007) +#define MIPC_API_SOCKET_CLOSE_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0008) +#define MIPC_API_SOCKET_GETSOCKOPT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0009) +#define MIPC_API_SOCKET_SETSOCKOPT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x000a) +#define MIPC_API_SOCKET_BIND_CMD (MIPC_API_SOCKET_CMD_BASE + 0x000b) +#define MIPC_API_SOCKET_LISTEN_CMD (MIPC_API_SOCKET_CMD_BASE + 0x000c) +#define MIPC_API_SOCKET_ACCEPT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x000d) +#define MIPC_API_SOCKET_SELECT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x000e) +#define MIPC_API_SOCKET_GETSOCKNAME_CMD (MIPC_API_SOCKET_CMD_BASE + 0x000f) +#define MIPC_API_SOCKET_GETPEERNAME_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0010) +#define MIPC_API_SOCKET_GETHOSTBYNAME_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0011) + +/* TLS cmd */ +#define MIPC_API_TLS_SET_VER_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0081) +#define MIPC_API_TLS_SET_CLIENT_CERT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0082) +#define MIPC_API_TLS_SET_SERVER_CERT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0083) +#define MIPC_API_TLS_ACCEPT_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0084) +#define MIPC_API_TLS_CONNECT_SNI_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0085) +#define MIPC_API_TLS_SEND_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0086) +#define MIPC_API_TLS_RECV_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0087) +#define MIPC_API_TLS_CLOSE_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0088) +#define MIPC_API_TLS_SET_NONBLOCK_CMD (MIPC_API_SOCKET_CMD_BASE + 0x0089) + +#define MIPC_API_MDNS_CMD_BASE (MIPC_API_CMD_BASE + 0x0300) +#define MIPC_API_MDNS_START_CMD (MIPC_API_MDNS_CMD_BASE + 0x0001) +#define MIPC_API_MDNS_STOP_CMD (MIPC_API_MDNS_CMD_BASE + 0x0002) +#define MIPC_API_MDNS_ANNOUNCE_CMD (MIPC_API_MDNS_CMD_BASE + 0x0003) +#define MIPC_API_MDNS_DEANNOUNCE_CMD (MIPC_API_MDNS_CMD_BASE + 0x0004) +#define MIPC_API_MDNS_DEANNOUNCE_ALL_CMD (MIPC_API_MDNS_CMD_BASE + 0x0005) +#define MIPC_API_MDNS_IFACE_STATE_CHANGE_CMD (MIPC_API_MDNS_CMD_BASE + 0x0006) +#define MIPC_API_MDNS_SET_HOSTNAME_CMD (MIPC_API_MDNS_CMD_BASE + 0x0007) +#define MIPC_API_MDNS_SET_TXT_REC_CMD (MIPC_API_MDNS_CMD_BASE + 0x0008) +/** + * API EVENT + */ +/* system */ +#define MIPC_API_SYS_EVENT_BASE (MIPC_API_EVENT_BASE + 0x0000) +#define MIPC_API_SYS_REBOOT_EVENT (MIPC_API_SYS_EVENT_BASE + 0x0001) + +/* wifi */ +#define MIPC_API_WIFI_EVENT_BASE (MIPC_API_EVENT_BASE + 0x0100) +#define MIPC_API_WIFI_STATUS_EVENT (MIPC_API_WIFI_EVENT_BASE + 0x0001) +#define MIPC_API_WIFI_BYPASS_INPUT_EVENT (MIPC_API_WIFI_EVENT_BASE + 0x0002) + +/* Exported macro-------------------------------------------------------------*/ + +/* Exported typedef ----------------------------------------------------------*/ +typedef uint16_t (*mipc_send_func_t)(uint8_t *data, uint16_t size); + +/* Exported functions --------------------------------------------------------*/ + +/* MX_IPC */ +int32_t mipc_init(mipc_send_func_t ipc_send); +int32_t mipc_deinit(void); + +/* ipc api request */ +int32_t mipc_request(uint16_t api_id, uint8_t *cparams, uint16_t cparams_size, + uint8_t *rbuffer, uint16_t *rbuffer_size, uint32_t timeout_ms); + +/* ipc handle response/event */ +void mipc_poll(uint32_t timeout); + +/* ipc echo test */ +int32_t mipc_echo(uint8_t *in, uint16_t in_len, uint8_t *out, uint16_t *out_len, + uint32_t timeout); + +/* Module API event callbacks ------------------------------------------------*/ +/* system */ +void mapi_reboot_event_callback(mx_buf_t *buff); + +/* wifi */ +#pragma pack(1) +typedef struct _wifi_scan_cparams_s +{ + int8_t ssid[33]; /* 32 + 1 '\0' string end */ +} wifi_scan_cparams_t; + +typedef struct _wifi_scan_rparams_s +{ + uint8_t num; + mwifi_ap_info_t ap[1]; /* ap info array memory */ +} wifi_scan_rparams_t; + +typedef struct +{ + uint8_t bssid[6]; /**< bssid of access-point */ + uint8_t channel; /**< channel of access-point */ + mwifi_security_t security; /**< security of access-point */ +} mwifi_connect_attr_t; + +typedef struct _wifi_connect_cparams_s +{ + int8_t ssid[33]; /* 32 + 1 '\0' string end */ + int8_t key[65]; /* 64 + 1 '\0' string end */ + int32_t key_len; + uint8_t use_attr; + uint8_t use_ip; + mwifi_connect_attr_t attr; + mwifi_ip_attr_t ip; +} wifi_connect_cparams_t; + +typedef struct +{ + int32_t is_connected; /**< The link to wlan is established or not, 0: disconnected, 1: connected. */ + int32_t rssi; /**< Signal strength of the current connected AP */ + int8_t ssid[33]; /**< SSID of the current connected wlan */ + uint8_t bssid[6]; /**< BSSID of the current connected wlan */ + int8_t key[65]; /**< The passphrase/PSK of the connected AP */ + int32_t channel; /**< Channel of the current connected wlan */ + mwifi_security_t security; /**< security of access-point */ +} mwifi_link_info_t; + +typedef struct _wifi_get_linkinof_rparams_s +{ + int32_t status; + mwifi_link_info_t info; +} wifi_get_linkinof_rparams_t; + +typedef struct _wifi_get_ip_rparams_s +{ + int32_t status; + mwifi_ip_attr_t ip; +} wifi_get_ip_rparams_t; + +typedef struct _wifi_softap_start_cparams_s +{ + int8_t ssid[32]; + int8_t key[64]; + int32_t channel; + mwifi_ip_attr_t ip; +} wifi_softap_start_cparams_t; + +/* ping */ +typedef struct wifi_ping_cparams_s +{ + char hostname[255]; + int32_t count; + int32_t delay_ms; +} wifi_ping_cparams_t; + +typedef struct wifi_ping_rparams_s +{ + int32_t num; + int32_t delay_ms[1]; +} wifi_ping_rparams_t; + +typedef struct wifi_bypass_set_cparams_s +{ + int32_t mode; +} wifi_bypass_set_cparams_t; + +typedef struct wifi_bypass_get_rparams_s +{ + int32_t mode; +} wifi_bypass_get_rparams_t; + +typedef struct wifi_bypass_out_cparams_s +{ + int32_t idx; + uint8_t useless[16]; + uint16_t data_len; +} wifi_bypass_out_cparams_t; + +typedef struct wifi_bypass_in_rparams_s +{ + int32_t idx; + uint8_t useless[16]; + uint16_t tot_len; +} wifi_bypass_in_rparams_t; +#pragma pack() + +void mapi_wifi_status_event_callback(mx_buf_t *nbuf); +void mapi_wifi_netlink_input_callback(mx_buf_t *nbuf); + + +#if MX_WIFI_NETWORK_BYPASS_MODE == 0 +/* socket */ +#pragma pack(1) +/* create */ +typedef struct _socket_create_cparams_s +{ + int32_t domain; + int32_t type; + int32_t protocol; +} socket_create_cparams_t; + +typedef struct _socket_create_rparams_s +{ + int32_t fd; +} socket_create_rparams_t; + +/* setsockopt */ +typedef struct _socket_setsockopt_cparams_s +{ + int32_t socket; + int32_t level; + int32_t optname; + socklen_t optlen; + uint8_t optval[16]; +} socket_setsockopt_cparams_t; + +typedef struct _socket_setsockopt_rparams_s +{ + int32_t status; +} socket_setsockopt_rparams_t; + +/* getsockopt */ +typedef struct _socket_getsockopt_cparams_s +{ + int32_t socket; + int32_t level; + int32_t optname; +} socket_getsockopt_cparams_t; + +typedef struct _socket_getsockopt_rparams_s +{ + int32_t status; + socklen_t optlen; + uint8_t optval[16]; +} socket_getsockopt_rparams_t; + +/* bind */ +typedef struct _socket_bind_cparams_s +{ + int32_t socket; + struct sockaddr addr; + socklen_t length; +} socket_bind_cparams_t; + +typedef struct _socket_bind_rparams_s +{ + int32_t status; +} socket_bind_rparams_t; + +/* connect */ +typedef struct _socket_connect_cparams_s +{ + int32_t socket; + struct sockaddr addr; + socklen_t length; +} socket_connect_cparams_t; + +typedef struct _socket_connect_rparams_s +{ + int32_t status; +} socket_connect_rparams_t; + +/* shutdown */ +typedef struct _socket_shutdown_cparams_s +{ + int32_t filedes; + int32_t how; +} socket_shutdown_cparams_t; + +typedef struct _socket_shutdown_rparams_s +{ + int32_t status; +} socket_shutdown_rparams_t; + +/* close */ +typedef struct _socket_close_cparams_s +{ + int32_t filedes; +} socket_close_cparams_t; + +typedef struct _socket_close_rparams_s +{ + int32_t status; +} socket_close_rparams_t; + +/* send */ +typedef struct _socket_send_cparams_s +{ + int32_t socket; + size_t size; + int32_t flags; + uint8_t buffer[1]; +} socket_send_cparams_t; + +typedef struct _socket_send_rparams_s +{ + int32_t sent; +} socket_send_rparams_t; + +/* sendto */ +typedef struct _socket_sendto_cparams_s +{ + int32_t socket; + size_t size; + int32_t flags; + struct sockaddr addr; + socklen_t length; + uint8_t buffer[1]; +} socket_sendto_cparams_t; + +typedef struct _socket_sendto_rparams_s +{ + int32_t sent; +} socket_sendto_rparams_t; + +/* recv */ +typedef struct _socket_recv_cparams_s +{ + int32_t socket; + size_t size; + int32_t flags; +} socket_recv_cparams_t; + +typedef struct _socket_recv_rparams_s +{ + int32_t received; + uint8_t buffer[1]; +} socket_recv_rparams_t; + +/* recvfrom */ +typedef struct _socket_recvfrom_cparams_s +{ + int32_t socket; + size_t size; + int32_t flags; +} socket_recvfrom_cparams_t; + +typedef struct _socket_recvfrom_rparams_s +{ + int32_t received; + struct sockaddr addr; + socklen_t length; + uint8_t buffer[1]; +} socket_recvfrom_rparams_t; + +/* gethostbyname */ +typedef struct _socket_gethostbyname_cparams_s +{ + char name[253]; +} socket_gethostbyname_cparams_t; + +typedef struct _socket_gethostbyname_rparams_s +{ + int32_t status; + uint32_t s_addr; +} socket_gethostbyname_rparams_t; + +/* getpeername */ +typedef struct _socket_getpeername_cparams_s +{ + int32_t s; +} socket_getpeername_cparams_t; + +typedef struct _socket_getpeername_rparams_s +{ + int32_t status; + struct sockaddr name; + socklen_t namelen; +} socket_getpeername_rparams_t; + +/* getsockname */ +typedef struct _socket_getsockname_cparams_s +{ + int32_t s; +} socket_getsockname_cparams_t; + +typedef struct _socket_getsockname_rparams_s +{ + int32_t status; + struct sockaddr name; + socklen_t namelen; +} socket_getsockname_rparams_t; + +/* listen */ +typedef struct _socket_listen_cparams_s +{ + int32_t socket; + int32_t n; +} socket_listen_cparams_t; + +typedef struct _socket_listen_rparams_s +{ + int32_t status; +} socket_listen_rparams_t; + +/* accept */ +typedef struct _socket_accept_cparams_s +{ + int32_t socket; +} socket_accept_cparams_t; + +typedef struct _socket_accept_rparams_s +{ + int32_t socket; + struct sockaddr addr; + socklen_t length; +} socket_accept_rparams_t; + +/* tls */ +/* tls set ver */ +typedef struct _tls_set_ver_cparams_s +{ + mtls_ver_t version; +} tls_set_ver_cparams_t; + +typedef struct _tls_set_ver_rparams_s +{ + int32_t ret; +} tls_set_ver_rparams_t; + +/* tls set client cert */ +typedef struct _tls_set_client_cert_cparams_s +{ + uint16_t cert_pem_size; + uint16_t private_key_pem_size; + char cert_data[1]; /* cert_pem + private_key_pem */ +} tls_set_client_cert_cparams_t; + +typedef struct _tls_set_client_cert_rparams_s +{ + int32_t ret; +} tls_set_client_cert_rparams_t; + +/* tls set server cert */ +typedef struct _tls_set_server_cert_cparams_s +{ + uint16_t cert_pem_size; + uint16_t private_key_pem_size; + uint16_t verify_ca_size; + char cert_data[1]; /* cert_pem + private_key_pem + verify_ca */ +} tls_set_server_cert_cparams_t; + +typedef struct _tls_set_server_cert_rparams_s +{ + int32_t ret; +} tls_set_server_cert_rparams_t; + +/* tls accept */ +typedef struct _tls_accept_cparams_s +{ + int32_t fd; +} tls_accept_cparams_t; + +typedef struct _tls_accept_rparams_s +{ + mtls_t tls; +} tls_accept_rparams_t; + +/* tls connect_sni */ +typedef struct _tls_connect_sni_cparams_s +{ + struct sockaddr addr; + socklen_t length; + char sni_servername[128]; + int32_t calen; + char ca[1]; +} tls_connect_sni_cparams_t; + +typedef struct _tls_connect_sni_rparams_s +{ + mtls_t tls; + int32_t errno; +} tls_connect_sni_rparams_t; + +/* tls send */ +typedef struct _tls_send_cparams_s +{ + mtls_t tls; + size_t size; + uint8_t buffer[1]; +} tls_send_cparams_t; + +typedef struct _tls_send_rparams_s +{ + int32_t sent; +} tls_send_rparams_t; + +/* tls recv */ +typedef struct _tls_recv_cparams_s +{ + mtls_t tls; + size_t size; +} tls_recv_cparams_t; + +typedef struct _tls_recv_rparams_s +{ + int32_t received; + uint8_t buffer[1]; +} tls_recv_rparams_t; + +/* tls close */ +typedef struct _tls_close_cparams_s +{ + mtls_t tls; +} tls_close_cparams_t; + +typedef struct _tls_close_rparams_s +{ + int32_t ret; +} tls_close_rparams_t; + +/* tls nonblock */ +typedef struct _tls_set_nonblock_cparams_s +{ + mtls_t tls; + int32_t nonblock; +} tls_set_nonblock_cparams_t; + +typedef struct _tls_set_nonblock_rparams_s +{ + int32_t ret; +} tls_set_nonblock_rparams_t; + +#pragma pack() + +#pragma pack(1) +typedef struct mdns_start_cparams_s +{ + char domain[MDNS_MAX_LABEL_LEN + 1]; + char hostname[MDNS_MAX_LABEL_LEN + 1]; +} mdns_start_cparams_t; +typedef struct mdns_announce_cparams_s +{ + uint8_t iface; + struct mc_mdns_service service_data; +} mdns_announce_cparams_t, mdns_deannounce_cparams_t; +typedef struct mdns_deannounce_all_cparams_s +{ + uint8_t iface; +} mdns_deannounce_all_cparams_t; +typedef struct mdns_iface_state_change_cparams_s +{ + uint8_t iface; + uint8_t state; +} mdns_iface_state_change_cparams_t; +typedef struct mdns_set_hostname_cparams_s +{ + char hostname[MDNS_MAX_LABEL_LEN + 1]; +} mdns_set_hostname_cparams_t; +typedef struct mdns_set_txt_rec_cparams_s +{ + struct mc_mdns_service service_data; + char keyvals[MDNS_MAX_KEYVAL_LEN + 1]; + char separator; +} mdns_set_txt_rec_cparams_t; +#pragma pack() +#endif /* MX_WIFI_NETWORK_BYPASS_MODE */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* MX_WIFI_IPC_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_slip.c b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_slip.c new file mode 100644 index 00000000000..80e837c02a3 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_slip.c @@ -0,0 +1,203 @@ +/** + ****************************************************************************** + * @file mx_wifi_slip.c + * @author MCD Application Team + * @brief Host driver SLIP protocol of MXCHIP Wi-Fi component. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +/*cstat -MISRAC2012-* */ +#include "stdio.h" +#include "stdlib.h" +/*cstat +MISRAC2012-* */ + +#include "mx_wifi_conf.h" +#include "mx_wifi_slip.h" +#include "mx_wifi_ipc.h" + +/* debug function */ +#ifdef MX_WIFI_SLIP_DEBUG +#define DEBUG_LOG(M, ...) printf((M), ##__VA_ARGS__) +#else +#define DEBUG_LOG(M, ...) +#endif /* MX_WIFI_SLIP_DEBUG */ + +#define DEBUG_WARNING(...) +/* slip buffer number */ +#define SLIP_BUFFER_SIZE (MIPC_PKT_MAX_SIZE + 100) + + +enum +{ + SLIP_STATE_IDLE, /* NOT START */ + SLIP_STATE_CONTINUE, /* receive data to buffer */ + SLIP_STATE_GOT_ESCAPE /* last byte is escape */ +}; + + +uint8_t *slip_transfer(uint8_t *data, uint16_t len, uint16_t *outlen) +{ + uint16_t i; + uint16_t j; + uint16_t inc = 2; + uint8_t *buff = NULL; + + for (i = 0; i < len; i++) + { + if ((data[i] == SLIP_START) || (data[i] == SLIP_END) || (data[i] == SLIP_ESCAPE)) + { + inc++; + } + } + + buff = (uint8_t *)MX_WIFI_MALLOC(len + inc); + if (buff == NULL) + { + return NULL; + } + + buff[0] = SLIP_START; + for (i = 0, j = 1; i < len; i++) + { + if (data[i] == SLIP_START) + { + buff[j++] = SLIP_ESCAPE; + buff[j++] = SLIP_ESCAPE_START; + } + else if (data[i] == SLIP_END) + { + buff[j++] = SLIP_ESCAPE; + buff[j++] = SLIP_ESCAPE_END; + } + else if (data[i] == SLIP_ESCAPE) + { + buff[j++] = SLIP_ESCAPE; + buff[j++] = SLIP_ESCAPE_ES; + } + else + { + buff[j++] = data[i]; + } + } + buff[j++] = SLIP_END; + *outlen = j; + + return buff; +} + + +mx_buf_t *slip_input_byte(uint8_t data) +{ + mx_buf_t *outgoing_nbuf = NULL; + static uint16_t slip_state = SLIP_STATE_IDLE; + static uint16_t slip_index = 0; + static uint8_t *slip_buffer = NULL; + static mx_buf_t *nbuf = NULL; + + if (slip_buffer == NULL) + { + bool first_miss = true; + do + { + nbuf = MX_NET_BUFFER_ALLOC(SLIP_BUFFER_SIZE); + if (nbuf == NULL) + { + DELAYms(1); + if (true == first_miss) + { + first_miss = false; + DEBUG_WARNING("Running Out of buffer for RX\n"); + } + } + } while (NULL == nbuf); + slip_buffer = MX_NET_BUFFER_PAYLOAD(nbuf); + } + + if (slip_index >= SLIP_BUFFER_SIZE) + { + slip_index = 0; + slip_state = SLIP_STATE_IDLE; + } + + switch (slip_state) + { + case SLIP_STATE_GOT_ESCAPE: + if (data == SLIP_START) + { + slip_index = 0; + } + else if (data == SLIP_ESCAPE_START) + { + slip_buffer[slip_index++] = SLIP_START; + } + else if (data == SLIP_ESCAPE_ES) + { + slip_buffer[slip_index++] = SLIP_ESCAPE; + } + else if (data == SLIP_ESCAPE_END) + { + slip_buffer[slip_index++] = SLIP_END; + } + else + { + goto RESET; + } + slip_state = SLIP_STATE_CONTINUE; + break; + + case SLIP_STATE_IDLE: + if (data == SLIP_START) + { + slip_index = 0; + slip_state = SLIP_STATE_CONTINUE; + } + break; + + case SLIP_STATE_CONTINUE: /* continue */ + if (data == SLIP_START) + { + slip_index = 0; + slip_state = SLIP_STATE_CONTINUE; + } + else if (data == SLIP_END) + { + outgoing_nbuf = nbuf; + slip_buffer = NULL; + MX_NET_BUFFER_SET_PAYLOAD_SIZE(nbuf, slip_index); + nbuf = NULL; + goto RESET; + } + else if (data == SLIP_ESCAPE) + { + slip_state = SLIP_STATE_GOT_ESCAPE; + } + else + { + slip_buffer[slip_index++] = data; + } + break; + + default: + break; + } + + return outgoing_nbuf; + +RESET: + slip_index = 0; + slip_state = SLIP_STATE_IDLE; + return outgoing_nbuf; +} + diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_slip.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_slip.h new file mode 100644 index 00000000000..4c35f089f02 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/core/mx_wifi_slip.h @@ -0,0 +1,74 @@ +/** + ****************************************************************************** + * @file mx_wifi_slip.h + * @author MCD Application Team + * @brief Header for mx_wifi_slip.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_SLIP_H +#define MX_WIFI_SLIP_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "mx_wifi_conf.h" + +/* + * CONFIGURATIONS + */ +#define MX_WIFI_SLIP_DEBUG + + +/* SLIP_PACKET + * |--------+---------+--------| + * | START | PAYLOAD | END | + * |--------+---------+--------| + * | 1Bytes | nBytes | 1Bytes | + * |--------+---------+--------| + */ + +/* + * API + */ + +/* transfer HCI data to SLIP data, + * return the SLIP buffer */ +uint8_t *slip_transfer(uint8_t *data, uint16_t len, uint16_t *outlen); + +/* PHY receive one serial byte to SLIP, + * return SLIP frame + * NOTE: use slip_buf_free to free slip buffer if data process finished. */ +mx_buf_t *slip_input_byte(uint8_t data); + +/* free slip frame buffer returned by slip_input_byte */ +void slip_buf_free(uint8_t *buf); + +enum +{ + SLIP_START = 0xC0, + SLIP_END = 0xD0, + SLIP_ESCAPE = 0xDB, + SLIP_ESCAPE_START = 0xDC, + SLIP_ESCAPE_ES = 0xDD, + SLIP_ESCAPE_END = 0xDE +}; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* MX_WIFI_SLIP_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi.c b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi.c new file mode 100644 index 00000000000..8db03dee1b7 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi.c @@ -0,0 +1,3252 @@ +/** + ****************************************************************************** + * @file mx_wifi.c + * @author MCD Application Team + * @brief Host driver API of MXCHIP Wi-Fi component. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "mx_wifi.h" +#include "core/mx_wifi_ipc.h" + +/* Private defines -----------------------------------------------------------*/ +/* debug log function */ +#ifdef MX_WIFI_API_DEBUG +#define DEBUG_LOG(M, ...) (void) printf((M), ##__VA_ARGS__) +#else +#define DEBUG_LOG(M, ...) +#endif /* MX_WIFI_API_DEBUG */ + +#define MX_HTONL(A) ((((uint32_t)(A) & 0xff000000U) >> 24) | \ + (((uint32_t)(A) & 0x00ff0000U) >> 8) | \ + (((uint32_t)(A) & 0x0000ff00U) << 8) | \ + (((uint32_t)(A) & 0x000000ffU) << 24)) + +#define MX_NTOHL MX_HTONL + + +#define MX_IN_RANGE(c, lo, up) (((c) >= (lo)) && ((c) <= (up))) +#define MX_IS_PRINT(c) (MX_IN_RANGE((c), 0x20, 0x7f)) +#define MX_ISDIGIT(c) (MX_IN_RANGE((c), '0', '9')) +#define MX_ISXDIGIT(c) (MX_ISDIGIT(c) || MX_IN_RANGE((c), 'a', 'f') || MX_IN_RANGE((c), 'A', 'F')) +#define MX_ISLOWER(c) (MX_IN_RANGE((c), 'a', 'z')) +#define MX_ISSPACE(c) (((c) == ' ')\ + || ((c) == '\f') || ((c) == '\n') || ((c) == '\r') || ((c) == '\t') || ((c) == '\v')) + +#if 0 +/* select function file descriptions */ +fd_set mc_select_rfds; +fd_set mc_select_wfds; +fd_set mc_select_efds; +int32_t mc_select_ret_value; +#endif /* 0 */ + +MX_STAT_DECLARE(); +void _MX_WIFI_RecvThread(void* ); + +/* Private data types -----------------------------------------------*/ +typedef struct mx_in_addr +{ + uint32_t s_addr; +} mx_in_addr_t; + +typedef struct +{ + uint32_t addr; +} mx_ip4_addr_t; + +typedef mx_ip4_addr_t mx_ip_addr_t; + + + +#define MX_SIN_ZERO_LEN 8 +typedef struct mx_sockaddr_in +{ + uint8_t sin_len; + uint8_t sin_family; + uint16_t sin_port; + mx_in_addr_t sin_addr; + int8_t sin_zero[MX_SIN_ZERO_LEN]; +} mx_sockaddr_in_t; + + +/* Private functions ---------------------------------------------------------*/ +static int32_t mx_aton(const int8_t *ptr, mx_ip_addr_t *addr); +static int32_t mx_aton_r(const int8_t *cp); +static int8_t *mx_ntoa(const mx_ip4_addr_t *addr); + +/** + * @brief Function description + * @param Params + * @retval socket status + */ + +static int32_t mx_aton(const int8_t *ptr, mx_ip_addr_t *addr) +{ + uint32_t val = 0; + uint32_t base; + int8_t c0; + const int8_t *cp = ptr; + uint32_t parts[4]; + uint32_t *pp = parts; + int32_t ret = 1; + int32_t done; + + c0 = *cp; + done = 0; + for (;;) + { + /* + * Collect number up to ``.''. + * Values are specified as for C: + * 0x=hex, 0=octal, 1-9=decimal. + */ + if (done == 1) + { + break; + } + + if (!MX_ISDIGIT(c0)) + { + ret = 0; + done = 1; + } + else + { + val = 0; + base = 10; + if (c0 == '0') + { + ++cp; + c0 = (int8_t) * cp; + if ((c0 == (int8_t) 'x') || (c0 == (int8_t) 'X')) + { + base = 16; + ++cp; + c0 = (int8_t) * cp; + } + else + { + base = 8; + } + } + + for (;;) + { + if (MX_ISDIGIT(c0)) + { + val = (val * base) + (uint32_t)c0 - (uint32_t) '0'; + ++cp; + c0 = (int8_t) * cp; + } + else if ((base == 16U) && MX_ISXDIGIT(c0)) + { + val = (val << 4) | ((uint32_t)c0 + 10U - (uint32_t)(MX_ISLOWER(c0) ? 'a' : 'A')); + ++cp; + c0 = (int8_t) * cp; + } + else + { + break; + } + } + + if (c0 == '.') + { + /* + * Internet format: + * a.b.c.d + * a.b.c (with c treated as 16 bits) + * a.b (with b treated as 24 bits) + */ + if (pp >= (parts + 3)) + { + ret = 0; + done = 1; + } + else + { + *pp = val; + pp++; + ++cp; + c0 = (int8_t) * cp; + } + } + else + { + done = 1; + } + } + } + /* + * Check for trailing characters. + */ + if ((c0 != (int8_t)'\0') && (MX_ISSPACE((c0)) == false)) + { + ret = 0; + } + else + + /* + * Concoct the address according to + * the number of parts specified. + */ + { + switch (pp - parts + 1) + { + case 0: + ret = 0; /* initial nondigit */ + break; + + case 1: /* a -- 32 bits */ + break; + + case 2: /* a.b -- 8.24 bits */ + if (val > 0xffffffUL) + { + ret = 0; + } + val |= parts[0] << 24; + break; + + case 3: /* a.b.c -- 8.8.16 bits */ + if (val > 0xffffU) + { + ret = 0; + break; + } + val |= (parts[0] << 24) | (parts[1] << 16); + break; + + case 4: /* a.b.c.d -- 8.8.8.8 bits */ + if (val > 0xffU) + { + ret = 0; + break; + } + val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); + break; + + default: + ret = 0; + break; + } + } + + if (ret == 1) + { + if (addr != NULL) + { + addr->addr = MX_HTONL(val); + } + } + return ret; +} + + + + +static int32_t mx_aton_r(const int8_t *cp) +{ + mx_ip_addr_t val; + int32_t ret; + val.addr = 0; + if (mx_aton(cp, &val) != 0) + { + ret = (int32_t) val.addr; + } + else + { + ret = 0; + } + return (ret); +} + + + +/** + * @brief Register physical interface IO operation function + * @param Obj mxchip wifi object + * @param IO_Init IO init function + * @param IO_DeInit IO deinit function + * @param IO_Delay IO delay function + * @param IO_Send IO send function + * @param IO_Receive IO recv function + * @return MX_WIFI_STATUS_T status code + */ +MX_WIFI_STATUS_T MX_WIFI_RegisterBusIO(MX_WIFIObject_t *Obj, + IO_Init_Func IO_Init, + IO_DeInit_Func IO_DeInit, + IO_Delay_Func IO_Delay, + IO_Send_Func IO_Send, + IO_Receive_Func IO_Receive) +{ + MX_WIFI_STATUS_T rc; + + if ((NULL == Obj) || (NULL == IO_Init) || (NULL == IO_DeInit) || (NULL == IO_Send) || \ + (NULL == IO_Receive) || (NULL == IO_Delay)) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + Obj->fops.IO_Init = IO_Init; + Obj->fops.IO_DeInit = IO_DeInit; + Obj->fops.IO_Send = IO_Send; + Obj->fops.IO_Receive = IO_Receive; + Obj->fops.IO_Delay = IO_Delay; + rc = MX_WIFI_STATUS_OK; + } + return rc; +} + +/** + * @brief reset wifi module by hardware + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_HardResetModule(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T rc; + int32_t ret; + + + MX_STAT_INIT(); + + if (NULL == Obj) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + /* reset Wi-Fi by reset pin */ + ret = Obj->fops.IO_Init(MX_WIFI_RESET); + if ((int32_t)0 == ret) + { + rc = MX_WIFI_STATUS_OK; + } + else + { + rc = MX_WIFI_STATUS_ERROR; + } + } + + return rc; +} + +/** + * @brief set timeout for mxchip wifi API + * @param Obj wifi object + * @param Timeout timeout in ms + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_SetTimeout(MX_WIFIObject_t *Obj, uint32_t Timeout) +{ + MX_WIFI_STATUS_T rc; + + if (NULL == Obj) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + Obj->Runtime.Timeout = Timeout; + rc = MX_WIFI_STATUS_OK; + } + return rc; +} + +/* + * run with RTOS + */ +THREAD_DECLARE(MX_WIFI_RecvThreadId); + + +/** + * @brief wifi stat recv thread for RTOS + * @param argument thread arguments + */ +void _MX_WIFI_RecvThread(void* arg) +{ + MX_WIFIObject_t *Obj = wifi_obj_get(); + + if (NULL != Obj) + { + while (true) + { + (void) mipc_poll(500); + + } + } + /* Delete the Thread */ + THREAD_TERMINATE(MX_WIFI_RecvThreadId); +} + + + +/** + * @brief wifi init + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_Init(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + uint16_t rparams_size; + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (Obj->Runtime.interfaces == 0u) + { + LOCK_INIT(Obj->lockcmd); + + /* 0. set cmd timeout */ + Obj->Runtime.Timeout = MX_WIFI_CMD_TIMEOUT; + + /* 1. init wifi low level IO(UART/SPI) */ + (void)(Obj->fops.IO_Init(MX_WIFI_INIT)); + { + /* 2. init wifi ipc */ + if (MIPC_CODE_SUCCESS == mipc_init(Obj->fops.IO_Send)) + { + + /* 2a start thread for RTOS implementation */ + + if (THREAD_OK != THREAD_INIT(MX_WIFI_RecvThreadId, _MX_WIFI_RecvThread, NULL, + MX_WIFI_RECEIVED_THREAD_STACK_SIZE, + MX_WIFI_RECEIVED_THREAD_PRIORITY)) + { + ret = MX_WIFI_STATUS_ERROR; + } + else + { + /* 3. get version */ + (void)memset(&(Obj->SysInfo.FW_Rev[0]), 0, MX_WIFI_FW_REV_SIZE); + rparams_size = MX_WIFI_FW_REV_SIZE; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_VERSION_CMD, + NULL, 0, + &(Obj->SysInfo.FW_Rev[0]), + &rparams_size, + MX_WIFI_CMD_TIMEOUT)) + { + (void)strncpy((char *)(Obj->SysInfo.Product_Name), + MX_WIFI_PRODUCT_NAME, MX_WIFI_PRODUCT_NAME_SIZE); + (void)strncpy((char *)(Obj->SysInfo.Product_ID), + MX_WIFI_PRODUCT_ID, MX_WIFI_PRODUCT_ID_SIZE); + + /* 4. get MAC */ + (void)memset(&(Obj->SysInfo.MAC[0]), 0, MX_WIFI_MAC_SIZE); + rparams_size = MX_WIFI_MAC_SIZE; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_GET_MAC_CMD, + NULL, 0, + &(Obj->SysInfo.MAC[0]), + &rparams_size, + MX_WIFI_CMD_TIMEOUT)) + { + ret = MX_WIFI_STATUS_OK; + Obj->Runtime.interfaces++; + } /* get MAC */ + } /* get version */ + } + } + } + } + else + { + Obj->Runtime.interfaces++; + ret = MX_WIFI_STATUS_OK; + } + } + + return ret; +} + +/** + * @brief wifi deinit + * @param Obj wifi object + * @return MX_WIFI_STATUS_T + */ +MX_WIFI_STATUS_T MX_WIFI_DeInit(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (Obj->Runtime.interfaces == 1u) + { + (void) THREAD_DEINIT(MX_WIFI_RecvThreadId); + (void)mipc_deinit(); + Obj->fops.IO_DeInit(); + ret = MX_WIFI_STATUS_OK; + Obj->Runtime.interfaces--; + } + else + { + ret = MX_WIFI_STATUS_OK; + if (Obj->Runtime.interfaces > 0u) + { + Obj->Runtime.interfaces--; + } + } + } + + return ret; +} + +/** + * @brief wifi data yield + * @param Obj wifi object + * @param timeout timetou in ms + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_IO_YIELD(MX_WIFIObject_t *Obj, uint32_t timeout) +{ + + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_OK; + if (NULL != Obj) + { +#if MX_WIFI_BARE_OS + mipc_poll(timeout); +#endif + } + return ret; +} + +/** + * @brief wifi software reboot + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_ResetModule(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_REBOOT_CMD, NULL, 0, + NULL, 0, MX_WIFI_CMD_TIMEOUT)) + { + ret = MX_WIFI_STATUS_OK; + } + } + return ret; +} + +/** + * @brief wifi factory reset + * @param Obj wifi object + * @return MX_WIFI_STATUS_T + */ +MX_WIFI_STATUS_T MX_WIFI_ResetToFactoryDefault(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_RESET_CMD, NULL, 0, + NULL, 0, MX_WIFI_CMD_TIMEOUT)) + { + ret = MX_WIFI_STATUS_OK; + } + } + return ret; +} + +/** + * @brief wifi get firmware version + * @param Obj wifi object + * @param version buffer to get version + * @param size buffer size + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_GetVersion(MX_WIFIObject_t *Obj, uint8_t *version, uint32_t size) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + uint16_t rparams_size; + + if ((NULL == Obj) || (NULL == version) || (size > (uint32_t)MX_WIFI_FW_REV_SIZE) \ + || ((uint32_t)0 == size)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + (void)memset(&(Obj->SysInfo.FW_Rev[0]), 0, MX_WIFI_FW_REV_SIZE); + rparams_size = MX_WIFI_FW_REV_SIZE; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SYS_VERSION_CMD, NULL, 0, + &(Obj->SysInfo.FW_Rev[0]), + &rparams_size, MX_WIFI_CMD_TIMEOUT)) + { + (void)memcpy(version, &(Obj->SysInfo.FW_Rev[0]), MX_WIFI_FW_REV_SIZE); + ret = MX_WIFI_STATUS_OK; + } + + } + return ret; +} + +/** + * @brief wifi get MAC address + * @param Obj wifi object + * @param mac buffer to get MAC address (6 bytes) + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_GetMACAddress(MX_WIFIObject_t *Obj, uint8_t *mac) +{ + MX_WIFI_STATUS_T ret; + + if ((NULL == Obj) || (NULL == mac)) + { + ret = MX_WIFI_STATUS_ERROR; + } + else + { + (void)memcpy(mac, Obj->SysInfo.MAC, MX_WIFI_MAC_SIZE); + ret = MX_WIFI_STATUS_OK; + } + + return ret; +} + +/** + * @brief wifi scan start + * @param Obj wifi object + * @param scan_mode scan mode + * @param ssid ssid to scan + * @param len max number to scan + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_Scan(MX_WIFIObject_t *Obj, mc_wifi_scan_mode_t scan_mode, + char *ssid, int32_t len) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + wifi_scan_cparams_t cparams; + wifi_scan_rparams_t *rparams_p = (wifi_scan_rparams_t *)(&(Obj->Runtime.scan_result[0])); + uint16_t rparams_size; + + if ((NULL == Obj) || (((mc_wifi_scan_mode_t)MC_SCAN_ACTIVE == scan_mode) && + ((NULL == ssid) || (len <= 0) || (len > 32)))) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + memcpy(&(cparams.ssid[0]), ssid, len); + rparams_size = MX_WIFI_SCAN_BUF_SIZE; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_SCAN_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)rparams_p, &rparams_size, + MX_WIFI_SCAN_TIMEOUT)) + { + Obj->Runtime.scan_number = rparams_p->num; + memcpy(&(Obj->Runtime.scan_result[0]), &(rparams_p->ap[0]), + Obj->Runtime.scan_number * sizeof(mwifi_ap_info_t)); + ret = MX_WIFI_STATUS_OK; + } + } + return ret; +} + +/** + * @brief get wifi scan result + * @param Obj wifi object + * @param results buffer to get scan result + * @param number max ap number to get + * @return int8_t ap number got + */ +int8_t MX_WIFI_Get_scan_result(MX_WIFIObject_t *Obj, uint8_t *results, uint8_t number) +{ + int8_t copy_number; + + if ((NULL == Obj) || (NULL == results) || ((uint8_t)0 == number)) + { + copy_number = 0; + } + else + { + copy_number = (int8_t)(MIN(Obj->Runtime.scan_number, number)); + (void)memcpy(results, Obj->Runtime.scan_result, (size_t)copy_number * sizeof(mwifi_ap_info_t)); + } + return copy_number; +} + +/** + * @brief register wifi station status event callback + * @param Obj wifi object + * @param cb callback function + * @param arg callback argument + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback(MX_WIFIObject_t *Obj, + mx_wifi_status_callback_t cb, + void *arg) +{ + MX_WIFI_STATUS_T rc; + + if (NULL == Obj) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + Obj->Runtime.status_cb[0] = cb; + Obj->Runtime.callback_arg[0] = arg; + rc = MX_WIFI_STATUS_OK; + } + return rc; +} + +/** + * @brief unregister wifi station event callback function + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T rc; + + if (NULL == Obj) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + Obj->Runtime.status_cb[0] = NULL; + Obj->Runtime.callback_arg[0] = NULL; + rc = MX_WIFI_STATUS_OK; + } + return rc; +} + +/** + * @brief register wifi event callback for station or AP mode + * @param Obj wifi object + * @param cb callback function + * @param arg callback argument + * @param interface wifi mode + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback_if(MX_WIFIObject_t *Obj, + mx_wifi_status_callback_t cb, + void *arg, + mwifi_if_t interface) +{ + MX_WIFI_STATUS_T rc; + + if (NULL == Obj) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + if ((mwifi_if_t)MC_SOFTAP == interface) + { + Obj->Runtime.status_cb[1] = cb; + Obj->Runtime.callback_arg[1] = arg; + } + else + { + Obj->Runtime.status_cb[0] = cb; + Obj->Runtime.callback_arg[0] = arg; + } + rc = MX_WIFI_STATUS_OK; + + } + return rc; +} + +/** + * @brief register wifi event callback for station or AP mode + * @param Obj wifi object + * @param interface wifi mode + * @return MX_WIFI_STATUS_T + */ +MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback_if(MX_WIFIObject_t *Obj, mwifi_if_t interface) +{ + MX_WIFI_STATUS_T rc; + + if (NULL == Obj) + { + rc = MX_WIFI_STATUS_ERROR; + } + else + { + if ((mwifi_if_t)MC_SOFTAP == interface) + { + Obj->Runtime.status_cb[1] = NULL; + Obj->Runtime.callback_arg[1] = NULL; + } + else + { + Obj->Runtime.status_cb[0] = NULL; + Obj->Runtime.callback_arg[0] = NULL; + } + rc = MX_WIFI_STATUS_OK; + } + return rc; +} + + +static int8_t *mx_ntoa(const mx_ip4_addr_t *addr) +{ + uint32_t MX_S_ADDR; + uint8_t val; + int8_t inv[3]; + uint8_t *ap; + uint8_t rem; + uint8_t i; + int32_t len = 0; + int8_t *buf_ret; + static int8_t buf[16]; + + MX_S_ADDR = addr->addr; + + ap = (uint8_t *)&MX_S_ADDR; + for (uint8_t n = 0; n < (uint8_t) 4; n++) + { + i = 0; + val = ap[n]; + do + { + rem = val % 10U; + val /= 10U; + inv[i] = (int8_t)'0' + rem; + i++; + } while (val != 0U); + + while (i != 0U) + { + i--; + if (len < 16) + { + buf[len] = inv[i]; + len++; + } + } + + if ((n < 3U) && (len < 16)) + { + buf[len] = (int8_t) '.'; + len++; + } + } + + if (len < 16) + { + buf[len] = (int8_t) '\0'; + buf_ret = buf; + + } + else + { + buf_ret = (int8_t *) "000.000.000.000"; + } + + return buf_ret; +} + + +/** + * @brief wifi connect to an AP + * @param Obj wifi object + * @param SSID ssid of AP + * @param Password password of AP + * @param SecType security type (not used, auto) + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_Connect(MX_WIFIObject_t *Obj, const char *SSID, + const char *Password, MX_WIFI_SecurityType_t SecType) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + wifi_connect_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t rparams_size; + mwifi_ip_attr_t ip_attr; + mx_ip4_addr_t net_ipaddr; + + (void)SecType; + + if ((NULL == Obj) || (NULL == SSID) || (strlen(SSID) > (uint32_t)MX_MAX_SSID_LEN) + || (NULL == Password) || (strlen(Password) > (uint32_t)MX_MAX_KEY_LEN)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + strncpy((char *)cparams.ssid, SSID, MX_MAX_SSID_LEN); + strncpy((char *)cparams.key, Password, MX_MAX_KEY_LEN); + cparams.key_len = strlen(Password); + cparams.use_attr = 0; + cparams.use_ip = 0; + + if ((uint8_t)0 == Obj->NetSettings.DHCP_IsEnabled) + { + (void)memset(&ip_attr, 0, sizeof(mwifi_ip_attr_t)); + (void)memcpy(&net_ipaddr, Obj->NetSettings.IP_Addr, 4); + (void)memcpy(ip_attr.localip, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN); + (void)memcpy(&net_ipaddr, Obj->NetSettings.IP_Mask, 4); + (void)memcpy(ip_attr.netmask, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN); + (void)memcpy(&net_ipaddr, Obj->NetSettings.Gateway_Addr, 4); + (void)memcpy(ip_attr.gateway, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN); + (void)memcpy(&net_ipaddr, Obj->NetSettings.DNS1, 4); + (void)memcpy(ip_attr.dnserver, mx_ntoa(&net_ipaddr), MX_MAX_IP_LEN); + cparams.use_ip = 1; + memcpy(&(cparams.ip), &ip_attr, sizeof(cparams.ip)); + } + + rparams_size = sizeof(status); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_CONNECT_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &rparams_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + + } + return ret; +} + +/** + * @brief connect to an AP with WAP-E + * @param Obj wifi object + * @param SSID ssid of AP + * @param Identity identity of client + * @param Password password of client + * @param attr EAP attribute + * @param ip ip attribute + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_EAP_Connect(MX_WIFIObject_t *Obj, const char *SSID, + const char *Identity, const char *Password, + mwifi_eap_attr_t *attr, mwifi_ip_attr_t *ip) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_OK; + +#if 0 + lib_ipc_eap_attr_t ipc_eap_attr; + + if ((NULL == Obj) || (NULL == SSID) || (strlen(SSID) > (uint32_t)MX_MAX_SSID_LEN) || \ + (NULL == Identity) || (strlen(Identity) > (uint32_t)MX_MAX_IDENTITY_LEN) || \ + (NULL == Password) || (strlen(Password) > (uint32_t)MX_MAX_KEY_LEN)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (!MX_WIFI_LOCK((Obj))) + { + ret = MX_WIFI_STATUS_TIMEOUT; + } + else + { + (void)memset(&ipc_eap_attr, 0, sizeof(ipc_eap_attr)); + + if (NULL != attr) + { + /* just set eap type here, rootca/cert/key set by specifical API */ + if (((uint8_t)EAP_TYPE_TLS != attr->eap_type) && ((uint8_t)EAP_TYPE_TTLS != attr->eap_type) && + ((uint8_t)EAP_TYPE_PEAP != attr->eap_type)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + ipc_eap_attr.eap_type = attr->eap_type; + + if (NULL != attr->rootca) + { + if (MIPC_CODE_SUCCESS != wifi_eap_set_rootca_cmd(attr->rootca, strlen(attr->rootca))) + { + ret = MX_WIFI_STATUS_ERROR; + } + } + + if ((MX_WIFI_STATUS_OK == ret) && (NULL != attr->client_cert)) + { + if (MIPC_CODE_SUCCESS != wifi_eap_set_client_cert_cmd(attr->client_cert, strlen(attr->client_cert))) + { + ret = MX_WIFI_STATUS_ERROR; + } + } + + if ((MX_WIFI_STATUS_OK == ret) && (NULL != attr->client_key)) + { + if (MIPC_CODE_SUCCESS != wifi_eap_set_client_key_cmd(attr->client_key, strlen(attr->client_key))) + { + ret = MX_WIFI_STATUS_ERROR; + } + } + } + } + else + { + ipc_eap_attr.eap_type = (uint8_t)EAP_TYPE_PEAP; /* default eap type */ + } + + if (MX_WIFI_STATUS_OK == ret) + { + if (MIPC_CODE_SUCCESS != wifi_eap_connect_cmd(SSID, (int32_t)strlen(SSID), + Identity, (int32_t)strlen(Identity), + Password, (int32_t)strlen(Password), + &ipc_eap_attr, sizeof(ipc_eap_attr), + ip, (NULL != ip) ? sizeof(mwifi_ip_attr_t) : 0u)) + { + ret = MX_WIFI_STATUS_ERROR; + } + } + + (void)MX_WIFI_UNLOCK((Obj)); + } + } +#endif /* 0 */ + + return ret; +} + +/** + * @brief wifi station disconnect + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_Disconnect(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + int32_t status = MIPC_CODE_ERROR; + uint16_t rparams_size; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + rparams_size = sizeof(status); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_DISCONNECT_CMD, NULL, 0, + (uint8_t *)&status, &rparams_size, + 15000)) /* disconnect max timeout 15s */ + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief connect AP with WPS + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_WPS_Connect(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_val; + int32_t addr_ret_flag; + int32_t *p_addr_ret_val; + int32_t *p_addr_ret_flag; + + if (NULL != Obj) + { + p_addr_ret_val = &ret; + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val)); + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == wifi_wps_connect_cmd(addr_ret_val, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout)) + { + ret = MX_WIFI_STATUS_OK; + } + } + } +#endif /* 0 */ + + return ret; +} + +/** + * @brief stop connecting to an AP with WPS + * @param Obj wifi object + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_WPS_Stop(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_val; + int32_t addr_ret_flag; + int32_t *p_addr_ret_val; + int32_t *p_addr_ret_flag; + + if (NULL != Obj) + { + p_addr_ret_val = &ret; + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val)); + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == wifi_wps_stop_cmd(addr_ret_val, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout)) + { + ret = MX_WIFI_STATUS_OK; + } + } + } +#endif /* 0 */ + + return ret; +} + +/** + * @brief get wifi station connect status + * @param Obj wifi object + * @return int8_t 1 -- connected, 0 -- not connected + */ +int8_t MX_WIFI_IsConnected(MX_WIFIObject_t *Obj) +{ + int8_t ret = 0; + wifi_get_linkinof_rparams_t rparams; + uint16_t rparams_size = sizeof(rparams); + rparams.status = MIPC_CODE_ERROR; + if (NULL != Obj) + { + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_GET_LINKINFO_CMD, NULL, 0, + (uint8_t *)&rparams, &rparams_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == rparams.status) + { + Obj->NetSettings.IsConnected = rparams.info.is_connected; + ret = Obj->NetSettings.IsConnected; + } + } + } + return ret; +} + +/** + * @brief get wifi IPv4 address + * @param Obj wifi object + * @param ipaddr address buffer + * @param wifi_if wifi interface + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_GetIPAddress(MX_WIFIObject_t *Obj, uint8_t *ipaddr, mwifi_if_t wifi_if) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + wifi_get_ip_rparams_t rparams; + uint16_t rparams_size = sizeof(rparams); + int32_t ip; + int32_t netmask; + int32_t gw; + int32_t dns; + + rparams.status = MIPC_CODE_ERROR; + + if (NULL != Obj) + { + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_GET_IP_CMD, + (uint8_t *)&wifi_if, sizeof(wifi_if), + (uint8_t *)&rparams, &rparams_size, + 1000)) + { + if (MIPC_CODE_SUCCESS == rparams.status) + { + ip = mx_aton_r((int8_t const *) & (rparams.ip.localip[0])); + memcpy(&(Obj->NetSettings.IP_Addr[0]), &ip, 4); + + netmask = mx_aton_r((int8_t const *) & (rparams.ip.netmask[0])); + memcpy(&(Obj->NetSettings.IP_Mask[0]), &netmask, 4); + + gw = mx_aton_r((int8_t const *) & (rparams.ip.gateway[0])); + memcpy(&(Obj->NetSettings.Gateway_Addr[0]), &gw, 4); + + dns = mx_aton_r((int8_t const *) & (rparams.ip.dnserver[0])); + memcpy(&(Obj->NetSettings.DNS1[0]), &dns, 4); + + (void)memcpy(ipaddr, Obj->NetSettings.IP_Addr, 4); + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief get wifi IPv6 address info + * @param Obj wifi object + * @param ipaddr6 ipv6 address buffer + * @param addr_num ipv6 address index (0,1,2) + * @param wifi_if wifi interface + * @return MX_WIFI_STATUS_T status + */ +MX_WIFI_STATUS_T MX_WIFI_GetIP6Address(MX_WIFIObject_t *Obj, uint8_t *ipaddr6, int32_t addr_num, mwifi_if_t wifi_if) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_flag; + int32_t *p_addr_ret_flag; + + if ((NULL != Obj) && (NULL != ipaddr6) && (addr_num < 3) && (addr_num >= 0)) + { + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == wifi_get_ip6_addr_cmd((int32_t)addr_num, (int32_t)wifi_if, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, Obj->Runtime.Timeout)) + { + (void)memcpy(ipaddr6, Obj->NetSettings.IP6_Addr[addr_num], 16); + ret = MX_WIFI_STATUS_OK; + } + } + } +#endif /* 0 */ + + return ret; +} + +/** + * @brief Get the local IPv6 address state of the wifi module. + * @param Obj: pointer to module handle + * @param addr_num: index of the IPv6 address (index: 0/1/2). + * @param wifi_if: wifi mode(station or softap). + * @retval IPV6 address State, error if < 0 + */ +int32_t MX_WIFI_GetIP6AddressState(MX_WIFIObject_t *Obj, int32_t addr_num, mwifi_if_t wifi_if) +{ + int32_t state = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_flag; + int32_t *p_addr_ret_flag; + + if ((NULL != Obj) && (addr_num < 3) && (addr_num >= 0)) + { + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == wifi_get_ip6_state_cmd((int32_t)addr_num, (int32_t)wifi_if, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, Obj->Runtime.Timeout)) + { + state = Obj->NetSettings.IP6_state[addr_num]; + } + } + } +#endif /* 0 */ + + return state; +} + +/* +* SoftAP + */ + +/** + * @brief Start softAP(miniAP) mode + * @param Obj: pointer to module handle + * @param ap_settings: softAP settings. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_StartAP(MX_WIFIObject_t *Obj, MX_WIFI_APSettings_t *ap_settings) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + wifi_softap_start_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t rparams_size = sizeof(status); + + if ((NULL == Obj) || (NULL == ap_settings)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memcpy((char *)cparams.ssid, ap_settings->SSID, sizeof(cparams.ssid)); + memcpy((char *)cparams.key, ap_settings->pswd, sizeof(cparams.key)); + cparams.channel = ap_settings->channel; + memcpy(&(cparams.ip), &(ap_settings->ip), sizeof(cparams.ip)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_SOFTAP_START_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &rparams_size, + 3000)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Stop softAP(miniAP) mode + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_StopAP(MX_WIFIObject_t *Obj) +{ + MX_WIFI_STATUS_T ret = MX_WIFI_STATUS_ERROR; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL != Obj) + { + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_SOFTAP_STOP_CMD, NULL, 0, + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +#if MX_WIFI_NETWORK_BYPASS_MODE == 0 +/** + * @brief Create a socket. + * @param Obj: pointer to module handle + * @param domain: socket domain + * @param type: socket type + * @param protocol: socket protocol + * @retval Socket file descriptor, return < 1 if failed. + */ +int32_t MX_WIFI_Socket_create(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol) +{ + int32_t ret_fd = -1; + socket_create_cparams_t cp; + socket_create_rparams_t rp; + uint16_t out_size = sizeof(rp); + + if (NULL != Obj) + { + cp.domain = domain; + cp.type = type; + cp.protocol = protocol; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_CREATE_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + ret_fd = rp.fd; + } + } + + return ret_fd; +} + +/** + * @brief Set option for a socket + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param level: option level + * @param optname: option to set + * @param optvalue: value buffer for the option + * @param optlen: length of the option value + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_setsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level, + int32_t optname, const void *optvalue, int32_t optlen) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_setsockopt_cparams_t cp; + socket_setsockopt_rparams_t rp; + uint16_t out_size = sizeof(rp); + + rp.status = MIPC_CODE_ERROR; + if ((NULL == Obj) || (sockfd < 0) || (NULL == optvalue) || (optlen <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.socket = sockfd; + cp.level = level; + cp.optname = optname; + cp.optlen = optlen > sizeof(cp.optval) ? sizeof(cp.optval) : optlen; + memcpy(&(cp.optval[0]), optvalue, cp.optlen); + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SETSOCKOPT_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Get option of a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param level: option level + * @param optname: option to set + * @param optvalue: buffer pointer of value of the option + * @param optlen: buffer pointer of length of the option value + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_getsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level, + int32_t optname, void *optvalue, uint32_t *optlen) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_getsockopt_cparams_t cp; + socket_getsockopt_rparams_t rp; + uint16_t out_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == optvalue) || (NULL == optlen)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.socket = sockfd; + cp.level = level; + cp.optname = optname; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETSOCKOPT_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + *optlen = (rp.optlen > (*optlen)) ? (*optlen) : rp.optlen; + memcpy(optvalue, &(rp.optval[0]), *optlen); + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Bind a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: socket address + * @param addrlen: address length + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_bind(MX_WIFIObject_t *Obj, int32_t sockfd, + const struct sockaddr *addr, int32_t addrlen) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_bind_cparams_t cp; + socket_bind_rparams_t rp; + uint16_t out_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (addrlen <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.socket = sockfd; + memcpy(&(cp.addr), addr, sizeof(cp.addr)); + cp.length = addrlen; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_BIND_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Listen a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param backlog: max number to queued. + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_listen(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t backlog) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_listen_cparams_t cp; + socket_listen_rparams_t rp; + uint16_t rp_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.socket = sockfd; + cp.n = backlog; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_LISTEN_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Accept a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: client address + * @param addrlen: length of client address + * @retval Accepted client socket fd, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_accept(MX_WIFIObject_t *Obj, int32_t sockfd, + struct sockaddr *addr, uint32_t *addrlen) +{ + int32_t ret_fd = -1; + socket_accept_cparams_t cp; + socket_accept_rparams_t rp; + uint16_t rp_size = sizeof(rp); + rp.socket = -1; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (NULL == addrlen)) + { + ret_fd = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.socket = sockfd; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_ACCEPT_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.socket >= 0) + { + memcpy(addr, &(rp.addr), sizeof(rp.addr)); + *addrlen = rp.length; + ret_fd = rp.socket; + } + } + } + return ret_fd; +} + +/** + * @brief Socket connect. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: client address + * @param addrlen: length of client address + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_connect(MX_WIFIObject_t *Obj, int32_t sockfd, + const struct sockaddr *addr, int32_t addrlen) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_connect_cparams_t cp; + socket_connect_rparams_t rp; + uint16_t out_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (addrlen <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.socket = sockfd; + memcpy(&(cp.addr), addr, sizeof(cp.addr)); + cp.length = addrlen; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_CONNECT_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Socket shutdown. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param mode: shutdown mode: + * 0 Stop receiving data for this socket; + * 1 Stop trying to transmit data from this socket + * 2 Stop all transmit from this socket + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_shutdown(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t mode) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_shutdown_cparams_t cp; + socket_shutdown_rparams_t rp; + uint16_t out_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.filedes = sockfd; + cp.how = mode; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SHUTDOWN_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Socket close. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_close(MX_WIFIObject_t *Obj, int32_t sockfd) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + socket_close_cparams_t cp; + socket_close_rparams_t rp; + uint16_t out_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.filedes = sockfd; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_CLOSE_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Socket send. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: send data buffer + * @param len: length of send data + * @param flags: zero for MXOS + * @retval Number of bytes sent, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_send(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, + int32_t len, int32_t flags) +{ + int32_t ret = -1; + socket_send_cparams_t *cp; + uint16_t cp_size; + socket_send_rparams_t rp; + uint16_t rp_size = sizeof(rp); + int32_t datalen; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0)) + { + ret = -1; + } + else + { + if ((len + sizeof(socket_send_cparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE) + { + datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_send_cparams_t) - 1)); + } + else + { + datalen = len; + } + rp.sent = 0; + cp_size = (sizeof(socket_send_cparams_t) - 1 + datalen); + cp = (socket_send_cparams_t *)MX_WIFI_MALLOC(cp_size); + if (NULL != cp) + { + cp->socket = sockfd; + memcpy(&(cp->buffer[0]), buf, datalen); + cp->size = datalen; + cp->flags = flags; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SEND_CMD, + (uint8_t *)cp, cp_size, + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + ret = rp.sent; + } + MX_WIFI_FREE(cp); + } + } + return ret; +} + +/** + * @brief Socket sendto. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: send data buffer + * @param len: length of send data + * @param flags: zero for MXOS + * @param toaddr: address to send + * @param toaddrlen: length of address to send + * @retval Number of bytes sent, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_sendto(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, + int32_t len, int32_t flags, + struct sockaddr *toaddr, int32_t toaddrlen) +{ + int32_t ret = -1; + socket_sendto_cparams_t *cp; + uint16_t cp_size; + socket_sendto_rparams_t rp; + uint16_t rp_size = sizeof(rp); + int32_t datalen; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0) || (NULL == toaddr) || (toaddrlen <= 0)) + { + ret = -1; + } + else + { + if ((len + sizeof(socket_sendto_cparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE) + { + datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_sendto_cparams_t) - 1)); + } + else + { + datalen = len; + } + cp_size = (sizeof(socket_sendto_cparams_t) - 1 + datalen); + cp = (socket_sendto_cparams_t *)MX_WIFI_MALLOC(cp_size); + if (NULL != cp) + { + rp.sent = 0; + cp->socket = sockfd; + memcpy(&(cp->buffer[0]), buf, datalen); + cp->size = datalen; + cp->flags = flags; + memcpy(&(cp->addr), toaddr, sizeof(cp->addr)); + cp->length = toaddrlen; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_SENDTO_CMD, + (uint8_t *)cp, cp_size, + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + ret = rp.sent; + } + MX_WIFI_FREE(cp); + } + } + return ret; +} + +/** + * @brief Socket recv. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: recv buffer + * @param len: length of recv buffer + * @param flags: zero for MXOS + * @retval Number of bytes received, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_recv(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, + int32_t len, int32_t flags) +{ + int32_t ret = -1; + socket_recv_cparams_t cp; + socket_recv_rparams_t *rp; + uint16_t rp_size; + int32_t datalen; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0)) + { + ret = -1; + } + else + { + ret = 0; + if ((len + sizeof(socket_recv_rparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE) + { + datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_recv_rparams_t) - 1)); + } + else + { + datalen = len; + } + rp_size = (sizeof(socket_recv_rparams_t) - 1 + datalen); + rp = (socket_recv_rparams_t *)MX_WIFI_MALLOC(rp_size); + if (NULL != rp) + { + rp->received = 0; + cp.socket = sockfd; + cp.size = datalen; + cp.flags = flags; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_RECV_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if ((rp->received <= datalen) && (rp->received > 0)) + { + memcpy(buf, &(rp->buffer[0]), rp->received); + } + ret = rp->received; + } + MX_WIFI_FREE(rp); + } + } + return ret; +} + +/** + * @brief Socket recvfrom. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: recv buffer + * @param len: length of recv buffer + * @param fromaddr: address of the data source + * @param fromaddrlen: length of address of the data source + * @param flags: zero for MXOS + * @retval Number of bytes received, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_recvfrom(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, + int32_t len, int32_t flags, + struct sockaddr *fromaddr, uint32_t *fromaddrlen) +{ + int32_t ret = -1; + socket_recvfrom_cparams_t cp; + socket_recvfrom_rparams_t *rp; + uint16_t rp_size; + int32_t datalen; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == buf) || (len <= 0) || (NULL == fromaddr) \ + || (NULL == fromaddrlen)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + ret = 0; + if ((len + sizeof(socket_recvfrom_rparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE) + { + datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(socket_recvfrom_rparams_t) - 1)); + } + else + { + datalen = len; + } + rp_size = (sizeof(socket_recvfrom_rparams_t) - 1 + datalen); + rp = (socket_recvfrom_rparams_t *)MX_WIFI_MALLOC(rp_size); + if (NULL != rp) + { + rp->received = 0; + cp.socket = sockfd; + cp.size = datalen; + cp.flags = flags; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_RECVFROM_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if ((rp->received <= datalen) && (rp->received > 0)) + { + memcpy(buf, &(rp->buffer[0]), rp->received); + ret = rp->received; + memcpy(fromaddr, &(rp->addr), sizeof(rp->addr)); + *fromaddrlen = rp->length; + } + } + MX_WIFI_FREE(rp); + } + } + return ret; +} + +/** + * @brief Gethostbyname, only for IPv4 address. + * @param Obj: pointer to module handle + * @param addr: address of the host + * @param name: hostname + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_gethostbyname(MX_WIFIObject_t *Obj, struct sockaddr *addr, char *name) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mx_sockaddr_in_t addr_in; + socket_gethostbyname_cparams_t cp; + socket_gethostbyname_rparams_t rp; + uint16_t rp_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (NULL == addr) || (NULL == name) || (strlen(name) > (uint32_t)MX_MAX_DNSNAME_LEN)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + uint32_t msize; + memset(&cp, 0, sizeof(cp)); + msize = MIN(sizeof(cp.name), strlen(name) + 1); + memcpy(&(cp.name[0]), name, msize); + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETHOSTBYNAME_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.status == MIPC_CODE_SUCCESS) + { + addr_in.sin_addr.s_addr = rp.s_addr; + addr_in.sin_family = AF_INET; + addr_in.sin_len = sizeof(addr_in); + memcpy(addr, &addr_in, sizeof(struct sockaddr)); + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Ping a host, only for IPv4 address. + * @param Obj: pointer to module handle + * @param addr: hostname + * @param count: ping max count + * @param delay: ping delay in millisecond + * @param response: response time array of ping result + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_ping(MX_WIFIObject_t *Obj, const char *hostname, + int32_t count, int32_t delay, int32_t response[]) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + wifi_ping_cparams_t cp; + int32_t ping_resp[1 + MX_WIFI_PING_MAX]; + wifi_ping_rparams_t *rp; + uint16_t rp_size = sizeof(ping_resp); + int32_t i = 0; + + if ((NULL == Obj) || (NULL == hostname) || (count <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + int32_t msize; + memset(&cp, 0, sizeof(cp)); + msize = MIN(sizeof(cp.hostname), strlen(hostname) + 1); + memcpy(&(cp.hostname[0]), hostname, msize); + cp.count = count; + cp.delay_ms = delay; + memset(ping_resp, 0, sizeof(ping_resp)); + rp = (wifi_ping_rparams_t *)&ping_resp; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_PING_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp->num > 0) + { + for (i = 0; i < rp->num; i++) + { + response[i] = rp->delay_ms[i]; + } + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +#if 0 +/** + * @brief Get IPv4/v6 address info by nodename. + * @param Obj: pointer to module handle + * @param nodename: descriptive name or address string of the host + * @param servname: not used, set NULL + * @param hints: structure containing input values that set socktype and protocol + * @param res: buf to store the result (set to NULL on failure) + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_getaddrinfo(MX_WIFIObject_t *Obj, const char *nodename, const char *servname, + const struct addrinfo *hints, struct mc_addrinfo *res) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_val; + int32_t addr_ret_flag; + int32_t *p_addr_ret_val; + int32_t *p_addr_ret_flag; + + if ((NULL == Obj) || (NULL == nodename) || (NULL == hints) || (NULL == res)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + p_addr_ret_val = &ret; + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val)); + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == socket_getaddrinfo_cmd(nodename, (int32_t)strlen(nodename), + servname, (int32_t)strlen(servname), + (void *)hints, sizeof(struct addrinfo), (int)res, + addr_ret_val, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, Obj->Runtime.Timeout)) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Monitor multiple file descriptors for sockets + * @attention Never doing operations in different threads + * @param Obj: pointer to module handle + * @param nfds: is the highest-numbered file descriptor in any of the three + * sets, plus 1 + * @param readfds: A file descriptor sets will be watched to see if characters + * become available for reading + * @param writefds: A file descriptor sets will be watched to see if a write + * will not block. + * @param exceptfds: A file descriptor sets will be watched for exceptions. + * @param timeout: The timeout argument specifies the interval that select() + * should block waiting for a file descriptor to become ready. + * If timeout is NULL (no timeout), select() can block until API timeout. + * @retval On success, return the number of file descriptors contained in the + * three returned descriptor sets (that is, the total number of bits + * that are set in readfds, writefds, exceptfds) which may be zero if + * the timeout expires before anything interesting happens. On error, + * -1 is returned, the file descriptor sets are unmodified, and timeout + * becomes undefined. + */ +int32_t MX_WIFI_Socket_select(MX_WIFIObject_t *Obj, int32_t nfds, fd_set *readfds, fd_set *writefds, + fd_set *exceptfds, struct mc_timeval *timeout) +{ + int32_t ret = -1; /* error */ + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t *p_ret_flag; + int32_t addr_ret_flag; + + if ((NULL != Obj) && (nfds > 0) && ((NULL != readfds) || (NULL != writefds) || (NULL != exceptfds))) + { + p_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_flag, &p_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == socket_select_cmd(nfds, readfds, sizeof(fd_set), + writefds, sizeof(fd_set), + exceptfds, sizeof(fd_set), + timeout, sizeof(struct mc_timeval), + addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, NULL, 200)) + { + ret = mc_select_ret_value; + if (ret > 0) + { + if (readfds) + { + (void)memcpy(readfds, &mc_select_rfds, sizeof(fd_set)); + } + if (writefds) + { + (void)memcpy(writefds, &mc_select_wfds, sizeof(fd_set)); + } + if (exceptfds) + { + (void)memcpy(exceptfds, &mc_select_efds, sizeof(fd_set)); + } + } + mc_select_ret_value = -1; + } + } + } + return ret; +} +#endif /* 0 */ + +/** + * @brief socket getpeername. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: address buffer + * @param addrlen: size of address buffer + * @retval get address of peer socket, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_getpeername(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen) +{ + int32_t ret = -1; + socket_getpeername_cparams_t cp; + socket_getpeername_rparams_t rp; + uint16_t rp_size = sizeof(rp); + + if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (NULL == addrlen) || (*addrlen <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.s = sockfd; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETPEERNAME_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == rp.status) + { + memcpy(addr, &(rp.name), sizeof(rp.name)); + *addrlen = rp.namelen; + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief socket getsockname. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: address buffer + * @param addrlen: size of address buffer + * @retval get address of local socket, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_getsockname(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen) +{ + int32_t ret = -1; + socket_getsockname_cparams_t cp; + socket_getsockname_rparams_t rp; + uint16_t rp_size = sizeof(rp); + rp.status = MIPC_CODE_ERROR; + + if ((NULL == Obj) || (sockfd < 0) || (NULL == addr) || (NULL == addrlen) || (*addrlen <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.s = sockfd; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_SOCKET_GETSOCKNAME_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == rp.status) + { + memcpy(addr, &(rp.name), sizeof(rp.name)); + *addrlen = rp.namelen; + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/* mDNS */ + +/** + * @brief start mDNS service. + * @param Obj: pointer to module handle + * @param domain: domain of service + * @param name: hostname + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_start(MX_WIFIObject_t *Obj, const char *domain, char *hostname) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_start_cparams_t cparams; + int32_t status; + uint16_t out_size = sizeof(status); + status = MIPC_CODE_ERROR; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + memcpy(&(cparams.domain[0]), domain, sizeof(cparams.domain)); + memcpy(&(cparams.hostname[0]), hostname, sizeof(cparams.hostname)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_START_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + + return ret; +} + +/** + * @brief stop mDNS service. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_stop(MX_WIFIObject_t *Obj) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + int32_t status = MIPC_CODE_ERROR; + uint16_t rparams_size; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + rparams_size = sizeof(status); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_STOP_CMD, NULL, 0, + (uint8_t *)&status, &rparams_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief announce a service. + * @param Obj: pointer to module handle + * @param service: service to announce + * @param interface: wifi interface + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_announce_service(MX_WIFIObject_t *Obj, + struct mc_mdns_service *service, mwifi_if_t interface) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_announce_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if ((NULL == Obj) || (NULL == service)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + cparams.iface = interface; + memcpy(&(cparams.service_data), service, sizeof(cparams.service_data)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_ANNOUNCE_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + + return ret; +} + +/** + * @brief deannounce a service. + * @param Obj: pointer to module handle + * @param service: service to deannounce + * @param interface: wifi interface + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_deannounce_service(MX_WIFIObject_t *Obj, + struct mc_mdns_service *service, + mwifi_if_t interface) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_deannounce_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if ((NULL == Obj) || (NULL == service)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + cparams.iface = interface; + memcpy(&(cparams.service_data), service, sizeof(cparams.service_data)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_DEANNOUNCE_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + + return ret; +} + +/** + * @brief deannounce all services. + * @param Obj: pointer to module handle + * @param interface: wifi interface + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_deannounce_service_all(MX_WIFIObject_t *Obj, mwifi_if_t interface) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_deannounce_all_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + cparams.iface = interface; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_DEANNOUNCE_ALL_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + + return ret; +} + +/** + * @brief Send interface state change event to mdns + * @param Obj: pointer to module handle + * @param interface: wifi interface + * @param state: state event, valid interface state from \ref iface_state + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_iface_state_change(MX_WIFIObject_t *Obj, mwifi_if_t interface, + enum iface_state state) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_iface_state_change_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + cparams.iface = interface; + cparams.state = state; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_IFACE_STATE_CHANGE_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + + return ret; +} + +/** + * @brief Set new host name, use mdns_iface_state_change(interface, REANNOUNCE) to anounce + * the new host name. + * @param Obj: pointer to module handle + * @param hostname: new hostname + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_set_hostname(MX_WIFIObject_t *Obj, char *hostname) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_set_hostname_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + strncpy(cparams.hostname, hostname, MDNS_MAX_LABEL_LEN); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_SET_HOSTNAME_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief sets the TXT record field for a given mDNS service. + * @param Obj: pointer to module handle + * @param service: mDNS service + * @param keyvals: new txt record string + * @param separator: the separator used to separate individual key value pairs + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_set_txt_rec(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, char *keyvals, + char separator) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + mdns_set_txt_rec_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + memset(&cparams, 0, sizeof(cparams)); + memcpy(&(cparams.service_data), service, sizeof(cparams.service_data)); + strncpy(cparams.keyvals, keyvals, MDNS_MAX_KEYVAL_LEN); + cparams.separator = separator; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_MDNS_SET_TXT_REC_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/* TLS */ + +/** + * @brief set the TLS protocol version. + * @param Obj: pointer to module handle + * @param version: TLS protocol version + * @retval Operation Status. + * @note This function should be called before TLS is ready to function (before + * mtls_connect and mtls_accept is called by application ). + */ +int32_t MX_WIFI_TLS_set_ver(MX_WIFIObject_t *Obj, mtls_ver_t version) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + tls_set_ver_cparams_t cp; + tls_set_ver_rparams_t rp; + uint16_t out_size = sizeof(rp); + + if ((NULL == Obj)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.version = version; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_VER_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == rp.ret) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + + return ret; +} + +/** + * @brief TLS set client certificate + * @param Obj: pointer to module handle + * @param client_cert: Point to buffer of client cert. + * @param cert_len: length of the client cert. + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_set_clientCertificate(MX_WIFIObject_t *Obj, uint8_t *client_cert, uint16_t cert_len) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + tls_set_client_cert_cparams_t *cp; + uint16_t cp_size; + tls_set_client_cert_rparams_t rp; + uint16_t out_size = sizeof(rp); + + cp_size = sizeof(tls_set_client_cert_cparams_t) -1 + cert_len; + if ((NULL == Obj) || (NULL == client_cert) || (cert_len == (uint16_t)0) + || (cp_size > (uint16_t)(MX_WIFI_IPC_PAYLOAD_SIZE))) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp = (tls_set_client_cert_cparams_t *)MX_WIFI_MALLOC(cp_size); + if (NULL != cp) + { + memset(cp, 0, cp_size); + cp->cert_pem_size = cert_len; + cp->private_key_pem_size = 0; + memcpy(&(cp->cert_data[0]), client_cert, cert_len); + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_CLIENT_CERT_CMD, + (uint8_t *)cp, cp_size, + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == rp.ret) + { + ret = MX_WIFI_STATUS_OK; + } + } + MX_WIFI_FREE(cp); + } + } + + return ret; +} + +/** + * @brief TLS set client private key + * @param Obj: pointer to module handle + * @param client_private_key: Point to buffer of client private key. + * @param key_len: length of the client cert. + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_set_clientPrivateKey(MX_WIFIObject_t *Obj, uint8_t *client_private_key, uint16_t key_len) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + tls_set_client_cert_cparams_t *cp; + uint16_t cp_size; + tls_set_client_cert_rparams_t rp; + uint16_t out_size = sizeof(rp); + + cp_size = sizeof(tls_set_client_cert_cparams_t) -1 + key_len; + if ((NULL == Obj) || (NULL == client_private_key) || (key_len == (uint16_t)0) + || (cp_size > (uint16_t)(MX_WIFI_IPC_PAYLOAD_SIZE))) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp = (tls_set_client_cert_cparams_t *)MX_WIFI_MALLOC(cp_size); + if (NULL != cp) + { + memset(cp, 0, cp_size); + cp->cert_pem_size = 0; + cp->private_key_pem_size = key_len; + memcpy(&(cp->cert_data[0]), client_private_key, key_len); + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_CLIENT_CERT_CMD, + (uint8_t *)cp, cp_size, + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == rp.ret) + { + ret = MX_WIFI_STATUS_OK; + } + } + MX_WIFI_FREE(cp); + } + } + return ret; +} + +/** + * @brief TLS client create a TLS connection. + * @param Obj: pointer to module handle + * @details This function is called on the client side and initiates an TLS/TLS handshake with a + * server. When this function is called, the underlying communication channel has already + * been set up. This function is called after TCP 3-way handshake finished. + * @param domain: Specifies a communication domain + * @param type: Specifies the communication semantics. + * @param protocol: specifies a particular protocol to be used with the socket. + * @param addr: Point to the target address to be connected + * @param addrlen: containing the size of the buffer pointed to by addr + * @param ca: pointer to the CA certificate string, used to verify server's certificate. + * @param calen: the string length of ca. 0=do not verify server's certificate. + * @retval return the TLS context pointer on success or NULL for fail. + */ +int32_t MX_WIFI_TLS_connect(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol, + const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + (void)domain; + (void)type; + (void)protocol; + + if ((NULL == Obj) || (NULL == addr) || (addrlen <= 0)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + ret = MX_WIFI_TLS_connect_sni(Obj, NULL, 0, addr, addrlen, ca, calen); + } + + return ret; +} + +/** + * @brief TLS client create a TLS connection with SNI. + * @param Obj: pointer to module handle + * @details This function is called on the client side and initiates an TLS/TLS handshake with a + * server. When this function is called, the underlying communication channel has already + * been set up. This function is called after TCP 3-way handshake finished. + * @param sni_servername: Specifies the SNI server name + * @param sni_servername_len: Specifies the SNI server name length, max size MX_TLS_SNI_SERVERNAME_SIZE + * @param addr: Point to the target address to be connected + * @param addrlen: containing the size of the buffer pointed to by addr + * @param ca: pointer to the CA certificate string, used to verify server's certificate. + * @param calen: the string length of ca. 0=do not verify server's certificate. + * @retval return the TLS context pointer on success or NULL for fail. + */ +int32_t MX_WIFI_TLS_connect_sni(MX_WIFIObject_t *Obj, const char *sni_servername, int32_t sni_servername_len, + const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + tls_connect_sni_cparams_t *cp; + uint16_t cp_size; + tls_connect_sni_rparams_t rp; + uint16_t out_size = sizeof(rp); + + cp_size = sizeof(tls_connect_sni_cparams_t) -1 + calen; + if ((NULL == Obj) || (NULL == addr) || (addrlen <= 0) || (cp_size > (uint16_t)(MX_WIFI_IPC_PAYLOAD_SIZE))) + { + ret = 0; /* null for MX_WIFI_STATUS_PARAM_ERROR */ + } + else + { + rp.tls = NULL; + cp = (tls_connect_sni_cparams_t *)MX_WIFI_MALLOC(cp_size); + if (NULL != cp) + { + memset(cp, 0, cp_size); + if ((sni_servername_len > 0) && (NULL != sni_servername)) + { + strncpy(&(cp->sni_servername[0]), sni_servername, sizeof(cp->sni_servername)); + } + memcpy(&(cp->addr), addr, sizeof(cp->addr)); + cp->length = addrlen; + cp->calen = calen; + if ((calen > 0) && (NULL != ca)) + { + memcpy(&(cp->ca[0]), ca, calen); + } + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_CONNECT_SNI_CMD, + (uint8_t *)cp, cp_size, + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (NULL == rp.tls) + { + ret = 0; /* NULL */ + } + else + { + ret = (int32_t)rp.tls; + } + } + MX_WIFI_FREE(cp); + } + } + + return ret; +} + +/** + * @brief TLS send data + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @param data: Point to data to send. + * @param len: data length. + * @retval On success, return the number of bytes sent. + * On error, error code (< 0) is returned. + */ +int32_t MX_WIFI_TLS_send(MX_WIFIObject_t *Obj, mtls_t tls, void *data, int32_t len) +{ + int32_t ret = -1; + tls_send_cparams_t *cp; + uint16_t cp_size; + tls_send_rparams_t rp; + uint16_t rp_size = sizeof(rp); + int32_t datalen; + + if ((NULL == Obj) || (NULL == tls) || (NULL == data) || (len <= 0)) + { + ret = -1; + } + else + { + rp.sent = 0; + if ((len + sizeof(tls_send_cparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE) + { + datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(tls_send_cparams_t) - 1)); + } + else + { + datalen = len; + } + cp_size = (sizeof(tls_send_cparams_t) - 1 + datalen); + cp = (tls_send_cparams_t *)MX_WIFI_MALLOC(cp_size); + if (NULL != cp) + { + cp->tls = tls; + memcpy(&(cp->buffer[0]), data, datalen); + cp->size = datalen; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SEND_CMD, + (uint8_t *)cp, cp_size, + (uint8_t *)&rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + ret = rp.sent; + } + MX_WIFI_FREE(cp); + } + } + return ret; +} + +/** + * @brief TLS redeive data + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @param data: Point to buffer to receive TLS data. + * @param len: max receive buffer length. + * @retval On success, return the number of bytes received. + * On error, error code (< 0) is returned. + */ +int32_t MX_WIFI_TLS_recv(MX_WIFIObject_t *Obj, mtls_t tls, void *buf, int32_t len) +{ + int32_t ret = -1; + tls_recv_cparams_t cp; + tls_recv_rparams_t *rp; + uint16_t rp_size; + int32_t datalen; + + if ((NULL == Obj) || (NULL == tls) || (NULL == buf) || (len <= 0)) + { + ret = -1; + } + else + { + ret = 0; + if ((len + sizeof(tls_recv_rparams_t) - 1) > MX_WIFI_IPC_PAYLOAD_SIZE) + { + datalen = (MX_WIFI_IPC_PAYLOAD_SIZE - (sizeof(tls_recv_rparams_t) - 1)); + } + else + { + datalen = len; + } + rp_size = (sizeof(tls_recv_rparams_t) - 1 + datalen); + rp = (tls_recv_rparams_t *)MX_WIFI_MALLOC(rp_size); + if (NULL != rp) + { + rp->received = 0; + cp.tls = tls; + cp.size = datalen; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_RECV_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)rp, &rp_size, + MX_WIFI_CMD_TIMEOUT)) + { + if ((rp->received <= datalen) && (rp->received > 0)) + { + memcpy(buf, &(rp->buffer[0]), rp->received); + } + ret = rp->received; + } + MX_WIFI_FREE(rp); + } + } + return ret; +} + +/** + * @brief Close the TLS session, release resource. + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_close(MX_WIFIObject_t *Obj, mtls_t tls) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + tls_close_cparams_t cp; + tls_close_rparams_t rp; + uint16_t out_size = sizeof(rp); + + if ((NULL == Obj) || (NULL == tls)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.tls = tls; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_CLOSE_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.ret == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Set TLS nonblock mode. + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @param nonblock: true - nonblock, false - block + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_set_nonblock(MX_WIFIObject_t *Obj, mtls_t tls, int32_t nonblock) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + tls_set_nonblock_cparams_t cp; + tls_set_nonblock_rparams_t rp; + uint16_t out_size = sizeof(rp); + + if ((NULL == Obj) || (NULL == tls)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cp.tls = tls; + cp.nonblock = nonblock; + memset(&rp, 0, sizeof(rp)); + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_TLS_SET_NONBLOCK_CMD, + (uint8_t *)&cp, sizeof(cp), + (uint8_t *)&rp, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (rp.ret == MIPC_CODE_SUCCESS) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Start webserver. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +int32_t MX_WIFI_Webserver_start(MX_WIFIObject_t *Obj) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_val; + int32_t addr_ret_flag; + int32_t *p_addr_ret_val; + int32_t *p_addr_ret_flag; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + p_addr_ret_val = &ret; + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val)); + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == web_start_cmd(addr_ret_val, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout)) + { + ret = MX_WIFI_STATUS_OK; + } + } + } +#endif /* 0 */ + + return ret; +} + +/** + * @brief Stop webserver. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +int32_t MX_WIFI_Webserver_stop(MX_WIFIObject_t *Obj) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_val; + int32_t addr_ret_flag; + int32_t *p_addr_ret_val; + int32_t *p_addr_ret_flag; + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + p_addr_ret_val = &ret; + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val)); + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == web_stop_cmd(addr_ret_val, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout)) + { + ret = MX_WIFI_STATUS_OK; + } + } + } +#endif /* 0 */ + + return ret; +} + +/** + * @brief Start FOTA. + * @param Obj: pointer to module handle + * @param url: HTTP/HTTPS url of bin file to update + * @param md5: MD5 string(32Bytes) of bin file to update + * @param ota_status_callback: callback function for ota status + * @retval Operation Status. + */ +int32_t MX_WIFI_FOTA_start(MX_WIFIObject_t *Obj, const char *url, const char *md5, + mx_wifi_fota_status_cb_t fota_status_callback, uint32_t user_args) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + +#if 0 + int32_t ret_flag = MIPC_RET_FLAG_CLR; + int32_t addr_ret_val; + int32_t addr_ret_flag; + int32_t *p_addr_ret_val; + int32_t *p_addr_ret_flag; + + if ((NULL == Obj) || (NULL == url) || (NULL == md5)) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (NULL != fota_status_callback) + { + Obj->Runtime.fota_status_cb = fota_status_callback; + Obj->Runtime.fota_user_args = user_args; + } + else + { + Obj->Runtime.fota_status_cb = NULL; + Obj->Runtime.fota_user_args = 0; + } + + p_addr_ret_val = &ret; + p_addr_ret_flag = &ret_flag; + (void)memcpy(&addr_ret_val, &p_addr_ret_val, sizeof(addr_ret_val)); + (void)memcpy(&addr_ret_flag, &p_addr_ret_flag, sizeof(addr_ret_flag)); + if (MIPC_CODE_SUCCESS == fota_start_cmd(url, (int32_t)strlen(url), md5, (int32_t)strlen(md5), + addr_ret_val, addr_ret_flag)) + { + if (MIPC_CODE_SUCCESS == mipc_poll(&ret_flag, &ret, Obj->Runtime.Timeout)) + { + ret = MX_WIFI_STATUS_OK; + } + } + } +#endif /* 0 */ + + return ret; +} + +#else /* MX_WIFI_NETWORK_BYPASS_MODE */ + +/** + * @brief Set network bypass mode + * @param Obj: pointer to module handle + * @param enable: 0=disable, 1=enable + * @param netlink_input_callbck: input data callback function + * @param user_args: user arguments for callback function + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Network_bypass_mode_set(MX_WIFIObject_t *Obj, int32_t enable, + mx_wifi_netlink_input_cb_t netlink_input_callbck, + void *user_args) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + wifi_bypass_set_cparams_t cparams; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if ((NULL != netlink_input_callbck) && (1 == enable)) + { + Obj->Runtime.netlink_input_cb = netlink_input_callbck; + Obj->Runtime.netlink_user_args = user_args; + } + else + { + Obj->Runtime.netlink_input_cb = NULL; + Obj->Runtime.netlink_user_args = NULL; + } + + cparams.mode = enable; + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_BYPASS_SET_CMD, + (uint8_t *)&cparams, sizeof(cparams), + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + +/** + * @brief Network bypass mode data output + * @param Obj: pointer to module handle + * @param pbuf: pbuf data to send + * @param size: pbuf size + * @param data: pbuf payload + * @param len: payload len + * @param interface: STATION_IDX, SOFTAP_IDX(not supported now) + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Network_bypass_netlink_output(MX_WIFIObject_t *Obj, void *data, + int32_t len, + int32_t interface) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + wifi_bypass_out_cparams_t *cparams; + uint16_t cparams_size; + int32_t status = MIPC_CODE_ERROR; + uint16_t rparams_size = sizeof(status); + + if ((NULL == Obj) || (len <= 0) || \ + (((int32_t)STATION_IDX != interface) && ((int32_t)SOFTAP_IDX != interface))) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + cparams_size = sizeof(wifi_bypass_out_cparams_t) + len; + if (cparams_size > MX_WIFI_IPC_PAYLOAD_SIZE) + { + len = MX_WIFI_IPC_PAYLOAD_SIZE - sizeof(wifi_bypass_out_cparams_t); + return MX_WIFI_STATUS_PARAM_ERROR; + } +#if MX_WIFI_TX_BUFFER_NO_COPY + /* structure of data buffer must support head room provision to add information in from of data payload */ + cparams = (wifi_bypass_out_cparams_t *)((uint8_t *)data - sizeof(wifi_bypass_out_cparams_t)); +#else + cparams = (wifi_bypass_out_cparams_t *)MX_WIFI_MALLOC(len + sizeof(wifi_bypass_out_cparams_t)); +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + + if (NULL != cparams) + { + cparams->idx = interface; + cparams->data_len = len; + +#if MX_WIFI_TX_BUFFER_NO_COPY == 0 + /* copy the whole payload */ + uint8_t *dst; + dst = (uint8_t *)cparams + sizeof(wifi_bypass_out_cparams_t); + memcpy(dst, data, len); +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + + if (MIPC_CODE_SUCCESS == mipc_request(MIPC_API_WIFI_BYPASS_OUT_CMD, + (uint8_t *)cparams, cparams_size, + (uint8_t *)&status, &rparams_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } +#if MX_WIFI_TX_BUFFER_NO_COPY == 0 + MX_WIFI_FREE(cparams); +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + } + else + { + /* no memory */ + DEBUG_LOG("No memory!!!\n"); + } + } + + return ret; +} +#endif /* MX_WIFI_NETWORK_BYPASS_MODE */ + +/** + * @brief set powersave onoff for wifi station mode. + * @param Obj: pointer to module handle + * @param ps_onoff: 0 -- powersave off, 1 -- powersave on + * @retval Operation Status. + */ +int32_t MX_WIFI_station_powersave(MX_WIFIObject_t *Obj, int32_t ps_onoff) +{ + int32_t ret = MX_WIFI_STATUS_ERROR; + uint16_t mipc_ps_cmd; + int32_t status = MIPC_CODE_ERROR; + uint16_t out_size = sizeof(status); + + if (NULL == Obj) + { + ret = MX_WIFI_STATUS_PARAM_ERROR; + } + else + { + if (ps_onoff) + { + mipc_ps_cmd = MIPC_API_WIFI_PS_ON_CMD; + } + else + { + mipc_ps_cmd = MIPC_API_WIFI_PS_OFF_CMD; + } + if (MIPC_CODE_SUCCESS == mipc_request(mipc_ps_cmd, NULL, 0, + (uint8_t *)&status, &out_size, + MX_WIFI_CMD_TIMEOUT)) + { + if (MIPC_CODE_SUCCESS == status) + { + ret = MX_WIFI_STATUS_OK; + } + } + } + return ret; +} + diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi.h new file mode 100644 index 00000000000..e7aba01f378 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi.h @@ -0,0 +1,1510 @@ +/** + ****************************************************************************** + * @file mx_wifi.h + * @author MCD Application Team + * @brief Header for mx_wifi.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_H +#define MX_WIFI_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "mx_wifi_conf.h" + + +/** + * @defgroup MX_WIFI Wi-Fi_API + * @brief Driver API on STM32 for MXCHIP Wi-Fi module, see mx_wifi.h + * @{ ** + */ + +/* API version V2.1.8 */ +#define MX_WIFI_API_VERSION_MAJ (2) +#define MX_WIFI_API_VERSION_SUB (1) +#define MX_WIFI_API_VERSION_REV (10) + +/******************************************************************************* + * MXCHIP Wi-Fi Module Defines + ******************************************************************************/ +/* common defines */ +#define MX_MAX_IP_LEN (16) +#define MX_MAX_SSID_LEN (32) +#define MX_MAX_KEY_LEN (64) +#define MX_MAX_BSSID_LEN (6) +#define MX_MAX_DNSNAME_LEN (253) +#define MX_MAX_IDENTITY_LEN (32) +#define MX_TLS_SNI_SERVERNAME_SIZE (128) +#define MX_SERVICE_NAME_SIZE (255) +#define MC_WIFI_INTERFACE_NUM (2) +#define MX_WIFI_PING_MAX (10) + +#define MX_WIFI_SCAN_TIMEOUT (5000) + +/** + * @brief Wi-Fi mode + */ +enum +{ + MC_SOFTAP, /**< wifi softap mode. */ + MC_STATION /**< wifi station mode. */ +}; + +typedef uint8_t mwifi_if_t; /**< wifi mode. */ + +/** + * @brief Wi-Fi scan mode + */ +enum +{ + MC_SCAN_PASSIVE = 0, /**< wifi passive scan mode. */ + MC_SCAN_ACTIVE = 1 /**< wifi active scan mode. */ +}; + +typedef uint8_t mc_wifi_scan_mode_t; /**< wifi scan mode. */ + +/** + * @brief Wi-Fi ip address info + */ +typedef struct +{ + char localip[MX_MAX_IP_LEN]; /**< lcoal ip address */ + char netmask[MX_MAX_IP_LEN]; /**< netmask */ + char gateway[MX_MAX_IP_LEN]; /**< gateway ip address */ + char dnserver[MX_MAX_IP_LEN]; /**< dns server ip address */ +} mwifi_ip_attr_t; /**< wifi ip address info. */ + +/** + * @brief Wi-Fi EAP type + */ +typedef enum +{ + EAP_TYPE_TLS = 13, /* RFC 2716 */ + EAP_TYPE_TTLS = 21, /* RFC 5281 */ + EAP_TYPE_PEAP = 25 /* draft-josefsson-pppext-eap-tls-eap-06.txt */ +} EapType; + +/** + * @brief Wi-Fi EAP info + */ +typedef struct +{ + uint8_t eap_type; /* support: EAP_TYPE_PEAP, EAP_TYPE_TTLS, EAP_TYPE_TLS */ + const char *rootca; /* the EAP server rootca. NULL for don't check the server's certificate */ + const char *client_cert; /* client cert, only need this if the server need check the client's certificate, + such as EAP_TYPE_TLS mode. */ + const char *client_key; /* client private key. DONOT support encrypted key. */ +} mwifi_eap_attr_t; + +/******************************************************************************* + * STM32Cube Driver API Defines + ******************************************************************************/ +/* status code */ +#define MX_WIFI_STATUS_OK (0) /**< status code success. */ +#define MX_WIFI_STATUS_ERROR (-1) /**< status code common error. */ +#define MX_WIFI_STATUS_TIMEOUT (-2) /**< status code timeout. */ +#define MX_WIFI_STATUS_IO_ERROR (-3) /**< status code I/O error. */ +#define MX_WIFI_STATUS_PARAM_ERROR (-4) /**< status code bad argument error. */ +#define MX_WIFI_STATUS_T int32_t /**< status code. */ + +/* macro */ +#define MX_WIFI_MAC_SIZE (6) /**< max length of MAC address. */ +#define MX_WIFI_SCAN_BUF_SIZE (2000) /**< max size of scan buffer. */ + +#define MIN(a, b) ( ((a) < (b)) ? (a) : (b)) /**< helper function: get minimum. */ + +#if 0 +/* IPv6 address states. */ +#define IP6_ADDR_INVALID 0x00 +#define IP6_ADDR_TENTATIVE 0x08 +#define IP6_ADDR_TENTATIVE_1 0x09 /* 1 probe sent */ +#define IP6_ADDR_TENTATIVE_2 0x0a /* 2 probes sent */ +#define IP6_ADDR_TENTATIVE_3 0x0b /* 3 probes sent */ +#define IP6_ADDR_TENTATIVE_4 0x0c /* 4 probes sent */ +#define IP6_ADDR_TENTATIVE_5 0x0d /* 5 probes sent */ +#define IP6_ADDR_TENTATIVE_6 0x0e /* 6 probes sent */ +#define IP6_ADDR_TENTATIVE_7 0x0f /* 7 probes sent */ +#define IP6_ADDR_VALID 0x10 +#define IP6_ADDR_PREFERRED 0x30 +#define IP6_ADDR_DEPRECATED 0x50 +#endif /* 0 */ + +/* +#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID) +#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE) +#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) +#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED) +#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED) + */ + +/** + * @brief Security settings for wifi network + */ +typedef enum +{ + MX_WIFI_SEC_NONE, /**< Open system. */ + MX_WIFI_SEC_WEP, /**< Wired Equivalent Privacy. WEP security. */ + MX_WIFI_SEC_WPA_TKIP, /**< WPA /w TKIP */ + MX_WIFI_SEC_WPA_AES, /**< WPA /w AES */ + MX_WIFI_SEC_WPA2_TKIP, /**< WPA2 /w TKIP */ + MX_WIFI_SEC_WPA2_AES, /**< WPA2 /w AES */ + MX_WIFI_SEC_WPA2_MIXED, /**< WPA2 /w AES or TKIP */ + MX_WIFI_SEC_AUTO /**< It is used when calling @ref mwifi_connect, + MXOS read security type from scan result. */ +} MX_WIFI_SecurityType_t; + +typedef int8_t (*IO_Init_Func)(uint16_t mode); /**< I/O interface init function. */ +typedef int8_t (*IO_DeInit_Func)(void); /**< I/O interface deinit function. */ +typedef void (*IO_Delay_Func)(uint32_t ms); /**< I/O interface delay function. */ +typedef uint16_t (*IO_Send_Func)(uint8_t *data, uint16_t len); /**< I/O interface send function. */ +typedef uint16_t (*IO_Receive_Func)(uint8_t *buffer, uint16_t buff_size); /**< I/O interface receive function. */ + +/** + * @brief Wi-Fi low level I/O interface operation handles + */ +typedef struct +{ + IO_Init_Func IO_Init; /**< I/O interface init function. */ + IO_DeInit_Func IO_DeInit; /**< I/O interface deinit function. */ + IO_Delay_Func IO_Delay; /**< I/O interface delay function. */ + IO_Send_Func IO_Send; /**< I/O interface send function. */ + IO_Receive_Func IO_Receive; /**< I/O interface receive function. */ +} MX_WIFI_IO_t; + +/** + * @brief Wi-Fi system info + */ +typedef struct +{ + /* FW info */ + uint8_t Product_Name[MX_WIFI_PRODUCT_NAME_SIZE];/**< product name. */ + uint8_t Product_ID[MX_WIFI_PRODUCT_ID_SIZE]; /**< product ID. */ + uint8_t FW_Rev[MX_WIFI_FW_REV_SIZE]; /**< firmware version. */ + uint8_t MAC[MX_WIFI_MAC_SIZE]; /**< Wi-Fi MAC address. */ +} MX_WIFI_SystemInfo_t; + +/** + * @brief Wi-Fi station info + */ +typedef struct +{ + /* wifi station setting */ + uint8_t SSID[MX_WIFI_MAX_SSID_NAME_SIZE + 1]; /**< Wi-Fi station SSID. */ + uint8_t pswd[MX_WIFI_MAX_PSWD_NAME_SIZE + 1]; /**< Wi-Fi station passwd. */ + MX_WIFI_SecurityType_t Security; /**< Wi-Fi station security. */ + uint8_t DHCP_IsEnabled; /**< Wi-Fi station DHCP. */ + /* status */ + int8_t IsConnected; /**< Wi-Fi station connection status. */ + /*ipv4 */ + uint8_t IP_Addr[4]; /**< Wi-Fi station IP address. */ + uint8_t IP_Mask[4]; /**< Wi-Fi station IP mask. */ + uint8_t Gateway_Addr[4]; /**< Wi-Fi station gateway. */ + uint8_t DNS1[4]; /**< Wi-Fi station DNS server. */ + /* ipv6 */ + int32_t IP6_state[3]; /**< Wi-Fi station IPv6 address state. */ + uint8_t IP6_Addr[3][16]; /**< Wi-Fi station IPv6 address. */ + uint8_t IP6_Mask[16]; /**< Wi-Fi station IPv6 mask. */ + uint8_t Gateway6_Addr[16]; /**< Wi-Fi station IPv6 gateway. */ + uint8_t IP6_DNS1[16]; /**< Wi-Fi station IPv6 DNS server. */ +} MX_WIFI_Network_t; + +/** + * @brief Wi-Fi softAP info + */ +typedef struct +{ + char SSID[MX_WIFI_MAX_SSID_NAME_SIZE + 1]; /**< Wi-Fi softAP SSID. */ + char pswd[MX_WIFI_MAX_PSWD_NAME_SIZE + 1]; /**< Wi-Fi softAP password. */ + /* MX_WIFI_SecurityType_t Security; OPEN: no passwd, WPA2: has passwd, NOT SUPPORTED NOW */ + uint8_t channel; /**< Wi-Fi softAP Channel. */ + mwifi_ip_attr_t ip; /**< Wi-Fi softAP IP settings. */ +} MX_WIFI_APSettings_t; + +/** Prototype of Wi-Fi status changed callback function. */ +/** + * @param cate wifi status: MC_STATION, MC_SOFTAP + * @param event wifi events: MWIFI_EVENT_STA_DOWN, + * MWIFI_EVENT_STA_UP, + * WIFI_EVENT_STA_GOT_IP, + * MWIFI_EVENT_AP_UP, + * MWIFI_EVENT_AP_DOWN + * @param arg user argument passed by @MX_WIFI_RegisterStatusCallback + */ +typedef void (*mx_wifi_status_callback_t)(uint8_t cate, uint8_t event, void *arg); + +/** + * @brief FOTA status + */ +typedef enum +{ + MX_WIFI_FOTA_SUCCESS, + MX_WIFI_FOTA_FAILED +} mx_wifi_fota_status_e; + +/** + * @brief Prototype of FOTA status callback function + */ +typedef void (*mx_wifi_fota_status_cb_t)(mx_wifi_fota_status_e status, uint32_t user_args); + +/** + * @brief Prototype of netlink input callback function for network bypass mode + */ +typedef void (*mx_wifi_netlink_input_cb_t)(mx_buf_t *pbuf, void *user_args); + +/** + * @brief Wi-Fi runtime info + */ +typedef struct +{ + uint32_t Timeout; /**< Wi-Fi cmd timeout in ms. */ + + mx_wifi_status_callback_t status_cb[MC_WIFI_INTERFACE_NUM]; /**< Wi-Fi status callback. */ + void *callback_arg[MC_WIFI_INTERFACE_NUM]; /**< Wi-Fi status callback argument. */ + + mx_wifi_fota_status_cb_t fota_status_cb; /**< FOTA status callback. */ + uint32_t fota_user_args; /**< FOTA status callback argument. */ + + mx_wifi_netlink_input_cb_t netlink_input_cb; /**< netlink input callback. */ + void *netlink_user_args; /**< netlink input callback argument. */ + + uint8_t scan_result[MX_WIFI_SCAN_BUF_SIZE]; /**< Wi-Fi scan result buffer. */ + uint8_t scan_number; /**< Num of Wi-Fi scan result to get. */ + + uint8_t interfaces; /**< Num of Wi-Fi interfaces inited, 2 if STA+AP inited. */ +} MX_WIFI_Runtime_t; + +/** + * @brief Wi-Fi Wi-Fi object handle + */ +typedef struct +{ + /* HW IO */ + MX_WIFI_IO_t fops; /**< Wi-Fi low level I/O operation handles. */ + + /* system info */ + MX_WIFI_SystemInfo_t SysInfo; /**< Wi-Fi system info. */ + + /* network info */ + MX_WIFI_Network_t NetSettings; /**< Wi-Fi station info. */ + MX_WIFI_APSettings_t APSettings; /**< Wi-Fi softAP info. */ + + /* run time data */ + MX_WIFI_Runtime_t Runtime; /**< Wi-Fi runtime info. */ + + /* wifi obj lock */ + LOCK_DECLARE(lockcmd); +} MX_WIFIObject_t; + + +/* Exported functions --------------------------------------------------------*/ + +/** + * @defgroup MX_WIFI_IO Driver_I/O + * @brief Driver I/O interface setting API + * @{ ** + */ + + +/** + * @brief Register low level IO interface. + * @param Obj wifi object handle. + * @param IO_Init IO init function + * @param IO_DeInit IO de-init function + * @param IO_Delay IO delay function in ms + * @param IO_Send IO send data function + * @param IO_Receive IO receive data function + * + * @return result + * @retval MX_WIFI_STATUS_OK success + * @retval others failure + */ +MX_WIFI_STATUS_T MX_WIFI_RegisterBusIO(MX_WIFIObject_t *Obj, + IO_Init_Func IO_Init, IO_DeInit_Func IO_DeInit, IO_Delay_Func IO_Delay, + IO_Send_Func IO_Send, IO_Receive_Func IO_Receive); +/** + * @brief Reset wifi module by hardware IO. + * @param Obj wifi object handle. + * + * @return result + * @retval MX_WIFI_STATUS_OK success + * @retval others failure + */ +MX_WIFI_STATUS_T MX_WIFI_HardResetModule(MX_WIFIObject_t *Obj); + +/** + * @} ** + */ + +/** + * @defgroup MX_WIFI_INIT Driver_init + * @brief Driver init API + * @{ ** + */ + +/** + * @brief Wi-Fi module init type + */ +typedef enum +{ + MX_WIFI_INIT = 0, /**< Wi-Fi module init(not reboot). */ + MX_WIFI_RESET = 1 /**< Wi-Fi module reset(reboot). */ +} MX_WIFI_InitMode_t; + +/** + * @brief Initialize WIFI module and get module fw & mac info. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Init(MX_WIFIObject_t *Obj); + +/** + * @brief DeInitialize WIFI module. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_DeInit(MX_WIFIObject_t *Obj); + +/** + * @brief Change default Timeout for wifi cmd. + * @param Obj: pointer to module handle + * @param Timeout: Timeout in mS + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_SetTimeout(MX_WIFIObject_t *Obj, uint32_t Timeout); + +/** + * @brief Yield data from Wi-Fi module. + * @param Obj: pointer to module handle + * @param timeout: yield timeout in ms + * @retval Operation Status. + * @note This will be called periodically + */ +MX_WIFI_STATUS_T MX_WIFI_IO_YIELD(MX_WIFIObject_t *Obj, uint32_t timeout); + +/** + * @} ** + */ + +/** + * @defgroup MX_WIFI_NETWORK_BYPASS_MODE Network bypass mode + * @brief Network bypass mode API + * @{ ** + */ + +/** + * @brief Network bypass interface index + */ +enum +{ + STATION_IDX = 0, + SOFTAP_IDX = 1 /* NOT SUPPORTED NOW */ +}; + + +MX_WIFIObject_t *wifi_obj_get(void); + + + +#if (MX_WIFI_NETWORK_BYPASS_MODE == 1) +/** + * @brief Set network bypass mode + * @param Obj: pointer to module handle + * @param enable: 0=disable, 1=enable + * @param netlink_input_callbck: input data callback function + * @param user_args: user arguments for callback function + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Network_bypass_mode_set(MX_WIFIObject_t *Obj, int32_t enable, + mx_wifi_netlink_input_cb_t netlink_input_callbck, void *user_args); + +/** + * @brief Network bypass mode data output + * @param Obj: pointer to module handle + * @param pbuf: pbuf data to send + * @param size: pbuf size + * @param data: pbuf payload + * @param len: payload len + * @param interface: STATION_IDX, SOFTAP_IDX(not supported now) + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Network_bypass_netlink_output(MX_WIFIObject_t *Obj, void *data, + int32_t len, + int32_t interface); +#endif /* MX_WIFI_NETWORK_BYPASS_MODE */ + + +/** + * @brief set powersave onoff for wifi station mode. + * @param Obj: pointer to module handle + * @param ps_onoff: 0 -- powersave off, 1 -- powersave on + * @retval Operation Status. + */ +int32_t MX_WIFI_station_powersave(MX_WIFIObject_t *Obj, int32_t ps_onoff); + + +/** + * @} ** + */ + +enum +{ + MWIFI_EVENT_NONE = 0x00, /* invalid event */ + MWIFI_EVENT_STA_DOWN = 0x01, /**< Wi-Fi station down event. */ + MWIFI_EVENT_STA_UP = 0x02, /**< Wi-Fi station up event. */ + MWIFI_EVENT_STA_GOT_IP = 0X03, /**< Wi-Fi station got ip event. */ + MWIFI_EVENT_AP_DOWN = 0x04, /**< Wi-Fi softap down event. */ + MWIFI_EVENT_AP_UP = 0x05, /**< Wi-Fi softap up event. */ +}; +typedef uint8_t mwifi_status_t; + +/** + * @defgroup MX_WIFI_BASIC Station + * @brief station mode API + * @{ ** + */ + +/** + * @brief Wi-Fi station link info + */ +#pragma pack(1) +typedef struct +{ + uint8_t is_connected; /**< Wi-Fi station connection status. */ + char ssid[MX_MAX_SSID_LEN]; /**< Wi-Fi connection AP ssid to connect. */ + uint8_t bssid[MX_MAX_BSSID_LEN]; /**< Wi-Fi connection AP bssid. */ + uint8_t security; /**< Wi-Fi connection security type. */ + uint8_t channel; /**< Wi-Fi connection channel. */ + int32_t rssi; /**< Wi-Fi connection rssi. */ +} mc_wifi_link_info_t; +#pragma pack() + +/** + * @brief Reset the module by Software. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_ResetModule(MX_WIFIObject_t *Obj); + +/** + * @brief Reset To factory defaults. + * @param Obj: pointer to module handle + * @note NOT USED NOW + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_ResetToFactoryDefault(MX_WIFIObject_t *Obj); + +/** + * @brief Get the firmware version string of the wifi module. + * @param Obj: pointer to module handle + * @param version: buffer pointer to receive the version string. + * @param size: length of the buffer, max size 24Bytes. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_GetVersion(MX_WIFIObject_t *Obj, uint8_t *version, uint32_t size); + +/** + * @brief Get the MAC address of the wifi module. + * @param Obj: pointer to module handle + * @param mac: pointer to the MAC address array, size 6Bytes. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_GetMACAddress(MX_WIFIObject_t *Obj, uint8_t *mac); + +/** + * @brief wifi block scan + * @param Obj: pointer to module handle + * @param scan_mode: scan mode + * @param ssid: ssid for active scan(scan specified AP), not used(set NULL) if do passive scan(scan all APs) + * @param len: ssid len of the AP to scan, not used(set 0) if do passive scan + * @note This API just start scan, use @MX_WIFI_Get_scan_result to get the scan result. + * @code Example: + * Active scan: + * MX_WIFI_Scan(pWifiObj, MC_SCAN_ACTIVE, "ssid_ap", 7); + * Passive scan: + * MX_WIFI_Scan(pWifiObj, MC_SCAN_PASSIVE, NULL, 0); + * + * Get scan result: + * mwifi_ap_info_t mx_aps[MX_WIFI_MAX_DETECTED_AP]; ( array to store scan AP info ) + * int32_t ap_num; + * ap_num = MX_WIFI_Get_scan_result(pWifiObj, (uint8_t*)&(mx_aps[0]), MX_WIFI_MAX_DETECTED_AP); + * if(ap_num > 0) + * { + * for(int32_t i = 0; i < ap_num; i++) + * { + * ( mx_aps[i].ssid ) + * ( mx_aps[i].rssi ) + * } + * } + * @endcode + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Scan(MX_WIFIObject_t *Obj, mc_wifi_scan_mode_t scan_mode, char *ssid, int32_t len); + +/** + * @brief wifi get scan result + * @param Obj: pointer to module handle + * @param results: scan result buffer, contains mwifi_ap_info_t * number + * @param number: max ap number to get, max 10 + * @retval return the real ap number got. + * @note must be called after @MX_WIFI_Scan + */ +int8_t MX_WIFI_Get_scan_result(MX_WIFIObject_t *Obj, uint8_t *results, uint8_t number); + +/** + * @brief Register wifi status changed callback + * @param Obj: pointer to module handle + * @param cb: wifi status callback function + * @param arg: argument pass to callback + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback(MX_WIFIObject_t *Obj, + mx_wifi_status_callback_t cb, void *arg); +MX_WIFI_STATUS_T MX_WIFI_RegisterStatusCallback_if(MX_WIFIObject_t *Obj, + mx_wifi_status_callback_t cb, + void *arg, + mwifi_if_t interface); + +/** + * @brief UnRegister wifi status changed callback + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback(MX_WIFIObject_t *Obj); +MX_WIFI_STATUS_T MX_WIFI_UnRegisterStatusCallback_if(MX_WIFIObject_t *Obj, mwifi_if_t interface); + +/** + * @brief Join an Access point. + * @param Obj: pointer to module handle + * @param Ssid: the access point id. + * @param Password: the Access point password. + * @param SecType: Security type. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Connect(MX_WIFIObject_t *Obj, const char *SSID, + const char *Password, MX_WIFI_SecurityType_t SecType); + +/** + * @brief Join an Access point with WPA-E. + * @param Obj: pointer to module handle + * @param Ssid: the access point ID. + * @param Identity: client identity. + * @param Password: client password. + * @param attr: extral attributes of EAP method. NULL for default mode EAP-PEAP. + * @param ip: Station IP settings, NULL for DHCP mode. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_EAP_Connect(MX_WIFIObject_t *Obj, const char *SSID, + const char *Identity, const char *Password, + mwifi_eap_attr_t *attr, mwifi_ip_attr_t *ip); + +/** + * @brief Disconnect from a network. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_Disconnect(MX_WIFIObject_t *Obj); + +/** + * @brief Join an Access point with WPS (PUSH-BUTTON) mode. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_WPS_Connect(MX_WIFIObject_t *Obj); + +/** + * @brief Stop WPS connect. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_WPS_Stop(MX_WIFIObject_t *Obj); + +/** + * @brief Check whether the module is connected to an access point. + * @retval link status 1: connected, otherwise not connect. + */ +int8_t MX_WIFI_IsConnected(MX_WIFIObject_t *Obj); + +/** + * @brief Get the local IPv4 address of the wifi module. + * @param Obj: pointer to module handle + * @param ipaddr: pointer to the IP address array(4 bytes). + * @param wifi_if: wifi mode(station or softap). + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_GetIPAddress(MX_WIFIObject_t *Obj, uint8_t *ipaddr, mwifi_if_t wifi_if); + +/** + * @brief Get the local IPv6 address of the wifi module. + * @param Obj: pointer to module handle + * @param ipaddr6: buf to the IPv6 address array(16 bytes). + * @param addr_num: index of the IPv6 address (index: 0/1/2). + * @param wifi_if: wifi mode(station or softap). + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_GetIP6Address(MX_WIFIObject_t *Obj, uint8_t *ipaddr6, int32_t addr_num, mwifi_if_t wifi_if); + +/** + * @brief Get the local IPv6 address state of the wifi module. + * @param Obj: pointer to module handle + * @param addr_num: index of the IPv6 address (index: 0/1/2). + * @param wifi_if: wifi mode(station or softap). + * @retval IPV6 address State, error if < 0 + */ +int32_t MX_WIFI_GetIP6AddressState(MX_WIFIObject_t *Obj, int32_t addr_num, mwifi_if_t wifi_if); + + +/** + * @} ** + */ + +/** + * @defgroup MX_WIFI_SOFTAP SoftAP + * @brief softAP mode API + * @{ ** + */ + +/** + * @brief Wi-Fi softAP info + */ +typedef uint8_t mwifi_security_t; +#pragma pack(1) +typedef struct +{ + int32_t rssi; /**< Signal strength of the AP */ + char ssid[33]; /**< SSID of the AP */ + uint8_t bssid[6]; /**< BSSID of the AP */ + int32_t channel; /**< Channel of the AP */ + mwifi_security_t security; /**< security of the AP */ +} mwifi_ap_info_t; +#pragma pack() + +/** + * @brief Start softAP(miniAP) mode + * @param Obj: pointer to module handle + * @param ap_settings: softAP settings. + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_StartAP(MX_WIFIObject_t *Obj, MX_WIFI_APSettings_t *ap_settings); + +/** + * @brief Stop softAP(miniAP) mode + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +MX_WIFI_STATUS_T MX_WIFI_StopAP(MX_WIFIObject_t *Obj); + +/** + * @} ** + */ + +#if MX_WIFI_NETWORK_BYPASS_MODE == 0 + +/** + * @defgroup WIFI_SOCKET Socket + * @brief socket related API + * @{ ** + */ + +#ifndef socklen_t +#define socklen_t uint32_t +#endif /* socklen_t */ + +/** + * @brief socket address struct + */ + +struct sockaddr +{ + uint8_t sa_len; + uint8_t sa_family; + uint8_t sa_data[14]; +}; + +/** + * @brief socket address(net format) + */ +struct in_addr +{ + uint32_t s_addr; +}; + +/** + * @brief socket address_in struct + */ +struct sockaddr_in +{ + uint8_t sin_len; + uint8_t sin_family; + uint16_t sin_port; + struct in_addr sin_addr; + char sin_zero[8]; +}; + +/** + * @brief socket address(IPV6 net format) + */ +struct in6_addr +{ + union + { + uint32_t u32_addr[4]; + uint8_t u8_addr[16]; + } un; + /* #define s6_addr un.u8_addr */ +}; + +/** + * @brief socket address_in6 struct + */ +struct sockaddr_in6 +{ + uint8_t sin6_len; /* length of this structure */ + uint8_t sin6_family; /* AF_INET6 */ + uint16_t sin6_port; /* Transport layer port # */ + uint32_t sin6_flowinfo; /* IPv6 flow information */ + struct in6_addr sin6_addr; /* IPv6 address */ + uint32_t sin6_scope_id; /* Set of interfaces for scope */ +}; + +struct sockaddr_storage +{ + uint8_t s2_len; + uint8_t ss_family; + char s2_data1[2]; + uint32_t s2_data2[3]; + uint32_t s2_data3[3]; +}; + +/** + * @brief socket address_in6 info + */ +struct addrinfo +{ + int32_t ai_flags; /* Input flags. */ + int32_t ai_family; /* Address family of socket. */ + int32_t ai_socktype; /* Socket type. */ + int32_t ai_protocol; /* Protocol of socket. */ + uint32_t ai_addrlen; /* Length of socket address. */ + struct sockaddr *ai_addr; /* Socket address of socket. */ + char *ai_canonname; /* Canonical name of service location. */ + struct addrinfo *ai_next; /* Pointer to next in list. */ +}; + +/* Socket protocol types (TCP/UDP/RAW) */ +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +#define SOL_SOCKET 0xfff /* options for socket level */ + +#define AF_UNSPEC 0 +#define AF_INET 2 +#define AF_INET6 10 + +#define PF_UNSPEC AF_UNSPEC +#define PF_INET AF_INET +#define PF_INET6 AF_INET6 + +#define IPPROTO_IP 0 +#define IPPROTO_ICMP 1 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 +#define IPPROTO_IPV6 41 +#define IPPROTO_ICMPV6 58 +#define IPPROTO_UDPLITE 136 + +#define F_GETFL 3 +#define F_SETFL 4 + +#define O_NONBLOCK 1 /* nonblocking I/O */ + +/** + * @brief socket option value + */ +typedef enum +{ + SO_DEBUG = 0x0001, /**< Unimplemented: turn on debugging info recording */ + SO_ACCEPTCONN = 0x0002, /**< socket has had listen() */ + SO_REUSEADDR = 0x0004, /**< Allow local address reuse */ + SO_KEEPALIVE = 0x0008, /**< keep connections alive */ + SO_DONTROUTE = 0x0010, /**< Just use interface addresses */ + SO_BROADCAST = 0x0020, /**< Permit to send and to receive broadcast messages */ + SO_USELOOPBACK = 0x0040, /**< Bypass hardware when possible */ + SO_LINGER = 0x0080, /**< linger on close if data present */ + SO_OOBINLINE = 0x0100, /**< Leave received OOB data in line */ + SO_REUSEPORT = 0x0200, /**< Allow local address & port reuse */ + SO_BLOCKMODE = 0x1000, /**< set socket as block(optval=0)/non-block(optval=1) mode. + Default is block mode. */ + SO_SNDBUF = 0x1001, + SO_SNDTIMEO = 0x1005, /**< Send timeout in block mode. block for ever in default mode. */ + SO_RCVTIMEO = 0x1006, /**< Recv timeout in block mode. block 1 second in default mode. */ + SO_ERROR = 0x1007, /**< Get socket error number. */ + SO_TYPE = 0x1008, /**< Get socket type. */ + SO_NO_CHECK = 0x100a /**< Don't create UDP checksum. */ + +} SOCK_OPT_VAL; + +#if !defined __GNUC__ +#define FD_SETSIZE 64 /**< MAX fd number is 64 in MXOS. */ +#define HOWMANY(x, y) (((x) + ((y) - 1)) / (y)) + +#define NBBY 8 /**< number of bits in a byte. */ +#define NFDBITS (sizeof(unsigned long) * NBBY) /**< bits per mask */ + +#define MC_FDSET_MASK(n) ((unsigned long)1 << ((n) % NFDBITS)) + +typedef struct _fd_set +{ + unsigned long fds_bits[HOWMANY(FD_SETSIZE, NFDBITS)]; +} fd_set; + +#define FD_SET(n, p) ((p)->fds_bits[(n)/NFDBITS] |= MC_FDSET_MASK(n)) /**< Add a fd to FD set. */ +#define FD_CLR(n, p) ((p)->fds_bits[(n)/NFDBITS] &= ~MC_FDSET_MASK(n)) /**< Remove fd from FD set. */ +#define FD_ISSET(n, p) ((p)->fds_bits[(n)/NFDBITS] & MC_FDSET_MASK(n)) /**< Check if the fd is set in FD set. */ +#define FD_ZERO(p) memset((p), 0, sizeof(*(p))) /**< Clear FD set. */ +#endif /* !__GNUC__ */ + +/** + * @brief IP option types, level: IPPROTO_IP + */ +typedef enum +{ + IP_ADD_MEMBERSHIP = 0x0003, /**< Join multicast group. */ + IP_DROP_MEMBERSHIP = 0x0004, /**< Leave multicast group. */ + IP_MULTICAST_TTL = 0x0005, + IP_MULTICAST_IF = 0x0006, + IP_MULTICAST_LOOP = 0x0007 +} IP_OPT_VAL; + +/** + * @brief Create a socket. + * @param Obj: pointer to module handle + * @param domain: socket domain + * @param type: socket type + * @param protocol: socket protocol + * @retval Socket file descriptor, return < 1 if failed. + */ +int32_t MX_WIFI_Socket_create(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol); + +/** + * @brief Set option for a socket + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param level: option level + * @param optname: option to set + * @param optvalue: value buffer for the option + * @param optlen: length of the option value + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_setsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level, + int32_t optname, const void *optvalue, int32_t optlen); + +/** + * @brief Get option of a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param level: option level + * @param optname: option to set + * @param optvalue: buffer pointer of value of the option + * @param optlen: buffer pointer of length of the option value + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_getsockopt(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t level, + int32_t optname, void *optvalue, uint32_t *optlen); + +/** + * @brief Bind a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: socket address + * @param addrlen: address length + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_bind(MX_WIFIObject_t *Obj, int32_t sockfd, const struct sockaddr *addr, int32_t addrlen); + +/** + * @brief Listen a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param backlog: max number to queued. + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_listen(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t backlog); + +/** + * @brief Accept a socket. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: client address + * @param addrlen: length of client address + * @retval Accepted client socket fd, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_accept(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen); + +/** + * @brief Socket connect. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: client address + * @param addrlen: length of client address + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_connect(MX_WIFIObject_t *Obj, int32_t sockfd, const struct sockaddr *addr, int32_t addrlen); + +/** + * @brief Socket shutdown. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param mode: shutdown mode: + * 0 Stop receiving data for this socket; + * 1 Stop trying to transmit data from this socket + * 2 Stop all transmit from this socket + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_shutdown(MX_WIFIObject_t *Obj, int32_t sockfd, int32_t mode); + +/** + * @brief Socket close. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_close(MX_WIFIObject_t *Obj, int32_t sockfd); + +/** + * @brief Socket send. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: send data buffer + * @param len: length of send data + * @param flags: zero for MXOS + * @retval Number of bytes sent, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_send(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags); + +/** + * @brief Socket recv. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: recv buffer + * @param len: length of recv buffer + * @param flags: zero for MXOS + * @retval Number of bytes received, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_recv(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags); + +/** + * @brief Socket sendto. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: send data buffer + * @param len: length of send data + * @param flags: zero for MXOS + * @param toaddr: address to send + * @param toaddrlen: length of address to send + * @retval Number of bytes sent, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_sendto(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags, + struct sockaddr *toaddr, int32_t toaddrlen); + +/** + * @brief Socket recvfrom. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param buf: recv buffer + * @param len: length of recv buffer + * @param fromaddr: address of the data source + * @param fromaddrlen: length of address of the data source + * @param flags: zero for MXOS + * @retval Number of bytes received, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_recvfrom(MX_WIFIObject_t *Obj, int32_t sockfd, uint8_t *buf, int32_t len, int32_t flags, + struct sockaddr *fromaddr, uint32_t *fromaddrlen); + +/** + * @brief Gethostbyname, only for IPv4 address. + * @param Obj: pointer to module handle + * @param addr: address of the host + * @param name: hostname + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_gethostbyname(MX_WIFIObject_t *Obj, struct sockaddr *addr, char *name); + +/** + * @brief Ping a host, only for IPv4 address. + * @param Obj: pointer to module handle + * @param addr: hostname + * @param count: ping max count + * @param delay: ping delay in millisecond + * @param response: response time array of ping result + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_ping(MX_WIFIObject_t *Obj, const char *hostname, int32_t count, int32_t delay, + int32_t response[]); + +#if 0 +/** + * @brief Get IPv4/v6 address info by nodename. + * @param Obj: pointer to module handle + * @param nodename: descriptive name or address string of the host + * @param servname: not used, set NULL + * @param hints: structure containing input values that set socktype and protocol + * @param res: buf to store the result (set to NULL on failure) + * @retval Operation Status. + */ +int32_t MX_WIFI_Socket_getaddrinfo(MX_WIFIObject_t *Obj, const char *nodename, const char *servname, + const struct addrinfo *hints, struct mc_addrinfo *res); + +/** + * @brief Monitor multiple file descriptors for sockets + * @attention Never doing operations in different threads + * @param Obj: pointer to module handle + * @param nfds: is the highest-numbered file descriptor in any of the three + * sets, plus 1 + * @param readfds: A file descriptor sets will be watched to see if characters + * become available for reading + * @param writefds: A file descriptor sets will be watched to see if a write + * will not block. + * @param exceptfds: A file descriptor sets will be watched for exceptions. + * @param timeout: The timeout argument specifies the interval that select() + * should block waiting for a file descriptor to become ready. + * If timeout is NULL (no timeout), select() can block until API timeout. + * @retval On success, return the number of file descriptors contained in the + * three returned descriptor sets (that is, the total number of bits + * that are set in readfds, writefds, exceptfds) which may be zero if + * the timeout expires before anything interesting happens. On error, + * -1 is returned, the file descriptor sets are unmodified, and timeout + * becomes undefined. + */ +int32_t MX_WIFI_Socket_select(MX_WIFIObject_t *Obj, int32_t nfds, fd_set *readfds, fd_set *writefds, + fd_set *exceptfds, struct mc_timeval *timeout); +#endif /* 0 */ + + +/** + * @brief socket getpeername. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: address buffer + * @param addrlen: size of address buffer + * @retval get address of peer socket, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_getpeername(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen); + +/** + * @brief socket getsockname. + * @param Obj: pointer to module handle + * @param sockfd: socket fd + * @param addr: address buffer + * @param addrlen: size of address buffer + * @retval get address of local socket, return < 0 if failed. + */ +int32_t MX_WIFI_Socket_getsockname(MX_WIFIObject_t *Obj, int32_t sockfd, struct sockaddr *addr, uint32_t *addrlen); + +/** + * @} ** + */ + +/** + * @defgroup MX_WIFI_MDNS mDNS + * @brief mDNS related API + * @{ ** + */ + +/** Maximum length of labels + * + * A label is one segment of a DNS name. For example, "foo" is a label in the + * name "foo.local.". RFC 1035 requires that labels do not exceed 63 bytes. + */ +#define MDNS_MAX_LABEL_LEN 63 /* defined by the standard */ + +/** Maximum length of names + * + * A name is a list of labels such as "My Webserver.foo.local" or + * mydevice.local. RFC 1035 requires that names do not exceed 255 bytes. + */ +#define MDNS_MAX_NAME_LEN 255 /* defined by the standard : 255*/ + +/** Maximum length of key/value pair + * + * TXT records associated with a service are populated with key/value pairs. + * These key/value pairs must not exceed this length. + */ +#define MDNS_MAX_KEYVAL_LEN 255 /* defined by the standard : 255*/ + +/** protocol values for the proto member of the mdns_service descriptor */ +/** TCP Protocol */ +#define MDNS_PROTO_TCP 0 +/** UDP Protocol */ +#define MDNS_PROTO_UDP 1 + +/** Maximum no. of services allowed to be announced on a single interface. */ +#define MAX_MDNS_LST 5 /* Maximum no. of services */ + +/* MDNS Error Codes */ +#define ERR_MDNS_BASE -36650 /**< Starting error code for all mdns errors. */ +#define ERR_MDNS_INVAL -36651 /**< invalid argument */ +#define ERR_MDNS_BADSRC -36652 /**< bad service descriptor */ +#define ERR_MDNS_TOOBIG -36653 /**< not enough room for everything */ +#define ERR_MDNS_NOIMPL -36654 /**< unimplemented feature */ +#define ERR_MDNS_NOMEM -36655 /**< insufficient memory */ +#define ERR_MDNS_INUSE -36656 /**< requested resource is in use */ +#define ERR_MDNS_NORESP -36657 /**< requested resource is in use */ +#define ERR_MDNS_FSOC -36658 /**< failed to create socket for mdns */ +#define ERR_MDNS_FREUSE -36659 /**< failed to reuse multicast socket */ +#define ERR_MDNS_FBINDTODEVICE -36660 /**< failed to bind mdns socket to device */ +#define ERR_MDNS_FBIND -36661 /**< failed to bind mdns socket */ +#define ERR_MDNS_FMCAST_JOIN -36662 /**< failed to join multicast socket */ +#define ERR_MDNS_FMCAST_SET -36663 /**< failed to set multicast socket */ +#define ERR_MDNS_FQUERY_SOC -36664 /**< failed to create query socket */ +#define ERR_MDNS_FQUERY_THREAD -36665 /**< failed to create mdns thread */ +#define ERR_MDNS_END -36670 /**< Last generic error code (inclusive) */ + +/** mDNS Interface State + * mDNS interface state can be changed by using mdns_iface_state_change() + * function. For details about when to use the enum please refer to + * documentation for mdns_iface_state_change(). */ +enum iface_state +{ + /** UP the interface and announce services + * mDNS will probe and announce all services announced via + * mdns_announce_service() and/or mdns_announce_service_arr(). + * mDNS will go through entire probing sequence explained in above + * functions. Interface state can be changed to UP, if its DOWN. + */ + UP = 0, + /** DOWN the interface and de-announce services + * mDNS sends good bye packet with ttl=0 so that mDNS clients can remove + * the services from their mDNS cache table. + */ + DOWN, + /** Forcefully re-announce services + * This state should be used after services are already + * announced and force announcement is needed due to some reason. + * mDNS will not perform probing sequence, as it does in case of UP, and + * will directly re-announce services. + */ + REANNOUNCE +}; + +/** + * @brief mDNS service info + */ +#pragma pack(1) +struct mc_mdns_service +{ + /** Name of MDNS service */ + char servname[MDNS_MAX_LABEL_LEN + 1]; + /** Type of MDNS service */ + char servtype[MDNS_MAX_LABEL_LEN + 1]; + /** Domain for MDNS service */ + char domain[MDNS_MAX_LABEL_LEN + 1]; + /** Port number */ + uint16_t port; + /** Protocol used */ + int32_t proto; + /** Key value pairs for TXT records*/ + char keyvals[MDNS_MAX_KEYVAL_LEN + 1]; + /** IP Address of device */ + uint32_t ipaddr; + /** IPv6 Address of device */ + uint32_t ip6addr[4]; + + /** separator for txt record */ + char separator; /* user set this for keyvals */ +}; +#pragma pack() + +/** + * @brief start mDNS service. + * @param Obj: pointer to module handle + * @param domain: domain of service + * @param name: hostname + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_start(MX_WIFIObject_t *Obj, const char *domain, char *hostname); + +/** + * @brief stop mDNS service. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_stop(MX_WIFIObject_t *Obj); + +/** + * @brief announce a service. + * @param Obj: pointer to module handle + * @param service: service to announce + * @param interface: wifi interface + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_announce_service(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, mwifi_if_t interface); + +/** + * @brief deannounce a service. + * @param Obj: pointer to module handle + * @param service: service to deannounce + * @param interface: wifi interface + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_deannounce_service(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, mwifi_if_t interface); + +/** + * @brief deannounce all services. + * @param Obj: pointer to module handle + * @param interface: wifi interface + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_deannounce_service_all(MX_WIFIObject_t *Obj, mwifi_if_t interface); + +/** + * @brief Send interface state change event to mdns + * @param Obj: pointer to module handle + * @param interface: wifi interface + * @param state: state event, valid interface state from \ref iface_state + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_iface_state_change(MX_WIFIObject_t *Obj, mwifi_if_t interface, enum iface_state state); + +/** + * @brief Set new host name, use mdns_iface_state_change(interface, REANNOUNCE) to anounce + * the new host name. + * @param Obj: pointer to module handle + * @param hostname: new hostname + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_set_hostname(MX_WIFIObject_t *Obj, char *hostname); + +/** + * @brief sets the TXT record field for a given mDNS service. + * @param Obj: pointer to module handle + * @param service: mDNS service + * @param keyvals: new txt record string + * @param separator: the separator used to separate individual key value pairs + * @retval Operation Status. + */ +int32_t MX_WIFI_MDNS_set_txt_rec(MX_WIFIObject_t *Obj, struct mc_mdns_service *service, char *keyvals, + char separator); + +/** + * @} ** + */ + +/** + * @defgroup MX_WIFI_TLS TLS + * @brief TLS related API + * @{ ** + */ + +/** + * @brief mxchip TLS handler type + */ +typedef void *mtls_t; + +/** + * @brief mxchip TLS version + */ +enum +{ + SSL_V3_MODE = 1, /**< SSL V3 */ + TLS_V1_0_MODE = 2, /**< TLS V1.0 */ + TLS_V1_1_MODE = 3, /**< TLS V1.1 */ + TLS_V1_2_MODE = 4 /**< TLS V1.2 */ +}; + +typedef uint8_t mtls_ver_t; + +/** + * @brief set the TLS protocol version. + * @param Obj: pointer to module handle + * @param version: TLS protocol version + * @retval Operation Status. + * @note This function should be called before TLS is ready to function (before + * mtls_connect and mtls_accept is called by application ). + */ +int32_t MX_WIFI_TLS_set_ver(MX_WIFIObject_t *Obj, mtls_ver_t version); + +/** + * @brief TLS set client certificate + * @param Obj: pointer to module handle + * @param client_cert: Point to buffer of client cert. + * @param cert_len: length of the client cert. + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_set_clientCertificate(MX_WIFIObject_t *Obj, uint8_t *client_cert, uint16_t cert_len); + +/** + * @brief TLS set client private key + * @param Obj: pointer to module handle + * @param client_private_key: Point to buffer of client private key. + * @param key_len: length of the client cert. + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_set_clientPrivateKey(MX_WIFIObject_t *Obj, uint8_t *client_private_key, uint16_t key_len); + +/** + * @brief TLS client create a TLS connection. + * @param Obj: pointer to module handle + * @details This function is called on the client side and initiates an TLS/TLS handshake with a + * server. When this function is called, the underlying communication channel has already + * been set up. This function is called after TCP 3-way handshak finished. + * @param domain: Specifies a communication domain + * @param type: Specifies the communication semantics. + * @param protocol: specifies a particular protocol to be used with the socket. + * @param addr: Point to the target address to be connected + * @param addrlen: containing the size of the buffer pointed to by addr + * @param ca: pointer to the CA certificate string, used to verify server's certificate. + * @param calen: the string length of ca. 0=do not verify server's certificate. + * @retval return the TLS context pointer on success or NULL for fail. + */ +int32_t MX_WIFI_TLS_connect(MX_WIFIObject_t *Obj, int32_t domain, int32_t type, int32_t protocol, + const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen); + +/** + * @brief TLS client create a TLS connection with SNI. + * @param Obj: pointer to module handle + * @details This function is called on the client side and initiates an TLS/TLS handshake with a + * server. When this function is called, the underlying communication channel has already + * been set up. This function is called after TCP 3-way handshak finished. + * @param sni_servername: Specifies the SNI servername + * @param sni_servername_len: Specifies the SNI servername length, max size MX_TLS_SNI_SERVERNAME_SIZE + * @param addr: Point to the target address to be connected + * @param addrlen: containing the size of the buffer pointed to by addr + * @param ca: pointer to the CA certificate string, used to verify server's certificate. + * @param calen: the string length of ca. 0=do not verify server's certificate. + * @retval return the TLS context pointer on success or NULL for fail. + */ +int32_t MX_WIFI_TLS_connect_sni(MX_WIFIObject_t *Obj, const char *sni_servername, int32_t sni_servername_len, + const struct sockaddr *addr, int32_t addrlen, char *ca, int32_t calen); + +/** + * @brief TLS send data + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @param data: Point to data to send. + * @param len: data length. + * @retval On success, return the number of bytes sent. On error, + * error code (< 0) is returned. + */ +int32_t MX_WIFI_TLS_send(MX_WIFIObject_t *Obj, mtls_t tls, void *data, int32_t len); + +/** + * @brief TLS redeive data + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @param data: Point to buffer to receive TLS data. + * @param len: max receive buffer length. + * @retval On success, return the number of bytes received. On error, + * error code (< 0) is returned. + */ +int32_t MX_WIFI_TLS_recv(MX_WIFIObject_t *Obj, mtls_t tls, void *buf, int32_t len); + +/** + * @brief Close the TLS session, release resource. + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_close(MX_WIFIObject_t *Obj, mtls_t tls); + +/** + * @brief Set TLS nonblock mode. + * @param Obj: pointer to module handle + * @param tls: Point to the TLS context. + * @param nonblock: true - nonblock, flase - block + * @retval Operation Status. + */ +int32_t MX_WIFI_TLS_set_nonblock(MX_WIFIObject_t *Obj, mtls_t tls, int32_t nonblock); + +/** + * @} ** + */ + + +/** + * @defgroup MX_WIFI_WEBSERVER Webserver + * @brief Webserver related API + * @{ ** + */ + + +/** + * @brief Start webserver. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +int32_t MX_WIFI_Webserver_start(MX_WIFIObject_t *Obj); + +/** + * @brief Stop webserver. + * @param Obj: pointer to module handle + * @retval Operation Status. + */ +int32_t MX_WIFI_Webserver_stop(MX_WIFIObject_t *Obj); + + +/** + * @} ** + */ + + +/** + * @defgroup MX_WIFI_FOTA FOTA + * @brief FOTA related API + * @{ ** + */ + + +/** + * @brief Start FOTA. + * @param Obj: pointer to module handle + * @param url: HTTP/HTTPS url of bin file to update + * @param md5: MD5 string(32Bytes) of bin file to update + * @param ota_status_callback: callback function for ota status + * @retval Operation Status. + */ +int32_t MX_WIFI_FOTA_start(MX_WIFIObject_t *Obj, const char *url, const char *md5, + mx_wifi_fota_status_cb_t fota_status_callback, uint32_t user_args); + +/** + * @} ** + */ + +/** + * @defgroup MX_WIFI_STATION_POWERSAVE + * @brief Wi-Fi station powersave API + * @{ ** + */ + +#endif /* MX_WIFI_NETWORK_BYPASS_MODE */ + +/** + * @} ** + */ + + +/** + * @} ** + */ + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* MX_WIFI_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi_conf_template.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi_conf_template.h new file mode 100644 index 00000000000..69b1dab766d --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi/mx_wifi_conf_template.h @@ -0,0 +1,251 @@ +/** + ****************************************************************************** + * @file mx_wifi_conf_template.h + * @author MCD Application Team + * @brief Header for mx_wifi_conf_template module + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_CONF_TEMPLATE_H +#define MX_WIFI_CONF_TEMPLATE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include + +int32_t mxwifi_probe(void **ll_drv_context); + +/* use SPI interface by default */ + +#ifndef MX_WIFI_USE_SPI +#define MX_WIFI_USE_SPI (1) +#endif /* MX_WIFI_USE_SPI */ + +/* do not use RTOS but bare metal approach by default */ +#ifndef MX_WIFI_USE_CMSIS_OS +#define MX_WIFI_USE_CMSIS_OS (0) +#endif /* MX_WIFI_USE_CMSIS_OS */ + +/* Use At command mode by default, TCP/IP stack is running on module */ +#ifndef MX_WIFI_NETWORK_BYPASS_MODE +#define MX_WIFI_NETWORK_BYPASS_MODE (0) +#endif /* MX_WIFI_NETWORK_BYPASS_MODE */ + + +/* Do not copy TX buffer */ +#ifndef MX_WIFI_TX_BUFFER_NO_COPY +#define MX_WIFI_TX_BUFFER_NO_COPY (1) +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + + +/* DEBUG LOG */ +/* #define MX_WIFI_API_DEBUG */ +/* #define MX_WIFI_IPC_DEBUG */ +/* #define MX_WIFI_HCI_DEBUG */ +/* #define MX_WIFI_SLIP_DEBUG */ +/* #define MX_WIFI_IO_DEBUG */ + +/* check if OS primitive are already declared */ +/* if not, include default declaration */ +#ifndef LOCK_DECLARE + +#if (MX_WIFI_USE_CMSIS_OS == 1) +#include "mx_wifi_cmsis_os.h" +#define MX_WIFI_BARE_OS 0 +#else +#if (MX_WIFI_USE_MBED_OS == 1) +#include "mx_wifi_mbed_os.h" +#define MX_WIFI_BARE_OS 0 +#else +#include "mx_wifi_bare_os.h" +#define MX_WIFI_BARE_OS 1 +#endif /* mx_wifi_mbed_os.h */ +#endif /* MX_WIFI_USE_CMSIS_OS */ + +#else +/* OS rempa are declared externally , so OS is present */ +#define MX_WIFI_BARE_OS 0 +#endif /* LOCK_DECLARE */ + + + +#define MX_WIFI_PRODUCT_NAME ("MXCHIP-WIFI") +#define MX_WIFI_PRODUCT_ID ("EMW3080B") + +#ifndef MX_WIFI_USE_SPI +#define MX_WIFI_USE_SPI (0) +#endif /* MX_WIFI_USE_SPI */ + + +#ifndef MX_WIFI_UART_BAUDRATE +#define MX_WIFI_UART_BAUDRATE (115200*2) +#endif /* MX_WIFI_UART_BAUDRATE */ + +#ifndef MX_WIFI_MTU_SIZE +#define MX_WIFI_MTU_SIZE (1500) +#endif /* MX_WIFI_MTU_SIZE */ + +#define MX_WIFI_BYPASS_HEADER_SIZE (28) /* MX_IPC_header(6) + sizeof(bypass_in_t)(22), + * set with PBUF_LINK_ENCAPSULATION_HLEN */ +#define MX_WIFI_PBUF_LINK_HLEN (14) /* link header (PBUF_LINK_HLEN) set in lwip */ + +#if (MX_WIFI_NETWORK_BYPASS_MODE==1) +/* Use lwip PBUF_POOL_BUFSIZE = TCP_MSS + 40 + PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN. */ +#define MX_WIFI_BUFFER_SIZE \ + (MX_WIFI_MTU_SIZE + MX_WIFI_BYPASS_HEADER_SIZE + MX_WIFI_PBUF_LINK_HLEN) +#else +#define MX_WIFI_BUFFER_SIZE (2500) /* bigger buffer size */ +#endif /* (MX_WIFI_NETWORK_BYPASS_MODE==1) */ + +/* MX_WIFI_BUFFER_SIZE - MX_IPC_header */ +#define MX_WIFI_IPC_PAYLOAD_SIZE ((MX_WIFI_BUFFER_SIZE) - 6) + +/* MX_WIFI_IPC_PAYLOAD_SIZE - socket_api_params_header */ +#define MX_WIFI_SOCKET_DATA_SIZE ((MX_WIFI_IPC_PAYLOAD_SIZE)-12) + +#ifndef MX_WIFI_CMD_TIMEOUT +#define MX_WIFI_CMD_TIMEOUT (10000) +#endif +#define MX_WIFI_MAX_SOCKET_NBR (8) +#define MX_WIFI_MAX_DETECTED_AP (10) + +#define MX_WIFI_MAX_SSID_NAME_SIZE 32 +#define MX_WIFI_MAX_PSWD_NAME_SIZE 64 + +#define MX_WIFI_PRODUCT_NAME_SIZE 32 +#define MX_WIFI_PRODUCT_ID_SIZE 32 + +#define MX_WIFI_FW_REV_SIZE 24 +#ifndef MX_WIFI_SPI_THREAD_PRIORITY +#define MX_WIFI_SPI_THREAD_PRIORITY (OSPRIORITYREALTIME) +#endif /* MX_WIFI_SPI_THREAD_PRIORITY */ +#ifndef MX_WIFI_SPI_THREAD_STACK_SIZE +#define MX_WIFI_SPI_THREAD_STACK_SIZE (1024) +#endif /* MX_WIFI_SPI_THREAD_STACK_SIZE */ + +#ifndef MX_WIFI_UART_THREAD_PRIORITY +#define MX_WIFI_UART_THREAD_PRIORITY (OSPRIORITYREALTIME) +#endif /* MX_WIFI_UART_THREAD_PRIORITY */ +#ifndef MX_WIFI_UART_THREAD_STACK_SIZE +#define MX_WIFI_UART_THREAD_STACK_SIZE (1024) +#endif /* MX_WIFI_UART_THREAD_STACK_SIZE */ + + +#ifndef MX_WIFI_RECEIVED_THREAD_PRIORITY +#define MX_WIFI_RECEIVED_THREAD_PRIORITY (OSPRIORITYABOVENORMAL) +#endif /* MX_WIFI_RECEIVED_THREAD_PRIORITY */ + +#ifndef MX_WIFI_RECEIVED_THREAD_STACK_SIZE +#define MX_WIFI_RECEIVED_THREAD_STACK_SIZE (1024) +#endif /* MX_WIFI_RECEIVED_THREAD_STACK_SIZE*/ + +#ifndef MX_WIFI_TRANSMIT_THREAD_PRIORITY +#define MX_WIFI_TRANSMIT_THREAD_PRIORITY (OSPRIORITYABOVENORMAL) +#endif /* MX_WIFI_TRANSMIT_THREAD_PRIORITY */ + +#ifndef MX_WIFI_TRANSMIT_THREAD_STACK_SIZE +#define MX_WIFI_TRANSMIT_THREAD_STACK_SIZE (1024) +#endif /* MX_WIFI_TRANSMIT_THREAD_STACK_SIZE */ + + +/* Maximum number of RX buffer that can be queued by Hardware interface (SPI/UART) */ +/* This is used to size internal queue, and avoid to block the IP thread if it can still push some buffers */ +/* Impact on Memory foot print is weak , one single void* per place in the queue */ +#ifndef MX_WIFI_MAX_RX_BUFFER_COUNT +#define MX_WIFI_MAX_RX_BUFFER_COUNT (2) +#endif /* MX_WIFI_MAX_RX_BUFFER_COUNT */ + + +/* Maximum number of TX buffer that can be queued by IP stack (LwIP or Netx) without blocking the calling thread */ +/* This is used to size internal queue, and avoid to block the IP thread if it can still push some buffers */ +/* Impact on Memory foot print is one single void* per place in the queue, but it may lead to over allocation */ +/* TCP/IP stack (LwIP for instance ) */ +#ifndef MX_WIFI_MAX_TX_BUFFER_COUNT +#define MX_WIFI_MAX_TX_BUFFER_COUNT (4) +#endif /* MX_WIFI_MAX_TX_BUFFER_COUNT */ + + + +/** + * For the TX buffer, by default no-copy feature is enabled, meaning that + * the IP buffer are used in the whole process and should come with + * available room in front of payload to accommodate transport header buffer. + * This is managed in interface between driver and IP stack + */ + +/** + * For LwIP "PBUF_LINK_ENCAPSULATION_HLEN" must be defined as > MX_WIFI_MIN_TX_HEADER_SIZE, + * see net_mx_wifi/c file for implementation. + */ +#define MX_WIFI_MIN_TX_HEADER_SIZE (28) + +#ifndef MX_WIFI_TX_BUFFER_NO_COPY +#define MX_WIFI_TX_BUFFER_NO_COPY (1) +#endif /* MX_WIFI_TX_BUFFER_NO_COPY */ + + +/* Sizeof the circular buffer for Uart mode, when buffer is hlaf full data are transmitted to next stage */ +#ifndef MX_CIRCULAR_UART_RX_BUFFER_SIZE +#define MX_CIRCULAR_UART_RX_BUFFER_SIZE (400) +#endif /* MX_CIRCULAR_UART_RX_BUFFER_SIZE */ + + + +#ifndef MX_STAT_ON +#define MX_STAT_ON 0 +#endif /* MX_STAT_ON */ + +#if MX_STAT_ON == 1 +typedef struct +{ + uint32_t alloc; + uint32_t free; + uint32_t cmd_get_answer; + uint32_t callback; + uint32_t in_fifo; + uint32_t out_fifo; +} mx_stat_t; + +extern mx_stat_t mx_stat; + +#define MX_STAT_LOG() \ + (void) printf("Number of allocated buffer for Rx and command answer %ld\n", mx_stat.alloc);\ + (void) printf("Number of free buffer %ld\n",mx_stat.free);\ + (void) printf("Number of command answer %ld , callback %ld, sum of both %ld (should match alloc && free)\n",\ + mx_stat.cmd_get_answer,mx_stat.callback,mx_stat.cmd_get_answer+mx_stat.callback);\ + (void) printf("Number of posted answer (callback + cmd answer) %ld, processed answer %ld\n",\ + mx_stat.in_fifo,mx_stat.out_fifo);\ + +#define MX_STAT_INIT() (void) memset((void*)&mx_stat, 0, sizeof(mx_stat)) +#define MX_STAT(A) mx_stat.A++ +#define MX_STAT_DECLARE() mx_stat_t mx_stat + +#else + +#define MX_STAT_INIT() +#define MX_STAT(A) +#define MX_STAT_LOG() +#define MX_STAT_DECLARE() + +#endif /* MX_STAT_ON */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* MX_WIFI_CONF_TEMPLATE_H */ + diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_conf.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_conf.h new file mode 100644 index 00000000000..5529c1b8421 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_conf.h @@ -0,0 +1,32 @@ +/** + *

© Copyright (c) 2021 STMicroelectronics. + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_CONF_H +#define MX_WIFI_CONF_H + +/* Define your Hardware config UART or SPI */ +#define MX_WIFI_USE_SPI (MBED_CONF_EMW3080B_WIFI_SPI_INTERFACE) + +/* Bypass mode or AT command */ +#define MX_WIFI_NETWORK_BYPASS_MODE (1) + +#define MX_WIFI_USE_MBED_OS (1) +//#define MX_WIFI_TX_BUFFER_NO_COPY (0) + + +/* Includes ------------------------------------------------------------------*/ +#include "mx_wifi_mbed_os.h" +#include "mx_wifi_conf_template.h" + +#endif /* MX_WIFI_CONF_H */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_mbed_os.cpp b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_mbed_os.cpp new file mode 100644 index 00000000000..579158bfb13 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_mbed_os.cpp @@ -0,0 +1,203 @@ +/** + *

© Copyright (c) 2021 STMicroelectronics. + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ + +#include "EMW3080B_EMAC.h" + +#include "mx_wifi_mbed_os.h" + +extern "C" +{ + +#if BASIC_MALLOC == 0 + + mx_buf_t *mx_buf_alloc(uint32_t len) + { + emac_mem_buf_t *p = emac3080b_global_memory_manager->alloc_pool(len, 0); + return (mx_buf_t *) p; + } + + + void mx_buf_free(mx_buf_t *netb_in) + { + emac_mem_buf_t *netb = (emac_mem_buf_t *) netb_in; + emac3080b_global_memory_manager->free(netb); + } + + + void mx_buf_hide_header(mx_buf_t *netb_in, int32_t n) + { + if (n <= 0) { + error("Hiding header is not supported\n"); + } else { + emac_mem_buf_t *netb = (emac_mem_buf_t *) netb_in; + ssize_t len = emac3080b_global_memory_manager->get_len(netb); + uint8_t *pdata = (uint8_t *) emac3080b_global_memory_manager->get_ptr(netb); + + memmove(pdata, pdata + n, len); + } + + } + + uint8_t *mx_buf_payload(mx_buf_t *netb_in) + { + emac_mem_buf_t *netb = (emac_mem_buf_t *) netb_in; + return (uint8_t *) emac3080b_global_memory_manager->get_ptr(netb); + } + + + uint32_t mx_buf_get_size(mx_buf_t *netb_in) + { + emac_mem_buf_t *netb = (emac_mem_buf_t *) netb_in; + return emac3080b_global_memory_manager->get_len(netb); + } + + void mx_buf_set_size(mx_buf_t *netb_in, int32_t n) + { + emac_mem_buf_t *netb = (emac_mem_buf_t *) netb_in; + return emac3080b_global_memory_manager->set_len(netb, n); + + } + +#endif /* BASIC_ALLOC */ + + + void mbed_delay(uint32_t delay) + { + ThisThread::sleep_for(std::chrono::duration(delay)); + } + + + void *mbed_mutex_new(void) + { + void *m; + m = new Mutex(); + return (void *) m; + } + + void mbed_mutex_delete(void *m) + { + delete ((Mutex *) m); + } + + + void mbed_mutex_lock(void *mutexin) + { + Mutex *mutex = (Mutex *) mutexin; + mutex->lock(); + } + + void mbed_mutex_unlock(void *mutexin) + { + Mutex *mutex = (Mutex *) mutexin; + mutex->unlock(); + } + + void *mbed_sem_new(uint32_t count) + { + Semaphore *sem; + sem = new Semaphore(count); + for (uint32_t ii = 0; ii < count ; ii++) { + sem->acquire(); + } + return (void *) sem; + + } + void mbed_sem_delete(void *insem) + { + Semaphore *sem = (Semaphore *) insem; + delete sem; + } + bool mbed_sem_signal(void *semin) + { + bool ret; + Semaphore *sem = (Semaphore *) semin; + ret = (sem->release() == osOK); + return ret; + } + bool mbed_sem_wait(void *semin, uint32_t timeout) + { + bool ret; + Semaphore *sem = (Semaphore *) semin; + ret = sem->try_acquire_for(std::chrono::duration(timeout)); + return ret; + } + +#define QSIZE 10 + + void *mbed_queue_new(uint32_t count) + { + Queue *queue; + queue = new Queue ; + return (void *) queue; + } + + void mbed_queue_delete(void *queuein) + { + Queue *queue = (Queue *) queuein; + delete queue; + } + + void *mbed_queue_pop(void *queuein, uint32_t timeout) + { + uint32_t *message = NULL; + Queue *queue = (Queue *) queuein; + while (true) { + if (queue->try_get_for(std::chrono::duration(timeout), &message)) { + break; + } + } + return (void *) message; + } + + bool mbed_queue_push(void *queuein, void *value, uint32_t timeout) + { + Queue *queue = (Queue *) queuein; + return queue->try_put_for(std::chrono::duration(timeout), (uint32_t *)value); + } + + + + void *mbed_thread_new(void (*thread_entry)(void), uint32_t stacksize, uint32_t prio_in) + { + osPriority_t priority; + priority = osPriorityNormal; + if (prio_in == OSPRIORITYREALTIME) { + priority = osPriorityRealtime; + } + if (prio_in == OSPRIORITYABOVENORMAL) { + priority = osPriorityAboveNormal; + } + + + Thread *thread = new Thread(priority, stacksize); + if (thread) { + thread->start(callback(thread_entry)); + } + return (void *) thread; + } + + void mbed_thread_delete(void *threadin) + { + Thread *thread = (Thread *) threadin; + thread->join(); + } + + void mbed_thread_terminate(void *threadin) + { + Thread *thread = (Thread *) threadin; + thread->terminate(); + } + +} /* end of extern "C" */ diff --git a/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_mbed_os.h b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_mbed_os.h new file mode 100644 index 00000000000..e621fab5d05 --- /dev/null +++ b/connectivity/drivers/wifi/TARGET_STM/COMPONENT_EMW3080B/mx_wifi_mbed_os.h @@ -0,0 +1,154 @@ +/** + *

© Copyright (c) 2021 STMicroelectronics. + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef MX_WIFI_CMSIS_OS_H +#define MX_WIFI_CMSIS_OS_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "mbed_assert.h" + +#ifndef MX_WIFI_MALLOC +#define MX_WIFI_MALLOC malloc +#endif /* MX_WIFI_MALLOC */ + +#ifndef MX_WIFI_FREE +#define MX_WIFI_FREE free +#endif /* MX_WIFI_FREE */ + +#define BASIC_MALLOC 1 +/* Assume that OS is not used when bypass is disabled */ + +#if BASIC_MALLOC +typedef struct mx_buf { + uint32_t len; + uint32_t header_len; + uint8_t data[1]; +} mx_buf_t; + +static inline mx_buf_t *mx_buf_alloc(uint32_t len) +{ + mx_buf_t *p = (mx_buf_t *) MX_WIFI_MALLOC(len + sizeof(mx_buf_t) -1U); + if (NULL != p) { + p->len = len; + p->header_len = 0; + } + return p; + +} + +#define MX_NET_BUFFER_ALLOC(len) mx_buf_alloc(len) +#define MX_NET_BUFFER_FREE(p) MX_WIFI_FREE(p) +#define MX_NET_BUFFER_HIDE_HEADER(p, n) (p)->header_len += (n) +#define MX_NET_BUFFER_PAYLOAD(p) &(p)->data[(p)->header_len] +#define MX_NET_BUFFER_SET_PAYLOAD_SIZE(p, size) (p)->len = (size) +#define MX_NET_BUFFER_GET_PAYLOAD_SIZE(p) (p)->len + +#else /* BASIC_ALLOC */ + +#define MX_NET_BUFFER_ALLOC(len) mx_buf_alloc((len)) +#define MX_NET_BUFFER_FREE(p) mx_buf_free((p)) +#define MX_NET_BUFFER_HIDE_HEADER(p, n) mx_buf_hide_header((p),(n)) +#define MX_NET_BUFFER_PAYLOAD(p) mx_buf_payload((p)) +#define MX_NET_BUFFER_SET_PAYLOAD_SIZE(p, size) mx_buf_set_size((p),(size)) +#define MX_NET_BUFFER_GET_PAYLOAD_SIZE(p) mx_buf_get_size((p)) + + +typedef void mx_buf_t; + +mx_buf_t *mx_buf_alloc(uint32_t len); +void mx_buf_free(mx_buf_t *p); +void mx_buf_hide_header(mx_buf_t *p, int32_t n); +uint8_t *mx_buf_payload(mx_buf_t *p); +uint32_t mx_buf_get_size(mx_buf_t *p); +void mx_buf_set_size(mx_buf_t *p, int32_t n); + +#endif /* BASIC_ALLOC */ + + +void mbed_delay(uint32_t delay); +void *mbed_mutex_new(void); +void mbed_mutex_delete(void *); +void mbed_mutex_lock(void *); +void mbed_mutex_unlock(void *); + + +void *mbed_sem_new(uint32_t count); +void mbed_sem_delete(void *sem); +bool mbed_sem_signal(void *sem); +bool mbed_sem_wait(void *sem, uint32_t timeout); + +void *mbed_queue_new(uint32_t count); +void mbed_queue_delete(void *sem); +void *mbed_queue_pop(void *sem, uint32_t timeout); + + +bool mbed_queue_push(void *sem, void *value, uint32_t timeout); + +void *mbed_thread_new(void (*thread_entry)(void), uint32_t stacksize, uint32_t priority); +void mbed_thread_delete(void *thread); +void mbed_thread_terminate(void *thread); + + +#define MX_ASSERT(a) MBED_ASSERT(a) + +#define LOCK_DECLARE(A) void* A +#define LOCK_INIT(A) A = mbed_mutex_new() +#define LOCK_DEINIT(A) mbed_mutex_delete(A) +#define LOCK(A) mbed_mutex_lock(A) +#define UNLOCK(A) mbed_mutex_unlock(A) + +#define SEM_DECLARE(A) void *A +#define SEM_INIT(A,COUNT) A = mbed_sem_new(COUNT); +#define SEM_DEINIT(A) mbed_sem_delete(A) +#define SEM_SIGNAL(A) mbed_sem_signal(A) +#define SEM_WAIT(A,TIMEOUT,IDLE_FUNC) mbed_sem_wait(A,TIMEOUT) + +#define THREAD_DECLARE(A) void *A +#define THREAD_INIT(A, THREAD_FUNC, THREAD_CONTEXT, STACKSIZE, PRIORITY) (((A = mbed_thread_new((THREAD_CONTEXT_FUNC_TYPE)THREAD_FUNC,STACKSIZE, PRIORITY))!= NULL)?true:false) +#define THREAD_DEINIT(A) mbed_thread_delete(A) +#define THREAD_TERMINATE(A) mbed_thread_terminate(A) +#define THREAD_CONTEXT_TYPE void +#define THREAD_CONTEXT_FUNC_TYPE void (*)(void) + +#define FIFO_DECLARE(QUEUE) void* QUEUE +#define FIFO_PUSH(QUEUE, VALUE, TIMEOUT, IDLE_FUNC) mbed_queue_push(QUEUE, VALUE, TIMEOUT) +#define FIFO_POP(QUEUE, TIMEOUT, IDLE_FUNC) mbed_queue_pop(QUEUE, TIMEOUT) +#define FIFO_INIT(QUEUE,QSIZE) QUEUE = mbed_queue_new(QSIZE) +#define FIFO_DEINIT(QUEUE) mbed_queue_delete(QUEUE) + + +#define WAIT_FOREVER 0xffffffff +#define SEM_OK true +#define THREAD_OK true +#define QUEUE_OK true +#define FIFO_OK true +#define OSPRIORITYNORMAL 1 +#define OSPRIORITYREALTIME 2 +#define OSPRIORITYABOVENORMAL 3 +#define DELAYms(n) mbed_delay(n) + +#ifdef __cplusplus +} +#endif + + +#endif /* MX_WIFI_MBED_OS_H */ diff --git a/connectivity/libraries/CMakeLists.txt b/connectivity/libraries/CMakeLists.txt index 7d856fa25ce..21af84b3175 100644 --- a/connectivity/libraries/CMakeLists.txt +++ b/connectivity/libraries/CMakeLists.txt @@ -2,7 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) - add_subdirectory(tests/UNITTESTS) + if(NOT BUILD_GREENTEA_TESTS) + add_subdirectory(tests/UNITTESTS) + endif() endif() add_subdirectory(mbed-coap) diff --git a/connectivity/lorawan/include/lorawan/LoRaRadio.h b/connectivity/lorawan/include/lorawan/LoRaRadio.h index 601c6b9e523..f6673399ac6 100644 --- a/connectivity/lorawan/include/lorawan/LoRaRadio.h +++ b/connectivity/lorawan/include/lorawan/LoRaRadio.h @@ -200,7 +200,7 @@ typedef struct radio_fsk_packet_handler { /** * Storage for RSSI value of the received signal. */ - int8_t rssi_value; + int16_t rssi_value; /** * Automated frequency correction value. @@ -333,7 +333,7 @@ typedef struct radio_lora_packet_handler { /** * RSSI value in dBm for the received packet. */ - int8_t rssi_value; + int16_t rssi_value; /** * Size of the transmitted or received packet. diff --git a/connectivity/lorawan/mbed_lib.json b/connectivity/lorawan/mbed_lib.json index 5de19498e9a..04201a94c8f 100644 --- a/connectivity/lorawan/mbed_lib.json +++ b/connectivity/lorawan/mbed_lib.json @@ -1,5 +1,6 @@ { "name": "lora", + "requires": ["mbedtls", "events"], "config": { "phy": { "help": "LoRa PHY region: EU868, AS923, AU915, CN470, CN779, EU433, IN865, KR920, US915", diff --git a/connectivity/lorawan/source/LoRaWANStack.cpp b/connectivity/lorawan/source/LoRaWANStack.cpp index d60fa0b9d48..22d45454739 100644 --- a/connectivity/lorawan/source/LoRaWANStack.cpp +++ b/connectivity/lorawan/source/LoRaWANStack.cpp @@ -619,29 +619,12 @@ void LoRaWANStack::post_process_tx_with_reception() } } } else { - // handle UNCONFIRMED case here, RX slots were turned off due to - // valid packet reception. - uint8_t prev_QOS_level = _loramac.get_prev_QOS_level(); - uint8_t QOS_level = _loramac.get_QOS_level(); - - // We will not apply QOS on the post-processing of the previous - // outgoing message as we would have received QOS instruction in response - // to that particular message - if (QOS_level > LORAWAN_DEFAULT_QOS && _qos_cnt < QOS_level - && (prev_QOS_level == QOS_level)) { - _ctrl_flags &= ~TX_DONE_FLAG; - const int ret = _queue->call(this, &LoRaWANStack::state_controller, - DEVICE_STATE_SCHEDULING); - MBED_ASSERT(ret != 0); - (void) ret; - _qos_cnt++; - tr_info("QOS: repeated transmission #%d queued", _qos_cnt); - } else { - _loramac.post_process_mcps_req(); - _ctrl_flags |= TX_DONE_FLAG; - make_tx_metadata_available(); - state_controller(DEVICE_STATE_STATUS_CHECK); - } + // On reception, end-device shall stop sending retransmission as stated in lorawan v1.0.2 + // specification, page 24, line 25-27 + _loramac.post_process_mcps_req(); + _ctrl_flags |= TX_DONE_FLAG; + make_tx_metadata_available(); + state_controller(DEVICE_STATE_STATUS_CHECK); } } @@ -756,7 +739,10 @@ void LoRaWANStack::process_reception_timeout(bool is_timeout) _loramac.on_radio_rx_timeout(is_timeout); if (slot == RX_SLOT_WIN_2 && !_loramac.nwk_joined()) { - state_controller(DEVICE_STATE_JOINING); + const int ret = _queue->call_in( + 500, this, &LoRaWANStack::state_controller, DEVICE_STATE_JOINING); + MBED_ASSERT(ret != 0); + (void)ret; return; } diff --git a/connectivity/lorawan/system/lorawan_data_structures.h b/connectivity/lorawan/system/lorawan_data_structures.h index 7ce8cb33cfc..724bc87e7f2 100644 --- a/connectivity/lorawan/system/lorawan_data_structures.h +++ b/connectivity/lorawan/system/lorawan_data_structures.h @@ -908,7 +908,7 @@ typedef struct { * * Provides a certain QOS level set by network server in LinkADRReq MAC * command. The device will transmit the given UNCONFIRMED message nb_trials - * time with same frame counter until a downlink is received. Standard defined + * time with the same frame counter OR until a downlink is received. Standard defined * range is 1:15. Data rates will NOT be adapted according to chapter 18.4. */ uint8_t nb_trials; diff --git a/connectivity/lwipstack/lwip-sys/arch/cc.h b/connectivity/lwipstack/lwip-sys/arch/cc.h index c84c523389c..8e46dd5eeb2 100644 --- a/connectivity/lwipstack/lwip-sys/arch/cc.h +++ b/connectivity/lwipstack/lwip-sys/arch/cc.h @@ -124,6 +124,10 @@ void trace_to_ascii_hex_dump(char* prefix, int len, char *data); #define LWIP_PLATFORM_HTONS(x) __REV16(x) #define LWIP_PLATFORM_HTONL(x) __REV(x) +// Provide inline replacements for htons() and htonl() +#define lwip_htons(x) __REV16(x) +#define lwip_htonl(x) __REV(x) + /* Define the memory area for the lwip's memory pools */ #ifndef MEMP_SECTION #if defined(TARGET_LPC1768) diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index 6e725819b44..bf7e742a5c8 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -161,6 +161,10 @@ "nd6-queueing": { "help": "queue outgoing IPv6 packets while MAC address is being resolved", "value": 0 + }, + "netbuf-recvinfo-enabled": { + "help": "Enable LWIP option to append destination addr and port to every netbuf", + "value": false } }, "target_overrides": { diff --git a/connectivity/mbedtls/CMakeLists.txt b/connectivity/mbedtls/CMakeLists.txt index f000967e336..7bacaa6d970 100644 --- a/connectivity/mbedtls/CMakeLists.txt +++ b/connectivity/mbedtls/CMakeLists.txt @@ -2,7 +2,9 @@ # SPDX-License-Identifier: Apache-2.0 if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) - add_subdirectory(tests/UNITTESTS) + if(NOT BUILD_GREENTEA_TESTS) + add_subdirectory(tests/UNITTESTS) + endif() endif() target_include_directories(mbed-mbedtls diff --git a/connectivity/nanostack/coap-service/source/coap_security_handler.c b/connectivity/nanostack/coap-service/source/coap_security_handler.c index 61c514aae24..1ebea0b4ba0 100644 --- a/connectivity/nanostack/coap-service/source/coap_security_handler.c +++ b/connectivity/nanostack/coap-service/source/coap_security_handler.c @@ -23,12 +23,12 @@ #ifdef COAP_SECURITY_AVAILABLE +#include "mbedtls/version.h" #include "mbedtls/sha256.h" #include "mbedtls/error.h" #include "mbedtls/platform.h" #include "mbedtls/ssl_cookie.h" #include "mbedtls/entropy.h" -#include "mbedtls/entropy_poll.h" #include "mbedtls/ctr_drbg.h" #include "mbedtls/hmac_drbg.h" #include "mbedtls/ssl_ciphersuites.h" @@ -310,6 +310,7 @@ static int simple_cookie_check(void *ctx, /**** Key export function ****/ #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) +#if (MBEDTLS_VERSION_MAJOR < 3) static int export_key_block(void *ctx, const unsigned char *mk, const unsigned char *kb, size_t maclen, size_t keylen, size_t ivlen) @@ -330,6 +331,7 @@ static int export_key_block(void *ctx, return 0; } #endif +#endif static int coap_security_handler_configure_keys(coap_security_t *sec, coap_security_keys_t keys, bool is_server) { @@ -343,9 +345,15 @@ static int coap_security_handler_configure_keys(coap_security_t *sec, coap_secur break; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_pk_parse_key(&sec->_pkey, keys._priv_key, keys._priv_key_len, NULL, 0, DRBG_RANDOM, &sec->_drbg) < 0) { + break; + } +#else if (mbedtls_pk_parse_key(&sec->_pkey, keys._priv_key, keys._priv_key_len, NULL, 0) < 0) { break; } +#endif if (0 != mbedtls_ssl_conf_own_cert(&sec->_conf, &sec->_owncert, &sec->_pkey)) { break; @@ -378,10 +386,15 @@ static int coap_security_handler_configure_keys(coap_security_t *sec, coap_secur mbedtls_ssl_conf_ciphersuites(&sec->_conf, ECJPAKE_SUITES); #endif /* !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) */ +#if (MBEDTLS_VERSION_MAJOR >= 3) + tr_error("FATAL ERROR: support for mbedtls_ssl_set_export_keys_cb() not implemented"); +#else //NOTE: If thread starts supporting PSK in other modes, then this will be needed! mbedtls_ssl_conf_export_keys_cb(&sec->_conf, export_key_block, &sec->_keyblk); +#endif + ret = 0; #endif break; @@ -512,9 +525,15 @@ int coap_security_handler_continue_connecting(coap_security_t *sec) return ret; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (sec->_ssl.private_state == MBEDTLS_SSL_HANDSHAKE_OVER) { + return 0; + } +#else if (sec->_ssl.state == MBEDTLS_SSL_HANDSHAKE_OVER) { return 0; } +#endif } if (ret == MBEDTLS_ERR_SSL_WANT_READ || ret == MBEDTLS_ERR_SSL_WANT_WRITE) { diff --git a/connectivity/nanostack/coap-service/source/include/coap_security_handler.h b/connectivity/nanostack/coap-service/source/include/coap_security_handler.h index 1f25a310d36..70c9d6075f7 100644 --- a/connectivity/nanostack/coap-service/source/include/coap_security_handler.h +++ b/connectivity/nanostack/coap-service/source/include/coap_security_handler.h @@ -20,12 +20,8 @@ #include "ns_types.h" #ifdef NS_USE_EXTERNAL_MBED_TLS -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else // cppcheck-suppress preprocessorErrorDirective -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/version.h" #if defined(MBEDTLS_SSL_TLS_C) #include "mbedtls/ssl.h" diff --git a/connectivity/nanostack/coap-service/test/coap-service/unittest/coap_security_handler/test_coap_security_handler.c b/connectivity/nanostack/coap-service/test/coap-service/unittest/coap_security_handler/test_coap_security_handler.c index 9b3b1bfd209..0f12c51a0bf 100644 --- a/connectivity/nanostack/coap-service/test/coap-service/unittest/coap_security_handler/test_coap_security_handler.c +++ b/connectivity/nanostack/coap-service/test/coap-service/unittest/coap_security_handler/test_coap_security_handler.c @@ -184,7 +184,7 @@ bool test_coap_security_handler_connect() } mbedtls_stub.counter = 0; - mbedtls_stub.retArray[5] = MBEDTLS_ERR_SSL_BAD_HS_FINISHED; + mbedtls_stub.retArray[5] = MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; if (-1 != coap_security_handler_connect_non_blocking(handle, true, DTLS, keys, 0, 1)) { return false; @@ -230,9 +230,9 @@ bool test_coap_security_handler_continue_connecting() } mbedtls_stub.counter = 0; - mbedtls_stub.retArray[0] = MBEDTLS_ERR_SSL_BAD_HS_FINISHED; + mbedtls_stub.retArray[0] = MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; - if (MBEDTLS_ERR_SSL_BAD_HS_FINISHED != coap_security_handler_continue_connecting(handle)) { + if (MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL != coap_security_handler_continue_connecting(handle)) { return false; } diff --git a/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c b/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c index be8d31955b7..b63eb0269d2 100644 --- a/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c +++ b/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c @@ -27,8 +27,11 @@ int mbedtls_ssl_handshake_step(mbedtls_ssl_context *ssl) if (mbedtls_stub.retArray[mbedtls_stub.counter] == HANDSHAKE_FINISHED_VALUE || mbedtls_stub.retArray[mbedtls_stub.counter] == HANDSHAKE_FINISHED_VALUE_RETURN_ZERO) { - +#if (MBEDTLS_VERSION_MAJOR >= 3) + ssl->private_state = MBEDTLS_SSL_HANDSHAKE_OVER; +#else ssl->state = MBEDTLS_SSL_HANDSHAKE_OVER; +#endif if (mbedtls_stub.retArray[mbedtls_stub.counter] == HANDSHAKE_FINISHED_VALUE_RETURN_ZERO) { return 0; } @@ -346,9 +349,16 @@ int mbedtls_entropy_add_source(mbedtls_entropy_context *a, } //From pk.h +#if (MBEDTLS_VERSION_MAJOR >= 3) +int mbedtls_pk_parse_key(mbedtls_pk_context *ctx, + const unsigned char *b, size_t c, + const unsigned char *d, size_t e, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng) +#else int mbedtls_pk_parse_key(mbedtls_pk_context *a, const unsigned char *b, size_t c, const unsigned char *d, size_t e) +#endif { if (mbedtls_stub.useCounter) { return mbedtls_stub.retArray[mbedtls_stub.counter++]; @@ -396,6 +406,7 @@ void mbedtls_ssl_conf_dtls_cookies(mbedtls_ssl_config *conf, } } +#if (MBEDTLS_VERSION_MAJOR < 3) void mbedtls_ssl_conf_export_keys_cb(mbedtls_ssl_config *conf, mbedtls_ssl_export_keys_t *f_export_keys, void *p_export_keys) @@ -408,6 +419,7 @@ void mbedtls_ssl_conf_export_keys_cb(mbedtls_ssl_config *conf, f_export_keys(p_export_keys, &value, "", 0, 20, 0); //success case } } +#endif int mbedtls_ssl_session_reset(mbedtls_ssl_context *ssl) { diff --git a/connectivity/nanostack/include/nanostack-interface/Nanostack.h b/connectivity/nanostack/include/nanostack-interface/Nanostack.h index 09ffc51f1eb..b4c83706b90 100644 --- a/connectivity/nanostack/include/nanostack-interface/Nanostack.h +++ b/connectivity/nanostack/include/nanostack-interface/Nanostack.h @@ -302,20 +302,6 @@ class Nanostack : public OnboardNetworkStack, private mbed::NonCopyable 0 * * Asynch data request is mac standard extension. asynch_channel_list include channel mask which channel message is requested to send. */ -typedef void mcps_data_request_ext(const mac_api_t *api, const mcps_data_req_t *data, const mcps_data_req_ie_list_t *ie_ext, const struct channel_list_s *asynch_channel_list, mac_data_priority_t priority); +typedef void mcps_data_request_ext(const mac_api_t *api, const mcps_data_req_t *data, const mcps_data_req_ie_list_t *ie_ext, const struct channel_list_s *asynch_channel_list, mac_data_priority_t priority, uint8_t phy_mode_id); /** * @brief mcps_purge_request MCPS_PURGE request call @@ -192,6 +193,16 @@ typedef void mcps_ack_data_req_ext(const mac_api_t *api, mcps_ack_data_payload_t typedef void mcps_edfe_handler(const mac_api_t *api, mcps_edfe_response_t *response_message); +/** + * @brief mode_switch_resolver Callback to resolve configuration behind received PHY mode ID + * @param api The API which handled the response + * @param phy_mode_id PHY mode ID to be resolved + * @param rf_config Resolved configuration + * @return 0 in case of success, negative otherwise + */ +typedef int8_t mode_switch_resolver(const mac_api_t *api, uint8_t phy_mode_id, phy_rf_channel_configuration_s *rf_config); + + /** * @brief mcps_purge_confirm MCPS-PURGE confirm is called as a response to MCPS-PURGE request * @param api The API which handled the request @@ -272,6 +283,16 @@ typedef int8_t mac_api_enable_mcps_ext(mac_api_t *api, typedef int8_t mac_api_enable_mcps_edfe_ext(mac_api_t *api, mcps_edfe_handler *edfe_ind_cb); +/** + * @brief mac_api_mode_switch_resolver_ext Initialises mode switch resolver callback. Upper layer must configure function when mode switch is used. + * @param api mac_api_t pointer, which is created by application. + * @param mode_resolver_cb Upper layer function to resolve received PHY mode ID + * @param base_phy_mode Base PHY mode, device returns to this mode after mode switch transmission or reception + * @return -1 if error, 0 otherwise + */ +typedef int8_t mac_api_mode_switch_resolver_ext(mac_api_t *api, + mode_switch_resolver *mode_resolver_cb, uint8_t base_phy_mode); + /** * \brief Struct mac_api_s defines functions for two-way communications between external MAC and Upper layer. * Application creates mac_api_t object by calling external MAC's creator function. @@ -279,30 +300,32 @@ typedef int8_t mac_api_enable_mcps_edfe_ext(mac_api_t *api, * Then MAC is operated by Upper layer by calling MLME or MCPS primitive functions. */ struct mac_api_s { - mac_api_initialize *mac_initialize; /**< MAC initialize function to use */ - mac_api_enable_mcps_ext *mac_mcps_extension_enable; /**< MAC MCPS IE extension enable function, optional feature */ - mac_api_enable_mcps_edfe_ext *mac_mcps_edfe_enable; /**< MAC MCPS MCPS EDFE frame extension enable function, optional feature */ + mac_api_initialize *mac_initialize; /**< MAC initialize function to use */ + mac_api_enable_mcps_ext *mac_mcps_extension_enable; /**< MAC MCPS IE extension enable function, optional feature */ + mac_api_enable_mcps_edfe_ext *mac_mcps_edfe_enable; /**< MAC MCPS MCPS EDFE frame extension enable function, optional feature */ + mac_api_mode_switch_resolver_ext *mac_mode_switch_resolver_set; /**< MAC Mode switch resolver function set, optional feature */ //External MAC callbacks - mlme_request *mlme_req; /**< MAC MLME request function to use */ - mcps_data_request *mcps_data_req; /**< MAC MCPS data request function to use */ - mcps_data_request_ext *mcps_data_req_ext; /**< MAC MCPS data request with Information element extension function to use */ - mcps_purge_request *mcps_purge_req; /**< MAC MCPS purge request function to use */ + mlme_request *mlme_req; /**< MAC MLME request function to use */ + mcps_data_request *mcps_data_req; /**< MAC MCPS data request function to use */ + mcps_data_request_ext *mcps_data_req_ext; /**< MAC MCPS data request with Information element extension function to use */ + mcps_purge_request *mcps_purge_req; /**< MAC MCPS purge request function to use */ //Upper layer callbacksMLME_ASSOCIATE - mcps_data_confirm *data_conf_cb; /**< MAC MCPS data confirm callback function */ - mcps_data_confirm_ext *data_conf_ext_cb; /**< MAC MCPS data confirm with payload callback function */ - mcps_data_indication *data_ind_cb; /**< MAC MCPS data indication callback function */ - mcps_data_indication_ext *data_ind_ext_cb; /**< MAC MCPS data indication with IE extension's callback function */ - mcps_edfe_handler *edfe_ind_cb; /**< MAC MCPS EDFE detection extension's callback function */ - mcps_ack_data_req_ext *enhanced_ack_data_req_cb; /**< Enhanced ACK IE element and payload request from MAC user */ - mcps_purge_confirm *purge_conf_cb; /**< MAC MCPS purge confirm callback function */ - mlme_confirm *mlme_conf_cb; /**< MAC MLME confirm callback function */ - mlme_indication *mlme_ind_cb; /**< MAC MLME indication callback function */ - mac_ext_mac64_address_set *mac64_set; /**< MAC extension function to set mac64 address */ - mac_ext_mac64_address_get *mac64_get; /**< MAC extension function to get mac64 address */ - mac_storage_decription_sizes_get *mac_storage_sizes_get; /**< Getter function to query data storage sizes from MAC */ - - int8_t parent_id; /**< Upper layer id */ - uint16_t phyMTU; /**< Maximum Transmission Unit(MTU) used by MAC*/ + mcps_data_confirm *data_conf_cb; /**< MAC MCPS data confirm callback function */ + mcps_data_confirm_ext *data_conf_ext_cb; /**< MAC MCPS data confirm with payload callback function */ + mcps_data_indication *data_ind_cb; /**< MAC MCPS data indication callback function */ + mcps_data_indication_ext *data_ind_ext_cb; /**< MAC MCPS data indication with IE extension's callback function */ + mcps_edfe_handler *edfe_ind_cb; /**< MAC MCPS EDFE detection extension's callback function */ + mode_switch_resolver *mode_resolver_cb; /**< MAC Mode switch resolver callback function */ + mcps_ack_data_req_ext *enhanced_ack_data_req_cb; /**< Enhanced ACK IE element and payload request from MAC user */ + mcps_purge_confirm *purge_conf_cb; /**< MAC MCPS purge confirm callback function */ + mlme_confirm *mlme_conf_cb; /**< MAC MLME confirm callback function */ + mlme_indication *mlme_ind_cb; /**< MAC MLME indication callback function */ + mac_ext_mac64_address_set *mac64_set; /**< MAC extension function to set mac64 address */ + mac_ext_mac64_address_get *mac64_get; /**< MAC extension function to get mac64 address */ + mac_storage_decription_sizes_get *mac_storage_sizes_get; /**< Getter function to query data storage sizes from MAC */ + + int8_t parent_id; /**< Upper layer id */ + uint16_t phyMTU; /**< Maximum Transmission Unit(MTU) used by MAC*/ }; /** diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h index eb87675af5c..6be75ae8fe9 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/net_interface.h @@ -99,6 +99,8 @@ typedef enum arm_library_event_type_e { #define SOCKET_NO_RAM (10 << 4) /** TCP connection problem indication (RFC 1122 R1) */ #define SOCKET_CONNECTION_PROBLEM (11 << 4) +/** Socket is busy or Radio is returning CCA failure */ +#define SOCKET_BUSY (12 << 4) #define SOCKET_BIND_DONE SOCKET_CONNECT_DONE /**< Backward compatibility */ #define SOCKET_BIND_FAIL SOCKET_CONNECT_FAIL /**< Backward compatibility */ diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test.h index 234c12e0b10..76ded833f12 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test.h @@ -39,6 +39,23 @@ extern "C" { #include "ns_types.h" +/** + * \brief Set Wi-SUN version number + * + * Sets the Wi-SUN protocol version. + * 1 = Wi-SUN FAN 1.0 + * 2 = Wi-SUN FAN 1.1 + * + * Set version to 0 to stop override and use stack default + * + * \param interface_id Network Interface + * \param version Wi-SUN version + * + * \return 0 OK + * \return <0 Failure + */ + +int ws_test_version_set(int8_t interface_id, uint8_t version); /** * \brief Set Pan size. * diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test_ext.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test_ext.h new file mode 100644 index 00000000000..137f0e8c466 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/net_ws_test_ext.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef NET_WS_TEST_EXT_H_ +#define NET_WS_TEST_EXT_H_ + +/** + * \file net_ws_test_ext.h + * \brief Wi-SUN Library External Test API. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ns_types.h" + +/* Test procedure triggers + * + * Example about using the triggers during bootstrap to trigger + * messages and state transitions. + * + * Border Router Node + * + * Join state 1 (select PAN) + * + * PROC_PA + * ------- PAN Advertisement------------> + * + * PROC_EAPOL + * Select EAPOL target + * Join state 2 (authenticate) + * <------ EAPOL authentication --------> + * Join State 3 (acquire PAN configuration) + * + * PROC_PC + * ------- PAN Configuration -----------> + * Join state 4 (configure routing) + * + * PROC_DIO + * ------- DIO -------------------------> + * Neighbor discovery (NS probing for ETX) + * Create RPL candidate parent set + * + * PROC_RPL + * Select RPL parent + * <------ DHCP ------------------------> + * + * PROC_DAO + * <------ DAO -------------------------- + * ------- DAO acknowledge -------------> + * + * Join state 5 (operational) + * + * + * On automatic mode the PROC_PAS, PROC_EAPOL, PROC_PCS, PROC_DIS and PROC_RPL + * will be triggered automatically by the node during the bootstrap. + * + */ + +/** + * @brief Test procedure triggers. + */ +typedef enum { + PROC_DIS, /* trigger DODAG information object solicit (node) */ + PROC_DIO, /* trigger DODAG information object (BR, node) */ + PROC_DAO, /* trigger Destination advertisement object (node) */ + + PROC_PAS, /* trigger PAN Advertisement Solicit (node) */ + PROC_PA, /* trigger PAN Advertisement (BR, node) */ + PROC_PCS, /* trigger PAN Configuration Solicit (node) */ + PROC_PC, /* trigger PAN Configuration (BR, node) */ + + PROC_EAPOL, /* trigger EAPOL target selection (initiates authentication, node) */ + PROC_RPL, /* trigger RPL parent selection (node) */ + + PROC_AUTO_ON, /* trigger bootstrap test procedures automatically */ + PROC_AUTO_OFF, /* disable automatic bootstrap test procedure triggering */ + + MSG_NONE +} ws_test_proc_t; + +/** + * Trigger a test procedure + * + * Can be used to trigger a test procedure, e.g. to send a message (DIS, + * DIO, DAO, PAS, PS, PCS and PC) or to trigger bootstrap state change + * on node e.g. EAPOL target selection. + * + * \param interface_id Network Interface ID >= 0 or -1 for Wi-SUN mesh interface + * Default value is -1 + * \param procedure Triggered procedure + * \param parameters Parameters for future extensions, shall be set to NULL + * + * \return 0 Success + * \return <0 Failure + */ +int ws_test_procedure_trigger(int8_t interface_id, ws_test_proc_t procedure, void *parameters); + +#ifdef __cplusplus +} +#endif + +#endif /* NET_WS_TEST_EXT_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h index fccded2cfa9..f550430e661 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h @@ -61,23 +61,39 @@ static inline void ns_sha256_clone(ns_sha256_context *dst, static inline void ns_sha256_starts(ns_sha256_context *ctx) { +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256_starts(ctx, 0); +#else (void)mbedtls_sha256_starts_ret(ctx, 0); +#endif } static inline void ns_sha256_update(ns_sha256_context *ctx, const void *input, size_t ilen) { +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256_update(ctx, input, ilen); +#else (void)mbedtls_sha256_update_ret(ctx, input, ilen); +#endif } static inline void ns_sha256_finish(ns_sha256_context *ctx, void *output) { +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256_finish(ctx, output); +#else (void)mbedtls_sha256_finish_ret(ctx, output); +#endif } static inline void ns_sha256(const void *input, size_t ilen, void *output) { +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256(input, ilen, output, 0); +#else (void)mbedtls_sha256_ret(input, ilen, output, 0); +#endif } /* Extensions to standard mbed TLS - output the first bits of a hash only */ @@ -85,10 +101,18 @@ static inline void ns_sha256(const void *input, size_t ilen, void *output) static inline void ns_sha256_finish_nbits(ns_sha256_context *ctx, void *output, unsigned obits) { if (obits == 256) { +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256_finish(ctx, output); +#else (void)mbedtls_sha256_finish_ret(ctx, output); +#endif } else { uint8_t sha256[32]; +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256_finish(ctx, sha256); +#else (void)mbedtls_sha256_finish_ret(ctx, sha256); +#endif memcpy(output, sha256, obits / 8); } } @@ -96,10 +120,18 @@ static inline void ns_sha256_finish_nbits(ns_sha256_context *ctx, void *output, static inline void ns_sha256_nbits(const void *input, size_t ilen, void *output, unsigned obits) { if (obits == 256) { +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256(input, ilen, output, 0); +#else (void)mbedtls_sha256_ret(input, ilen, output, 0); +#endif } else { uint8_t sha256[32]; +#if (MBEDTLS_VERSION_MAJOR >= 3) + (void)mbedtls_sha256(input, ilen, sha256, 0); +#else (void)mbedtls_sha256_ret(input, ilen, sha256, 0); +#endif memcpy(output, sha256, obits / 8); } } diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_time_api.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_time_api.h index 4b1907cfc90..14be92dd94a 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_time_api.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/ns_time_api.h @@ -28,6 +28,24 @@ #include "ns_types.h" +/** + * Time zone information structure. + * + * Daylight saving time and time zone information learned by network stack + * + */ +typedef struct timezone_info { + /** Timestamp of the Daylight saving time change*/ + uint64_t timestamp; + /** Time zone information in minutes*/ + int16_t timezone; + /** Change that is applied when timestamp is reached*/ + int16_t deviation; + /** Time configuration status bit field + * "bit xxxxxxxxxxxxxxxS" 0 = false 1 = true Daylight saving time status*/ + uint16_t status; +} timezone_info_t; + /** * System time read callback. * @@ -48,6 +66,22 @@ typedef uint64_t ns_time_api_system_time_callback(void); */ typedef void ns_time_api_system_time_write_callback(uint64_t write_time); +/** + * New time zone and daylight saving time information learned from stack. + * + * Called when network stack learns the time zone and daylights saving time information. + * + * In Wi-SUN Border router can distribute this information to synchronize all nodes in network. + * This information is updated roughly once a day using DHCPv6 protocol + * + * If network stack does not have the information this is not called and can be called when information becomes available. + * This can be called multiple times with same information. + * + * \param info_ptr time zone and daylight saving time configuration. + * + */ +typedef void ns_time_api_time_configuration_notify_callback(timezone_info_t *info_ptr); + /** * System time read callback set. * @@ -68,4 +102,15 @@ void ns_time_api_system_time_callback_set(ns_time_api_system_time_callback callb */ void ns_time_api_system_time_write_callback_set(ns_time_api_system_time_write_callback callback_wr); +/** + * Set system time configuration notify callback. + * + * Sets system time configuration notify callback that is called if network stack + * learns time information from other devices in the network. + * + * \param callback_wr system time write callback. + * + */ +void ns_time_api_time_configuration_notify_callback_set(ns_time_api_time_configuration_notify_callback callback_wr); + #endif /* NS_TIME_API_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/platform/arm_hal_phy.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/platform/arm_hal_phy.h index b4a19137426..05b34be2368 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/platform/arm_hal_phy.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/platform/arm_hal_phy.h @@ -143,6 +143,7 @@ typedef struct phy_signal_info_s { typedef struct phy_csma_params { uint32_t backoff_time; /**< CSMA Backoff us time before start CCA & TX. 0 should disable current backoff*/ bool cca_enabled; /**< True will affect CCA check false start TX direct after backoff */ + bool mode_switch_phr; /**< True - Frame is a mode switch PHR. In this case PHY driver should skip FCS and send two byte PHR as it is given by TX callback */ } phy_csma_params_t; /** PHY modulation scheme */ diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h index 7cf8b577484..fe19acd75e6 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/socket_api.h @@ -115,6 +115,7 @@ extern "C" { * | | | TCP: some data acknowledged (d_len = data remaining in send queue) | * | SOCKET_NO_RAM | 0xA0 | No RAM available. | * | SOCKET_CONNECTION_PROBLEM | 0xB0 | TCP connection is retrying. | + * | SOCKET_BUSY | 0xC0 | Socket is busy or Radio channel is returning CCA failure. | * * * \section socket-tcp How to use TCP sockets: diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h index a1c15aa0614..2450de8546d 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h @@ -74,6 +74,36 @@ typedef struct bbr_radius_timing { uint8_t radius_retry_count; } bbr_radius_timing_t; +/** + * \brief Daylights saving time parameters. + */ +typedef struct bbr_timezone_configuration { + /** Timestamp of the Daylight saving time change*/ + uint64_t timestamp; + /** Time zone information in minutes*/ + int16_t timezone; + /** Change that is applied when timestamp is reached*/ + int16_t deviation; + /** Time configuration status bit field + * "bit xxxxxxxxxxxxxxxS" 0 = false 1 = true Daylight saving time status*/ + uint16_t status; +} bbr_timezone_configuration_t; + + +/** + * \brief Border router configuration. + */ +typedef struct bbr_configuration_s { + uint32_t dhcp_address_lifetime; /**< DHCP address lifetime in seconds minimum 2 hours and maximum few days*/ + uint32_t rpl_default_lifetime; /**< RPL default lifetime value from 30 minutes to 16 hours*/ + uint16_t dag_max_rank_increase; /**< DIO Max rank increase. Range 0-2048 */ + uint16_t min_hop_rank_increase; /**< DIO Min hop rank increase. range 32-256 */ + uint16_t options; /**< Border router configuration options */ + uint8_t dio_interval_min; /**< DIO interval min. range 1-255 */ + uint8_t dio_interval_doublings; /**< DIO interval doublings. range 1-8 */ + uint8_t dio_redundancy_constant; /**< DIO redundancy constant. Range 0-10 */ +} bbr_configuration_t; + /** * Start backbone border router service. * @@ -256,7 +286,52 @@ int ws_bbr_eapol_node_limit_set(int8_t interface_id, uint16_t limit); int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validation); /** - * Sets RPL parameters + * Sets Border router configuration + * + * Sets the configuration to the border router. Use ws_configuration_get to get + * the settings and modify wanted parameters. + * + * Minor validation is done to parameters, but full validation must be done + * at application level + * + * \param interface_id Network interface ID. + * \param configuration_ptr Configuration structure. + * + * \return 0, Configuration parameters set. + * \return <0 Parameter set failed. + */ +int ws_bbr_configuration_set(int8_t interface_id, bbr_configuration_t *configuration_ptr); + +/** + * Get Border router configuration + * + * Gets the current configuration to the border router. + * + * \param interface_id Network interface ID. + * \param configuration_ptr Configuration structure. + * + * \return 0, Configuration parameters set. + * \return <0 Parameter set failed. + */ +int ws_bbr_configuration_get(int8_t interface_id, bbr_configuration_t *configuration_ptr); + +/** + * validate Border router configuration + * + * Minor validation is done to parameters. + * Full validation must be done at application level. + * + * \param interface_id Network interface ID. + * \param configuration_ptr Configuration structure. + * + * \return 0, Configuration parameters set. + * \return <0 Parameter set failed. + */ +int ws_bbr_configuration_validate(int8_t interface_id, bbr_configuration_t *configuration_ptr); + +/** + * Sets RPL parameters (DEPRECATED) + * Use ws_bbr_configuration_set instead. * * Sets RPL DIO trickle parameters. * @@ -271,7 +346,8 @@ int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validatio int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uint8_t dio_interval_doublings, uint8_t dio_redundancy_constant); /** - * Gets RPL parameters + * Gets RPL parameters (DEPRECATED) + * Use ws_bbr_configuration_get instead. * * Gets RPL DIO trickle parameters. * @@ -286,7 +362,8 @@ int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uin int ws_bbr_rpl_parameters_get(int8_t interface_id, uint8_t *dio_interval_min, uint8_t *dio_interval_doublings, uint8_t *dio_redundancy_constant); /** - * Validate RPL parameters + * Validate RPL parameters (DEPRECATED) + * Use ws_bbr_configuration_validate instead. * * Validates RPL DIO trickle parameters. * @@ -521,4 +598,22 @@ int ws_bbr_radius_timing_validate(int8_t interface_id, bbr_radius_timing_t *timi */ int ws_bbr_dns_query_result_set(int8_t interface_id, const uint8_t address[16], char *domain_name_ptr); +/** + * \brief A function to set time zone and daylights saving time configuration + * + * Border router distributes this information in DHCP Reply messages to + * all the devices joining to the Wi-SUN mesh network. + * + * Border router keeps this information until reboot and continues to distribute the information. + * If the information is changed the updates are sent to devices in network when they + * renew their address. This can take time from 1 to 24 hours + * + * \param interface_id Network interface ID. + * \param daylight_saving_time_ptr daylights saving time configuration. NULL if you want to remove the configuration. + * + * \return < 0 failure + * \return >= 0 success + */ +int ws_bbr_timezone_configuration_set(int8_t interface_id, bbr_timezone_configuration_t *daylight_saving_time_ptr); + #endif /* WS_BBR_API_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h b/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h index ddab5d40e51..b436bf24abd 100644 --- a/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h +++ b/connectivity/nanostack/sal-stack-nanostack/nanostack/ws_management_api.h @@ -78,6 +78,17 @@ extern "C" { #define CHANNEL_SPACING_800 0x05 /**< 800 khz */ #define CHANNEL_SPACING_1200 0x06 /**< 1200 khz */ +/* + * Wi-SUN FAN 1.1 Phy capability types. + * + */ +#define WS_PHY_TYPE_ID_FSK 0 /**< FSK phy type */ +#define WS_PHY_TYPE_ID_FSK_FEC 1 /**< FSK with FEC phy type */ +#define WS_PHY_TYPE_ID_OFDM1 2 /**< OFDM1 phy type */ +#define WS_PHY_TYPE_ID_OFDM2 3 /**< OFDM2 phy type */ +#define WS_PHY_TYPE_ID_OFDM3 4 /**< OFDM3 phy type */ +#define WS_PHY_TYPE_ID_OFDM4 5 /**< OFDM4 phy type */ + /* * Network Size definitions are device amount in hundreds of devices. * These definitions are meant to give some estimates of sizes. Any value can be given as parameter @@ -225,6 +236,28 @@ typedef struct ws_neighbour_info { ws_management_neighbor_type_e type; } ws_neighbour_info_t; + +/** + * @brief ws_management_pcap_t Wi-SUN FAN 1.1 Phy Capability type and operating mode + */ +typedef struct ws_management_pcap { + /** Phy type */ + uint8_t phy_type; + /** Phy operating mode */ + uint16_t operating_mode; +} ws_management_pcap_t; + +/** + * @brief ws_management_pcap_info_t Wi-SUN FAN 1.1 Phy Capability list for MDR support + */ +typedef struct ws_management_pcap_info { + /** Length of the capability */ + uint8_t length_of_list: 3; + /** Capability information */ + ws_management_pcap_t pcap[7]; +} ws_management_pcap_info_t; + + /** * Initialize Wi-SUN stack. * @@ -875,6 +908,20 @@ int ws_device_min_sens_set( int8_t interface_id, uint8_t device_min_sens); +/** + * Set Phy Capability support for MDR, FAN 1.1 feature + * + * + * \param interface_id Network interface ID. + * \param pcap_list pointer to supported list + * + * \return 0 Success. + * \return <0 Failure. + */ +int ws_management_phy_capability_set( + int8_t interface_id, + ws_management_pcap_info_t *pcap_list); + #ifdef __cplusplus } #endif diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan.c index 3069e00a56c..4f730e4763c 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan.c @@ -118,7 +118,7 @@ static uint8_t protocol_buffer_valid(buffer_t *b, protocol_interface_info_entry_ void protocol_init(void) { - tr_debug("P.Init\n"); + tr_debug("P.Init"); #ifdef PANA sec_libray_init(); #endif @@ -134,7 +134,7 @@ void protocol_6lowpan_stack(buffer_t *b) { protocol_interface_info_entry_t *cur = b->interface; if (protocol_buffer_valid(b, cur) == 0) { - tr_debug("Drop Packets\n"); + tr_debug("Drop Packets"); buffer_free(b); return; } @@ -230,7 +230,7 @@ void protocol_6lowpan_stack(buffer_t *b) b = tcp_up(b); break; default: - tr_debug("LLL\n"); + tr_debug("LLL"); b = buffer_free(b); break; } @@ -871,7 +871,7 @@ bool protocol_6lowpan_stagger_estimate_get(int8_t interface_id, uint32_t data_am } // For small networks sets 10 seconds stagger - if (network_size <= 100 && ws_info(cur_interface)) { + if (ws_info(cur_interface) && (network_size <= 100 || ws_test_proc_auto_trg(cur_interface))) { stagger_value = 10; } else { stagger_value = 1 + ((data_amount * 1024 * 8 * network_size) / datarate); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c index fa7ecae8b13..80b53382f1c 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c @@ -1548,7 +1548,7 @@ int8_t arm_network_processor_up(protocol_interface_info_entry_t *cur) { int8_t ret_val = -1; if ((cur->configure_flags & INTERFACE_SETUP_NETWORK_DRIVER_MASK) != INTERFACE_SETUP_NETWORK_DRIVER_READY) { - tr_debug("Interface not yet fully configured\n"); + tr_debug("Interface not yet fully configured"); ret_val = -5; } else { protocol_6lowpan_register_handlers(cur); @@ -2123,7 +2123,7 @@ static void nwk_rpl_dio_scan(protocol_interface_info_entry_t *cur) if (nwk_bootstrap_icmp_rpl_dis_msg_tx(cur)) { cur->bootsrap_state_machine_cnt = 45 << cur->nwk_rpl_scan_counter; cur->nwk_rpl_scan_counter++; - tr_debug("MC_DIS\n"); + tr_debug("MC_DIS"); cur->nwk_bootstrap_state = ER_RPL_SCAN; } else { cur->bootsrap_state_machine_cnt = 3; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/CMakeLists.txt index dc6e3f5c718..ef3b50ce2c0 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack @@ -83,6 +83,10 @@ target_sources(mbed-nanostack-sal_stack ws/ws_bbr_api.c ws/ws_bootstrap.c + ws/ws_bootstrap_6lbr.c + ws/ws_bootstrap_6ln.c + ws/ws_bootstrap_6lr.c + ws/ws_bootstrap_ffn.c ws/ws_cfg_settings.c ws/ws_common.c ws/ws_eapol_auth_relay.c @@ -104,6 +108,7 @@ target_sources(mbed-nanostack-sal_stack ws/ws_pae_supp.c ws/ws_pae_time.c ws/ws_pae_timers.c + ws/ws_phy.c ws/ws_stats.c ws/ws_test_api.c ) diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c index 515c16ce186..dbea21add57 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c @@ -476,13 +476,14 @@ void mac_helper_security_key_clean(protocol_interface_info_entry_t *interface) void mac_helper_coordinator_address_set(protocol_interface_info_entry_t *interface, addrtype_t adr_type, uint8_t *adr_ptr) { + uint16_t short_addr; mlme_set_t set_req; set_req.attr_index = 0; if (adr_type == ADDR_802_15_4_SHORT) { memcpy(interface->mac_parameters->mac_cordinator_info.mac_mlme_coord_address, adr_ptr, 2); interface->mac_parameters->mac_cordinator_info.cord_adr_mode = MAC_ADDR_MODE_16_BIT; - uint16_t short_addr = common_read_16_bit(interface->mac_parameters->mac_cordinator_info.mac_mlme_coord_address); + short_addr = common_read_16_bit(interface->mac_parameters->mac_cordinator_info.mac_mlme_coord_address); set_req.attr = macCoordShortAddress; set_req.value_pointer = &short_addr; set_req.value_size = 2; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.c index e6329bfbca0..5c054b99f54 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.c @@ -144,6 +144,33 @@ uint16_t mac_ie_nested_discover(uint8_t *payload_ptr, uint16_t length, mac_neste return 0; } +uint16_t mac_ie_nested_tagged_discover(uint8_t *payload_ptr, uint16_t length, mac_nested_payload_IE_t *nested_ie, uint8_t sub_tag_id) +{ + mac_nested_payload_IE_t ie_element; + uint8_t *sub_tag_ptr; + while (length >= 2) { + mac_ie_nested_id_parse(&ie_element, payload_ptr); + + if (length < ie_element.length + 2) { + return 0; + } + + sub_tag_ptr = ie_element.content_ptr; + if (ie_element.length > 1 && nested_ie->id == ie_element.id && *sub_tag_ptr == sub_tag_id) { + sub_tag_ptr++; + ie_element.length--; + nested_ie->content_ptr = sub_tag_ptr; + nested_ie->length = ie_element.length; + return ie_element.length; + } + + length -= ie_element.length + 2; + + payload_ptr += ie_element.length + 2; + } + return 0; +} + uint8_t mac_ie_header_discover(uint8_t *header_ptr, uint16_t length, mac_header_IE_t *header_ie) { mac_header_IE_t ie_element; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.h index 6cd0f5f82e9..0b6a36630ff 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_ie_lib.h @@ -49,6 +49,9 @@ uint16_t mac_ie_payload_discover(uint8_t *payload_ptr, uint16_t length, struct m /** Nested IE element discover inside parsed payload element */ uint16_t mac_ie_nested_discover(uint8_t *payload_ptr, uint16_t length, mac_nested_payload_IE_t *nested_ie); +/** Nested IE element discover with Sub Tag ID inside parsed payload element */ +uint16_t mac_ie_nested_tagged_discover(uint8_t *payload_ptr, uint16_t length, mac_nested_payload_IE_t *nested_ie, uint8_t sub_tag_id); + /** Header IE elemnt discover */ uint8_t mac_ie_header_discover(uint8_t *header_ptr, uint16_t length, struct mac_header_IE_s *header_ie); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c index 40aa092de52..380a2413b1b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ND/nd_router_object.c @@ -849,6 +849,7 @@ static void nd_update_registration(protocol_interface_info_entry_t *cur_interfac /* Register with 2 seconds off the lifetime - don't want the NCE to expire before the route */ ipv6_route_add_metric(neigh->ip_address, 128, cur_interface->id, neigh->ip_address, ROUTE_ARO, NULL, 0, neigh->lifetime - 2, 32); +#ifdef HAVE_RPL /* We need to know peer is a host before publishing - this needs MLE. Not yet established * what to do without MLE - might need special external/non-external prioritisation at root. * This "publish for RFD" rule comes from ZigBee IP. @@ -861,6 +862,7 @@ static void nd_update_registration(protocol_interface_info_entry_t *cur_interfac rpl_control_publish_host_address(protocol_6lowpan_rpl_domain, neigh->ip_address, neigh->lifetime); } } +#endif // HAVE_RPL protocol_6lowpan_neighbor_address_state_synch(cur_interface, aro->eui64, neigh->ip_address + 8); } else { @@ -870,10 +872,13 @@ static void nd_update_registration(protocol_interface_info_entry_t *cur_interfac neigh->lifetime = 2; ipv6_neighbour_set_state(&cur_interface->ipv6_neighbour_cache, neigh, IP_NEIGHBOUR_STALE); ipv6_route_add_metric(neigh->ip_address, 128, cur_interface->id, neigh->ip_address, ROUTE_ARO, NULL, 0, 4, 32); +#ifdef HAVE_RPL rpl_control_unpublish_address(protocol_6lowpan_rpl_domain, neigh->ip_address); +#endif } } +#ifdef HAVE_RPL void nd_remove_registration(protocol_interface_info_entry_t *cur_interface, addrtype_t ll_type, const uint8_t *ll_address) { ns_list_foreach_safe(ipv6_neighbour_t, cur, &cur_interface->ipv6_neighbour_cache.list) { @@ -888,7 +893,9 @@ void nd_remove_registration(protocol_interface_info_entry_t *cur_interface, addr } } } +#endif // HAVE_RPL +#ifdef HAVE_RPL /* Process ICMP Neighbor Solicitation (RFC 4861 + RFC 6775) ARO. */ bool nd_ns_aro_handler(protocol_interface_info_entry_t *cur_interface, const uint8_t *aro_opt, const uint8_t *slla_opt, const uint8_t *src_addr, aro_t *aro_out) { @@ -1032,6 +1039,7 @@ bool nd_ns_aro_handler(protocol_interface_info_entry_t *cur_interface, const uin return false; /* Tell ns_handler to not transmit now */ } } +#endif //HAVE_RPL buffer_t *nd_dac_handler(buffer_t *buf, protocol_interface_info_entry_t *cur) { @@ -1304,6 +1312,7 @@ void nd_ra_process_lowpan_context_option(protocol_interface_info_entry_t *cur, c lowpan_context_update(&cur->lowpan_contexts, cid_flags, lifetime, opt + 8, ctx_len, true); } #ifdef HAVE_6LOWPAN_ROUTER +#ifdef HAVE_RPL static void nd_ra_build(nd_router_t *cur, const uint8_t *address, protocol_interface_info_entry_t *cur_interface) { if (!(cur_interface->lowpan_info & INTERFACE_NWK_BOOTSRAP_ADDRESS_REGISTER_READY) || !icmp_nd_router_prefix_valid(cur)) { @@ -1393,7 +1402,6 @@ void nd_ra_build_by_abro(const uint8_t *abro, const uint8_t *dest, protocol_inte } } - void nd_trigger_ras_from_rs(const uint8_t *unicast_adr, protocol_interface_info_entry_t *cur_interface) { ns_list_foreach(nd_router_t, cur, &nd_router_list) { @@ -1470,7 +1478,7 @@ static nd_router_t *nd_router_object_scan_by_prefix(const uint8_t *ptr, nwk_inte return NULL; } - +#endif //HAVE_RPL #endif void gp_address_add_to_end(gp_ipv6_address_list_t *list, const uint8_t address[static 16]) diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bootstrap.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bootstrap.c index af16058f13d..38665c343d2 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bootstrap.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_bootstrap.c @@ -2308,7 +2308,7 @@ void thread_bootstrap_state_machine(protocol_interface_info_entry_t *cur) break; case ER_BOOTSRAP_DONE: - tr_debug("Thread SM:Bootstrap Done"); + tr_info("Thread SM:Bootstrap Done"); cur->nwk_nd_re_scan_count = 0; break; case ER_BOOTSTRAP_SCAN_FAIL: diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_commissioning_api.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_commissioning_api.c index f9939a1cc2f..fb69e2f087b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_commissioning_api.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_commissioning_api.c @@ -262,7 +262,7 @@ static int thread_commissioning_active_get_cb(int8_t service_id, uint8_t source_ if ((len = thread_meshcop_tlv_find(response_ptr->payload_ptr, response_ptr->payload_len, MESHCOP_TLV_NETWORK_MESH_LOCAL_ULA, &ptr)) > 0) { state = COMMISSIONING_STATE_ACCEPT; - tr_debug(" TLV ml prefix=%s\r\n", trace_array(ptr, len)); + tr_debug(" TLV ml prefix=%s", trace_array(ptr, len)); memcpy(this->leader_address, ptr, 8); memcpy(this->leader_address + 8, ADDR_SHORT_ADR_SUFFIC, 6); common_write_16_bit(0xfc00, this->leader_address + 14); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c index a5146cc29b4..67fc029be81 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_common.c @@ -2006,7 +2006,7 @@ void thread_reset_neighbour_info(protocol_interface_info_entry_t *cur, mac_neigh if (!thread_i_am_router(cur) && thread_endnode_parent && thread_endnode_parent->shortAddress == neighbour->mac16) { if (cur->nwk_bootstrap_state != ER_CHILD_ID_REQ) { - tr_warn("End device lost parent, reset!\n"); + tr_warn("End device lost parent, reset!"); thread_bootstrap_connection_error(cur->id, CON_PARENT_CONNECT_DOWN, NULL); } } @@ -2238,18 +2238,18 @@ int thread_common_primary_bbr_get(struct protocol_interface_info_entry *cur, uin (service_tlv_ptr[0] & 0x80) && // THREAD_ENTERPRISE_NUMBER service_tlv_ptr[1] == 1 && // length 1 service_tlv_ptr[2] == THREAD_SERVICE_DATA_BBR) { - //tr_info("BBR service TLV: %s\r\n", trace_array(service_tlv_ptr, service_tlv_len)); + //tr_info("BBR service TLV: %s", trace_array(service_tlv_ptr, service_tlv_len)); // try to parse SUB-TLVs // network_data_server_tlv_parse(service_tlv_ptr, tlv_length); uint16_t server_tlv_len = 0; uint8_t *server_tlv_ptr = thread_common_server_tlv_list_get(service_tlv_ptr, service_tlv_len, &server_tlv_len); uint16_t found_tlv_len; uint8_t *found_tlv = NULL; - //tr_info("BBR server TLV: %s\r\n", trace_array(server_tlv_ptr, server_tlv_len)); + //tr_info("BBR server TLV: %s", trace_array(server_tlv_ptr, server_tlv_len)); do { found_tlv_len = thread_meshcop_tlv_find_next(server_tlv_ptr, server_tlv_len, THREAD_NWK_DATA_TYPE_SERVER_DATA | THREAD_NWK_STABLE_DATA, &found_tlv); if (found_tlv && found_tlv_len > 8) { - //tr_info("BBR server TLV: %s\r\n", trace_array(found_tlv, found_tlv_len)); + //tr_info("BBR server TLV: %s", trace_array(found_tlv, found_tlv_len)); if (addr_ptr) { thread_addr_write_mesh_local_16(addr_ptr, common_read_16_bit(found_tlv), cur->thread_info); } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/adaptation_interface.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/adaptation_interface.c index 4423636e030..55904778f07 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/adaptation_interface.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/adaptation_interface.c @@ -1137,7 +1137,7 @@ static void lowpan_data_request_to_mac(protocol_interface_info_entry_t *cur, buf } else { mcps_data_req_ie_list_t ie_list; memset(&ie_list, 0, sizeof(mcps_data_req_ie_list_t)); - cur->mac_api->mcps_data_req_ext(cur->mac_api, &dataReq, &ie_list, NULL, data_priority); + cur->mac_api->mcps_data_req_ext(cur->mac_api, &dataReq, &ie_list, NULL, data_priority, 0); } } @@ -1747,6 +1747,9 @@ static uint8_t map_mlme_status_to_socket_event(uint8_t mlme_status) case MLME_SUCCESS: socket_event = SOCKET_TX_DONE; break; + case MLME_BUSY_CHAN: + socket_event = SOCKET_BUSY; + break; case MLME_TX_NO_ACK: case MLME_SECURITY_FAIL: case MLME_TRANSACTION_EXPIRED: diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c index 051fca51adb..db4bf5e2de5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c @@ -31,6 +31,7 @@ #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" #include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_pae_key_storage.h" #include "6LoWPAN/ws/ws_pae_nvm_store.h" @@ -70,7 +71,7 @@ static uint8_t current_instance_id = RPL_INSTANCE_ID; //TAG ID This must be update if NVM_BBR_INFO_LEN or data structure #define NVM_BBR_INFO_TAG 1 // BSI 2 bytes -#define NVM_BBR_INFO_LEN 2 +#define NVM_BBR_INFO_LEN 4 typedef struct bbr_info_nvm_tlv { uint16_t tag; /**< Unique tag */ @@ -97,6 +98,9 @@ static uint8_t current_global_prefix[16] = {0}; // DHCP requires 16 bytes prefix static uint32_t bbr_delay_timer = BBR_CHECK_INTERVAL; // initial delay. static uint32_t global_prefix_unavailable_timer = 0; // initial delay. +static bbr_timezone_configuration_t *bbr_time_config = NULL; + + static rpl_dodag_conf_t rpl_conf = { // Lifetime values .default_lifetime = 120, @@ -132,41 +136,57 @@ static bbr_info_nvm_tlv_t bbr_info_nvm_tlv = { }; static uint16_t ws_bbr_fhss_bsi = 0; +static uint16_t ws_bbr_pan_id = 0xffff; -static int8_t ws_bbr_nvm_info_read(bbr_info_nvm_tlv_t *tlv_entry) +static int8_t ws_bbr_info_tlv_read(bbr_info_nvm_tlv_t *tlv_entry, uint16_t *bsi, uint16_t *pan_id) { - tlv_entry->tag = NVM_BBR_INFO_TAG; - tlv_entry->len = NVM_BBR_INFO_LEN; - - int8_t ret_val = ws_pae_nvm_store_tlv_file_read(BBR_INFO_FILE, (nvm_tlv_t *) &bbr_info_nvm_tlv); - - if (ret_val < 0 || tlv_entry->tag != NVM_BBR_INFO_TAG || tlv_entry->len != NVM_BBR_INFO_LEN) { - ws_pae_nvm_store_tlv_file_remove(BBR_INFO_FILE); - tlv_entry->len = 0; + if (tlv_entry->tag != NVM_BBR_INFO_TAG || tlv_entry->len != NVM_BBR_INFO_LEN) { return -1; } + + uint8_t *tlv = (uint8_t *) &tlv_entry->data[0]; + + *bsi = common_read_16_bit(tlv); + tlv += 2; + *pan_id = common_read_16_bit(tlv); + return 0; } -static void ws_bbr_nvm_info_write(bbr_info_nvm_tlv_t *tlv_entry) +static void ws_bbr_info_tlv_write(bbr_info_nvm_tlv_t *tlv_entry, uint16_t bsi, uint16_t pan_id) { tlv_entry->tag = NVM_BBR_INFO_TAG; tlv_entry->len = NVM_BBR_INFO_LEN; - ws_pae_nvm_store_tlv_file_write(BBR_INFO_FILE, (nvm_tlv_t *) tlv_entry); - tr_debug("BBR info NVM update"); + + uint8_t *tlv = (uint8_t *) &tlv_entry->data[0]; + + tlv = common_write_16_bit(bsi, tlv); + common_write_16_bit(pan_id, tlv); } -static uint16_t ws_bbr_bsi_read(bbr_info_nvm_tlv_t *tlv_entry) +static int8_t ws_bbr_nvm_info_read(uint16_t *bsi, uint16_t *pan_id) { - if (tlv_entry->tag != NVM_BBR_INFO_TAG || tlv_entry->len != NVM_BBR_INFO_LEN) { - return 0; + ws_pae_nvm_store_generic_tlv_create((nvm_tlv_t *) &bbr_info_nvm_tlv, NVM_BBR_INFO_TAG, NVM_BBR_INFO_LEN); + + if (ws_pae_nvm_store_tlv_file_read(BBR_INFO_FILE, (nvm_tlv_t *) &bbr_info_nvm_tlv) < 0) { + ws_pae_nvm_store_tlv_file_remove(BBR_INFO_FILE); + return -1; + } + + if (ws_bbr_info_tlv_read(&bbr_info_nvm_tlv, bsi, pan_id) < 0) { + ws_pae_nvm_store_tlv_file_remove(BBR_INFO_FILE); + return -1; } - return common_read_16_bit(tlv_entry->data + BBR_NVM_BSI_OFFSET); + + return 0; } -static void ws_bbr_bsi_write(bbr_info_nvm_tlv_t *tlv_entry, uint16_t bsi) +static void ws_bbr_nvm_info_write(uint16_t bsi, uint16_t pan_id) { - common_write_16_bit(bsi, tlv_entry->data + BBR_NVM_BSI_OFFSET); + ws_bbr_info_tlv_write(&bbr_info_nvm_tlv, bsi, pan_id); + + ws_pae_nvm_store_tlv_file_write(BBR_INFO_FILE, (nvm_tlv_t *) &bbr_info_nvm_tlv); + tr_debug("BBR info NVM update"); } static void ws_bbr_rpl_version_timer_start(protocol_interface_info_entry_t *cur, uint8_t version) @@ -488,24 +508,32 @@ static uint8_t *ws_bbr_dhcp_server_dynamic_vendor_data_write(int8_t interfaceId, // If local time is not available vendor data is not written and data_len is not modified (void)interfaceId; - uint64_t time_read; + uint64_t time_read = 0; - if (0 != ns_time_system_time_read(&time_read)) { - return ptr; - } + ns_time_system_time_read(&time_read); if (data_len) { - *data_len += net_vendor_option_current_time_length(); + if (time_read) { + *data_len += net_vendor_option_current_time_length(); + } + if (bbr_time_config) { + *data_len += net_vendor_option_time_configuration_length(); + } } if (!ptr) { return ptr; } - time_read += 2208988800; // Time starts now from the 0 era instead of First day of Unix (1 Jan 1970) + if (time_read) { + time_read += 2208988800; // Time starts now from the 0 era instead of First day of Unix (1 Jan 1970) - uint32_t era = time_read / (uint64_t)(4294967296); - uint32_t timestamp = time_read - (era * (uint64_t)(4294967296)); - ptr = net_vendor_option_current_time_write(ptr, era, timestamp, 0); + uint32_t era = time_read / (uint64_t)(4294967296); + uint32_t timestamp = time_read - (era * (uint64_t)(4294967296)); + ptr = net_vendor_option_current_time_write(ptr, era, timestamp, 0); + } + if (bbr_time_config) { + ptr = net_vendor_option_time_configuration_write(ptr, bbr_time_config->timestamp, bbr_time_config->timezone, bbr_time_config->deviation, bbr_time_config->status); + } return ptr; } @@ -953,24 +981,21 @@ static void ws_bbr_forwarding_cb(protocol_interface_info_entry_t *interface, buf } } - - void ws_bbr_init(protocol_interface_info_entry_t *interface) { (void) interface; //Read From NVM - if (ws_bbr_nvm_info_read(&bbr_info_nvm_tlv) < 0) { + if (ws_bbr_nvm_info_read(&ws_bbr_fhss_bsi, &ws_bbr_pan_id) < 0) { //NVM value not available Randomize Value Here by first time ws_bbr_fhss_bsi = randLIB_get_16bit(); tr_debug("Randomized init value BSI %u", ws_bbr_fhss_bsi); } else { - ws_bbr_fhss_bsi = ws_bbr_bsi_read(&bbr_info_nvm_tlv); tr_debug("Read BSI %u from NVM", ws_bbr_fhss_bsi); + tr_debug("Read PAN ID %u from NVM", ws_bbr_pan_id); } interface->if_common_forwarding_out_cb = &ws_bbr_forwarding_cb; } - uint16_t ws_bbr_bsi_generate(protocol_interface_info_entry_t *interface) { (void) interface; @@ -979,11 +1004,16 @@ uint16_t ws_bbr_bsi_generate(protocol_interface_info_entry_t *interface) //Update value for next round ws_bbr_fhss_bsi++; //Store To NVN - ws_bbr_bsi_write(&bbr_info_nvm_tlv, ws_bbr_fhss_bsi); - ws_bbr_nvm_info_write(&bbr_info_nvm_tlv); + ws_bbr_nvm_info_write(ws_bbr_fhss_bsi, ws_bbr_pan_id); return bsi; } +uint16_t ws_bbr_pan_id_get(protocol_interface_info_entry_t *interface) +{ + (void) interface; + return ws_bbr_pan_id; +} + #endif //HAVE_WS_BORDER_ROUTER /* Public APIs @@ -1180,6 +1210,94 @@ int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validatio return -1; #endif } +int ws_bbr_configuration_set(int8_t interface_id, bbr_configuration_t *configuration_ptr) +{ +#ifdef HAVE_WS_BORDER_ROUTER + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + + ws_bbr_cfg_t cfg; + if (!configuration_ptr || ws_cfg_bbr_get(&cfg) < 0) { + return -1; + } + + cfg.dio_interval_min = configuration_ptr->dio_interval_min; + cfg.dio_interval_doublings = configuration_ptr->dio_interval_doublings; + cfg.dio_redundancy_constant = configuration_ptr->dio_redundancy_constant; + cfg.dag_max_rank_increase = configuration_ptr->dag_max_rank_increase; + cfg.min_hop_rank_increase = configuration_ptr->min_hop_rank_increase; + cfg.dhcp_address_lifetime = configuration_ptr->dhcp_address_lifetime; + cfg.rpl_default_lifetime = configuration_ptr->rpl_default_lifetime; + + /* Configuration change is different from settings change as it changes + * PAN version instead of RPL version. + */ + ws_bbr_configure(interface_id, configuration_ptr->options); + + if (ws_cfg_bbr_set(cur, &cfg, 0) < 0) { + return -2; + } + + return 0; +#else + (void) interface_id; + (void) configuration_ptr; + return -1; +#endif +} + +int ws_bbr_configuration_get(int8_t interface_id, bbr_configuration_t *configuration_ptr) +{ +#ifdef HAVE_WS_BORDER_ROUTER + (void) interface_id; + ws_bbr_cfg_t cfg; + if (!configuration_ptr || ws_cfg_bbr_get(&cfg) < 0) { + return -1; + } + + configuration_ptr->dio_interval_min = cfg.dio_interval_min; + configuration_ptr->dio_interval_doublings = cfg.dio_interval_doublings; + configuration_ptr->dio_redundancy_constant = cfg.dio_redundancy_constant; + configuration_ptr->dag_max_rank_increase = cfg.dag_max_rank_increase; + configuration_ptr->min_hop_rank_increase = cfg.min_hop_rank_increase; + configuration_ptr->dhcp_address_lifetime = cfg.dhcp_address_lifetime; + configuration_ptr->rpl_default_lifetime = cfg.rpl_default_lifetime; + configuration_ptr->options = configuration; + return 0; +#else + (void) interface_id; + (void) configuration_ptr; + return -1; +#endif +} + +int ws_bbr_configuration_validate(int8_t interface_id, bbr_configuration_t *configuration_ptr) +{ +#ifdef HAVE_WS_BORDER_ROUTER + (void) interface_id; + ws_bbr_cfg_t cfg; + if (!configuration_ptr || ws_cfg_bbr_get(&cfg) < 0) { + return -1; + } + + cfg.dio_interval_min = configuration_ptr->dio_interval_min; + cfg.dio_interval_doublings = configuration_ptr->dio_interval_doublings; + cfg.dio_redundancy_constant = configuration_ptr->dio_redundancy_constant; + cfg.dag_max_rank_increase = configuration_ptr->dag_max_rank_increase; + cfg.min_hop_rank_increase = configuration_ptr->min_hop_rank_increase; + cfg.dhcp_address_lifetime = configuration_ptr->dhcp_address_lifetime; + cfg.rpl_default_lifetime = configuration_ptr->rpl_default_lifetime; + + if (ws_cfg_bbr_validate(&cfg) < 0) { + return -3; + } + + return 0; +#else + (void) interface_id; + (void) configuration_ptr; + return -1; +#endif +} int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uint8_t dio_interval_doublings, uint8_t dio_redundancy_constant) { @@ -1188,7 +1306,7 @@ int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uin protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); ws_bbr_cfg_t cfg; - if (ws_cfg_bbr_get(&cfg, NULL) < 0) { + if (ws_cfg_bbr_get(&cfg) < 0) { return -1; } @@ -1202,7 +1320,7 @@ int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uin cfg.dio_redundancy_constant = dio_redundancy_constant; } - if (ws_cfg_bbr_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_bbr_set(cur, &cfg, 0) < 0) { return -2; } @@ -1224,7 +1342,7 @@ int ws_bbr_rpl_parameters_get(int8_t interface_id, uint8_t *dio_interval_min, ui } ws_bbr_cfg_t cfg; - if (ws_cfg_bbr_get(&cfg, NULL) < 0) { + if (ws_cfg_bbr_get(&cfg) < 0) { return -2; } @@ -1246,7 +1364,7 @@ int ws_bbr_rpl_parameters_validate(int8_t interface_id, uint8_t dio_interval_min (void) interface_id; #ifdef HAVE_WS_BORDER_ROUTER ws_bbr_cfg_t cfg; - if (ws_cfg_bbr_get(&cfg, NULL) < 0) { + if (ws_cfg_bbr_get(&cfg) < 0) { return -2; } @@ -1260,7 +1378,7 @@ int ws_bbr_rpl_parameters_validate(int8_t interface_id, uint8_t dio_interval_min cfg.dio_redundancy_constant = dio_redundancy_constant; } - if (ws_cfg_bbr_validate(NULL, &cfg) < 0) { + if (ws_cfg_bbr_validate(&cfg) < 0) { return -3; } @@ -1289,8 +1407,7 @@ int ws_bbr_bsi_set(int8_t interface_id, uint16_t new_bsi) ws_bootstrap_restart_delayed(cur->id); } - ws_bbr_bsi_write(&bbr_info_nvm_tlv, new_bsi); - ws_bbr_nvm_info_write(&bbr_info_nvm_tlv); + ws_bbr_nvm_info_write(ws_bbr_fhss_bsi, ws_bbr_pan_id); ws_bbr_fhss_bsi = new_bsi; return 0; #else @@ -1299,24 +1416,16 @@ int ws_bbr_bsi_set(int8_t interface_id, uint16_t new_bsi) #endif } - int ws_bbr_pan_configuration_set(int8_t interface_id, uint16_t pan_id) { (void) interface_id; #ifdef HAVE_WS_BORDER_ROUTER - protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); - - ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { - return -1; - } - - cfg.network_pan_id = pan_id; - - if (ws_cfg_gen_set(cur, NULL, &cfg, 0) < 0) { - return -2; + if (ws_bbr_pan_id != pan_id) { + ws_bbr_pan_id = pan_id; + // Store to NVM and restart bootstrap + ws_bbr_nvm_info_write(ws_bbr_fhss_bsi, ws_bbr_pan_id); + ws_bootstrap_restart_delayed(interface_id); } - return 0; #else (void) pan_id; @@ -1332,12 +1441,7 @@ int ws_bbr_pan_configuration_get(int8_t interface_id, uint16_t *pan_id) return -1; } - ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { - return -2; - } - - *pan_id = cfg.network_pan_id; + *pan_id = ws_bbr_pan_id; return 0; #else @@ -1349,21 +1453,10 @@ int ws_bbr_pan_configuration_get(int8_t interface_id, uint16_t *pan_id) int ws_bbr_pan_configuration_validate(int8_t interface_id, uint16_t pan_id) { (void) interface_id; + (void) pan_id; #ifdef HAVE_WS_BORDER_ROUTER - ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { - return -1; - } - - cfg.network_pan_id = pan_id; - - if (ws_cfg_gen_validate(NULL, &cfg) < 0) { - return -2; - } - return 0; #else - (void) pan_id; return -1; #endif } @@ -1553,3 +1646,32 @@ int ws_bbr_dns_query_result_set(int8_t interface_id, const uint8_t address[16], return -1; #endif } + +int ws_bbr_timezone_configuration_set(int8_t interface_id, bbr_timezone_configuration_t *daylight_saving_time_ptr) +{ +#ifdef HAVE_WS_BORDER_ROUTER + (void) interface_id; + + if (!daylight_saving_time_ptr) { + // Delete configuration + ns_dyn_mem_free(bbr_time_config); + bbr_time_config = NULL; + return 0; + } + + if (!bbr_time_config) { + bbr_time_config = ns_dyn_mem_alloc(sizeof(bbr_timezone_configuration_t)); + } + + if (!bbr_time_config) { + return -2; + } + *bbr_time_config = *daylight_saving_time_ptr; + + return 0; +#else + (void) interface_id; + (void) daylight_saving_time_ptr; + return -1; +#endif +} diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api_internal.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api_internal.h index dab05547eb9..0ab7c1dda3c 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api_internal.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api_internal.h @@ -38,6 +38,7 @@ bool ws_bbr_ready_to_start(protocol_interface_info_entry_t *cur); bool ws_bbr_backbone_address_get(uint8_t *address); uint16_t ws_bbr_bsi_generate(protocol_interface_info_entry_t *interface); +uint16_t ws_bbr_pan_id_get(protocol_interface_info_entry_t *interface); void ws_bbr_init(protocol_interface_info_entry_t *interface); #else @@ -50,6 +51,7 @@ void ws_bbr_init(protocol_interface_info_entry_t *interface); #define ws_bbr_ready_to_start(cur) true #define ws_bbr_backbone_address_get(address) 0 #define ws_bbr_bsi_generate(interface) 0 +#define ws_bbr_pan_id_get(interface) 0 #define ws_bbr_init(interface) (void) 0 #endif //HAVE_WS_BORDER_ROUTER diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c index b3f97518c34..73473fe5885 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c @@ -62,6 +62,11 @@ #include "6LoWPAN/ws/ws_ie_lib.h" #include "6LoWPAN/ws/ws_stats.h" #include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/ws/ws_bootstrap_6lbr.h" +#include "6LoWPAN/ws/ws_bootstrap_6lr.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" +#include "6LoWPAN/ws/ws_bootstrap_6ln.h" +#include "6LoWPAN/ws/ws_phy.h" #include "6LoWPAN/lowpan_adaptation_interface.h" #include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" @@ -84,64 +89,23 @@ #define TRACE_GROUP "wsbs" - static void ws_bootstrap_event_handler(arm_event_s *event); -static void ws_bootstrap_state_change(protocol_interface_info_entry_t *cur, icmp_state_t nwk_bootstrap_state); -static bool ws_bootstrap_state_discovery(struct protocol_interface_info_entry *cur); -static bool ws_bootstrap_state_active(struct protocol_interface_info_entry *cur); -static bool ws_bootstrap_state_wait_rpl(struct protocol_interface_info_entry *cur); static int8_t ws_bootsrap_event_trig(ws_bootsrap_event_type_e event_type, int8_t interface_id, arm_library_event_priority_e priority, void *event_data); - -static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new); static uint16_t ws_bootstrap_routing_cost_calculate(protocol_interface_info_entry_t *cur); -static uint16_t ws_bootstrap_rank_get(protocol_interface_info_entry_t *cur); -static uint16_t ws_bootstrap_min_rank_inc_get(protocol_interface_info_entry_t *cur); - static void ws_bootstrap_mac_security_enable(protocol_interface_info_entry_t *cur); static void ws_bootstrap_nw_key_set(protocol_interface_info_entry_t *cur, uint8_t operation, uint8_t index, uint8_t *key); static void ws_bootstrap_nw_key_clear(protocol_interface_info_entry_t *cur, uint8_t slot); static void ws_bootstrap_nw_key_index_set(protocol_interface_info_entry_t *cur, uint8_t index); static void ws_bootstrap_nw_frame_counter_set(protocol_interface_info_entry_t *cur, uint32_t counter, uint8_t slot); static void ws_bootstrap_nw_frame_counter_read(protocol_interface_info_entry_t *cur, uint32_t *counter, uint8_t slot); -static void ws_bootstrap_nw_info_updated(protocol_interface_info_entry_t *interface_ptr, uint16_t pan_id, uint16_t pan_version, char *network_name); static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_t *cur, auth_result_e result, uint8_t *target_eui_64); static const uint8_t *ws_bootstrap_authentication_next_target(protocol_interface_info_entry_t *cur, const uint8_t *previous_eui_64, uint16_t *pan_id); -static bool ws_bootstrap_eapol_congestion_get(protocol_interface_info_entry_t *interface_ptr, uint16_t active_supp); -static void ws_bootstrap_pan_version_increment(protocol_interface_info_entry_t *cur); static ws_nud_table_entry_t *ws_nud_entry_discover(protocol_interface_info_entry_t *cur, void *neighbor); static void ws_nud_entry_remove(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *entry_ptr); static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data); +static void ws_bootstrap_test_procedure_trigger_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); -static void ws_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]); -static int8_t ws_bootstrap_neighbor_set(protocol_interface_info_entry_t *cur, parent_info_t *parent_ptr, bool clear_list); -static void ws_bootstrap_parent_confirm(protocol_interface_info_entry_t *cur, struct rpl_instance *instance); - -static void ws_bootstrap_candidate_table_reset(protocol_interface_info_entry_t *cur); -static parent_info_t *ws_bootstrap_candidate_parent_get(struct protocol_interface_info_entry *cur, const uint8_t *addr, bool create); -static void ws_bootstrap_candidate_parent_sort(struct protocol_interface_info_entry *cur, parent_info_t *new_entry); -static void ws_bootstrap_packet_congestion_init(protocol_interface_info_entry_t *cur); - -static void ws_bootstrap_asynch_trickle_stop(protocol_interface_info_entry_t *cur); -static void ws_bootstrap_advertise_start(protocol_interface_info_entry_t *cur); -static void ws_bootstrap_rpl_scan_start(protocol_interface_info_entry_t *cur); - -static uint16_t ws_randomize_fixed_channel(uint16_t configured_fixed_channel, uint8_t number_of_channels, uint32_t *channel_mask); - -typedef enum { - WS_PARENT_SOFT_SYNCH = 0, /**< let FHSS make decision if synchronization is needed*/ - WS_PARENT_HARD_SYNCH, /**< Synch FHSS with latest synch information*/ - WS_EAPOL_PARENT_SYNCH, /**< Broadcast synch with EAPOL parent*/ -} ws_parent_synch_e; - - -static void ws_bootsrap_create_ll_address(uint8_t *ll_address, const uint8_t *mac64) -{ - memcpy(ll_address, ADDR_LINK_LOCAL_PREFIX, 8); - memcpy(ll_address + 8, mac64, 8); - ll_address[8] ^= 2; -} - - +uint16_t test_pan_version = 1; static mac_neighbor_table_entry_t *ws_bootstrap_mac_neighbor_allocate(struct protocol_interface_info_entry *interface, const uint8_t *src64) { @@ -160,7 +124,6 @@ static mac_neighbor_table_entry_t *ws_bootstrap_mac_neighbor_allocate(struct pro } mac_neighbor_table_entry_t *ws_bootstrap_mac_neighbor_add(struct protocol_interface_info_entry *interface, const uint8_t *src64) - { mac_neighbor_table_entry_t *neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(interface), src64, MAC_ADDR_MODE_64_BIT); if (neighbor) { @@ -200,13 +163,13 @@ static void ws_bootstrap_neighbor_delete(struct protocol_interface_info_entry *i ws_neighbor_class_entry_remove(&interface->ws_info->neighbor_storage, entry_ptr->index); } -static void ws_bootstrap_neighbor_list_clean(struct protocol_interface_info_entry *interface) +void ws_bootstrap_neighbor_list_clean(struct protocol_interface_info_entry *interface) { mac_neighbor_table_neighbor_list_clean(mac_neighbor_info(interface)); } -static void ws_address_reregister_trig(struct protocol_interface_info_entry *interface) +void ws_address_reregister_trig(struct protocol_interface_info_entry *interface) { if (interface->ws_info->aro_registration_timer == 0) { interface->ws_info->aro_registration_timer = WS_NEIGHBOR_NUD_TIMEOUT; @@ -226,7 +189,7 @@ static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_ //Trigger Address Registration only when Bootstrap is ready if (interface->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { tr_debug("Address registration %s", trace_ipv6(addr->address)); - ws_address_registration_update(interface, addr->address); + ws_bootstrap_6lr_address_registration_update(interface, addr->address); } ws_address_reregister_trig(interface); } @@ -264,19 +227,87 @@ static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_ } } } +#ifdef HAVE_WS_VERSION_1_1 + +static ws_pcap_ie_t ws_neighbour_phy_cap_list_compare(ws_phy_cap_info_t *prefered_mode, ws_phy_cap_info_t *neighbour_cap_list) +{ + ws_pcap_ie_t pref_setup; + + ws_pcap_ie_t *prefered_setup = prefered_mode->pcap; + int length_of_list = prefered_mode->length_of_list; + while (length_of_list) { + for (int i = 0; i < neighbour_cap_list->length_of_list; i++) { + //Check first phy type is matching + if (neighbour_cap_list->pcap[i].phy_type != prefered_setup->phy_type) { + continue; + } + //Validate supported + if (neighbour_cap_list->pcap[i].operating_mode & prefered_setup->operating_mode) { + + //Take only matched opeating modes + pref_setup.operating_mode = neighbour_cap_list->pcap[i].operating_mode & prefered_setup->operating_mode; + pref_setup.phy_type = prefered_setup->phy_type; + return pref_setup; + } + break; + } + prefered_setup++; + length_of_list--; + } + //Mark zero operating modes + pref_setup.operating_mode = 0; + return pref_setup; +} + +static void ws_neighbour_mdr_mode_analyze(struct protocol_interface_info_entry *interface) +{ + if (!ws_version_1_1(interface)) { + return; + } + + if (!interface->ws_info->uptime || (interface->ws_info->uptime % 10)) { + return; + } + + if (!interface->ws_info->phy_cap_info.length_of_list) { + //No Preferred Cap modes + return; + } + + ns_list_foreach_safe(mac_neighbor_table_entry_t, cur, &mac_neighbor_info(interface)->neighbour_list) { + + ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, cur->index); + + if (!ws_neighbor || ws_neighbor->phy_mode_id || !ws_neighbor->pcap_info.length_of_list) { + continue; + } + + ws_pcap_ie_t preferred = ws_neighbour_phy_cap_list_compare(&interface->ws_info->phy_cap_info, ws_neighbour_cap_pointer(ws_neighbor)); + uint8_t phy_mode_id = ws_ie_lib_phy_mode_id_get_from_phy_cap(&preferred); + if (ws_neighbor->phy_mode_id != phy_mode_id) { + tr_debug("Updated Neigh %u MDR phy mode id %u -> %u", cur->index, ws_neighbor->phy_mode_id, phy_mode_id); + ws_neighbor->phy_mode_id = phy_mode_id; + } + + } +} +#else +#define ws_neighbour_mdr_mode_analyze(interface) ((void)0) +#endif + -static void ws_bootstrap_configure_max_retries(protocol_interface_info_entry_t *cur, uint8_t max_mac_retries) +void ws_bootstrap_configure_max_retries(protocol_interface_info_entry_t *cur, uint8_t max_mac_retries) { mac_helper_mac_mlme_max_retry_set(cur->id, max_mac_retries); } -static void ws_bootstrap_configure_csma_ca_backoffs(protocol_interface_info_entry_t *cur, uint8_t max_backoffs, uint8_t min_be, uint8_t max_be) +void ws_bootstrap_configure_csma_ca_backoffs(protocol_interface_info_entry_t *cur, uint8_t max_backoffs, uint8_t min_be, uint8_t max_be) { mac_helper_mac_mlme_max_csma_backoffs_set(cur->id, max_backoffs); mac_helper_mac_mlme_be_set(cur->id, min_be, max_be); } -static void ws_bootstrap_configure_data_request_restart(protocol_interface_info_entry_t *cur, uint8_t cca_failure_restart_max, uint8_t tx_failure_restart_max, uint16_t blacklist_min_ms, uint16_t blacklist_max_ms) +void ws_bootstrap_configure_data_request_restart(protocol_interface_info_entry_t *cur, uint8_t cca_failure_restart_max, uint8_t tx_failure_restart_max, uint16_t blacklist_min_ms, uint16_t blacklist_max_ms) { mlme_request_restart_config_t request_restart_config; request_restart_config.cca_failure_restart_max = cca_failure_restart_max; @@ -301,6 +332,7 @@ static int ws_bootstrap_tasklet_init(protocol_interface_info_entry_t *cur) return 0; } + static void ws_nwk_event_post(protocol_interface_info_entry_t *cur, arm_nwk_interface_status_type_e posted_event) { arm_event_s event = { @@ -329,7 +361,7 @@ static int8_t ws_bootsrap_event_trig(ws_bootsrap_event_type_e event_type, int8_t return eventOS_event_send(&event); } -static void ws_nud_table_reset(protocol_interface_info_entry_t *cur) +void ws_nud_table_reset(protocol_interface_info_entry_t *cur) { //Empty active list ns_list_foreach_safe(ws_nud_table_entry_t, entry, &cur->ws_info->active_nud_process) { @@ -361,7 +393,6 @@ static ws_nud_table_entry_t *ws_nud_entry_get_free(protocol_interface_info_entry return entry; } - void ws_nud_entry_remove_active(protocol_interface_info_entry_t *cur, void *neighbor) { ws_nud_table_entry_t *entry = ws_nud_entry_discover(cur, neighbor); @@ -378,7 +409,6 @@ void ws_nud_entry_remove_active(protocol_interface_info_entry_t *cur, void *neig } } - static ws_nud_table_entry_t *ws_nud_entry_discover(protocol_interface_info_entry_t *cur, void *neighbor) { ns_list_foreach(ws_nud_table_entry_t, entry, &cur->ws_info->active_nud_process) { @@ -389,7 +419,6 @@ static ws_nud_table_entry_t *ws_nud_entry_discover(protocol_interface_info_entry return NULL; } - static void ws_nud_state_clean(protocol_interface_info_entry_t *cur, ws_nud_table_entry_t *entry) { mac_neighbor_table_entry_t *neighbor = entry->neighbor_info; @@ -408,6 +437,7 @@ static void ws_nud_entry_remove(protocol_interface_info_entry_t *cur, mac_neighb ws_nud_state_clean(cur, nud_entry); } } + if_address_entry_t *ws_probe_aro_address(protocol_interface_info_entry_t *interface) { if (interface->global_address_available) { @@ -420,7 +450,6 @@ if_address_entry_t *ws_probe_aro_address(protocol_interface_info_entry_t *interf return NULL; } - static bool ws_nud_message_build(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *neighbor, bool nud_process) { //Send NS @@ -430,7 +459,7 @@ static bool ws_nud_message_build(protocol_interface_info_entry_t *cur, mac_neigh aro_t *aro_ptr = NULL; uint8_t *src_address_ptr = NULL; - ws_bootsrap_create_ll_address(ll_target, neighbor->mac64); + ws_common_create_ll_address(ll_target, neighbor->mac64); if (nud_process) { tr_info("NUD generate NS %u", neighbor->index); } else { @@ -508,7 +537,7 @@ void ws_nud_active_timer(protocol_interface_info_entry_t *cur, uint16_t ticks) } } -static fhss_ws_neighbor_timing_info_t *ws_get_neighbor_info(const fhss_api_t *api, uint8_t eui64[8]) +static fhss_ws_neighbor_timing_info_t *ws_bootstrap_get_neighbor_info(const fhss_api_t *api, uint8_t eui64[8]) { protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_fhss_api(api); if (!cur || !cur->mac_parameters || !mac_neighbor_info(cur)) { @@ -529,7 +558,8 @@ static fhss_ws_neighbor_timing_info_t *ws_get_neighbor_info(const fhss_api_t *ap } return &temp_entry->neigh_info_list.fhss_data; } -static void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry *cur, const fhss_ws_configuration_t *fhss_configuration) + +void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry *cur, const fhss_ws_configuration_t *fhss_configuration) { cur->ws_info->hopping_schdule.uc_fixed_channel = fhss_configuration->unicast_fixed_channel; cur->ws_info->hopping_schdule.bc_fixed_channel = fhss_configuration->broadcast_fixed_channel; @@ -542,7 +572,7 @@ static void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry cur->ws_info->hopping_schdule.fhss_bsi = fhss_configuration->bsi; } -static uint8_t ws_generate_exluded_channel_list_from_active_channels(ws_excluded_channel_data_t *excluded_data, const uint32_t *selected_channel_mask, const uint32_t *global_channel_mask, uint16_t number_of_channels) +static uint8_t ws_bootstrap_generate_exluded_channel_list_from_active_channels(ws_excluded_channel_data_t *excluded_data, const uint32_t *selected_channel_mask, const uint32_t *global_channel_mask, uint16_t number_of_channels) { bool active_range = false; @@ -550,7 +580,7 @@ static uint8_t ws_generate_exluded_channel_list_from_active_channels(ws_excluded memset(excluded_data, 0, sizeof(ws_excluded_channel_data_t)); for (uint8_t i = 0; i < number_of_channels; i++) { - if (!(global_channel_mask[0 + (i / 32)] & (1 << (i % 32)))) { + if (!(global_channel_mask[i / 32] & (1U << (i % 32)))) { //Global exluded channel if (active_range) { //Mark range stop here @@ -559,7 +589,7 @@ static uint8_t ws_generate_exluded_channel_list_from_active_channels(ws_excluded continue; } - if (selected_channel_mask[0 + (i / 32)] & (1 << (i % 32))) { + if (selected_channel_mask[i / 32] & (1U << (i % 32))) { if (active_range) { //Mark range stop here active_range = false; @@ -567,7 +597,7 @@ static uint8_t ws_generate_exluded_channel_list_from_active_channels(ws_excluded } else { //Mark excluded channel //Swap Order already here - excluded_data->channel_mask[0 + (i / 32)] |= 1 << (31 - (i % 32)); + excluded_data->channel_mask[i / 32] |= 1U << (31 - (i % 32)); excluded_data->excluded_channel_count++; if (excluded_data->excluded_range_length < WS_EXCLUDED_MAX_RANGE_TO_SEND) { @@ -605,33 +635,28 @@ static uint8_t ws_generate_exluded_channel_list_from_active_channels(ws_excluded return channel_plan; } -static void ws_fhss_configure_channel_masks(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration) +void ws_bootstrap_fhss_configure_channel_masks(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration) { fhss_configuration->channel_mask_size = cur->ws_info->hopping_schdule.number_of_channels; - ws_generate_channel_list(fhss_configuration->channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class, cur->ws_info->hopping_schdule.channel_plan_id); - ws_generate_channel_list(fhss_configuration->unicast_channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class, cur->ws_info->hopping_schdule.channel_plan_id); + ws_common_generate_channel_list(fhss_configuration->channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class, cur->ws_info->hopping_schdule.channel_plan_id); + ws_common_generate_channel_list(fhss_configuration->unicast_channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class, cur->ws_info->hopping_schdule.channel_plan_id); // using bitwise AND operation for user set channel mask to remove channels not allowed in this device for (uint8_t n = 0; n < 8; n++) { fhss_configuration->unicast_channel_mask[n] &= cur->ws_info->cfg->fhss.fhss_channel_mask[n]; } //Update Exluded channels - cur->ws_info->hopping_schdule.channel_plan = ws_generate_exluded_channel_list_from_active_channels(&cur->ws_info->hopping_schdule.excluded_channels, fhss_configuration->unicast_channel_mask, fhss_configuration->channel_mask, cur->ws_info->hopping_schdule.number_of_channels); + cur->ws_info->hopping_schdule.channel_plan = ws_bootstrap_generate_exluded_channel_list_from_active_channels(&cur->ws_info->hopping_schdule.excluded_channels, fhss_configuration->unicast_channel_mask, fhss_configuration->channel_mask, cur->ws_info->hopping_schdule.number_of_channels); } -static int8_t ws_fhss_initialize(protocol_interface_info_entry_t *cur) +int8_t ws_bootstrap_fhss_initialize(protocol_interface_info_entry_t *cur) { fhss_api_t *fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); fhss_ws_configuration_t fhss_configuration; memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); if (!fhss_api) { // When FHSS doesn't exist yet, create one - ws_fhss_configure_channel_masks(cur, &fhss_configuration); - - fhss_configuration.fhss_uc_dwell_interval = cur->ws_info->cfg->fhss.fhss_uc_dwell_interval; - fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; - fhss_configuration.ws_bc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_bc_channel_function; - fhss_configuration.fhss_bc_dwell_interval = cur->ws_info->cfg->fhss.fhss_bc_dwell_interval; - fhss_configuration.fhss_broadcast_interval = cur->ws_info->cfg->fhss.fhss_bc_interval; + ws_bootstrap_fhss_configure_channel_masks(cur, &fhss_configuration); + ws_bootstrap_fhss_set_defaults(cur, &fhss_configuration); fhss_api = ns_fhss_ws_create(&fhss_configuration, cur->ws_info->fhss_timer_ptr); if (!fhss_api) { @@ -641,32 +666,13 @@ static int8_t ws_fhss_initialize(protocol_interface_info_entry_t *cur) // Allow transmitting unicast frames only on TX slots in normal and expedited forwarding mode ns_fhss_ws_set_tx_allowance_level(fhss_api, WS_TX_SLOT, WS_TX_SLOT); } else { - // Read defaults from the configuration to help FHSS testing - const fhss_ws_configuration_t *fhss_configuration_copy = ns_fhss_ws_configuration_get(fhss_api); - if (!fhss_configuration_copy) { - // no configuration set yet - return 0; - } - fhss_configuration = *fhss_configuration_copy; - //Overwrite domain channel setup this will over write a default 35 channel - int num_of_channels = channel_list_count_channels(fhss_configuration_copy->unicast_channel_mask); - cur->ws_info->hopping_schdule.number_of_channels = (uint8_t) num_of_channels; - memcpy(cur->ws_info->cfg->fhss.fhss_channel_mask, fhss_configuration_copy->unicast_channel_mask, sizeof(uint32_t) * 8); - cur->ws_info->cfg->fhss.fhss_uc_channel_function = fhss_configuration_copy->ws_uc_channel_function; - cur->ws_info->cfg->fhss.fhss_bc_channel_function = fhss_configuration_copy->ws_bc_channel_function; - cur->ws_info->cfg->fhss.fhss_bc_dwell_interval = fhss_configuration_copy->fhss_bc_dwell_interval; - cur->ws_info->cfg->fhss.fhss_bc_interval = fhss_configuration_copy->fhss_broadcast_interval; - cur->ws_info->cfg->fhss.fhss_uc_dwell_interval = fhss_configuration_copy->fhss_uc_dwell_interval; - cur->ws_info->cfg->fhss.fhss_bc_fixed_channel = fhss_configuration_copy->broadcast_fixed_channel; - cur->ws_info->cfg->fhss.fhss_uc_fixed_channel = fhss_configuration_copy->unicast_fixed_channel; - ws_fhss_configure_channel_masks(cur, &fhss_configuration); - ns_fhss_ws_configuration_set(fhss_api, &fhss_configuration); + return -1; } return 0; } -static int8_t ws_fhss_set_defaults(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration) +int8_t ws_bootstrap_fhss_set_defaults(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration) { fhss_configuration->fhss_uc_dwell_interval = cur->ws_info->cfg->fhss.fhss_uc_dwell_interval; fhss_configuration->ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; @@ -679,42 +685,20 @@ static int8_t ws_fhss_set_defaults(protocol_interface_info_entry_t *cur, fhss_ws fhss_configuration->broadcast_fixed_channel = cur->ws_info->cfg->fhss.fhss_bc_fixed_channel; return 0; } -static int8_t ws_fhss_border_router_configure(protocol_interface_info_entry_t *cur) -{ - // Read configuration of existing FHSS and start using the default values for any network - fhss_ws_configuration_t fhss_configuration; - memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); - - if (ns_fhss_ws_configuration_get(cur->ws_info->fhss_api)) { - memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); - } - - //GET BSI from BBR module - fhss_configuration.bsi = ws_bbr_bsi_generate(cur); - ws_fhss_configure_channel_masks(cur, &fhss_configuration); - // Randomize fixed channels. Only used if channel plan is fixed. - cur->ws_info->cfg->fhss.fhss_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); - cur->ws_info->cfg->fhss.fhss_bc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); - ws_fhss_set_defaults(cur, &fhss_configuration); - ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); - ws_bootstrap_llc_hopping_update(cur, &fhss_configuration); - - return 0; -} -static bool ws_channel_allowed(uint8_t channel, uint32_t *channel_mask) +static bool ws_bootstrap_channel_allowed(uint8_t channel, uint32_t *channel_mask) { - if ((1 << (channel % 32)) & (channel_mask[channel / 32])) { + if ((1U << (channel % 32)) & (channel_mask[channel / 32])) { return true; } return false; } -static uint16_t ws_randomize_fixed_channel(uint16_t configured_fixed_channel, uint8_t number_of_channels, uint32_t *channel_mask) +uint16_t ws_bootstrap_randomize_fixed_channel(uint16_t configured_fixed_channel, uint8_t number_of_channels, uint32_t *channel_mask) { if (configured_fixed_channel == 0xFFFF) { uint16_t random_channel = randLIB_get_random_in_range(0, number_of_channels - 1); - while (ws_channel_allowed(random_channel, channel_mask) == false) { + while (ws_bootstrap_channel_allowed(random_channel, channel_mask) == false) { random_channel = randLIB_get_random_in_range(0, number_of_channels - 1); } return random_channel; @@ -723,74 +707,37 @@ static uint16_t ws_randomize_fixed_channel(uint16_t configured_fixed_channel, ui } } -static int8_t ws_fhss_configure(protocol_interface_info_entry_t *cur, bool discovery) -{ - // Read configuration of existing FHSS and start using the default values for any network - fhss_ws_configuration_t fhss_configuration; - memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); - - if (ns_fhss_ws_configuration_get(cur->ws_info->fhss_api)) { - memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); - ws_fhss_set_defaults(cur, &fhss_configuration); - ws_fhss_configure_channel_masks(cur, &fhss_configuration); - } - // Discovery is done using fixed channel - if (discovery) { - fhss_configuration.ws_uc_channel_function = WS_FIXED_CHANNEL; - } else { - fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; - } - fhss_configuration.ws_bc_channel_function = WS_FIXED_CHANNEL; - fhss_configuration.fhss_broadcast_interval = 0; - uint8_t tmp_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); - uint8_t tmp_bc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); - fhss_configuration.unicast_fixed_channel = tmp_uc_fixed_channel; - fhss_configuration.broadcast_fixed_channel = tmp_bc_fixed_channel; - ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); - ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, 0xff); - ws_bootstrap_llc_hopping_update(cur, &fhss_configuration); - - return 0; -} - -static int8_t ws_fhss_enable(protocol_interface_info_entry_t *cur) +static int8_t ws_bootstrap_fhss_enable(protocol_interface_info_entry_t *cur) { - const fhss_ws_configuration_t *fhss_configuration = ns_fhss_ws_configuration_get(cur->ws_info->fhss_api); + fhss_ws_configuration_t fhss_configuration = ws_common_get_current_fhss_configuration(cur); - if (!cur->ws_info->fhss_api || !fhss_configuration) { - return -1; - } // Set the LLC information to follow the actual fhss settings - ws_bootstrap_llc_hopping_update(cur, fhss_configuration); + ws_bootstrap_llc_hopping_update(cur, &fhss_configuration); // Set neighbor info callback - if (ns_fhss_set_neighbor_info_fp(cur->ws_info->fhss_api, &ws_get_neighbor_info)) { + if (ns_fhss_set_neighbor_info_fp(cur->ws_info->fhss_api, &ws_bootstrap_get_neighbor_info)) { return -1; } - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, 0); - } + return 0; } /* Sets the parent and broadcast schedule we are following * */ -static void ws_bootstrap_primary_parent_set(struct protocol_interface_info_entry *cur, llc_neighbour_req_t *neighbor_info, ws_parent_synch_e synch_req) +void ws_bootstrap_primary_parent_set(struct protocol_interface_info_entry *cur, llc_neighbour_req_t *neighbor_info, ws_parent_synch_e synch_req) { - - fhss_ws_configuration_t fhss_configuration; if (!neighbor_info->ws_neighbor->broadcast_timing_info_stored) { tr_error("No BC timing info for set new parent"); return; } - memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); + fhss_ws_configuration_t fhss_configuration = ws_common_get_current_fhss_configuration(cur); // Learning broadcast network configuration if (neighbor_info->ws_neighbor->broadcast_shedule_info_stored) { if (synch_req != WS_EAPOL_PARENT_SYNCH) { - ws_fhss_set_defaults(cur, &fhss_configuration); + ws_bootstrap_fhss_set_defaults(cur, &fhss_configuration); } fhss_configuration.ws_bc_channel_function = (fhss_ws_channel_functions)neighbor_info->ws_neighbor->fhss_data.bc_timing_info.broadcast_channel_function; if (fhss_configuration.ws_bc_channel_function == WS_FIXED_CHANNEL) { @@ -831,7 +778,7 @@ void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, } } -static void ws_bootstrap_ll_address_validate(struct protocol_interface_info_entry *cur) +void ws_bootstrap_ll_address_validate(struct protocol_interface_info_entry *cur) { // Configure EUI64 for MAC if missing uint8_t mac64[8]; @@ -931,134 +878,7 @@ bool ws_bootstrap_nd_ns_transmit(protocol_interface_info_entry_t *cur, ipv6_neig // True means we skip the message sending return true; } - -static void ws_bootstrap_dhcp_neighbour_update_cb(int8_t interface_id, uint8_t ll_addr[static 16]) -{ - if (memcmp(ll_addr, ADDR_LINK_LOCAL_PREFIX, 8)) { - return; - } - - protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur) { - return; - } - - uint8_t mac64[8]; - memcpy(mac64, ll_addr + 8, 8); - mac64[0] ^= 2; - ws_bootstrap_mac_neighbor_short_time_set(cur, mac64, WS_NEIGHBOUR_DHCP_ENTRY_LIFETIME); -} - -static void ws_bootstrap_dhcp_info_notify_cb(int8_t interface, dhcp_option_notify_t *options, dhcp_server_notify_info_t *server_info) -{ - protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface); - if (!cur) { - return; - } - uint8_t server_ll64[16]; - memcpy(server_ll64, ADDR_LINK_LOCAL_PREFIX, 8); - - if (server_info->duid_length == 8) { - memcpy(server_ll64 + 8, server_info->duid, 8); - } else { - server_ll64[8] = server_info->duid[0]; - server_ll64[9] = server_info->duid[1]; - server_ll64[10] = server_info->duid[2]; - server_ll64[11] = 0xff; - server_ll64[12] = 0xfe; - server_ll64[13] = server_info->duid[3]; - server_ll64[14] = server_info->duid[4]; - server_ll64[15] = server_info->duid[5]; - } - server_ll64[8] ^= 2; - - switch (options->option_type) { - case DHCPV6_OPTION_VENDOR_SPECIFIC_INFO: - if (options->option.vendor_spesific.enterprise_number != ARM_ENTERPRISE_NUMBER) { - break; - } - while (options->option.vendor_spesific.data_length) { - uint16_t option_type; - char *domain; - uint8_t *address; - uint16_t option_len; - option_len = net_dns_option_vendor_option_data_get_next(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &option_type); - tr_debug("DHCP vendor specific data type:%u length %d", option_type, option_len); - //tr_debug("DHCP vendor specific data %s", trace_array(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length)); - - if (option_len == 0) { - // Option fields were corrupted - break; - } - if (option_type == ARM_DHCP_VENDOR_DATA_DNS_QUERY_RESULT) { - // Process ARM DNS query result - domain = NULL; - address = NULL; - if (net_dns_option_vendor_option_data_dns_query_read(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &address, &domain) > 0 || - domain || address) { - // Valid ARM DNS query entry - net_dns_query_result_set(interface, address, domain, server_info->life_time); - } - } - if (option_type == ARM_DHCP_VENDOR_DATA_NETWORK_TIME) { - // Process ARM Network Time - // Get Current time - // Get Round trip time of the DHCP request - // Estimated error is elapsed time of request - // If current time difference is larger than estimated error update current time - // set the time for server time + *.5 RTT - int32_t era; - uint32_t offset; - if (net_vendor_option_current_time_read(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &era, &offset, NULL)) { - uint64_t current_time; - uint64_t network_time = (era * (uint64_t)(4294967296)) + offset - 2208988800; //Convert to First day of Unix (1 Jan 1970) - - tr_debug("Network Time option Era:%"PRId32" Offset:%"PRIu32" rtt: %"PRId32" time: %"PRIu64, era, offset, server_info->rtt, network_time); - if (0 == ns_time_system_time_read(¤t_time)) { - uint64_t difference; - // We only adjust clock if time has drifted more than 10 seconds to avoid constant changing of time - // If Round trip time is very high the accuracy is reduced. - uint32_t estimated_error = 10 + server_info->rtt / 10; - // Take into account the round trip time it took the response to arrive from the time server Write the time. - network_time += server_info->rtt / 20; - - if (current_time > network_time) { - difference = current_time - network_time; - } else { - difference = network_time - current_time; - } - if (difference > estimated_error) { - // Larger than 10 second difference update the time - int ret = ns_time_system_time_write(network_time); - tr_info("Network Time %s: Era:%"PRId32" Offset:%"PRIu32" old time: %"PRIu64" time: %"PRIu64, ret == 0 ? "updated" : "update FAILED", era, offset, current_time, network_time); - } - } - } - } - - options->option.vendor_spesific.data_length -= option_len; - options->option.vendor_spesific.data += option_len; - } - break; - - case DHCPV6_OPTION_DNS_SERVERS: - while (options->option.generic.data_length && options->option.generic.data_length >= 16 && options->option.generic.data_length % 16 == 0) { - // Validate payload to have full 16 byte length addresses without any extra bytes - net_dns_server_address_set(interface, server_ll64, options->option.generic.data, server_info->life_time); - options->option.generic.data_length -= 16; - options->option.generic.data += 16; - } - break; - case DHCPV6_OPTION_DOMAIN_LIST: - net_dns_server_search_list_set(interface, server_ll64, options->option.generic.data, options->option.generic.data_length, server_info->life_time); - break; - default: - break; - } - -} - -static void ws_bootstrap_memory_configuration() +void ws_bootstrap_memory_configuration() { /* Configure memory limits for garbage collection based on total memory size * Starting from these values @@ -1082,155 +902,6 @@ static void ws_bootstrap_memory_configuration() return; } - -static int8_t ws_bootstrap_up(protocol_interface_info_entry_t *cur) -{ - int8_t ret_val = -1; - - if (!cur) { - return -1; - } - - if ((cur->configure_flags & INTERFACE_SETUP_MASK) != INTERFACE_SETUP_READY) { - tr_error("Interface not yet fully configured"); - return -2; - } - if (ws_fhss_initialize(cur) != 0) { - tr_error("fhss initialization failed"); - return -3; - } - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - //BBR init like NVM read - ws_bbr_init(cur); - } - // Save FHSS api - cur->ws_info->fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); - - ws_bootstrap_ll_address_validate(cur); - - addr_interface_set_ll64(cur, NULL); - cur->nwk_nd_re_scan_count = 0; - // Trigger discovery for bootstrap - ret_val = nwk_6lowpan_up(cur); - if (ret_val) { - goto cleanup; - } - - /* Wi-sun will trig event for stamechine this timer must be zero on init */ - cur->bootsrap_state_machine_cnt = 0; - /* Disable SLLAO send/mandatory receive with the ARO */ - cur->ipv6_neighbour_cache.use_eui64_as_slla_in_aro = true; - /* Omit sending of NA if ARO SUCCESS */ - cur->ipv6_neighbour_cache.omit_na_aro_success = true; - /* Omit sending of NA and consider ACK to be success */ - cur->ipv6_neighbour_cache.omit_na = true; - // do not process AROs from NA. This is overriden by Wi-SUN specific failure handling - cur->ipv6_neighbour_cache.recv_na_aro = false; - /* Disable NUD Probes */ - cur->ipv6_neighbour_cache.send_nud_probes = false; - cur->ipv6_neighbour_cache.probe_avoided_routers = true; - /*Replace NS handler to disable multicast address queries */ - cur->if_ns_transmit = ws_bootstrap_nd_ns_transmit; - - dhcp_client_init(cur->id, DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE); - dhcp_service_link_local_rx_cb_set(cur->id, ws_bootstrap_dhcp_neighbour_update_cb); - dhcp_client_configure(cur->id, true, true, true); //RENEW uses SOLICIT, Interface will use 1 instance for address get, IAID address hint is not used. - - dhcp_client_solicit_timeout_set(cur->id, WS_DHCP_SOLICIT_TIMEOUT, WS_DHCP_SOLICIT_MAX_RT, WS_DHCP_SOLICIT_MAX_RC, WS_DHCP_SOLICIT_MAX_DELAY); - dhcp_client_option_notification_cb_set(cur->id, ws_bootstrap_dhcp_info_notify_cb); - - // Configure memory limits and garbage collection values; - ws_bootstrap_memory_configuration(); - ws_nud_table_reset(cur); - - ws_bootstrap_candidate_table_reset(cur); - // Zero uptime counters - cur->ws_info->uptime = 0; - cur->ws_info->authentication_time = 0; - cur->ws_info->connected_time = 0; - - blacklist_params_set( - WS_BLACKLIST_ENTRY_LIFETIME, - WS_BLACKLIST_TIMER_MAX_TIMEOUT, - WS_BLACKLIST_TIMER_TIMEOUT, - WS_BLACKLIST_ENTRY_MAX_NBR, - WS_BLACKLIST_PURGE_NBR, - WS_BLACKLIST_PURGE_TIMER_TIMEOUT); - - ws_bootstrap_event_discovery_start(cur); - - return 0; -cleanup: - return ret_val; -} - -void ws_bootstrap_disconnect(protocol_interface_info_entry_t *cur, ws_bootsrap_event_type_e event_type) -{ - if (cur->nwk_bootstrap_state == ER_RPL_NETWORK_LEAVING) { - //Already moved to leaving state. - return; - } - // We are no longer connected - cur->ws_info->connected_time = 0; - - if (cur->rpl_domain && cur->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { - //Stop Asych Timer - ws_bootstrap_asynch_trickle_stop(cur); - tr_debug("Start Network soft leaving"); - if (event_type == WS_FAST_DISCONNECT) { - rpl_control_instant_poison(cur, cur->rpl_domain); - cur->bootsrap_state_machine_cnt = 80; //Give 8 seconds time to send Poison - } else { - rpl_control_poison(cur->rpl_domain, 1); - cur->bootsrap_state_machine_cnt = 6000; //Give 10 minutes time for poison if RPL is not report - } - - } else { - ws_bootstrap_event_discovery_start(cur); - } - cur->nwk_bootstrap_state = ER_RPL_NETWORK_LEAVING; -} - - -static void ws_bootstrap_asynch_trickle_stop(protocol_interface_info_entry_t *cur) -{ - cur->ws_info->trickle_pas_running = false; - cur->ws_info->trickle_pa_running = false; - cur->ws_info->trickle_pcs_running = false; - cur->ws_info->trickle_pc_running = false; - cur->ws_info->trickle_pc_consistency_block_period = 0; -} - -static int8_t ws_bootstrap_down(protocol_interface_info_entry_t *cur) -{ - if (!cur || !(cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { - return -1; - } - - tr_info("Wi-SUN ifdown"); - // Reset MAC for safe upper layer memory free - protocol_mac_reset(cur); - ns_sw_mac_fhss_unregister(cur->mac_api); - ns_fhss_delete(cur->ws_info->fhss_api); - cur->ws_info->fhss_api = NULL; - // Reset WS information - ws_bootstrap_asynch_trickle_stop(cur); - ws_llc_reset(cur); - if (nd_proxy_downstream_interface_unregister(cur->id) != 0) { - tr_warn("nd proxy unregister failed"); - } - ws_nud_table_reset(cur); - dhcp_client_delete(cur->id); - ws_eapol_relay_delete(cur); - ws_eapol_auth_relay_delete(cur); - ws_pae_controller_stop(cur); - ws_bootstrap_candidate_table_reset(cur); - blacklist_clear(); - cur->if_common_forwarding_out_cb = NULL; - - return nwk_6lowpan_down(cur); -} - void ws_bootstrap_configuration_reset(protocol_interface_info_entry_t *cur) { // Configure IP stack to operate as Wi-SUN node @@ -1266,7 +937,7 @@ void ws_bootstrap_configuration_reset(protocol_interface_info_entry_t *cur) return; } -static bool ws_bootstrap_network_name_matches(const struct mcps_data_ie_list *ie_ext, const char *network_name_ptr) +bool ws_bootstrap_network_name_matches(const struct mcps_data_ie_list *ie_ext, const char *network_name_ptr) { ws_wp_network_name_t network_name; @@ -1291,50 +962,6 @@ static bool ws_bootstrap_network_name_matches(const struct mcps_data_ie_list *ie return true; } -static void ws_bootstrap_pan_advertisement_analyse_active(struct protocol_interface_info_entry *cur, ws_pan_information_t *pan_information) -{ - /* In Active state - * - * A consistent transmission is defined as a PAN Advertisement received by a node with PAN ID and - * NETNAME-IE / Network Name matching that of the receiving node, and with a PAN-IE / Routing Cost - * the same or worse than (bigger than or equal to) that of the receiving node. - * - * Inconsistent: - * - * Received Routing Cost is smaller than stored one - * - * A PAN Advertisement received by a node with PAN ID and NETNAME-IE / Network name matching - * that of the receiving node, and PAN-IE / Routing Cost better than (smaller than) that of the receiving node. - * - */ - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - //Border router never set consistent that will guarantee that BR will send advertisment - return; - } -#ifdef WISUN_1_0_ERRATA_FIX - if (pan_information->pan_size == cur->ws_info->pan_information.pan_size) { - //If same pan size information then set consistent value - trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); - } -#else - // Wi-SUN 1.0 specified functionality, causes extra inconsistencies when we hear higher rank advertisements - if (pan_information->routing_cost >= ws_bootstrap_routing_cost_calculate(cur)) { - trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); - } else { - trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); - } -#endif -} - -static parent_info_t *ws_bootstrap_candidate_parent_get_best(protocol_interface_info_entry_t *cur) -{ - ns_list_foreach_safe(parent_info_t, entry, &cur->ws_info->parent_list_reserved) { - tr_info("candidate list a:%s panid:%x cost:%d size:%d rssi:%d txFailure:%u age:%"PRIu32, trace_array(entry->addr, 8), entry->pan_id, entry->pan_information.routing_cost, entry->pan_information.pan_size, entry->signal_dbm, entry->tx_fail, protocol_core_monotonic_time - entry->age); - } - - return ns_list_get_first(&cur->ws_info->parent_list_reserved); -} - static void ws_bootstrap_decode_exclude_range_to_mask_by_range(void *mask_buffer, ws_excluded_channel_range_t *range_info, uint16_t number_of_channels) { uint16_t range_start, range_stop; @@ -1355,8 +982,8 @@ static void ws_bootstrap_decode_exclude_range_to_mask_by_range(void *mask_buffer //channel_index = 0; } if (channel >= range_start && channel <= range_stop) { - //mask_ptr[mask_index] |= 1 << (31 - channel_index); - mask_ptr[0 + (channel / 32)] |= 1 << (31 - (channel % 32)); + //mask_ptr[mask_index] |= 1U << (31 - channel_index); + mask_ptr[channel / 32] |= 1U << (31 - (channel % 32)); } else if (channel > range_stop) { break; } @@ -1364,7 +991,7 @@ static void ws_bootstrap_decode_exclude_range_to_mask_by_range(void *mask_buffer } } -static void ws_bootstrap_candidate_parent_store(parent_info_t *parent, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us, ws_pan_information_t *pan_information) +void ws_bootstrap_candidate_parent_store(parent_info_t *parent, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us, ws_pan_information_t *pan_information) { parent->ws_utt = *ws_utt; // Saved from unicast IE @@ -1406,7 +1033,16 @@ static void ws_bootstrap_candidate_parent_store(parent_info_t *parent, const str parent->age = protocol_core_monotonic_time; } -static void ws_bootstrap_candidate_table_reset(protocol_interface_info_entry_t *cur) +parent_info_t *ws_bootstrap_candidate_parent_get_best(protocol_interface_info_entry_t *cur) +{ + ns_list_foreach_safe(parent_info_t, entry, &cur->ws_info->parent_list_reserved) { + tr_info("candidate list a:%s panid:%x cost:%d size:%d rssi:%d txFailure:%u age:%"PRIu32, trace_array(entry->addr, 8), entry->pan_id, entry->pan_information.routing_cost, entry->pan_information.pan_size, entry->signal_dbm, entry->tx_fail, protocol_core_monotonic_time - entry->age); + } + + return ns_list_get_first(&cur->ws_info->parent_list_reserved); +} + +void ws_bootstrap_candidate_table_reset(protocol_interface_info_entry_t *cur) { //Empty active list ns_list_foreach_safe(parent_info_t, entry, &cur->ws_info->parent_list_free) { @@ -1442,7 +1078,7 @@ static parent_info_t *ws_bootstrap_candidate_parent_allocate(protocol_interface_ return entry; } -static parent_info_t *ws_bootstrap_candidate_parent_get(struct protocol_interface_info_entry *cur, const uint8_t *addr, bool create) +parent_info_t *ws_bootstrap_candidate_parent_get(struct protocol_interface_info_entry *cur, const uint8_t *addr, bool create) { ns_list_foreach_safe(parent_info_t, entry, &cur->ws_info->parent_list_reserved) { if (memcmp(entry->addr, addr, 8) == 0) { @@ -1510,7 +1146,7 @@ static bool ws_bootstrap_candidate_parent_compare(parent_info_t *p1, parent_info return false; } -static void ws_bootstrap_candidate_list_clean(struct protocol_interface_info_entry *cur, uint8_t pan_max, uint32_t current_time, uint16_t pan_id) +void ws_bootstrap_candidate_list_clean(struct protocol_interface_info_entry *cur, uint8_t pan_max, uint32_t current_time, uint16_t pan_id) { int pan_count = 0; @@ -1533,7 +1169,7 @@ static void ws_bootstrap_candidate_list_clean(struct protocol_interface_info_ent } } -static void ws_bootstrap_candidate_parent_sort(struct protocol_interface_info_entry *cur, parent_info_t *new_entry) +void ws_bootstrap_candidate_parent_sort(struct protocol_interface_info_entry *cur, parent_info_t *new_entry) { //Remove from the list @@ -1557,374 +1193,38 @@ static void ws_bootstrap_candidate_parent_sort(struct protocol_interface_info_en ns_list_add_to_end(&cur->ws_info->parent_list_reserved, new_entry); } -static void ws_bootstrap_pan_information_store(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us, ws_pan_information_t *pan_information) +static bool ws_channel_plan_zero_compare(ws_channel_plan_zero_t *rx_plan, ws_hopping_schedule_t *hopping_schdule) { - - parent_info_t *new_entry; - /* Have List of 20 heard neighbours - * Order those as best based on pan cost - * In single pan order based on signal quality - * in single PAN limit the amount of devices to 5 - * If there is no advertisement heard for last hour Clear the neigbour. - */ - - // Discovery state processing - //tr_info("neighbour: addr:%s panid:%x signal:%d", trace_array(data->SrcAddr, 8), data->SrcPANId, data->signal_dbm); - - // Clean old entries - ws_bootstrap_candidate_list_clean(cur, WS_PARENT_LIST_MAX_PAN_IN_DISCOVERY, protocol_core_monotonic_time, data->SrcPANId); - - new_entry = ws_bootstrap_candidate_parent_get(cur, data->SrcAddr, true); - if (!new_entry) { - tr_warn("neighbour creation fail"); - return; - } - // Safe the information - ws_bootstrap_candidate_parent_store(new_entry, data, ws_utt, ws_us, pan_information); - if (!new_entry->link_acceptable) { - // This entry is either poor quality or changed to poor quality link so we will remove this - // Todo in future possibility to try poor link parents if we have not found any good link parents - tr_info("neighbour not accepted: addr:%s panid:%x rsl:%d device_min_sens: %d", trace_array(new_entry->addr, 8), new_entry->pan_id, ws_neighbor_class_rsl_from_dbm_calculate(new_entry->signal_dbm), DEVICE_MIN_SENS); - ns_list_remove(&cur->ws_info->parent_list_reserved, new_entry); - ns_list_add_to_end(&cur->ws_info->parent_list_free, new_entry); - return; + if (rx_plan->operation_class != hopping_schdule->operating_class) { + return false; + } else if (rx_plan->regulator_domain != hopping_schdule->regulatory_domain) { + return false; } - // set to the correct place in list - ws_bootstrap_candidate_parent_sort(cur, new_entry); - - return; + return true; } -static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +static bool ws_channel_plan_one_compare(ws_channel_plan_one_t *rx_plan, ws_hopping_schedule_t *hopping_schdule) { - - //Validate Pan Conrfirmation is at packet - ws_pan_information_t pan_information; - if (!ws_wp_nested_pan_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &pan_information)) { - // Corrupted - tr_error("No pan information"); - return; + uint16_t num_of_channel = hopping_schdule->number_of_channels; + if (rx_plan->ch0 != hopping_schdule->ch0_freq) { + return false; + } else if (rx_plan->channel_spacing != hopping_schdule->channel_spacing) { + return false; + } else if (rx_plan->number_of_channel != num_of_channel) { + return false; } + return true; +} - if (ws_us->excluded_channel_ctrl) { - //Validate that we can storage data - if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK && ws_us->excluded_channels.mask.mask_len_inline > 32) { - return; - } +static bool ws_channel_plan_two_compare(ws_channel_plan_two_t *rx_plan, ws_hopping_schedule_t *hopping_schdule) +{ + if (rx_plan->channel_plan_id != hopping_schdule->channel_plan_id) { + return false; + } else if (rx_plan->regulator_domain != hopping_schdule->regulatory_domain) { + return false; } - - // Check pan flags so that it is valid - if (!pan_information.rpl_routing_method) { - // NOT RPL routing - //tr_warn("Not supported routing"); - return; - } - - // Store heard pans and possible candidate parents - ws_bootstrap_pan_information_store(cur, data, ws_utt, ws_us, &pan_information); - - if (!(ws_bootstrap_state_active(cur) || - ws_bootstrap_state_wait_rpl(cur))) { - // During discovery/eapol/config learn we dont do further processing for advertisements - return; - } - // Active state processing - //tr_debug("Advertisement active"); - - // In active operation less neighbours per pan is allowed - ws_bootstrap_candidate_list_clean(cur, WS_PARENT_LIST_MAX_PAN_IN_ACTIVE, protocol_core_monotonic_time, data->SrcPANId); - - // Check if valid PAN - if (data->SrcPANId != cur->ws_info->network_pan_id) { - return; - } - - // Save route cost for all known neighbors - llc_neighbour_req_t neighbor_info; - neighbor_info.neighbor = NULL; - if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { - neighbor_info.ws_neighbor->routing_cost = pan_information.routing_cost; - } - - ws_bootstrap_pan_advertisement_analyse_active(cur, &pan_information); - - // Learn latest network information - if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER && neighbor_info.neighbor) { - uint8_t ll_address[16]; - ws_bootsrap_create_ll_address(ll_address, neighbor_info.neighbor->mac64); - - if (rpl_control_is_dodag_parent(cur, ll_address)) { - cur->ws_info->pan_information.pan_size = pan_information.pan_size; - cur->ws_info->pan_information.routing_cost = pan_information.routing_cost; - cur->ws_info->pan_information.rpl_routing_method = pan_information.rpl_routing_method; - cur->ws_info->pan_information.use_parent_bs = pan_information.use_parent_bs; - cur->ws_info->pan_information.version = pan_information.version; - } - } -} - -static void ws_bootstrap_pan_advertisement_solicit_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) -{ - - (void)data; - (void)ws_utt; - (void)ws_us; - /* - * An inconsistent transmission is defined as: - * A PAN Advertisement Solicit with NETNAME-IE matching that of the receiving node. - */ - trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); - /* - * A consistent transmission is defined as - * a PAN Advertisement Solicit with NETNAME-IE / Network Name matching that configured on the receiving node. - */ - trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit); - /* - * Optimized PAN discovery to select the parent faster if we hear solicit from someone else - */ - - if (ws_bootstrap_state_discovery(cur) && ws_cfg_network_config_get(cur) <= CONFIG_MEDIUM && - cur->bootsrap_state_machine_cnt > cur->ws_info->trickle_params_pan_discovery.Imin * 2) { - - cur->bootsrap_state_machine_cnt = cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_random_in_range(0, cur->ws_info->trickle_params_pan_discovery.Imin); - - tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); - } - - if (ws_bootstrap_state_active(cur) && cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - mac_neighbor_table_entry_t *neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(cur), data->SrcAddr, ADDR_802_15_4_LONG); - if (neighbor && neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { - ws_bootstrap_parent_confirm(cur, NULL); - } - } -} - - -static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) -{ - - uint16_t pan_version; - ws_bs_ie_t ws_bs_ie; - uint8_t *gtkhash_ptr; - - if (data->SrcPANId != cur->ws_info->network_pan_id) { - return; - } - ws_bt_ie_t ws_bt_ie; - if (!ws_wh_bt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_bt_ie)) { - tr_warn("BT-IE"); - return; - } - - /* - * A consistent transmission is defined as a PAN Configuration with a PAN-ID matching that of the receiving node and - * a PANVER-IE / PAN Version greater than or equal to the receiving node’s current PAN version. - * - * A inconsistent transmission is defined as: - * - * A PAN Configuration with PAN-ID matching that of the receiving node and a - * PANVER-IE / PAN Version that is less than the receiving node’s current PAN version. - */ - - // TODO Add this to neighbor table - // TODO save all information from config message if version number has changed - - if (!ws_wp_nested_pan_version_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &pan_version)) { - // Corrupted - tr_warn("no version"); - return; - } - - gtkhash_ptr = ws_wp_nested_gtkhash_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength); - - if (!gtkhash_ptr) { - // Corrupted - tr_error("No gtk hash"); - return; - } - - if (!ws_wp_nested_bs_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_bs_ie)) { - // Corrupted - tr_error("No broadcast schedule"); - return; - } - - llc_neighbour_req_t neighbor_info; - bool neighbour_pointer_valid; - - //Validate BSI - if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - - if (cur->ws_info->ws_bsi_block.block_time && cur->ws_info->ws_bsi_block.old_bsi == ws_bs_ie.broadcast_schedule_identifier) { - tr_debug("Do not accept a old BSI: %u in time %"PRIu32, cur->ws_info->ws_bsi_block.old_bsi, cur->ws_info->ws_bsi_block.block_time); - //Refresh Block time when hear a old BSI - cur->ws_info->ws_bsi_block.block_time = cur->ws_info->cfg->timing.pan_timeout; - return; - } - - //When Config is learned and USE Parent BS is enabled compare is this new BSI - if (cur->ws_info->configuration_learned && cur->ws_info->pan_information.use_parent_bs && ws_bs_ie.broadcast_schedule_identifier != cur->ws_info->hopping_schdule.fhss_bsi) { - //Accept only next possible BSI number - if ((cur->ws_info->hopping_schdule.fhss_bsi + 1) != ws_bs_ie.broadcast_schedule_identifier) { - tr_debug("Do not accept a unknown BSI: %u", ws_bs_ie.broadcast_schedule_identifier); - } else { - tr_debug("NEW Brodcast Schedule %u...BR rebooted", ws_bs_ie.broadcast_schedule_identifier); - cur->ws_info->ws_bsi_block.block_time = cur->ws_info->cfg->timing.pan_timeout; - cur->ws_info->ws_bsi_block.old_bsi = cur->ws_info->hopping_schdule.fhss_bsi; - ws_bootstrap_event_disconnect(cur, WS_NORMAL_DISCONNECT); - } - return; - } - } - - - if (cur->ws_info->configuration_learned || cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - //If we are border router or learned configuration we only update already learned neighbours. - neighbour_pointer_valid = ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false); - - } else { - neighbour_pointer_valid = ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, true); - if (!neighbour_pointer_valid) { - return; - } - ws_bootstrap_neighbor_set_stable(cur, data->SrcAddr); - } - - if (neighbour_pointer_valid) { - //Update Neighbor Broadcast and Unicast Parameters - ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp, (uint8_t *) data->SrcAddr); - ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us, &cur->ws_info->hopping_schdule); - ws_neighbor_class_neighbor_broadcast_time_info_update(neighbor_info.ws_neighbor, &ws_bt_ie, data->timestamp); - ws_neighbor_class_neighbor_broadcast_schedule_set(neighbor_info.ws_neighbor, &ws_bs_ie); - } - - if (cur->ws_info->configuration_learned) { - tr_info("PAN Config analyse own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); - if (cur->ws_info->pan_information.pan_version == pan_version) { - //Check if Trgigle have been resetted in short time skip this then - if (cur->ws_info->trickle_pc_consistency_block_period == 0) { - // Same version heard so it is consistent - trickle_consistent_heard(&cur->ws_info->trickle_pan_config); - } - - if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { - ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_SOFT_SYNCH); - } - // no need to process more - return; - } else { - // received version is different so we need to reset the trickle - trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); - if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { - ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_HARD_SYNCH); - } - if (common_serial_number_greater_16(cur->ws_info->pan_information.pan_version, pan_version)) { - // older version heard ignoring the message - return; - } - cur->ws_info->trickle_pc_consistency_block_period = WS_CONFIG_CONSISTENT_FILTER_PERIOD; - } - } - - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - //Border router does not learn network information - return; - } - - /* - * Learn new information from neighbor - */ - tr_info("Updated PAN configuration own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); - - // restart PAN version timer - //Check Here Do we have a selected Primary parent - if (!cur->ws_info->configuration_learned || cur->ws_info->rpl_state == RPL_EVENT_DAO_DONE) { - ws_common_border_router_alive_update(cur); - } - - cur->ws_info->pan_information.pan_version = pan_version; - - ws_pae_controller_gtk_hash_update(cur, gtkhash_ptr); - - ws_pae_controller_nw_key_index_update(cur, data->Key.KeyIndex - 1); - - if (!cur->ws_info->configuration_learned) { - // Generate own hopping schedules Follow first parent broadcast and plans and also use same unicast dwell - tr_info("learn network configuration"); - cur->ws_info->configuration_learned = true; - // return to state machine after 1-2 s - cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(10, 20); - // enable frequency hopping for unicast channel and start listening first neighbour - ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_HARD_SYNCH); - // set neighbor as priority parent clear if there is others - protocol_6lowpan_neighbor_priority_clear_all(cur->id, PRIORITY_1ST); - neighbor_info.neighbor->link_role = PRIORITY_PARENT_NEIGHBOUR; - } -} - -static void ws_bootstrap_pan_config_solicit_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) -{ - if (data->SrcPANId != cur->ws_info->network_pan_id) { - return; - } - - /* TODO smart neighbour process - * - * Unsecure packet we cant trust the device? - * - * Question mark in specification also present, now we create neighbour. - * this is moved in future to NS/ND processing triggered by RPL - * - */ - - llc_neighbour_req_t neighbor_info; - if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { - ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp, (uint8_t *) data->SrcAddr); - ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us, &cur->ws_info->hopping_schdule); - } - - if (ws_bootstrap_state_active(cur) && cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - mac_neighbor_table_entry_t *neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(cur), data->SrcAddr, ADDR_802_15_4_LONG); - if (neighbor && neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { - ws_bootstrap_parent_confirm(cur, NULL); - } - } - - /* - * A consistent transmission is defined as a PAN Configuration Solicit with - * a PAN-ID matching that of the receiving node and a NETNAME-IE / Network Name - * matching that configured on the receiving node. - */ - trickle_consistent_heard(&cur->ws_info->trickle_pan_config_solicit); - /* - * inconsistent transmission is defined as either: - * A PAN Configuration Solicit with a PAN-ID matching that of the receiving node and - * a NETNAME-IE / Network Name matching the network name configured on the receiving - */ - trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); -} -static bool ws_channel_plan_zero_compare(ws_channel_plan_zero_t *rx_plan, ws_hopping_schedule_t *hopping_schdule) -{ - if (rx_plan->operation_class != hopping_schdule->operating_class) { - return false; - } else if (rx_plan->regulator_domain != hopping_schdule->regulatory_domain) { - return false; - } - return true; -} - -static bool ws_channel_plan_one_compare(ws_channel_plan_one_t *rx_plan, ws_hopping_schedule_t *hopping_schdule) -{ - uint16_t num_of_channel = hopping_schdule->number_of_channels; - if (rx_plan->ch0 != hopping_schdule->ch0_freq) { - return false; - } else if (rx_plan->channel_spacing != hopping_schdule->channel_spacing) { - return false; - } else if (rx_plan->number_of_channel != num_of_channel) { - return false; - } - return true; -} + return true; +} bool ws_bootstrap_validate_channel_plan(ws_us_ie_t *ws_us, struct protocol_interface_info_entry *cur) { @@ -1936,6 +1236,15 @@ bool ws_bootstrap_validate_channel_plan(ws_us_ie_t *ws_us, struct protocol_inter if (!ws_channel_plan_one_compare(&ws_us->plan.one, &cur->ws_info->hopping_schdule)) { return false; } + } else if (ws_us->channel_plan == 2) { + if (!ws_version_1_1(cur)) { + return false; + } + if (!ws_channel_plan_two_compare(&ws_us->plan.two, &cur->ws_info->hopping_schdule)) { + return false; + } + } else { + return false; } return true; @@ -1962,92 +1271,6 @@ bool ws_bootstrap_validate_channel_function(ws_us_ie_t *ws_us, ws_bs_ie_t *ws_bs return true; } -static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type) -{ - // Store weakest heard packet RSSI - if (cur->ws_info->weakest_received_rssi > data->signal_dbm) { - cur->ws_info->weakest_received_rssi = data->signal_dbm; - } - - if (data->SrcAddrMode != MAC_ADDR_MODE_64_BIT) { - // Not from long address - return; - } - ws_stats_update(cur, STATS_WS_ASYNCH_RX, 1); - //Validate network name - switch (message_type) { - case WS_FT_PAN_ADVERT: - case WS_FT_PAN_ADVERT_SOL: - case WS_FT_PAN_CONF_SOL: - //Check Network Name - if (!ws_bootstrap_network_name_matches(ie_ext, cur->ws_info->cfg->gen.network_name)) { - // Not in our network - return; - } - break; - case WS_FT_PAN_CONF: - break; - default: - return; - } - //UTT-IE and US-IE are mandatory for all Asynch Messages - ws_utt_ie_t ws_utt; - if (!ws_wh_utt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_utt)) { - // Corrupted - return; - } - - ws_us_ie_t ws_us; - if (!ws_wp_nested_us_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_us)) { - // Corrupted - return; - } - - if (!ws_bootstrap_validate_channel_plan(&ws_us, cur) || - !ws_bootstrap_validate_channel_function(&ws_us, NULL)) { - return; - } - - //Handle Message's - switch (message_type) { - case WS_FT_PAN_ADVERT: - // Analyse Advertisement - ws_stats_update(cur, STATS_WS_ASYNCH_RX_PA, 1); - tr_info("received ADVERT Src:%s panid:%x rssi:%d", trace_array(data->SrcAddr, 8), data->SrcPANId, data->signal_dbm); - ws_bootstrap_pan_advertisement_analyse(cur, data, ie_ext, &ws_utt, &ws_us); - break; - case WS_FT_PAN_ADVERT_SOL: - ws_stats_update(cur, STATS_WS_ASYNCH_RX_PAS, 1); - tr_info("received ADVERT SOL Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); - ws_bootstrap_pan_advertisement_solicit_analyse(cur, data, &ws_utt, &ws_us); - break; - case WS_FT_PAN_CONF: - ws_stats_update(cur, STATS_WS_ASYNCH_RX_PC, 1); - tr_info("received CONFIG Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); - ws_bootstrap_pan_config_analyse(cur, data, ie_ext, &ws_utt, &ws_us); - break; - case WS_FT_PAN_CONF_SOL: - ws_stats_update(cur, STATS_WS_ASYNCH_RX_PCS, 1); - tr_info("received CONFIG SOL Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); - ws_bootstrap_pan_config_solicit_analyse(cur, data, &ws_utt, &ws_us); - default: - // Unknown message do not process - break; - } -} - -static void ws_bootstrap_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message) -{ - ws_stats_update(interface, STATS_WS_ASYNCH_TX, 1); - if (interface->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - if (asynch_message == WS_FT_PAN_CONF && interface->ws_info->pending_key_index_info.state == PENDING_KEY_INDEX_ACTIVATE) { - interface->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; - tr_info("Activate new default key %u", interface->ws_info->pending_key_index_info.index + 1); - mac_helper_security_auto_request_key_index_set(interface, interface->ws_info->pending_key_index_info.index, interface->ws_info->pending_key_index_info.index + 1); - } - } -} - uint32_t ws_time_from_last_unicast_traffic(uint32_t current_time_stamp, ws_neighbor_class_entry_t *ws_neighbor) { uint32_t time_from_last_unicast_shedule = current_time_stamp; @@ -2141,7 +1364,7 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent } -static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new) +bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new) { neighbor_buffer->ws_neighbor = NULL; neighbor_buffer->neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(interface), mac_64, ADDR_802_15_4_LONG); @@ -2234,7 +1457,7 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, return false; } - ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); + ws_common_create_ll_address(ll_address, entry_ptr->mac64); if (time_from_start > WS_NEIGHBOR_NUD_TIMEOUT) { @@ -2280,7 +1503,7 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, //ETX Sample 1: random 2-16 //ETX Sample 2: random 4-32 - ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); + ws_common_create_ll_address(ll_address, entry_ptr->mac64); if (!rpl_control_probe_parent_candidate(cur, ll_address)) { return false; } @@ -2394,7 +1617,22 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) goto init_fail; } - ws_llc_create(cur, &ws_bootstrap_asynch_ind, &ws_bootstrap_asynch_confirm, &ws_bootstrap_neighbor_info_request); + if (wisun_mode_host(cur)) { + // Configure for LFN device +#if defined(HAVE_WS) && defined(HAVE_WS_HOST) + ws_llc_create(cur, & ws_bootstrap_6ln_asynch_ind, & ws_bootstrap_6ln_asynch_confirm, &ws_bootstrap_neighbor_info_request, &ws_bootstrap_6ln_eapol_relay_state_active); +#endif + } else if (wisun_mode_router(cur)) { + // Configure FFN device +#if defined(HAVE_WS) && defined(HAVE_WS_ROUTER) + ws_llc_create(cur, &ws_bootstrap_6lr_asynch_ind, &ws_bootstrap_6lr_asynch_confirm, &ws_bootstrap_neighbor_info_request, &ws_bootstrap_6lr_eapol_relay_state_active); +#endif + } else if (wisun_mode_border_router(cur)) { + // Configure as Border router +#if defined(HAVE_WS) && defined(HAVE_WS_BORDER_ROUTER) + ws_llc_create(cur, &ws_bootstrap_6lbr_asynch_ind, &ws_bootstrap_6lbr_asynch_confirm, &ws_bootstrap_neighbor_info_request, &ws_bootstrap_6lbr_eapol_relay_state_active); +#endif + } mpx_api_t *mpx_api = ws_llc_mpx_api_get(cur); if (!mpx_api) { @@ -2428,7 +1666,11 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) ret_val = -4; goto init_fail; } - if (ws_pae_controller_cb_register(cur, &ws_bootstrap_authentication_completed, &ws_bootstrap_authentication_next_target, &ws_bootstrap_nw_key_set, &ws_bootstrap_nw_key_clear, &ws_bootstrap_nw_key_index_set, &ws_bootstrap_nw_frame_counter_set, &ws_bootstrap_nw_frame_counter_read, &ws_bootstrap_pan_version_increment, &ws_bootstrap_nw_info_updated, &ws_bootstrap_eapol_congestion_get) < 0) { + if (ws_pae_controller_nw_key_cb_register(cur, &ws_bootstrap_nw_key_set, &ws_bootstrap_nw_key_clear, &ws_bootstrap_nw_key_index_set, &ws_bootstrap_nw_frame_counter_set, &ws_bootstrap_nw_frame_counter_read) < 0) { + ret_val = -4; + goto init_fail; + } + if (ws_pae_controller_authentication_cb_register(cur, &ws_bootstrap_authentication_completed, &ws_bootstrap_authentication_next_target) < 0) { ret_val = -4; goto init_fail; } @@ -2450,8 +1692,21 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) cur->ipv6_neighbour_cache.link_mtu = cur->max_link_mtu = WS_MPX_MAX_MTU; - cur->if_up = ws_bootstrap_up; - cur->if_down = ws_bootstrap_down; + switch (bootstrap_mode) { + // case NET_6LOWPAN_SLEEPY_HOST: + case NET_6LOWPAN_HOST: + cur->if_up = ws_bootstrap_6ln_up; + cur->if_down = ws_bootstrap_6ln_down; + break; + case NET_6LOWPAN_ROUTER: + case NET_6LOWPAN_BORDER_ROUTER: + cur->if_up = ws_bootstrap_ffn_up; + cur->if_down = ws_bootstrap_ffn_down; + break; + default: + break; + } + cur->ws_info->neighbor_storage = neigh_info; cur->etx_read_override = ws_etx_read; @@ -2515,7 +1770,45 @@ int ws_bootstrap_restart_delayed(int8_t interface_id) return 0; } -int ws_bootstrap_set_rf_config(protocol_interface_info_entry_t *cur, phy_rf_channel_configuration_s rf_configs) +static int8_t ws_bootstrap_phy_mode_resolver(const mac_api_t *api, uint8_t phy_mode_id, phy_rf_channel_configuration_s *rf_config) +{ + rf_config->modulation = ws_phy_get_modulation_using_phy_mode_id(phy_mode_id); + if (rf_config->modulation == M_UNDEFINED) { + return -1; + } + protocol_interface_info_entry_t *interface = protocol_stack_interface_info_get_by_id(api->parent_id); + if (!interface) { + return -1; + } + uint8_t regulatory_domain = interface->ws_info->hopping_schdule.regulatory_domain; + uint8_t base_channel_plan_id = interface->ws_info->hopping_schdule.channel_plan_id; + if (base_channel_plan_id == 255) { + base_channel_plan_id = ws_phy_convert_operating_class_to_channel_plan_id(interface->ws_info->hopping_schdule.operating_class, regulatory_domain); + } + if (!base_channel_plan_id) { + return -1; + } + // Function returns base channel plan ID, if it matches the PHY mode ID. Otherwise, nearest matching channel plan ID where PHY mode ID is allowed will be returned. + uint8_t channel_plan_id = ws_phy_get_channel_plan_id_using_phy_mode_id(phy_mode_id, regulatory_domain, base_channel_plan_id); + if (!channel_plan_id) { + return -1; + } + + rf_config->channel_0_center_frequency = ws_phy_get_channel_0_frequency_using_channel_plan_id(channel_plan_id); + rf_config->channel_spacing = ws_phy_get_channel_spacing_using_channel_plan_id(channel_plan_id); + rf_config->number_of_channels = ws_phy_get_number_of_channels_using_channel_plan_id(channel_plan_id); + rf_config->datarate = ws_phy_get_datarate_using_phy_mode_id(phy_mode_id); + if (!rf_config->channel_0_center_frequency || !rf_config->channel_spacing || !rf_config->number_of_channels || !rf_config->datarate) { + return -1; + } + rf_config->ofdm_option = ws_phy_get_ofdm_option_using_phy_mode_id(phy_mode_id); + rf_config->ofdm_mcs = ws_phy_get_ofdm_mcs_using_phy_mode_id(phy_mode_id); + rf_config->fec = ws_phy_get_fsk_fec_enabled_using_phy_mode_id(phy_mode_id); + rf_config->modulation_index = ws_phy_get_modulation_index_using_phy_mode_id(phy_mode_id); + return 0; +} + +static int ws_bootstrap_set_rf_config(protocol_interface_info_entry_t *cur, phy_rf_channel_configuration_s rf_configs) { mlme_set_t set_request; // Set MAC mode @@ -2545,8 +1838,23 @@ int ws_bootstrap_set_rf_config(protocol_interface_info_entry_t *cur, phy_rf_chan set_request.value_pointer = &multi_csma_params; set_request.value_size = sizeof(mlme_multi_csma_ca_param_t); cur->mac_api->mlme_req(cur->mac_api, MLME_SET, &set_request); - // Start automatic CCA threshold - mac_helper_start_auto_cca_threshold(cur->id, cur->ws_info->hopping_schdule.number_of_channels, CCA_DEFAULT_DBM, CCA_HIGH_LIMIT, CCA_LOW_LIMIT); + if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_JP) { + // For Japan regulatory domain, use static CCA threshold -80dBm as defined by Wi-SUN FAN specification + mac_helper_start_auto_cca_threshold(cur->id, cur->ws_info->hopping_schdule.number_of_channels, -80, -80, -80); + } else { + // Start automatic CCA threshold + mac_helper_start_auto_cca_threshold(cur->id, cur->ws_info->hopping_schdule.number_of_channels, CCA_DEFAULT_DBM, CCA_HIGH_LIMIT, CCA_LOW_LIMIT); + } + // Enable MAC mode switch when base PHY mode ID could be found, otherwise disable the feature + uint8_t phy_mode_id = cur->ws_info->hopping_schdule.phy_mode_id; + if (phy_mode_id == 255) { + phy_mode_id = ws_phy_convert_operating_mode_to_phy_mode_id(cur->ws_info->hopping_schdule.operating_mode); + } + if (!phy_mode_id) { + cur->mac_api->mac_mode_switch_resolver_set(cur->mac_api, NULL, phy_mode_id); + } else { + cur->mac_api->mac_mode_switch_resolver_set(cur->mac_api, &ws_bootstrap_phy_mode_resolver, phy_mode_id); + } return 0; } @@ -2567,35 +1875,35 @@ int ws_bootstrap_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t return 0; } -static int ws_bootstrap_set_domain_rf_config(protocol_interface_info_entry_t *cur) +static int ws_bootstrap_operating_mode_resolver(protocol_interface_info_entry_t *cur, phy_rf_channel_configuration_s *rf_config) +{ + memset(rf_config, 0, sizeof(phy_rf_channel_configuration_s)); + rf_config->fec = false; + rf_config->modulation = M_2FSK; + rf_config->datarate = ws_phy_get_datarate_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); + rf_config->modulation_index = ws_phy_get_modulation_index_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); + rf_config->channel_0_center_frequency = (uint32_t)cur->ws_info->hopping_schdule.ch0_freq * 100000; + rf_config->channel_spacing = ws_phy_decode_channel_spacing(cur->ws_info->hopping_schdule.channel_spacing); + rf_config->number_of_channels = cur->ws_info->hopping_schdule.number_of_channels; + return 0; +} + +int ws_bootstrap_set_domain_rf_config(protocol_interface_info_entry_t *cur) { - phy_rf_channel_configuration_s rf_configs; - memset(&rf_configs, 0, sizeof(phy_rf_channel_configuration_s)); + phy_rf_channel_configuration_s rf_config; + memset(&rf_config, 0, sizeof(phy_rf_channel_configuration_s)); uint8_t phy_mode_id = cur->ws_info->hopping_schdule.phy_mode_id; - if (((phy_mode_id >= 34) && (phy_mode_id <= 38)) || - ((phy_mode_id >= 51) && (phy_mode_id <= 54)) || - ((phy_mode_id >= 68) && (phy_mode_id <= 70)) || - ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { - rf_configs.modulation = M_OFDM; - rf_configs.datarate = ws_get_datarate_using_phy_mode_id(cur->ws_info->hopping_schdule.phy_mode_id); - rf_configs.ofdm_option = ws_get_ofdm_option_using_phy_mode_id(cur->ws_info->hopping_schdule.phy_mode_id); - rf_configs.ofdm_mcs = ws_get_ofdm_mcs_using_phy_mode_id(cur->ws_info->hopping_schdule.phy_mode_id); - } else { - if ((phy_mode_id >= 17) && (phy_mode_id <= 24)) { - rf_configs.fec = true; - } else { - rf_configs.fec = false; - } - rf_configs.modulation = M_2FSK; - rf_configs.datarate = ws_get_datarate_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); - rf_configs.modulation_index = ws_get_modulation_index_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); + if (phy_mode_id == 255) { + phy_mode_id = ws_phy_convert_operating_mode_to_phy_mode_id(cur->ws_info->hopping_schdule.operating_mode); } - rf_configs.channel_0_center_frequency = (uint32_t)cur->ws_info->hopping_schdule.ch0_freq * 100000; - rf_configs.channel_spacing = ws_decode_channel_spacing(cur->ws_info->hopping_schdule.channel_spacing); - rf_configs.number_of_channels = cur->ws_info->hopping_schdule.number_of_channels; - ws_bootstrap_set_rf_config(cur, rf_configs); + if (!phy_mode_id || ws_bootstrap_phy_mode_resolver(cur->mac_api, phy_mode_id, &rf_config)) { + // Cannot resolve RF configuration using PHY mode ID, try with operating mode + ws_bootstrap_operating_mode_resolver(cur, &rf_config); + } + + ws_bootstrap_set_rf_config(cur, rf_config); return 0; } @@ -2618,10 +1926,10 @@ static void ws_bootstrap_mac_activate(protocol_interface_info_entry_t *cur, uint } } -static void ws_bootstrap_fhss_activate(protocol_interface_info_entry_t *cur) +void ws_bootstrap_fhss_activate(protocol_interface_info_entry_t *cur) { tr_debug("FHSS activate"); - ws_fhss_enable(cur); + ws_bootstrap_fhss_enable(cur); ws_llc_hopping_schedule_config(cur, &cur->ws_info->hopping_schdule); // Only supporting fixed channel @@ -2633,32 +1941,7 @@ static void ws_bootstrap_fhss_activate(protocol_interface_info_entry_t *cur) return; } -static void ws_bootstrap_network_configuration_learn(protocol_interface_info_entry_t *cur) -{ - tr_debug("Start using PAN configuration"); - - // Timing information can be modified here - ws_llc_set_pan_information_pointer(cur, &cur->ws_info->pan_information); - uint8_t *gtkhash = ws_pae_controller_gtk_hash_ptr_get(cur); - ws_llc_set_gtkhash(cur, gtkhash); - // TODO update own fhss schedules we are starting to follow first parent - - return; -} - -static void ws_bootstrap_ip_stack_addr_clear(protocol_interface_info_entry_t *cur) -{ - tr_debug("ip stack address clear"); - ns_list_foreach_safe(if_address_entry_t, addr, &cur->ip_addresses) { - if (addr->source != ADDR_SOURCE_STATIC && - addr_ipv6_scope(addr->address, cur) > IPV6_SCOPE_LINK_LOCAL) { - // Remove all exept User set address - addr_delete_entry(cur, addr); - } - } -} - -static void ws_bootstrap_ip_stack_reset(protocol_interface_info_entry_t *cur) +void ws_bootstrap_ip_stack_reset(protocol_interface_info_entry_t *cur) { tr_debug("ip stack reset"); // Delete all temporary cached information @@ -2666,7 +1949,7 @@ static void ws_bootstrap_ip_stack_reset(protocol_interface_info_entry_t *cur) lowpan_context_list_free(&cur->lowpan_contexts); } -static void ws_bootstrap_ip_stack_activate(protocol_interface_info_entry_t *cur) +void ws_bootstrap_ip_stack_activate(protocol_interface_info_entry_t *cur) { tr_debug("ip stack init"); clear_power_state(ICMP_ACTIVE); @@ -2674,448 +1957,40 @@ static void ws_bootstrap_ip_stack_activate(protocol_interface_info_entry_t *cur) ws_bootstrap_ip_stack_reset(cur); } -static void ws_set_fhss_hop(protocol_interface_info_entry_t *cur) +static uint16_t ws_bootstrap_routing_cost_calculate(protocol_interface_info_entry_t *cur) { - uint16_t own_rank = ws_bootstrap_rank_get(cur); - uint16_t rank_inc = ws_bootstrap_min_rank_inc_get(cur); - if (own_rank == 0xffff || rank_inc == 0xffff) { - return; + mac_neighbor_table_entry_t *mac_neighbor = mac_neighbor_entry_get_priority(mac_neighbor_info(cur)); + if (!mac_neighbor) { + return 0xffff; + } + ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&cur->ws_info->neighbor_storage, mac_neighbor->index); + if (!ws_neighbor) { + return 0xffff; } - // Calculate own hop count. This method gets inaccurate when hop count increases. - uint8_t own_hop = (own_rank - rank_inc) / rank_inc; - ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, own_hop); - if (own_hop == 1) { - // Allow transmitting unicast frames only on TX slots in normal mode and always in expedited forwarding mode for first hop - ns_fhss_ws_set_tx_allowance_level(cur->ws_info->fhss_api, WS_TX_SLOT, WS_TX_ALWAYS); + + uint16_t etx = ws_local_etx_read(cur, ADDR_802_15_4_LONG, mac_neighbor->mac64); + if (etx == 0) { + etx = WS_ETX_MAX; //SET maximum value here if ETX is unknown } else { - // Allow transmitting unicast frames only on TX slots in normal and expedited forwarding mode for other hops - ns_fhss_ws_set_tx_allowance_level(cur->ws_info->fhss_api, WS_TX_SLOT, WS_TX_SLOT); + //Scale to 128 based ETX (local read return 0x100 - 0xffff + etx = etx >> 1; + } + // Make the 0xffff as maximum value + if (ws_neighbor->routing_cost + etx > 0xffff) { + return 0xffff; } - tr_debug("own hop: %u, own rank: %u, rank inc: %u", own_hop, own_rank, rank_inc); + + return ws_neighbor->routing_cost + etx; } -static void ws_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) +void ws_bootstrap_network_start(protocol_interface_info_entry_t *cur) { - rpl_control_register_address(interface, addr); - // Timer is used only to track full registrations + //Set Network names, Pan information configure, hopping schedule & GTKHash + ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->cfg->gen.network_name, strlen(cur->ws_info->cfg->gen.network_name)); + ws_llc_set_pan_information_pointer(cur, &cur->ws_info->pan_information); +} - if (addr != NULL && interface->ws_info->aro_registration_timer) { - // Single address update and timer is running - return; - } - - if (interface->ws_info->aro_registration_timer == 0) { - // Timer expired and check if we have valid address to register - ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { - if (!addr_is_ipv6_link_local(address->address)) { - // We have still valid addresses let the timer run for next period - tr_info("ARO registration timer start"); - interface->ws_info->aro_registration_timer = WS_NEIGHBOR_NUD_TIMEOUT; - return; - } - } - } -} - -static void ws_address_parent_update(protocol_interface_info_entry_t *interface) -{ - tr_info("RPL parent update ... register ARO"); - ws_address_registration_update(interface, NULL); -} - -static void ws_bootstrap_parent_confirm(protocol_interface_info_entry_t *cur, struct rpl_instance *instance) -{ - /* Possible problem with the parent connection - * Give some time for parent to rejoin and confirm the connection with ARO and DAO - */ - const rpl_dodag_conf_t *config = NULL; - uint32_t Imin_secs = 0; - - if (!ws_bootstrap_state_active(cur)) { - // If we are not in Active state no need to confirm parent - return; - } - - tr_info("RPL parent confirm"); - - if (!instance) { - // If we dont have instance we take any available to get reference - instance = rpl_control_enumerate_instances(cur->rpl_domain, NULL); - } - - if (instance) { - config = rpl_control_get_dodag_config(instance); - } - - if (config) { - //dio imin Period caluclate in seconds - uint32_t Imin_ms = config->dio_interval_min < 32 ? (1ul << config->dio_interval_min) : 0xfffffffful; - //Covert to seconds and multiple by 2 so we give time to recovery so divide by 500 do that operation - Imin_secs = (Imin_ms + 499) / 500; - - if (Imin_secs > 0xffff) { - Imin_secs = 0xffff; - } - } - if (Imin_secs == 0) { - // If we dont have RPL configuration we assume conservative value - Imin_secs = 60; - } - - /*Speed up the ARO registration*/ - if (cur->ws_info->aro_registration_timer > Imin_secs) { - cur->ws_info->aro_registration_timer = Imin_secs; - } -} - -static void ws_rpl_parent_dis_callback(const uint8_t *ll_parent_address, void *handle, struct rpl_instance *instance) -{ - (void) ll_parent_address; - protocol_interface_info_entry_t *cur = handle; - if (!cur->rpl_domain || cur->interface_mode != INTERFACE_UP) { - return; - } - //Multicast DIS from parent indicate that Parent is not valid in short time window possible - ws_bootstrap_parent_confirm(cur, instance); -} - - -static void ws_bootstrap_rpl_callback(rpl_event_t event, void *handle) -{ - - protocol_interface_info_entry_t *cur = handle; - if (!cur->rpl_domain || cur->interface_mode != INTERFACE_UP) { - return; - } - - if (event == RPL_EVENT_POISON_FINISHED) { - //If we are waiting poison we will trig Discovery after couple seconds - if (cur->nwk_bootstrap_state == ER_RPL_NETWORK_LEAVING) { - cur->bootsrap_state_machine_cnt = 80; //Give 8 seconds time to send Poison - } - return; - } - - // if waiting for RPL and - if (event == RPL_EVENT_DAO_DONE) { - // Trigger statemachine check - cur->bootsrap_state_machine_cnt = 1; - rpl_dodag_info_t dodag_info; - struct rpl_instance *instance = rpl_control_enumerate_instances(cur->rpl_domain, NULL); - - if (instance && rpl_control_read_dodag_info(instance, &dodag_info)) { - tr_debug("Enable DHCPv6 relay"); - dhcp_relay_agent_enable(cur->id, dodag_info.dodag_id); - - tr_debug("Start EAPOL relay"); - // Set both own port and border router port to 10253 - ws_eapol_relay_start(cur, EAPOL_RELAY_SOCKET_PORT, dodag_info.dodag_id, EAPOL_RELAY_SOCKET_PORT); - // Set network information to PAE - ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->pan_information.pan_version, cur->ws_info->cfg->gen.network_name); - // Network key is valid, indicate border router IID to controller - ws_pae_controller_nw_key_valid(cur, &dodag_info.dodag_id[8]); - //Update here Suplikant target by validated Primary Parent - if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - mac_neighbor_table_entry_t *mac_neighbor = mac_neighbor_entry_get_priority(mac_neighbor_info(cur)); - if (mac_neighbor) { - ws_pae_controller_set_target(cur, cur->ws_info->network_pan_id, mac_neighbor->mac64); - } - } - - // After successful DAO ACK connection to border router is verified - ws_common_border_router_alive_update(cur); - } - - if (!cur->ws_info->trickle_pa_running || !cur->ws_info->trickle_pc_running) { - //Enable wi-sun asynch adverisment - ws_bootstrap_advertise_start(cur); - } - - ws_set_fhss_hop(cur); - // Set retry configuration for bootstrap ready state - ws_bootstrap_configure_max_retries(cur, WS_MAX_FRAME_RETRIES); - // Set TX failure request restart configuration - ws_bootstrap_configure_data_request_restart(cur, WS_CCA_REQUEST_RESTART_MAX, WS_TX_REQUEST_RESTART_MAX, WS_REQUEST_RESTART_BLACKLIST_MIN, WS_REQUEST_RESTART_BLACKLIST_MAX); - } else if (event == RPL_EVENT_LOCAL_REPAIR_NO_MORE_DIS) { - /* - * RPL goes to passive mode, but does not require any extra changed - * - * We could remove our current addresses learned from RPL - * We could send solicit for configuration and then select new parent when those arrive - * - */ - - } else if (event == RPL_EVENT_LOCAL_REPAIR_START) { - tr_debug("RPL local repair start"); - //Disable Async and go to state 4 to confirm parent connection - ws_bootstrap_parent_confirm(cur, NULL); - // Move to state 4 if we see issues with primary parent - if (ws_bootstrap_state_active(cur)) { - tr_info("Move state 4 to wait parent connection confirmation"); - ws_bootstrap_rpl_scan_start(cur); - ws_nwk_event_post(cur, ARM_NWK_NWK_CONNECTION_DOWN); - } - } else if (event == RPL_EVENT_DAO_PARENT_ADD) { - ws_address_parent_update(cur); - } - cur->ws_info->rpl_state = event; - tr_info("RPL event %d", event); -} - -static void ws_dhcp_client_global_adress_cb(int8_t interface, uint8_t dhcp_addr[static 16], uint8_t prefix[static 16], bool register_status) -{ - (void)prefix; - (void)interface; - //TODO add handler for negative status - tr_debug("DHCPv6 %s status %u with link %s", trace_ipv6(prefix), register_status, trace_ipv6(dhcp_addr)); - if (register_status) { - protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface); - if (cur) { - ws_address_reregister_trig(cur); - } - } else { - //Delete dhcpv6 client - dhcp_client_global_address_delete(interface, dhcp_addr, prefix); - } -} - - -void ws_dhcp_client_address_request(protocol_interface_info_entry_t *cur, uint8_t *prefix, uint8_t *parent_link_local) -{ - if (dhcp_client_get_global_address(cur->id, parent_link_local, prefix, ws_dhcp_client_global_adress_cb) != 0) { - tr_error("DHCPp client request fail"); - } -} - -void ws_dhcp_client_address_delete(protocol_interface_info_entry_t *cur, uint8_t *prefix) -{ - dhcp_client_global_address_delete(cur->id, NULL, prefix); -} - -bool ws_eapol_relay_state_active(protocol_interface_info_entry_t *cur) -{ - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER || cur->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { - return true; - } - - return false; -} - -static void ws_rpl_prefix_callback(prefix_entry_t *prefix, void *handle, uint8_t *parent_link_local) -{ - protocol_interface_info_entry_t *cur = (protocol_interface_info_entry_t *) handle; - /* Check if A-Flag. - * A RPL node may use this option for the purpose of Stateless Address Autoconfiguration (SLAAC) - * from a prefix advertised by a parent. - */ - if (prefix->options & PIO_A) { - - if (parent_link_local) { - if (icmpv6_slaac_prefix_update(cur, prefix->prefix, prefix->prefix_len, prefix->lifetime, prefix->preftime) != 0) { - ipv6_interface_slaac_handler(cur, prefix->prefix, prefix->prefix_len, prefix->lifetime, prefix->preftime); - /* - * Give SLAAC addresses a different label and low precedence to indicate that - * they probably shouldn't be used for external traffic. SLAAC use in Wi-SUN is non-standard, - * and we use it for mesh-local traffic we should prefer any DHCP-assigned addresses - * for talking to the outside world - * - */ - addr_policy_table_add_entry(prefix->prefix, prefix->prefix_len, 2, WS_NON_PREFFRED_LABEL); - } - } else { - icmpv6_slaac_prefix_update(cur, prefix->prefix, prefix->prefix_len, 0, 0); - } - } else if (prefix->prefix_len) { - // Create new address using DHCP - if (parent_link_local) { - ws_dhcp_client_address_request(cur, prefix->prefix, parent_link_local); - } else { - /* Deprecate address and remove client */ - tr_debug("Prefix invalidation %s", trace_ipv6(prefix->prefix)); - dhcp_client_global_address_delete(cur->id, NULL, prefix->prefix); - } - } -} - -static bool ws_rpl_candidate_soft_filtering(protocol_interface_info_entry_t *cur, struct rpl_instance *instance) -{ - //Already many candidates - uint16_t candidate_list_size = rpl_control_candidate_list_size(cur, instance); - if (candidate_list_size >= cur->ws_info->cfg->gen.rpl_parent_candidate_max) { - return false; - } - - uint16_t selected_parents = rpl_control_selected_parent_count(cur, instance); - - //Already enough selected candidates - if (selected_parents >= cur->ws_info->cfg->gen.rpl_selected_parent_max) { - candidate_list_size -= selected_parents; - if (candidate_list_size >= 2) { - //We have more candidates than selected - return false; - } - } - - return true; -} - -static bool ws_rpl_new_parent_callback(uint8_t *ll_parent_address, void *handle, struct rpl_instance *instance, uint16_t candidate_rank) -{ - - protocol_interface_info_entry_t *cur = handle; - if (!cur->rpl_domain || cur->interface_mode != INTERFACE_UP) { - return false; - } - - if (blacklist_reject(ll_parent_address)) { - // Rejected by blacklist - return false; - } - - uint8_t mac64[10]; - //bool replace_ok = false; - //bool create_ok = false; - llc_neighbour_req_t neigh_buffer; - - //Discover neigh ready here for possible ETX validate - memcpy(mac64, ll_parent_address + 8, 8); - mac64[0] ^= 2; - - - ws_bootstrap_neighbor_info_request(cur, mac64, &neigh_buffer, false); - //Discover Multicast temporary entry for create neighbour table entry for new candidate - ws_neighbor_temp_class_t *entry = ws_llc_get_multicast_temp_entry(cur, mac64); - - if (!ws_rpl_candidate_soft_filtering(cur, instance)) { - - //Acept only better than own rank here - if (candidate_rank >= rpl_control_current_rank(instance)) { - //Do not accept no more siblings - return false; - } - - uint16_t candidate_list_size = rpl_control_candidate_list_size(cur, instance); - if (candidate_list_size > cur->ws_info->cfg->gen.rpl_parent_candidate_max + 1) { - //Accept only 1 better 1 time - return false; - } - - if (!neigh_buffer.neighbor) { - //Do not accept any new in that Place - return false; - } - - uint8_t replacing[16]; - //Accept Know neighbour if it is enough good - if (!rpl_control_find_worst_neighbor(cur, instance, replacing)) { - return false; - } - // +2 Is for PAN ID space - memcpy(mac64, replacing + 8, 8); - mac64[0] ^= 2; - - if (ws_local_etx_read(cur, ADDR_802_15_4_LONG, mac64) == 0xffff) { - //Not probed yet because ETX is 0xffff - return false; - } - - uint16_t etx = 0; - if (neigh_buffer.neighbor) { - etx = ws_local_etx_read(cur, ADDR_802_15_4_LONG, neigh_buffer.neighbor->mac64); - } - - // Accept now only better one's when max candidates selected and max candidate list size is reached - return rpl_possible_better_candidate(cur, instance, replacing, candidate_rank, etx); - } - - //Neighbour allready - if (neigh_buffer.neighbor) { - return true; - } - - if (!entry) { - //No Multicast Entry Available - return false; - } - - //Create entry - bool create_ok = ws_bootstrap_neighbor_info_request(cur, entry->mac64, &neigh_buffer, true); - if (create_ok) { - ws_neighbor_class_entry_t *ws_neigh = neigh_buffer.ws_neighbor; - ws_bootstrap_neighbor_set_stable(cur, entry->mac64); - //Copy fhss temporary data - *ws_neigh = entry->neigh_info_list; - mac_neighbor_table_trusted_neighbor(mac_neighbor_info(cur), neigh_buffer.neighbor, true); - } - ws_llc_free_multicast_temp_entry(cur, entry); - -#if 0 -neigh_create_ok: - - if (create_ok && replace_ok) { - //Try remove here when accepted new better one possible - tr_debug("Remove %s by %s", trace_ipv6(replacing), trace_ipv6(ll_parent_address)); - rpl_control_neighbor_delete_from_instance(cur, instance, replacing); - } -#endif - return create_ok; -} - -static void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur) -{ - tr_debug("RPL Activate"); - bool downstream = true; - bool leaf = false; - - addr_add_router_groups(cur); - rpl_control_set_domain_on_interface(cur, protocol_6lowpan_rpl_domain, downstream); - rpl_control_set_callback(protocol_6lowpan_rpl_domain, ws_bootstrap_rpl_callback, ws_rpl_prefix_callback, ws_rpl_new_parent_callback, ws_rpl_parent_dis_callback, cur); - // If i am router I Do this - rpl_control_force_leaf(protocol_6lowpan_rpl_domain, leaf); - rpl_control_process_routes(protocol_6lowpan_rpl_domain, false); // Wi-SUN assumes that no default route needed - rpl_control_request_parent_link_confirmation(true); - rpl_control_set_dio_multicast_min_config_advertisment_count(WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT); - rpl_control_set_address_registration_timeout((WS_NEIGHBOR_LINK_TIMEOUT / 60) + 1); - rpl_control_set_dao_retry_count(WS_MAX_DAO_RETRIES); - rpl_control_set_initial_dao_ack_wait(WS_MAX_DAO_INITIAL_TIMEOUT); - rpl_control_set_mrhof_parent_set_size(WS_MAX_PARENT_SET_COUNT); - rpl_control_set_force_tunnel(true); - if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - rpl_control_set_memory_limits(WS_NODE_RPL_SOFT_MEM_LIMIT, WS_NODE_RPL_HARD_MEM_LIMIT); - } - // Set RPL Link ETX Validation Threshold to 2.5 - 33.0 - // This setup will set ETX 0x800 to report ICMP error 18% probability - // When ETX start go over 0x280 forward dropping probability start increase linear to 100% at 0x2100 - rpl_policy_forward_link_etx_threshold_set(0x280, 0x2100); - - // Set the minimum target refresh to sen DAO registrations before pan timeout - rpl_control_set_minimum_dao_target_refresh(WS_RPL_DAO_MAX_TIMOUT); - - cur->ws_info->rpl_state = 0xff; // Set invalid state and learn from event -} - -static void ws_bootstrap_network_start(protocol_interface_info_entry_t *cur) -{ - //Set Network names, Pan information configure, hopping schedule & GTKHash - ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->cfg->gen.network_name, strlen(cur->ws_info->cfg->gen.network_name)); - ws_llc_set_pan_information_pointer(cur, &cur->ws_info->pan_information); -} - -static void ws_bootstrap_network_discovery_configure(protocol_interface_info_entry_t *cur) -{ - // Reset information to defaults - cur->ws_info->network_pan_id = 0xffff; - - ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); - ws_bootstrap_set_domain_rf_config(cur); - ws_fhss_configure(cur, true); - - //Set Network names, Pan information configure, hopping schedule & GTKHash - ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->cfg->gen.network_name, strlen(cur->ws_info->cfg->gen.network_name)); -} - - -static void ws_bootstrap_advertise_start(protocol_interface_info_entry_t *cur) +void ws_bootstrap_advertise_start(protocol_interface_info_entry_t *cur) { cur->ws_info->trickle_pa_running = true; trickle_start(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); @@ -3124,73 +1999,8 @@ static void ws_bootstrap_advertise_start(protocol_interface_info_entry_t *cur) trickle_start(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); } -static void ws_bootstrap_pan_version_increment(protocol_interface_info_entry_t *cur) -{ - (void)cur; - ws_bbr_pan_version_increase(cur); -} - -// Start network scan -static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) -{ - tr_debug("router discovery start"); - // Remove network keys from MAC - ws_pae_controller_nw_keys_remove(cur); - ws_bootstrap_state_change(cur, ER_ACTIVE_SCAN); - cur->nwk_nd_re_scan_count = 0; - cur->ws_info->configuration_learned = false; - cur->ws_info->pan_timeout_timer = 0; - cur->ws_info->weakest_received_rssi = 0; - - // Clear learned candidate parents - ws_bootstrap_candidate_table_reset(cur); - - // Clear RPL information - rpl_control_free_domain_instances_from_interface(cur); - // Clear EAPOL relay address - ws_eapol_relay_delete(cur); - - // Clear ip stack from old information - ws_bootstrap_ip_stack_reset(cur); - // New network scan started old addresses not assumed valid anymore - ws_bootstrap_ip_stack_addr_clear(cur); - - if ((cur->lowpan_info & INTERFACE_NWK_BOOTSRAP_ACTIVE) != INTERFACE_NWK_BOOTSRAP_ACTIVE) { - // we have sent bootstrap ready event and now - // restarted discovery so bootstrap down event is sent - cur->lowpan_info |= INTERFACE_NWK_BOOTSRAP_ACTIVE; - ws_nwk_event_post(cur, ARM_NWK_NWK_CONNECTION_DOWN); - } - - // Start advertisement solicit trickle and calculate when we are checking the status - cur->ws_info->trickle_pas_running = true; - if (cur->ws_info->trickle_pan_advertisement_solicit.I != cur->ws_info->trickle_params_pan_discovery.Imin) { - // Trickle not reseted so starting a new interval - trickle_start(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); - } - - // Discovery statemachine is checkked after we have sent the Solicit - uint32_t time_to_solicit = 0; - if (cur->ws_info->trickle_pan_advertisement_solicit.t > cur->ws_info->trickle_pan_advertisement_solicit.now) { - time_to_solicit = cur->ws_info->trickle_pan_advertisement_solicit.t - cur->ws_info->trickle_pan_advertisement_solicit.now; - } - - tr_debug("Disc params imin %u, imax %u, expirations %u, k %u PAS Trickle I %u t %u, now %u, c %u", - cur->ws_info->trickle_params_pan_discovery.Imin, cur->ws_info->trickle_params_pan_discovery.Imax, cur->ws_info->trickle_params_pan_discovery.TimerExpirations, cur->ws_info->trickle_params_pan_discovery.k, - cur->ws_info->trickle_pan_advertisement_solicit.I, cur->ws_info->trickle_pan_advertisement_solicit.t, cur->ws_info->trickle_pan_advertisement_solicit.now, cur->ws_info->trickle_pan_advertisement_solicit.c); - - time_to_solicit += cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_random_in_range(0, cur->ws_info->trickle_params_pan_discovery.Imin); - - if (time_to_solicit > 0xffff) { - time_to_solicit = 0xffff; - } - cur->bootsrap_state_machine_cnt = time_to_solicit; - - tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); -} - // Start authentication -static void ws_bootstrap_start_authentication(protocol_interface_info_entry_t *cur) +void ws_bootstrap_start_authentication(protocol_interface_info_entry_t *cur) { // Set PAN ID and network name to controller ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->pan_information.pan_version, cur->ws_info->cfg->gen.network_name); @@ -3241,40 +2051,10 @@ static void ws_bootstrap_nw_frame_counter_read(protocol_interface_info_entry_t * mac_helper_key_link_frame_counter_read(cur->id, counter, slot); } -static void ws_bootstrap_nw_info_updated(protocol_interface_info_entry_t *cur, uint16_t pan_id, uint16_t pan_version, char *network_name) -{ - /* For border router, the PAE controller reads PAN ID, PAN version and network name from storage. - * If they are set, takes them into use here. - */ - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - // Get PAN ID and network name - ws_gen_cfg_t gen_cfg; - if (ws_cfg_gen_get(&gen_cfg, NULL) < 0) { - return; - } - - // If PAN ID has not been set, set it - if (gen_cfg.network_pan_id == 0xffff) { - gen_cfg.network_pan_id = pan_id; - // Sets PAN version - cur->ws_info->pan_information.pan_version = pan_version; - cur->ws_info->pan_information.pan_version_set = true; - } - - // If network name has not been set, set it - if (strlen(gen_cfg.network_name) == 0) { - strncpy(gen_cfg.network_name, network_name, 32); - } - - // Stores the settings - ws_cfg_gen_set(cur, NULL, &gen_cfg, 0); - } -} - static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_t *cur, auth_result_e result, uint8_t *target_eui_64) { if (result == AUTH_RESULT_OK) { - tr_debug("authentication success eui64:%s", trace_array(target_eui_64, 8)); + tr_info("authentication success eui64:%s", trace_array(target_eui_64, 8)); if (target_eui_64) { // Authentication was made contacting the authenticator cur->ws_info->authentication_time = cur->ws_info->uptime; @@ -3322,138 +2102,6 @@ static const uint8_t *ws_bootstrap_authentication_next_target(protocol_interface return previous_eui_64; } -static void ws_bootstrap_eapol_congestion_init(protocol_interface_info_entry_t *cur) -{ - random_early_detection_free(cur->llc_random_early_detection); - cur->llc_random_early_detection = NULL; - - if (cur->llc_random_early_detection == NULL) { - cur->llc_random_early_detection = random_early_detection_create( - cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_min, - cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_max, - 100, RED_AVERAGE_WEIGHT_EIGHTH); - } - - random_early_detection_free(cur->llc_eapol_random_early_detection); - cur->llc_eapol_random_early_detection = NULL; - - if (cur->llc_eapol_random_early_detection == NULL) { - cur->llc_eapol_random_early_detection = random_early_detection_create( - cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_min, - cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_max, - 100, RED_AVERAGE_WEIGHT_EIGHTH); - } -} - -static bool ws_bootstrap_eapol_congestion_get(protocol_interface_info_entry_t *cur, uint16_t active_supp) -{ - if (cur == NULL || cur->random_early_detection == NULL || cur->llc_random_early_detection == NULL || cur->llc_eapol_random_early_detection == NULL) { - return false; - } - - bool return_value = false; - static struct red_info_s *red_info = NULL; - uint16_t adaptation_average = 0; - uint16_t llc_average = 0; - uint16_t llc_eapol_average = 0; - uint16_t average_sum = 0; - uint8_t active_max = 0; - - //TODO implement API for HEAP info request - uint32_t heap_size; - const mem_stat_t *mem_stats = ns_dyn_mem_get_mem_stat(); - if (mem_stats) { - heap_size = mem_stats->heap_sector_size; - } else { - heap_size = 0; - } - - /* - * For different memory sizes the max simultaneous authentications will be - * 32k: (32k / 50k) * 2 + 1 = 1 - * 65k: (65k / 50k) * 2 + 1 = 3 - * 250k: (250k / 50k) * 2 + 1 = 11 - * 1000k: (1000k / 50k) * 2 + 1 = 41 - * 2000k: (2000k / 50k) * 2 + 1 = 50 (upper limit) - */ - active_max = (heap_size / 50000) * 2 + 1; - if (active_max > 50) { - active_max = 50; - } - - // Read the values for adaptation and LLC queues - adaptation_average = random_early_detetction_aq_read(cur->random_early_detection); - llc_average = random_early_detetction_aq_read(cur->llc_random_early_detection); - llc_eapol_average = random_early_detetction_aq_read(cur->llc_eapol_random_early_detection); - // Calculate combined average - average_sum = adaptation_average + llc_average + llc_eapol_average; - - // Maximum for active supplicants based on memory reached, fail - if (active_supp >= active_max) { - return_value = true; - goto congestion_get_end; - } - - // Always allow at least five negotiations (if memory does not limit) - if (active_supp < 5) { - goto congestion_get_end; - } - - if (red_info == NULL) { - red_info = random_early_detection_create( - cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_min, - cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_max, - 100, RED_AVERAGE_WEIGHT_DISABLED); - } - if (red_info == NULL) { - goto congestion_get_end; - } - - // Check drop probability - average_sum = random_early_detetction_aq_calc(red_info, average_sum); - return_value = random_early_detection_congestion_check(red_info); - -congestion_get_end: - tr_info("Active supplicant limit, active: %i max: %i summed averageQ: %i adapt averageQ: %i LLC averageQ: %i LLC EAPOL averageQ: %i drop: %s", active_supp, active_max, average_sum, adaptation_average, llc_average, llc_eapol_average, return_value ? "T" : "F"); - - return return_value; -} - -// Start configuration learning -static void ws_bootstrap_start_configuration_learn(protocol_interface_info_entry_t *cur) -{ - tr_debug("router configuration learn start"); - ws_bootstrap_state_change(cur, ER_SCAN); - - cur->ws_info->configuration_learned = false; - - // Clear all temporary information - ws_bootstrap_ip_stack_reset(cur); - - cur->ws_info->pas_requests = 0; - //Calculate max time for config learn state - cur->ws_info->pan_config_sol_max_timeout = trickle_timer_max(&cur->ws_info->trickle_params_pan_discovery, PCS_MAX); - // Reset advertisement solicit trickle to start discovering network - cur->ws_info->trickle_pcs_running = true; - trickle_start(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery); - trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery); -} -static void ws_bootstrap_rpl_scan_start(protocol_interface_info_entry_t *cur) -{ - tr_debug("Start RPL learn"); - // Stop Trickle timers - ws_bootstrap_asynch_trickle_stop(cur); - - // routers wait until RPL root is contacted - ws_bootstrap_state_change(cur, ER_RPL_SCAN); - // Change state as the state is checked in state machine - cur->ws_info->rpl_state = RPL_EVENT_LOCAL_REPAIR_START; - //For Large network and medium should do passive scan - if (ws_cfg_network_config_get(cur) > CONFIG_SMALL) { - // Set timeout for check to 30 - 60 seconds - cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_INITIAL_TIMEOUT / 2, WS_RPL_DIS_INITIAL_TIMEOUT); - } -} /* * Event transitions @@ -3484,21 +2132,28 @@ void ws_bootstrap_event_disconnect(protocol_interface_info_entry_t *cur, ws_boot { ws_bootsrap_event_trig(event_type, cur->bootStrapId, ARM_LIB_LOW_PRIORITY_EVENT, NULL); } +void ws_bootstrap_event_test_procedure_trigger(protocol_interface_info_entry_t *cur, ws_bootsrap_procedure_t procedure) +{ + if (cur->bootStrapId < 0) { + return; + } + ws_bootsrap_event_trig(WS_TEST_PROC_TRIGGER, cur->bootStrapId, ARM_LIB_LOW_PRIORITY_EVENT, (void *) procedure); +} void ws_bootstrap_configuration_trickle_reset(protocol_interface_info_entry_t *cur) { trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); } -static void ws_set_asynch_channel_list(protocol_interface_info_entry_t *cur, asynch_request_t *async_req) +static void ws_bootstrap_set_asynch_channel_list(protocol_interface_info_entry_t *cur, asynch_request_t *async_req) { memset(&async_req->channel_list, 0, sizeof(channel_list_s)); if (cur->ws_info->cfg->fhss.fhss_uc_channel_function == WS_FIXED_CHANNEL) { //SET 1 Channel only uint16_t channel_number = cur->ws_info->cfg->fhss.fhss_uc_fixed_channel; - async_req->channel_list.channel_mask[0 + (channel_number / 32)] = (1 << (channel_number % 32)); + async_req->channel_list.channel_mask[channel_number / 32] = 1U << (channel_number % 32); } else { - ws_generate_channel_list(async_req->channel_list.channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class, cur->ws_info->hopping_schdule.channel_plan_id); + ws_common_generate_channel_list(async_req->channel_list.channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class, cur->ws_info->hopping_schdule.channel_plan_id); } async_req->channel_list.channel_page = CHANNEL_PAGE_10; @@ -3514,92 +2169,30 @@ static void ws_bootstrap_pan_advert_solicit(protocol_interface_info_entry_t *cur async_req.wp_requested_nested_ie_list.us_ie = true; async_req.wp_requested_nested_ie_list.net_name_ie = true; - ws_set_asynch_channel_list(cur, &async_req); - - - async_req.security.SecurityLevel = 0; - - ws_stats_update(cur, STATS_WS_ASYNCH_TX_PAS, 1); - ws_llc_asynch_request(cur, &async_req); -} + ws_bootstrap_set_asynch_channel_list(cur, &async_req); -static void ws_bootstrap_pan_config_solicit(protocol_interface_info_entry_t *cur) -{ - asynch_request_t async_req; - memset(&async_req, 0, sizeof(asynch_request_t)); - async_req.message_type = WS_FT_PAN_CONF_SOL; - //Request UTT Header and US and Net name from payload - async_req.wh_requested_ie_list.utt_ie = true; - async_req.wp_requested_nested_ie_list.us_ie = true; - async_req.wp_requested_nested_ie_list.net_name_ie = true; - ws_set_asynch_channel_list(cur, &async_req); async_req.security.SecurityLevel = 0; - ws_stats_update(cur, STATS_WS_ASYNCH_TX_PCS, 1); - ws_llc_asynch_request(cur, &async_req); -} - -static struct rpl_instance *ws_get_rpl_instance(protocol_interface_info_entry_t *cur) -{ - if (!cur || !cur->rpl_domain) { - return NULL; - } - struct rpl_instance *best_instance = NULL; - ns_list_foreach(struct rpl_instance, instance, &cur->rpl_domain->instances) { - best_instance = instance; - // Select best grounded and lowest rank? But there should be only one really - } - return best_instance; -} - -static uint16_t ws_bootstrap_routing_cost_calculate(protocol_interface_info_entry_t *cur) -{ - mac_neighbor_table_entry_t *mac_neighbor = mac_neighbor_entry_get_priority(mac_neighbor_info(cur)); - if (!mac_neighbor) { - return 0xffff; - } - ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&cur->ws_info->neighbor_storage, mac_neighbor->index); - if (!ws_neighbor) { - return 0xffff; - } - - uint16_t etx = ws_local_etx_read(cur, ADDR_802_15_4_LONG, mac_neighbor->mac64); - if (etx == 0) { - etx = WS_ETX_MAX; //SET maximum value here if ETX is unknown - } else { - //Scale to 128 based ETX (local read return 0x100 - 0xffff - etx = etx >> 1; - } - // Make the 0xffff as maximum value - if (ws_neighbor->routing_cost + etx > 0xffff) { - return 0xffff; - } - - return ws_neighbor->routing_cost + etx; + ws_stats_update(cur, STATS_WS_ASYNCH_TX_PAS, 1); + ws_llc_asynch_request(cur, &async_req); } -static uint16_t ws_bootstrap_rank_get(protocol_interface_info_entry_t *cur) +static void ws_bootstrap_pan_config_solicit(protocol_interface_info_entry_t *cur) { - struct rpl_instance *rpl_instance = ws_get_rpl_instance(cur); - if (!rpl_instance) { - return 0xffff; - } - return rpl_control_current_rank(rpl_instance); -} + asynch_request_t async_req; + memset(&async_req, 0, sizeof(asynch_request_t)); + async_req.message_type = WS_FT_PAN_CONF_SOL; + //Request UTT Header and US and Net name from payload + async_req.wh_requested_ie_list.utt_ie = true; + async_req.wp_requested_nested_ie_list.us_ie = true; + async_req.wp_requested_nested_ie_list.net_name_ie = true; + ws_bootstrap_set_asynch_channel_list(cur, &async_req); + async_req.security.SecurityLevel = 0; -static uint16_t ws_bootstrap_min_rank_inc_get(protocol_interface_info_entry_t *cur) -{ - struct rpl_instance *rpl_instance = ws_get_rpl_instance(cur); - if (!rpl_instance) { - return 0xffff; - } - struct rpl_dodag_info_t dodag_info; - if (!rpl_control_read_dodag_info(rpl_instance, &dodag_info)) { - return 0xffff; - } - return dodag_info.dag_min_hop_rank_inc; + ws_stats_update(cur, STATS_WS_ASYNCH_TX_PCS, 1); + ws_llc_asynch_request(cur, &async_req); } static void ws_bootstrap_pan_advert(protocol_interface_info_entry_t *cur) @@ -3612,8 +2205,11 @@ static void ws_bootstrap_pan_advert(protocol_interface_info_entry_t *cur) async_req.wp_requested_nested_ie_list.us_ie = true; async_req.wp_requested_nested_ie_list.pan_ie = true; async_req.wp_requested_nested_ie_list.net_name_ie = true; + if (ws_version_1_1(cur)) { + async_req.wp_requested_nested_ie_list.phy_cap_ie = true; + } - ws_set_asynch_channel_list(cur, &async_req); + ws_bootstrap_set_asynch_channel_list(cur, &async_req); async_req.security.SecurityLevel = 0; if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { @@ -3643,8 +2239,11 @@ static void ws_bootstrap_pan_config(protocol_interface_info_entry_t *cur) async_req.wp_requested_nested_ie_list.pan_version_ie = true; async_req.wp_requested_nested_ie_list.gtkhash_ie = true; async_req.wp_requested_nested_ie_list.vp_ie = true; + if (ws_version_1_1(cur)) { + async_req.wp_requested_nested_ie_list.lfn_gtk_version_ie = ws_lfn_version_learned(cur); + } - ws_set_asynch_channel_list(cur, &async_req); + ws_bootstrap_set_asynch_channel_list(cur, &async_req); async_req.security.SecurityLevel = mac_helper_default_security_level_get(cur); async_req.security.KeyIdMode = mac_helper_default_security_key_id_mode_get(cur); @@ -3659,207 +2258,32 @@ static void ws_bootstrap_pan_config(protocol_interface_info_entry_t *cur) ws_llc_asynch_request(cur, &async_req); } -static int8_t ws_bootstrap_backbone_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address) -{ - (void) interface_ptr; - (void) address; - - if (ws_bbr_backbone_address_get(address)) { - return 0; - } - - return -1; -} - - static void ws_bootstrap_event_handler(arm_event_s *event) { - ws_bootsrap_event_type_e event_type; - event_type = (ws_bootsrap_event_type_e)event->event_type; protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_bootstrap_id(event->receiver); if (!cur) { return; } - switch (event_type) { - case WS_INIT_EVENT: - tr_debug("tasklet init"); - break; - case WS_DISCOVERY_START: - tr_info("Discovery start"); - protocol_mac_reset(cur); - ws_llc_reset(cur); - lowpan_adaptation_interface_reset(cur->id); - //Clear Pending Key Index State - cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; - cur->mac_parameters->mac_default_key_index = 0; - - ipv6_destination_cache_clean(cur->id); - - // Clear parent blacklist - blacklist_clear(); - - // All trickle timers stopped to allow entry from any state - ws_bootstrap_asynch_trickle_stop(cur); - //Init Packet congestion - ws_bootstrap_packet_congestion_init(cur); - - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - tr_info("Border router start network"); - - - if (!ws_bbr_ready_to_start(cur)) { - // Wi-SUN not started yet we wait for Border router permission - ws_bootstrap_state_change(cur, ER_WAIT_RESTART); - cur->nwk_nd_re_scan_count = randLIB_get_random_in_range(40, 100); - return; - } - // Clear Old information from stack - - ws_nud_table_reset(cur); - ws_bootstrap_neighbor_list_clean(cur); - ws_bootstrap_ip_stack_reset(cur); - ws_pae_controller_auth_init(cur); - - if (cur->ws_info->cfg->gen.network_pan_id == 0xffff) { - cur->ws_info->network_pan_id = randLIB_get_random_in_range(0, 0xfffd); - } else { - cur->ws_info->network_pan_id = cur->ws_info->cfg->gen.network_pan_id; - } - if (!cur->ws_info->pan_information.pan_version_set) { - cur->ws_info->pan_information.pan_version = randLIB_get_random_in_range(0, 0xffff); - cur->ws_info->pan_information.pan_version_set = true; - } - cur->ws_info->pan_information.pan_size = 0; - cur->ws_info->pan_information.routing_cost = 0; - cur->ws_info->pan_information.rpl_routing_method = true; - cur->ws_info->pan_information.use_parent_bs = true; - cur->ws_info->pan_information.version = WS_FAN_VERSION_1_0; - - uint8_t *gtkhash = ws_pae_controller_gtk_hash_ptr_get(cur); - ws_llc_set_gtkhash(cur, gtkhash); - ws_bbr_pan_version_increase(cur); - - // Set default parameters for FHSS when starting a discovery - ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); - ws_fhss_border_router_configure(cur); - ws_bootstrap_set_domain_rf_config(cur); - ws_bootstrap_fhss_activate(cur); - - uint8_t ll_addr[16]; - addr_interface_get_ll_address(cur, ll_addr, 1); - - //SET EAPOL authenticator EUI64 - ws_pae_controller_border_router_addr_write(cur, cur->mac); - - // Set EAPOL relay to port 10255 and authenticator relay to 10253 (and to own ll address) - ws_eapol_relay_start(cur, BR_EAPOL_RELAY_SOCKET_PORT, ll_addr, EAPOL_RELAY_SOCKET_PORT); - - // Set authenticator relay to port 10253 and PAE to 10254 (and to own ll address) - ws_eapol_auth_relay_start(cur, EAPOL_RELAY_SOCKET_PORT, ll_addr, PAE_AUTH_SOCKET_PORT); - - // Set PAN ID and network name to controller - ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->pan_information.pan_version, cur->ws_info->cfg->gen.network_name); - - // Set backbone IP address get callback - ws_pae_controller_auth_cb_register(cur, ws_bootstrap_backbone_ip_addr_get); - - // Set PAE port to 10254 and authenticator relay to 10253 (and to own ll address) - ws_pae_controller_authenticator_start(cur, PAE_AUTH_SOCKET_PORT, ll_addr, EAPOL_RELAY_SOCKET_PORT); - - // Initialize eapol congestion tracking - ws_bootstrap_eapol_congestion_init(cur); - - // Set retry configuration for bootstrap ready state - ws_bootstrap_configure_max_retries(cur, WS_MAX_FRAME_RETRIES); - - // Set TX failure request restart configuration - ws_bootstrap_configure_data_request_restart(cur, WS_CCA_REQUEST_RESTART_MAX, WS_TX_REQUEST_RESTART_MAX, WS_REQUEST_RESTART_BLACKLIST_MIN, WS_REQUEST_RESTART_BLACKLIST_MAX); - - // Set CSMA-CA backoff configuration - ws_bootstrap_configure_csma_ca_backoffs(cur, WS_MAX_CSMA_BACKOFFS, WS_MAC_MIN_BE, WS_MAC_MAX_BE); - - ws_bootstrap_event_operation_start(cur); - break; - } - ws_pae_controller_supp_init(cur); - // Clear learned neighbours - ws_bootstrap_neighbor_list_clean(cur); - // Configure LLC for network discovery - ws_bootstrap_network_discovery_configure(cur); - ws_bootstrap_fhss_activate(cur); - // Set retry configuration for discovery state - ws_bootstrap_configure_max_retries(cur, WS_MAX_FRAME_RETRIES_BOOTSTRAP); - // Set TX failure request restart configuration for discovery state - ws_bootstrap_configure_data_request_restart(cur, WS_CCA_REQUEST_RESTART_MAX, WS_TX_REQUEST_RESTART_MAX_BOOTSTRAP, WS_REQUEST_RESTART_BLACKLIST_MIN, WS_REQUEST_RESTART_BLACKLIST_MAX); - // Set CSMA-CA backoff configuration - ws_bootstrap_configure_csma_ca_backoffs(cur, WS_MAX_CSMA_BACKOFFS, WS_MAC_MIN_BE, WS_MAC_MAX_BE); - // Start network scan - ws_bootstrap_start_discovery(cur); - break; - - case WS_CONFIGURATION_START: - tr_info("Configuration start"); - // Old configuration is considered invalid stopping all - ws_bootstrap_asynch_trickle_stop(cur); - - // Build list of possible neighbours and learn first broadcast schedule - - ws_bootstrap_start_configuration_learn(cur); - break; - case WS_OPERATION_START: - tr_info("operation start"); - // Advertisements stopped during the RPL scan - ws_bootstrap_asynch_trickle_stop(cur); - // Activate RPL - // Activate IPv6 stack - ws_bootstrap_ip_stack_activate(cur); - ws_bootstrap_rpl_activate(cur); - ws_bootstrap_network_start(cur); - // Wait for RPL start - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - ws_bootstrap_event_routing_ready(cur); - } else { - ws_bootstrap_rpl_scan_start(cur); - /* While in Join State 4, if a non Border Router determines it has been unable to communicate with the PAN Border - * Router for an interval of PAN_TIMEOUT, a node MUST assume failure of the PAN Border Router and MUST - * Transition to Join State 1 - */ - ws_common_border_router_alive_update(cur); - } - break; - case WS_ROUTING_READY: - tr_info("Routing ready"); - // stopped all to make sure we can enter here from any state - ws_bootstrap_asynch_trickle_stop(cur); - - // Indicate PAE controller that bootstrap is ready - ws_pae_controller_bootstrap_done(cur); - - ws_bootstrap_advertise_start(cur); - ws_bootstrap_state_change(cur, ER_BOOTSRAP_DONE); - break; - case WS_FAST_DISCONNECT: - ws_bootstrap_disconnect(cur, WS_FAST_DISCONNECT); - break; - case WS_NORMAL_DISCONNECT: - ws_bootstrap_disconnect(cur, WS_NORMAL_DISCONNECT); - break; - - default: - tr_err("Invalid event received"); - break; + if (wisun_mode_host(cur)) { + ws_bootstrap_6ln_event_handler(cur, event); + } else if (wisun_mode_router(cur)) { + ws_bootstrap_6lr_event_handler(cur, event); + } else if (wisun_mode_border_router(cur)) { + ws_bootstrap_6lbr_event_handler(cur, event); } } -static int8_t ws_bootstrap_neighbor_set(protocol_interface_info_entry_t *cur, parent_info_t *parent_ptr, bool clear_list) +int8_t ws_bootstrap_neighbor_set(protocol_interface_info_entry_t *cur, parent_info_t *parent_ptr, bool clear_list) { uint16_t pan_id = cur->ws_info->network_pan_id; // Add EAPOL neighbor cur->ws_info->network_pan_id = parent_ptr->pan_id; - cur->ws_info->pan_information = parent_ptr->pan_information; + cur->ws_info->pan_information.pan_size = parent_ptr->pan_information.pan_size; + cur->ws_info->pan_information.routing_cost = parent_ptr->pan_information.routing_cost; + cur->ws_info->pan_information.use_parent_bs = parent_ptr->pan_information.use_parent_bs; cur->ws_info->pan_information.pan_version = 0; // This is learned from actual configuration // If PAN ID changes, clear learned neighbors and activate FHSS @@ -3887,72 +2311,34 @@ static int8_t ws_bootstrap_neighbor_set(protocol_interface_info_entry_t *cur, pa * State machine * * */ -void ws_bootstrap_network_scan_process(protocol_interface_info_entry_t *cur) -{ - - parent_info_t *selected_parent_ptr; - - tr_debug("analyze network discovery result"); - -select_best_candidate: - selected_parent_ptr = ws_bootstrap_candidate_parent_get_best(cur); - - if (!selected_parent_ptr) { - // Configure LLC for network discovery - ws_bootstrap_network_discovery_configure(cur); - // randomize new channel and start MAC - ws_bootstrap_fhss_activate(cur); - // Next check will be after one trickle - uint32_t random_start = cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_random_in_range(0, cur->ws_info->trickle_params_pan_discovery.Imin); - if (random_start > 0xffff) { - random_start = 0xffff; - } - cur->bootsrap_state_machine_cnt = random_start; - - tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); - return; - } - tr_info("selected parent:%s panid %u", trace_array(selected_parent_ptr->addr, 8), selected_parent_ptr->pan_id); - - if (ws_bootstrap_neighbor_set(cur, selected_parent_ptr, false) < 0) { - goto select_best_candidate; - } - - ws_pae_controller_set_target(cur, selected_parent_ptr->pan_id, selected_parent_ptr->addr); // temporary!!! store since auth - ws_bootstrap_event_authentication_start(cur); - return; -} - -void ws_bootstrap_configure_process(protocol_interface_info_entry_t *cur) +void ws_bootstrap_state_disconnect(protocol_interface_info_entry_t *cur, ws_bootsrap_event_type_e event_type) { - - if (cur->ws_info->configuration_learned) { - ws_bootstrap_network_configuration_learn(cur); - ws_bootstrap_event_operation_start(cur); + if (cur->nwk_bootstrap_state == ER_RPL_NETWORK_LEAVING) { + //Already moved to leaving state. return; } - return; -} -void ws_bootstrap_rpl_wait_process(protocol_interface_info_entry_t *cur) -{ + // We are no longer connected + cur->ws_info->connected_time = 0; - if (cur->ws_info->rpl_state == RPL_EVENT_DAO_DONE) { - // RPL routing is ready - cur->ws_info->connected_time = cur->ws_info->uptime; - ws_bootstrap_event_routing_ready(cur); - } else if (!rpl_control_have_dodag(cur->rpl_domain)) { - // RPL not ready send DIS message if possible - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_ROUTER) { - // TODO Multicast DIS should be sent only if no DIO heard for some time - rpl_control_transmit_dis(cur->rpl_domain, cur, 0, 0, NULL, 0, ADDR_LINK_LOCAL_ALL_RPL_NODES); + if (cur->rpl_domain && cur->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { + //Stop Asych Timer + ws_bootstrap_asynch_trickle_stop(cur); + tr_debug("Start Network soft leaving"); + if (event_type == WS_FAST_DISCONNECT) { + rpl_control_instant_poison(cur, cur->rpl_domain); + cur->bootsrap_state_machine_cnt = 80; //Give 8 seconds time to send Poison + } else { + rpl_control_poison(cur->rpl_domain, 1); + cur->bootsrap_state_machine_cnt = 6000; //Give 10 minutes time for poison if RPL is not report } - // set timer for next DIS - cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_TIMEOUT / 2, WS_RPL_DIS_TIMEOUT); + + } else { + ws_bootstrap_event_discovery_start(cur); } - return; + cur->nwk_bootstrap_state = ER_RPL_NETWORK_LEAVING; } -static bool ws_bootstrap_state_discovery(struct protocol_interface_info_entry *cur) +bool ws_bootstrap_state_discovery(struct protocol_interface_info_entry *cur) { if (cur->nwk_bootstrap_state == ER_ACTIVE_SCAN) { return true; @@ -3960,7 +2346,7 @@ static bool ws_bootstrap_state_discovery(struct protocol_interface_info_entry *c return false; } -static bool ws_bootstrap_state_authenticate(struct protocol_interface_info_entry *cur) +bool ws_bootstrap_state_authenticate(struct protocol_interface_info_entry *cur) { // Think about the state value if (cur->nwk_bootstrap_state == ER_PANA_AUTH) { @@ -3969,7 +2355,7 @@ static bool ws_bootstrap_state_authenticate(struct protocol_interface_info_entry return false; } -static bool ws_bootstrap_state_configure(struct protocol_interface_info_entry *cur) +bool ws_bootstrap_state_configure(struct protocol_interface_info_entry *cur) { // Think about the state value if (cur->nwk_bootstrap_state == ER_SCAN) { @@ -3978,7 +2364,7 @@ static bool ws_bootstrap_state_configure(struct protocol_interface_info_entry *c return false; } -static bool ws_bootstrap_state_wait_rpl(struct protocol_interface_info_entry *cur) +bool ws_bootstrap_state_wait_rpl(struct protocol_interface_info_entry *cur) { // Think about the state value if (cur->nwk_bootstrap_state == ER_RPL_SCAN) { @@ -3987,7 +2373,7 @@ static bool ws_bootstrap_state_wait_rpl(struct protocol_interface_info_entry *cu return false; } -static bool ws_bootstrap_state_active(struct protocol_interface_info_entry *cur) +bool ws_bootstrap_state_active(struct protocol_interface_info_entry *cur) { if (cur->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { return true; @@ -3995,56 +2381,15 @@ static bool ws_bootstrap_state_active(struct protocol_interface_info_entry *cur) return false; } -static void ws_bootstrap_state_change(protocol_interface_info_entry_t *cur, icmp_state_t nwk_bootstrap_state) +void ws_bootstrap_state_change(protocol_interface_info_entry_t *cur, icmp_state_t nwk_bootstrap_state) { cur->bootsrap_state_machine_cnt = 1; cur->nwk_bootstrap_state = nwk_bootstrap_state; } -void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur) +void ws_bootstrap_network_down(protocol_interface_info_entry_t *cur) { - - switch (cur->nwk_bootstrap_state) { - case ER_WAIT_RESTART: - tr_debug("WS SM:Wait for startup"); - ws_bootstrap_event_discovery_start(cur); - break; - case ER_ACTIVE_SCAN: - tr_debug("WS SM:Active Scan"); - ws_bootstrap_network_scan_process(cur); - break; - case ER_SCAN: - tr_debug("WS SM:configuration Scan"); - ws_bootstrap_configure_process(cur); - break; - case ER_PANA_AUTH: - tr_info("authentication start"); - // Advertisements stopped during the EAPOL - ws_bootstrap_asynch_trickle_stop(cur); - ws_fhss_configure(cur, false); - int8_t new_default = cur->ws_info->weakest_received_rssi - 1; - if ((new_default < CCA_DEFAULT_DBM) && (new_default >= CCA_LOW_LIMIT) && (new_default <= CCA_HIGH_LIMIT)) { - // Restart automatic CCA threshold using weakest received RSSI as new default - mac_helper_start_auto_cca_threshold(cur->id, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->weakest_received_rssi - 1, CCA_HIGH_LIMIT, CCA_LOW_LIMIT); - } - ws_bootstrap_start_authentication(cur); - break; - case ER_RPL_SCAN: - tr_debug("WS SM:Wait RPL to contact DODAG root"); - ws_bootstrap_rpl_wait_process(cur); - break; - case ER_BOOTSRAP_DONE: - tr_debug("WS SM:Bootstrap Done"); - // Bootstrap_done event to application - nwk_bootsrap_state_update(ARM_NWK_BOOTSTRAP_READY, cur); - break; - case ER_RPL_NETWORK_LEAVING: - tr_debug("WS SM:RPL Leaving ready trigger discovery"); - ws_bootstrap_event_discovery_start(cur); - break; - default: - tr_warn("WS SM:Invalid state %d", cur->nwk_bootstrap_state); - } + ws_nwk_event_post(cur, ARM_NWK_NWK_CONNECTION_DOWN); } void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t ticks) @@ -4108,50 +2453,18 @@ void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t t } } +void ws_bootstrap_asynch_trickle_stop(protocol_interface_info_entry_t *cur) +{ + cur->ws_info->trickle_pas_running = false; + cur->ws_info->trickle_pa_running = false; + cur->ws_info->trickle_pcs_running = false; + cur->ws_info->trickle_pc_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; +} + void ws_bootstrap_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) { - /* Border router keep alive check - */ - if (cur->ws_info->pan_timeout_timer) { - // PAN version timer running - if (cur->ws_info->pan_timeout_timer > seconds) { - cur->ws_info->pan_timeout_timer -= seconds; - if (cur->ws_info->pan_timeout_timer < cur->ws_info->cfg->timing.pan_timeout / 10) { - /* pan timeout is closing need to verify that DAO is tested before the pan times out. - This will give some extra time for RPL to find better parents. - Border router liveliness can be checked from version number change or from successful DAO registrations - in this case there has not been any version number changes during this PAN lifetime. - */ - rpl_control_dao_timeout(cur->rpl_domain, 20); - } - } else { - // Border router has timed out - //Clear Timeout timer - cur->ws_info->pan_timeout_timer = 0; - tr_warn("Border router has timed out"); - ws_bootstrap_event_disconnect(cur, WS_FAST_DISCONNECT); - } - } - if (cur->ws_info->aro_registration_timer) { - if (cur->ws_info->aro_registration_timer > seconds) { - cur->ws_info->aro_registration_timer -= seconds; - } else { - // Update all addressess. This function will update the timer value if needed - cur->ws_info->aro_registration_timer = 0; - ws_address_registration_update(cur, NULL); - } - } - - if (cur->ws_info->ws_bsi_block.block_time) { - if (cur->ws_info->ws_bsi_block.block_time > seconds) { - cur->ws_info->ws_bsi_block.block_time -= seconds; - } else { - //Clear A BSI blokker - cur->ws_info->ws_bsi_block.block_time = 0; - cur->ws_info->ws_bsi_block.old_bsi = 0; - } - } /*Update join state statistics*/ if (ws_bootstrap_state_discovery(cur)) { ws_stats_update(cur, STATS_WS_STATE_1, 1); @@ -4163,37 +2476,14 @@ void ws_bootstrap_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t s ws_stats_update(cur, STATS_WS_STATE_4, 1); } else if (ws_bootstrap_state_active(cur)) { ws_stats_update(cur, STATS_WS_STATE_5, 1); + //Update neighbour MDR phy capability mode id + ws_neighbour_mdr_mode_analyze(cur); } cur->ws_info->uptime++; ws_llc_timer_seconds(cur, seconds); -} - -void ws_bootstrap_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor) -{ - if (interface->ws_info) { - llc_neighbour_req_t neighbor_info; - neighbor_info.neighbor = neighbor; - neighbor_info.ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neighbor->index); - ws_bootstrap_primary_parent_set(interface, &neighbor_info, WS_PARENT_HARD_SYNCH); - uint8_t link_local_address[16]; - ws_bootsrap_create_ll_address(link_local_address, neighbor->mac64); - dhcp_client_server_address_update(interface->id, NULL, link_local_address); - - ws_bootstrap_secondary_parent_update(interface); - } -} - -void ws_bootstrap_secondary_parent_update(protocol_interface_info_entry_t *interface) -{ - if (interface->ws_info) { - ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { - if (!addr_is_ipv6_link_local(address->address)) { - ws_address_parent_update(interface); - } - } - } + ws_bootstrap_test_procedure_trigger_timer(cur, seconds); } int ws_bootstrap_stack_info_get(protocol_interface_info_entry_t *cur, struct ws_stack_info *info_ptr) @@ -4206,7 +2496,7 @@ int ws_bootstrap_stack_info_get(protocol_interface_info_entry_t *cur, struct ws_ if (mac_parent) { ws_neighbour = ws_neighbor_class_entry_get(&cur->ws_info->neighbor_storage, mac_parent->index); - ws_bootsrap_create_ll_address(info_ptr->parent, mac_parent->mac64); + ws_common_create_ll_address(info_ptr->parent, mac_parent->mac64); } if (ws_neighbour) { info_ptr->rsl_in = ws_neighbor_class_rsl_in_get(ws_neighbour); @@ -4268,7 +2558,7 @@ int ws_bootstrap_neighbor_info_get(protocol_interface_info_entry_t *cur, ws_neig if (neighbor_ptr[count].etx != 0xffff) { neighbor_ptr[count].etx = neighbor_ptr[count].etx >> 1; } - ws_bootsrap_create_ll_address(ll_address, mac_entry->mac64); + ws_common_create_ll_address(ll_address, mac_entry->mac64); memcpy(neighbor_ptr[count].link_local_address, ll_address, 16); if (rpl_control_is_dodag_parent_candidate(cur, ll_address, cur->ws_info->cfg->gen.rpl_parent_candidate_max)) { @@ -4344,9 +2634,7 @@ static uint16_t ws_bootstrap_packet_per_seconds(protocol_interface_info_entry_t return data_rate / 5; } - - -static void ws_bootstrap_packet_congestion_init(protocol_interface_info_entry_t *cur) +void ws_bootstrap_packet_congestion_init(protocol_interface_info_entry_t *cur) { random_early_detection_free(cur->random_early_detection); cur->random_early_detection = NULL; @@ -4376,4 +2664,232 @@ static void ws_bootstrap_packet_congestion_init(protocol_interface_info_entry_t } +static bool auto_test_proc_trg_enabled = false; + +int ws_bootstrap_test_procedure_trigger(protocol_interface_info_entry_t *cur, ws_bootsrap_procedure_t procedure) +{ + switch (procedure) { + case PROCEDURE_AUTO_ON: + tr_info("Trigger bootstrap test procedures automatically"); + auto_test_proc_trg_enabled = true; + return 0; + case PROCEDURE_AUTO_OFF: + tr_info("Disable automatic bootstrap test procedure triggering"); + auto_test_proc_trg_enabled = false; + return 0; + default: + break; + } + + if (!cur) { + return -1; + } + + switch (procedure) { + case PROCEDURE_DIS: + case PROCEDURE_DAO: + case PROCEDURE_PAS: + case PROCEDURE_PCS: + case PROCEDURE_EAPOL: + case PROCEDURE_RPL: + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + tr_info("Not allowed on Border Router"); + return -1; + } + break; + default: + break; + } + + if (cur->interface_mode != INTERFACE_UP) { + tr_info("Interface is not up"); + return -1; + } + + ws_bootstrap_event_test_procedure_trigger(cur, procedure); + return 0; +} + +void ws_bootstrap_test_procedure_trigger_exec(protocol_interface_info_entry_t *cur, ws_bootsrap_procedure_t procedure) +{ + switch (procedure) { + case PROCEDURE_DIS: + if (cur->nwk_bootstrap_state == ER_RPL_SCAN || ws_bootstrap_state_active(cur)) { + tr_info("trigger DODAG information object solicit"); + rpl_control_transmit_dis(cur->rpl_domain, cur, 0, 0, NULL, 0, ADDR_LINK_LOCAL_ALL_RPL_NODES); + } else { + tr_info("wrong state: DODAG information object solicit not triggered"); + } + break; + case PROCEDURE_DIO: + if (ws_bootstrap_state_active(cur)) { + tr_info("trigger DODAG information object"); + rpl_control_transmit_dio_trigger(cur, cur->rpl_domain); + } else { + tr_info("wrong state: DODAG information object not triggered"); + } + break; + case PROCEDURE_DAO: + // Can be triggered if in correct state and there is selected RPL parent + if ((cur->nwk_bootstrap_state == ER_RPL_SCAN || ws_bootstrap_state_active(cur)) + && rpl_control_parent_candidate_list_size(cur, true) > 0) { + tr_info("trigger Destination advertisement object"); + rpl_control_dao_timeout(cur->rpl_domain, 2); + } else { + tr_info("wrong state: Destination advertisement object not triggered"); + } + break; + case PROCEDURE_PAS: + case PROCEDURE_PAS_TRICKLE_INCON: + tr_info("trigger PAN advertisement Solicit"); + if (procedure != PROCEDURE_PAS_TRICKLE_INCON) { + tr_info("send PAN advertisement Solicit"); + ws_bootstrap_pan_advert_solicit(cur); + } + if (cur->ws_info->trickle_pas_running) { + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); + } + break; + case PROCEDURE_PA: + if (cur->ws_info->trickle_pa_running) { + tr_info("trigger PAN advertisement"); + ws_bootstrap_pan_advert(cur); + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); + } else { + tr_info("wrong state: PAN advertisement not triggered"); + } + break; + case PROCEDURE_PCS: + case PROCEDURE_PCS_TRICKLE_INCON: + if (cur->ws_info->trickle_pcs_running || ws_bootstrap_state_active(cur)) { + tr_info("trigger PAN configuration Solicit"); + if (procedure != PROCEDURE_PCS_TRICKLE_INCON) { + tr_info("send PAN configuration Solicit"); + ws_bootstrap_pan_config_solicit(cur); + } + if (cur->ws_info->trickle_pcs_running) { + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery); + } + } else { + tr_info("wrong state: PAN configuration Solicit not triggered"); + } + break; + case PROCEDURE_PC: + if (cur->ws_info->trickle_pc_running) { + tr_info("trigger PAN configuration"); + ws_bootstrap_pan_config(cur); + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); + } else { + tr_info("wrong state: PAN configuration not triggered"); + } + break; + case PROCEDURE_EAPOL: + if (cur->nwk_bootstrap_state == ER_ACTIVE_SCAN) { + tr_info("trigger EAPOL target selection"); + if (cur->bootsrap_state_machine_cnt > 3) { + cur->bootsrap_state_machine_cnt = 3; + } + } else { + tr_info("wrong state: EAPOL target selection not triggered"); + } + break; + case PROCEDURE_RPL: { + bool neigth_has_ext = false; + for (int n = 0; n < mac_neighbor_info(cur)->list_total_size; n++) { + mac_neighbor_table_entry_t *mac_entry = mac_neighbor_table_attribute_discover(mac_neighbor_info(cur), n); + if (mac_entry) { + uint16_t etx = ws_local_etx_read(cur, ADDR_802_15_4_LONG, mac_entry->mac64); + if (etx != 0xFFFF) { + neigth_has_ext = true; + } + } + } + /* If selecting RPL parent, there is some RPL candidates and neighbors with ETX try + the RPL parent selection procedure */ + if (cur->nwk_bootstrap_state == ER_RPL_SCAN && neigth_has_ext && + rpl_control_parent_candidate_list_size(cur, false) > 0) { + tr_info("trigger RPL parent selection"); + rpl_control_parent_selection_trigger(cur->rpl_domain); + } else { + tr_info("wrong state: RPL parent selection not triggered"); + } + break; + } + default: + break; + } +} + +static void ws_bootstrap_test_procedure_trigger_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) +{ + if (!auto_test_proc_trg_enabled) { + cur->ws_info->test_proc_trg.auto_trg_enabled = false; + return; + } + + cur->ws_info->test_proc_trg.auto_trg_enabled = true; + + if (cur->nwk_bootstrap_state == ER_ACTIVE_SCAN) { + if (cur->ws_info->trickle_pas_running) { + if (cur->ws_info->test_proc_trg.pas_trigger_timer > seconds) { + cur->ws_info->test_proc_trg.pas_trigger_timer -= seconds; + } else { + if (cur->ws_info->test_proc_trg.pas_trigger_count > 2) { + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_PAS_TRICKLE_INCON); + } else { + cur->ws_info->test_proc_trg.pas_trigger_count++; + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_PAS); + } + cur->ws_info->test_proc_trg.pas_trigger_timer = (cur->ws_info->trickle_params_pan_discovery.Imin / 10); + } + if (cur->ws_info->test_proc_trg.eapol_trigger_timer > seconds) { + cur->ws_info->test_proc_trg.eapol_trigger_timer -= seconds; + } else { + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_EAPOL); + cur->ws_info->test_proc_trg.eapol_trigger_timer = (cur->ws_info->trickle_params_pan_discovery.Imin / 10) / 2; + } + } + } else if (cur->nwk_bootstrap_state == ER_SCAN) { + if (cur->ws_info->trickle_pcs_running) { + if (cur->ws_info->test_proc_trg.pcs_trigger_timer > seconds) { + cur->ws_info->test_proc_trg.pcs_trigger_timer -= seconds; + } else { + if (cur->ws_info->test_proc_trg.pcs_trigger_count > 2) { + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_PCS_TRICKLE_INCON); + } else { + cur->ws_info->test_proc_trg.pcs_trigger_count++; + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_PCS); + } + cur->ws_info->test_proc_trg.pcs_trigger_timer = (cur->ws_info->trickle_params_pan_discovery.Imin / 10); + } + } + } else if (cur->nwk_bootstrap_state == ER_RPL_SCAN) { + if (cur->ws_info->test_proc_trg.dis_trigger_timer > seconds) { + cur->ws_info->test_proc_trg.dis_trigger_timer -= seconds; + } else { + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_DIS); + cur->ws_info->test_proc_trg.dis_trigger_timer_val *= 2; + if (cur->ws_info->test_proc_trg.dis_trigger_timer_val > (WS_RPL_DIS_INITIAL_TIMEOUT / 10) * 4) { + cur->ws_info->test_proc_trg.dis_trigger_timer_val = (WS_RPL_DIS_INITIAL_TIMEOUT / 10) * 4; + } + cur->ws_info->test_proc_trg.dis_trigger_timer = cur->ws_info->test_proc_trg.dis_trigger_timer_val; + } + if (cur->ws_info->test_proc_trg.rpl_trigger_timer > seconds) { + cur->ws_info->test_proc_trg.rpl_trigger_timer -= seconds; + } else { + ws_bootstrap_test_procedure_trigger_exec(cur, PROCEDURE_RPL); + cur->ws_info->test_proc_trg.rpl_trigger_timer_val *= 2; + if (cur->ws_info->test_proc_trg.rpl_trigger_timer_val > (WS_RPL_DIS_INITIAL_TIMEOUT / 10) * 2) { + cur->ws_info->test_proc_trg.rpl_trigger_timer_val = (WS_RPL_DIS_INITIAL_TIMEOUT / 10) * 2; + } + cur->ws_info->test_proc_trg.rpl_trigger_timer = cur->ws_info->test_proc_trg.rpl_trigger_timer_val; + } + } else { + cur->ws_info->test_proc_trg.dis_trigger_timer_val = (WS_RPL_DIS_INITIAL_TIMEOUT / 10) / 2; + cur->ws_info->test_proc_trg.rpl_trigger_timer_val = (WS_RPL_DIS_INITIAL_TIMEOUT / 10) / 2; + cur->ws_info->test_proc_trg.pas_trigger_count = 0; + cur->ws_info->test_proc_trg.pcs_trigger_count = 0; + } +} + #endif //HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h index 1d41c80a75e..b114ee91467 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.h @@ -18,7 +18,6 @@ #ifndef WS_BOOTSTRAP_H_ #define WS_BOOTSTRAP_H_ - typedef enum { WS_INIT_EVENT = 0, /**< tasklet initializion event*/ WS_DISCOVERY_START, /**< discovery start*/ @@ -26,66 +25,83 @@ typedef enum { WS_OPERATION_START, /**< active operation start*/ WS_ROUTING_READY, /**< RPL routing connected to BR*/ WS_FAST_DISCONNECT, /**< Do fast timeout after Border router timeout*/ - WS_NORMAL_DISCONNECT /**< Border have been rebooted so Slow poison Process*/ + WS_NORMAL_DISCONNECT, /**< Border have been rebooted so Slow poison Process*/ + WS_TEST_PROC_TRIGGER /**< Trigger test procedure */ } ws_bootsrap_event_type_e; +/* Bootstrap internal test procedures, these must match to ws_test_proc_t + on net_ws_test_ext.h */ +typedef enum { + PROCEDURE_DIS, + PROCEDURE_DIO, + PROCEDURE_DAO, + + PROCEDURE_PAS, + PROCEDURE_PA, + PROCEDURE_PCS, + PROCEDURE_PC, + + PROCEDURE_EAPOL, + PROCEDURE_RPL, + PROCEDURE_AUTO_ON, + PROCEDURE_AUTO_OFF, + + /* Above must match to ws_test_proc_t */ + + PROCEDURE_PAS_TRICKLE_INCON, + PROCEDURE_PCS_TRICKLE_INCON + +} ws_bootsrap_procedure_t; + +typedef enum { + WS_PARENT_SOFT_SYNCH = 0, /**< let FHSS make decision if synchronization is needed*/ + WS_PARENT_HARD_SYNCH, /**< Synch FHSS with latest synch information*/ + WS_EAPOL_PARENT_SYNCH, /**< Broadcast synch with EAPOL parent*/ +} ws_parent_synch_e; + #ifdef HAVE_WS +//#include "6LoWPAN/ws/ws_llc.h" +#include "6LoWPAN/ws/ws_common_defines.h" + +struct rpl_instance; struct llc_neighbour_req; -struct ws_us_ie; -struct ws_bs_ie; -struct ws_neighbor_class_entry; struct ws_stack_info; struct ws_neighbour_info; +struct mcps_data_ie_list; +struct mcps_data_ind_s; -int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode); +extern uint16_t test_pan_version; -void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur); +int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode); int ws_bootstrap_restart(int8_t interface_id); int ws_bootstrap_restart_delayed(int8_t interface_id); -int ws_bootstrap_set_rf_config(protocol_interface_info_entry_t *cur, phy_rf_channel_configuration_s rf_configs); - int ws_bootstrap_neighbor_remove(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); int ws_bootstrap_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); -/*State machine transactions*/ -void ws_bootstrap_event_discovery_start(protocol_interface_info_entry_t *cur); - -void ws_bootstrap_event_configuration_start(protocol_interface_info_entry_t *cur); - -void ws_bootstrap_event_authentication_start(protocol_interface_info_entry_t *cur); - -void ws_bootstrap_event_operation_start(protocol_interface_info_entry_t *cur); - -void ws_bootstrap_event_routing_ready(protocol_interface_info_entry_t *cur); - -void ws_bootstrap_event_disconnect(protocol_interface_info_entry_t *cur, ws_bootsrap_event_type_e event_type); - void ws_bootstrap_configuration_trickle_reset(protocol_interface_info_entry_t *cur); void ws_bootstrap_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); -void ws_bootstrap_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor); - -void ws_bootstrap_secondary_parent_update(protocol_interface_info_entry_t *interface); - void ws_nud_entry_remove_active(protocol_interface_info_entry_t *cur, void *neighbor); void ws_nud_active_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); -void ws_dhcp_client_address_request(protocol_interface_info_entry_t *cur, uint8_t *prefix, uint8_t *parent_link_local); +void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); + +void ws_bootstrap_ll_address_validate(struct protocol_interface_info_entry *cur); -void ws_dhcp_client_address_delete(protocol_interface_info_entry_t *cur, uint8_t *prefix); +uint16_t ws_local_etx_read(protocol_interface_info_entry_t *interface, addrtype_t addr_type, const uint8_t *mac_adddress); -bool ws_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +bool ws_bootstrap_nd_ns_transmit(protocol_interface_info_entry_t *cur, ipv6_neighbour_t *entry, bool unicast, uint8_t seq); -void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); +void ws_bootstrap_memory_configuration(); bool ws_bootstrap_validate_channel_plan(struct ws_us_ie *ws_us, struct protocol_interface_info_entry *cur); @@ -99,18 +115,90 @@ int ws_bootstrap_neighbor_info_get(protocol_interface_info_entry_t *cur, struct void ws_bootstrap_mac_neighbor_short_time_set(struct protocol_interface_info_entry *interface, const uint8_t *src64, uint32_t valid_time); +int ws_bootstrap_test_procedure_trigger(protocol_interface_info_entry_t *cur, ws_bootsrap_procedure_t procedure); + +/* + * Functions shared with different bootstrap modes + */ + +bool ws_bootstrap_network_name_matches(const struct mcps_data_ie_list *ie_ext, const char *network_name_ptr); + +/*State machine transactions*/ +void ws_bootstrap_event_discovery_start(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_event_configuration_start(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_event_authentication_start(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_event_operation_start(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_event_routing_ready(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_event_disconnect(protocol_interface_info_entry_t *cur, ws_bootsrap_event_type_e event_type); + +void ws_bootstrap_test_procedure_trigger_exec(protocol_interface_info_entry_t *cur, ws_bootsrap_procedure_t procedure); + +void ws_bootstrap_network_down(protocol_interface_info_entry_t *cur); + +// Bootstrap functions +void ws_bootstrap_start_authentication(protocol_interface_info_entry_t *cur); + + +// Bootstrap state machine state Functions +bool ws_bootstrap_state_discovery(struct protocol_interface_info_entry *cur); +bool ws_bootstrap_state_authenticate(struct protocol_interface_info_entry *cur); +bool ws_bootstrap_state_configure(struct protocol_interface_info_entry *cur); +bool ws_bootstrap_state_wait_rpl(struct protocol_interface_info_entry *cur); +bool ws_bootstrap_state_active(struct protocol_interface_info_entry *cur); +void ws_bootstrap_state_disconnect(protocol_interface_info_entry_t *cur, ws_bootsrap_event_type_e event_type); +void ws_bootstrap_state_change(protocol_interface_info_entry_t *cur, icmp_state_t nwk_bootstrap_state); + +void ws_bootstrap_candidate_list_clean(struct protocol_interface_info_entry *cur, uint8_t pan_max, uint32_t current_time, uint16_t pan_id); +void ws_bootstrap_candidate_parent_store(parent_info_t *parent, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us, ws_pan_information_t *pan_information); +void ws_bootstrap_candidate_table_reset(protocol_interface_info_entry_t *cur); +parent_info_t *ws_bootstrap_candidate_parent_get(struct protocol_interface_info_entry *cur, const uint8_t *addr, bool create); +void ws_bootstrap_candidate_parent_sort(struct protocol_interface_info_entry *cur, parent_info_t *new_entry); +parent_info_t *ws_bootstrap_candidate_parent_get_best(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_primary_parent_set(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info, ws_parent_synch_e synch_req); +bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, struct llc_neighbour_req *neighbor_buffer, bool request_new); +void ws_bootstrap_neighbor_list_clean(struct protocol_interface_info_entry *interface); +int8_t ws_bootstrap_neighbor_set(protocol_interface_info_entry_t *cur, parent_info_t *parent_ptr, bool clear_list); +void ws_address_reregister_trig(struct protocol_interface_info_entry *interface); +void ws_nud_table_reset(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_configure_csma_ca_backoffs(protocol_interface_info_entry_t *cur, uint8_t max_backoffs, uint8_t min_be, uint8_t max_be); +void ws_bootstrap_fhss_configure_channel_masks(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration); +int8_t ws_bootstrap_fhss_initialize(protocol_interface_info_entry_t *cur); +int8_t ws_bootstrap_fhss_set_defaults(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration); +void ws_bootstrap_fhss_activate(protocol_interface_info_entry_t *cur); +uint16_t ws_bootstrap_randomize_fixed_channel(uint16_t configured_fixed_channel, uint8_t number_of_channels, uint32_t *channel_mask); +int ws_bootstrap_set_domain_rf_config(protocol_interface_info_entry_t *cur); +void ws_bootstrap_configure_max_retries(protocol_interface_info_entry_t *cur, uint8_t max_mac_retries); +void ws_bootstrap_configure_data_request_restart(protocol_interface_info_entry_t *cur, uint8_t cca_failure_restart_max, uint8_t tx_failure_restart_max, uint16_t blacklist_min_ms, uint16_t blacklist_max_ms); + + +void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry *cur, const fhss_ws_configuration_t *fhss_configuration); + +void ws_bootstrap_ip_stack_reset(protocol_interface_info_entry_t *cur); +void ws_bootstrap_ip_stack_activate(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_packet_congestion_init(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_asynch_trickle_stop(protocol_interface_info_entry_t *cur); +void ws_bootstrap_advertise_start(protocol_interface_info_entry_t *cur); + +void ws_bootstrap_network_start(protocol_interface_info_entry_t *cur); #else #define ws_bootstrap_init(interface_id, bootstrap_mode) (-1) -#define ws_bootstrap_state_machine(cur) #define ws_bootstrap_restart(cur) #define ws_bootstrap_neighbor_remove(cur, ll_address) #define ws_bootstrap_aro_failure(cur, ll_address) #define ws_bootstrap_neighbor_set_stable(interface, src64) -#define ws_bootstrap_primary_parent_update(interface, neighbor) -#define ws_bootstrap_secondary_parent_update(interface) #define ws_bootstrap_stack_info_get(cur, info_ptr) #define ws_bootstrap_neighbor_info_get(cur, neighbor_ptr, count) +#define ws_bootstrap_test_procedure_trigger(cur, procedure); #endif //HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.c new file mode 100644 index 00000000000..34139e44a4e --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.c @@ -0,0 +1,600 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "nsconfig.h" +#if defined(HAVE_WS) && defined(HAVE_WS_BORDER_ROUTER) +#include "ns_types.h" +#include "ns_trace.h" +#include "nsdynmemLIB.h" +#include "net_interface.h" +#include "eventOS_event.h" +#include "randLIB.h" +#include "common_functions.h" +#include "mac_common_defines.h" +#include "sw_mac.h" +#include "ccmLIB.h" +#include "Core/include/ns_monitor.h" +#include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan_interface.h" +#include "ipv6_stack/protocol_ipv6.h" +#include "ipv6_stack/ipv6_routing_table.h" +#include "6LoWPAN/MAC/mac_helper.h" +#include "6LoWPAN/MAC/mac_data_poll.h" +#include "6LoWPAN/MAC/mpx_api.h" +#include "6LoWPAN/MAC/mac_ie_lib.h" +#include "MPL/mpl.h" +#include "RPL/rpl_protocol.h" +#include "RPL/rpl_control.h" +#include "RPL/rpl_data.h" +#include "RPL/rpl_policy.h" +#include "Common_Protocols/icmpv6.h" +#include "Common_Protocols/icmpv6_radv.h" +#include "Common_Protocols/ipv6_constants.h" +#include "Common_Protocols/ip.h" +#include "Service_Libs/Trickle/trickle.h" +#include "Service_Libs/fhss/channel_list.h" +#include "Service_Libs/utils/ns_time.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_common.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" +#include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bbr_api_internal.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_llc.h" +#include "6LoWPAN/ws/ws_neighbor_class.h" +#include "6LoWPAN/ws/ws_ie_lib.h" +#include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/lowpan_adaptation_interface.h" +#include "Service_Libs/etx/etx.h" +#include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" +#include "Service_Libs/nd_proxy/nd_proxy.h" +#include "Service_Libs/blacklist/blacklist.h" +#include "platform/topo_trace.h" +#include "dhcp_service_api.h" +#include "libDHCPv6/libDHCPv6.h" +#include "libDHCPv6/libDHCPv6_vendordata.h" +#include "DHCPv6_client/dhcpv6_client_api.h" +#include "ws_management_api.h" +#include "net_rpl.h" +#include "mac_api.h" +#include "6LoWPAN/ws/ws_pae_controller.h" +#include "6LoWPAN/ws/ws_eapol_pdu.h" +#include "6LoWPAN/ws/ws_eapol_auth_relay.h" +#include "6LoWPAN/ws/ws_eapol_relay.h" +#include "libNET/src/net_dns_internal.h" +#include "Service_Libs/random_early_detection/random_early_detection_api.h" + + +#define TRACE_GROUP "wsbs" + +static int8_t ws_bootstrap_6lbr_fhss_configure(protocol_interface_info_entry_t *cur) +{ + // Read configuration of existing FHSS and start using the default values for any network + fhss_ws_configuration_t fhss_configuration = ws_common_get_current_fhss_configuration(cur); + //GET BSI from BBR module + fhss_configuration.bsi = ws_bbr_bsi_generate(cur); + ws_bootstrap_fhss_configure_channel_masks(cur, &fhss_configuration); + // Randomize fixed channels. Only used if channel plan is fixed. + cur->ws_info->cfg->fhss.fhss_uc_fixed_channel = ws_bootstrap_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); + cur->ws_info->cfg->fhss.fhss_bc_fixed_channel = ws_bootstrap_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); + ws_bootstrap_fhss_set_defaults(cur, &fhss_configuration); + ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); + ws_bootstrap_llc_hopping_update(cur, &fhss_configuration); + + return 0; +} + +static int8_t ws_bootstrap_6lbr_backbone_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address) +{ + (void) interface_ptr; + (void) address; + + if (ws_bbr_backbone_address_get(address)) { + return 0; + } + + return -1; +} + +static void ws_bootstrap_6lbr_eapol_congestion_init(protocol_interface_info_entry_t *cur) +{ + random_early_detection_free(cur->llc_random_early_detection); + cur->llc_random_early_detection = NULL; + + if (cur->llc_random_early_detection == NULL) { + cur->llc_random_early_detection = random_early_detection_create( + cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_min, + cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_max, + 100, RED_AVERAGE_WEIGHT_EIGHTH); + } + + random_early_detection_free(cur->llc_eapol_random_early_detection); + cur->llc_eapol_random_early_detection = NULL; + + if (cur->llc_eapol_random_early_detection == NULL) { + cur->llc_eapol_random_early_detection = random_early_detection_create( + cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_min, + cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_max, + 100, RED_AVERAGE_WEIGHT_EIGHTH); + } +} + +static void ws_bootstrap_6lbr_pan_config_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +{ + ws_bs_ie_t ws_bs_ie; + ws_bt_ie_t ws_bt_ie; + llc_neighbour_req_t neighbor_info; + + if (data->SrcPANId != cur->ws_info->network_pan_id) { + return; + } + if (!ws_wh_bt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_bt_ie)) { + tr_warn("BT-IE"); + return; + } + + if (!ws_wp_nested_bs_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_bs_ie)) { + // Corrupted + tr_error("No broadcast schedule"); + return; + } + + //If we are border router or learned configuration we only update already learned neighbours. + + if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { + //Update Neighbor Broadcast and Unicast Parameters + ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp, (uint8_t *) data->SrcAddr); + ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us, &cur->ws_info->hopping_schdule); + ws_neighbor_class_neighbor_broadcast_time_info_update(neighbor_info.ws_neighbor, &ws_bt_ie, data->timestamp); + ws_neighbor_class_neighbor_broadcast_schedule_set(neighbor_info.ws_neighbor, &ws_bs_ie); + } +} + +static void ws_bootstrap_6lbr_pan_config_solicit_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +{ + llc_neighbour_req_t neighbor_info; + + if (data->SrcPANId != cur->ws_info->network_pan_id) { + return; + } + + if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { + ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp, (uint8_t *) data->SrcAddr); + ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us, &cur->ws_info->hopping_schdule); + } +} + +void ws_bootstrap_6lbr_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type) +{ + // Store weakest heard packet RSSI + if (cur->ws_info->weakest_received_rssi > data->signal_dbm) { + cur->ws_info->weakest_received_rssi = data->signal_dbm; + } + + if (data->SrcAddrMode != MAC_ADDR_MODE_64_BIT) { + // Not from long address + return; + } + ws_stats_update(cur, STATS_WS_ASYNCH_RX, 1); + //Validate network name + switch (message_type) { + case WS_FT_PAN_ADVERT: + case WS_FT_PAN_ADVERT_SOL: + case WS_FT_PAN_CONF_SOL: + //Check Network Name + if (!ws_bootstrap_network_name_matches(ie_ext, cur->ws_info->cfg->gen.network_name)) { + // Not in our network + return; + } + break; + case WS_FT_PAN_CONF: + break; + default: + return; + } + //UTT-IE and US-IE are mandatory for all Asynch Messages + ws_utt_ie_t ws_utt; + if (!ws_wh_utt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_utt)) { + // Corrupted + return; + } + + ws_us_ie_t ws_us; + if (!ws_wp_nested_us_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_us)) { + // Corrupted + return; + } + + if (!ws_bootstrap_validate_channel_plan(&ws_us, cur) || + !ws_bootstrap_validate_channel_function(&ws_us, NULL)) { + return; + } + + //Handle Message's + switch (message_type) { + case WS_FT_PAN_ADVERT: + // Analyse Advertisement + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PA, 1); + tr_info("received ADVERT Src:%s panid:%x rssi:%d", trace_array(data->SrcAddr, 8), data->SrcPANId, data->signal_dbm); + // Border routers do not do any analysing on the Advertisements heard from others + // in future if we need PANID conflict detection we could use this + break; + case WS_FT_PAN_ADVERT_SOL: + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PAS, 1); + tr_info("received ADVERT SOL Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); + + break; + case WS_FT_PAN_CONF: + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PC, 1); + tr_info("received CONFIG Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); + ws_bootstrap_6lbr_pan_config_analyse(cur, data, ie_ext, &ws_utt, &ws_us); + break; + case WS_FT_PAN_CONF_SOL: + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PCS, 1); + tr_info("received CONFIG SOL Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); + ws_bootstrap_6lbr_pan_config_solicit_analyse(cur, data, &ws_utt, &ws_us); + default: + // Unknown message do not process + break; + } +} + +void ws_bootstrap_6lbr_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message) +{ + ws_stats_update(interface, STATS_WS_ASYNCH_TX, 1); + if (interface->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + if (asynch_message == WS_FT_PAN_CONF && interface->ws_info->pending_key_index_info.state == PENDING_KEY_INDEX_ACTIVATE) { + interface->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + tr_info("Activate new default key %u", interface->ws_info->pending_key_index_info.index + 1); + mac_helper_security_auto_request_key_index_set(interface, interface->ws_info->pending_key_index_info.index, interface->ws_info->pending_key_index_info.index + 1); + } + } +} + +bool ws_bootstrap_6lbr_eapol_relay_state_active(protocol_interface_info_entry_t *cur) +{ + (void) cur; + + return true; +} + +static void ws_bootstrap_6lbr_pan_version_increment(protocol_interface_info_entry_t *cur) +{ + (void)cur; + ws_bbr_pan_version_increase(cur); +} + +static void ws_bootstrap_6lbr_nw_info_updated(protocol_interface_info_entry_t *cur, uint16_t pan_id, uint16_t pan_version, char *network_name) +{ + /* For border router, the PAE controller reads PAN ID, PAN version and network name from storage. + * If they are set, takes them into use here. + */ + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + // Get network name + ws_gen_cfg_t gen_cfg; + if (ws_cfg_gen_get(&gen_cfg) < 0) { + return; + } + + // If PAN ID has not been set, set it + if (cur->ws_info->network_pan_id == 0xffff) { + cur->ws_info->network_pan_id = pan_id; + // Sets PAN version + cur->ws_info->pan_information.pan_version = pan_version; + cur->ws_info->pan_information.pan_version_set = true; + } + + // If network name has not been set, set it + if (strlen(gen_cfg.network_name) == 0) { + strncpy(gen_cfg.network_name, network_name, 32); + } + + // Stores the settings + ws_cfg_gen_set(cur, &gen_cfg, 0); + } +} + +static bool ws_bootstrap_6lbr_eapol_congestion_get(protocol_interface_info_entry_t *cur, uint16_t active_supp) +{ + if (cur == NULL || cur->random_early_detection == NULL || cur->llc_random_early_detection == NULL || cur->llc_eapol_random_early_detection == NULL) { + return false; + } + + bool return_value = false; + static struct red_info_s *red_info = NULL; + uint16_t adaptation_average = 0; + uint16_t llc_average = 0; + uint16_t llc_eapol_average = 0; + uint16_t average_sum = 0; + uint8_t active_max = 0; + + //TODO implement API for HEAP info request + uint32_t heap_size; + const mem_stat_t *mem_stats = ns_dyn_mem_get_mem_stat(); + if (mem_stats) { + heap_size = mem_stats->heap_sector_size; + } else { + heap_size = 0; + } + + /* + * For different memory sizes the max simultaneous authentications will be + * 32k: (32k / 50k) * 2 + 1 = 1 + * 65k: (65k / 50k) * 2 + 1 = 3 + * 250k: (250k / 50k) * 2 + 1 = 11 + * 1000k: (1000k / 50k) * 2 + 1 = 41 + * 2000k: (2000k / 50k) * 2 + 1 = 50 (upper limit) + */ + active_max = (heap_size / 50000) * 2 + 1; + if (active_max > 50) { + active_max = 50; + } + + // Read the values for adaptation and LLC queues + adaptation_average = random_early_detetction_aq_read(cur->random_early_detection); + llc_average = random_early_detetction_aq_read(cur->llc_random_early_detection); + llc_eapol_average = random_early_detetction_aq_read(cur->llc_eapol_random_early_detection); + // Calculate combined average + average_sum = adaptation_average + llc_average + llc_eapol_average; + + // Maximum for active supplicants based on memory reached, fail + if (active_supp >= active_max) { + return_value = true; + goto congestion_get_end; + } + + // Always allow at least five negotiations (if memory does not limit) + if (active_supp < 5) { + goto congestion_get_end; + } + + if (red_info == NULL) { + red_info = random_early_detection_create( + cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_min, + cur->ws_info->cfg->sec_prot.max_simult_sec_neg_tx_queue_max, + 100, RED_AVERAGE_WEIGHT_DISABLED); + } + if (red_info == NULL) { + goto congestion_get_end; + } + + // Check drop probability + average_sum = random_early_detetction_aq_calc(red_info, average_sum); + return_value = random_early_detection_congestion_check(red_info); + +congestion_get_end: + tr_info("Active supplicant limit, active: %i max: %i summed averageQ: %i adapt averageQ: %i LLC averageQ: %i LLC EAPOL averageQ: %i drop: %s", active_supp, active_max, average_sum, adaptation_average, llc_average, llc_eapol_average, return_value ? "T" : "F"); + + return return_value; +} + +void ws_bootstrap_6lbr_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event) +{ + ws_bootsrap_event_type_e event_type; + event_type = (ws_bootsrap_event_type_e)event->event_type; + + switch (event_type) { + case WS_INIT_EVENT: + tr_debug("tasklet init"); + break; + case WS_DISCOVERY_START: + tr_info("Discovery start"); + protocol_mac_reset(cur); + ws_llc_reset(cur); + lowpan_adaptation_interface_reset(cur->id); + //Clear Pending Key Index State + cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + cur->mac_parameters->mac_default_key_index = 0; + + ipv6_destination_cache_clean(cur->id); + + // Clear parent blacklist + blacklist_clear(); + + // All trickle timers stopped to allow entry from any state + ws_bootstrap_asynch_trickle_stop(cur); + //Init Packet congestion + ws_bootstrap_packet_congestion_init(cur); + + tr_info("Border router start network"); + + + if (!ws_bbr_ready_to_start(cur)) { + // Wi-SUN not started yet we wait for Border router permission + ws_bootstrap_state_change(cur, ER_WAIT_RESTART); + cur->nwk_nd_re_scan_count = randLIB_get_random_in_range(40, 100); + return; + } + // Clear Old information from stack + cur->ws_info->network_pan_id = 0xffff; + cur->ws_info->pan_information.pan_version_set = false; + ws_nud_table_reset(cur); + ws_bootstrap_neighbor_list_clean(cur); + ws_bootstrap_ip_stack_reset(cur); + ws_pae_controller_auth_init(cur); + + uint16_t pan_id = ws_bbr_pan_id_get(cur); + if (pan_id != 0xffff) { + cur->ws_info->network_pan_id = pan_id; + } else { + if (cur->ws_info->network_pan_id == 0xffff) { + cur->ws_info->network_pan_id = randLIB_get_random_in_range(0, 0xfffd); + } + } + if (!cur->ws_info->pan_information.pan_version_set) { + cur->ws_info->pan_information.pan_version = randLIB_get_random_in_range(0, 0xffff); + cur->ws_info->pan_information.pan_version_set = true; + } + cur->ws_info->pan_information.pan_size = 0; + cur->ws_info->pan_information.routing_cost = 0; + cur->ws_info->pan_information.rpl_routing_method = true; + cur->ws_info->pan_information.use_parent_bs = true; + cur->ws_info->pan_information.version = WS_FAN_VERSION_1_0; + // initialize for FAN 1.1 defaults + if (ws_version_1_1(cur)) { + cur->ws_info->pan_information.version = WS_FAN_VERSION_1_1; +#ifdef HAVE_WS_VERSION_1_1 + if (!cur->ws_info->lfngtk.lfn_version_learned) { + //Randomize LFN version + cur->ws_info->lfngtk.lfn_version = randLIB_get_random_in_range(0, 0xffff); + cur->ws_info->lfngtk.lfn_version_learned = true; + } +#endif + } + + uint8_t *gtkhash = ws_pae_controller_gtk_hash_ptr_get(cur); + ws_llc_set_gtkhash(cur, gtkhash); + ws_bbr_pan_version_increase(cur); + + // Set default parameters for FHSS when starting a discovery + ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); + ws_bootstrap_6lbr_fhss_configure(cur); + ws_bootstrap_set_domain_rf_config(cur); + ws_bootstrap_fhss_activate(cur); + ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, 0); + + uint8_t ll_addr[16]; + addr_interface_get_ll_address(cur, ll_addr, 1); + + //SET EAPOL authenticator EUI64 + ws_pae_controller_border_router_addr_write(cur, cur->mac); + + // Set EAPOL relay to port 10255 and authenticator relay to 10253 (and to own ll address) + ws_eapol_relay_start(cur, BR_EAPOL_RELAY_SOCKET_PORT, ll_addr, EAPOL_RELAY_SOCKET_PORT); + + // Set authenticator relay to port 10253 and PAE to 10254 (and to own ll address) + ws_eapol_auth_relay_start(cur, EAPOL_RELAY_SOCKET_PORT, ll_addr, PAE_AUTH_SOCKET_PORT); + + // Set PAN ID and network name to controller + ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->pan_information.pan_version, cur->ws_info->cfg->gen.network_name); + + // Set information callbacks (backbone IP address get callback, network information, congestion) + ws_pae_controller_information_cb_register(cur, ws_bootstrap_6lbr_backbone_ip_addr_get, &ws_bootstrap_6lbr_nw_info_updated, &ws_bootstrap_6lbr_eapol_congestion_get); + + // Set PAN version control callbacks + ws_pae_controller_pan_version_cb_register(cur, &ws_bootstrap_6lbr_pan_version_increment); + + // Set PAE port to 10254 and authenticator relay to 10253 (and to own ll address) + ws_pae_controller_authenticator_start(cur, PAE_AUTH_SOCKET_PORT, ll_addr, EAPOL_RELAY_SOCKET_PORT); + + // Initialize eapol congestion tracking + ws_bootstrap_6lbr_eapol_congestion_init(cur); + + // Set retry configuration for bootstrap ready state + ws_bootstrap_configure_max_retries(cur, WS_MAX_FRAME_RETRIES); + + // Set TX failure request restart configuration + ws_bootstrap_configure_data_request_restart(cur, WS_CCA_REQUEST_RESTART_MAX, WS_TX_REQUEST_RESTART_MAX, WS_REQUEST_RESTART_BLACKLIST_MIN, WS_REQUEST_RESTART_BLACKLIST_MAX); + + // Set CSMA-CA backoff configuration + ws_bootstrap_configure_csma_ca_backoffs(cur, WS_MAX_CSMA_BACKOFFS, WS_MAC_MIN_BE, WS_MAC_MAX_BE); + + ws_bootstrap_event_operation_start(cur); + break; + + case WS_CONFIGURATION_START: + tr_info("6LBR Configuration start"); + break; + case WS_OPERATION_START: + tr_info("operation start"); + // Advertisements stopped during the RPL scan + ws_bootstrap_asynch_trickle_stop(cur); + // Activate RPL + // Activate IPv6 stack + ws_bootstrap_ip_stack_activate(cur); + ws_bootstrap_ffn_rpl_configure(cur); + ws_bootstrap_network_start(cur); + // Wait for RPL start + ws_bootstrap_event_routing_ready(cur); + break; + case WS_ROUTING_READY: + tr_info("Routing ready"); + // stopped all to make sure we can enter here from any state + ws_bootstrap_asynch_trickle_stop(cur); + + // Indicate PAE controller that bootstrap is ready + ws_pae_controller_bootstrap_done(cur); + + ws_bootstrap_advertise_start(cur); + ws_bootstrap_state_change(cur, ER_BOOTSRAP_DONE); + break; + case WS_FAST_DISCONNECT: + ws_bootstrap_state_disconnect(cur, WS_FAST_DISCONNECT); + break; + case WS_NORMAL_DISCONNECT: + ws_bootstrap_state_disconnect(cur, WS_NORMAL_DISCONNECT); + break; + + case WS_TEST_PROC_TRIGGER: + ws_bootstrap_test_procedure_trigger_exec(cur, (ws_bootsrap_procedure_t) event->data_ptr); + break; + + default: + tr_err("Invalid event received"); + break; + } +} + +void ws_bootstrap_6lbr_state_machine(protocol_interface_info_entry_t *cur) +{ + + switch (cur->nwk_bootstrap_state) { + case ER_WAIT_RESTART: + tr_debug("WS SM:Wait for startup"); + ws_bootstrap_event_discovery_start(cur); + break; + case ER_ACTIVE_SCAN: + tr_debug("WS SM:Active Scan"); + break; + case ER_SCAN: + tr_debug("WS SM:configuration Scan"); + break; + case ER_PANA_AUTH: + tr_info("authentication start"); + break; + case ER_RPL_SCAN: + tr_debug("WS SM:Wait RPL to contact DODAG root"); + break; + case ER_BOOTSRAP_DONE: + tr_info("WS SM:Bootstrap Done"); + // Bootstrap_done event to application + nwk_bootsrap_state_update(ARM_NWK_BOOTSTRAP_READY, cur); + break; + case ER_RPL_NETWORK_LEAVING: + tr_debug("WS SM:RPL Leaving ready trigger discovery"); + ws_bootstrap_event_discovery_start(cur); + break; + default: + tr_warn("WS SM:Invalid state %d", cur->nwk_bootstrap_state); + } +} + +void ws_bootstrap_6lbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) +{ + (void)cur; + (void)seconds; +} + + +#endif //HAVE_WS_BORDER_ROUTER && HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h new file mode 100644 index 00000000000..716454484e3 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lbr.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_BOOTSTRAP_6LBR_H_ +#define WS_BOOTSTRAP_6LBR_H_ + +#if defined(HAVE_WS) && defined(HAVE_WS_BORDER_ROUTER) + +void ws_bootstrap_6lbr_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); +void ws_bootstrap_6lbr_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); +bool ws_bootstrap_6lbr_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6lbr_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); +void ws_bootstrap_6lbr_state_machine(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6lbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); + +#define wisun_mode_border_router(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) + +#else + +#define ws_bootstrap_6lbr_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) +#define ws_bootstrap_6lbr_asynch_confirm(interface, asynch_message) ((void) 0) +#define ws_bootstrap_6lbr_eapol_relay_state_active(cur) false +#define ws_bootstrap_6lbr_event_handler(cur, event) ((void) 0) +#define ws_bootstrap_6lbr_state_machine(cur) ((void) 0) +#define ws_bootstrap_6lbr_seconds_timer(cur, seconds) ((void) 0) + +#define wisun_mode_border_router(cur) (false) + +#endif //HAVE_WS + +#endif /* WS_BOOTSTRAP_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.c new file mode 100644 index 00000000000..824cb19646c --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "nsconfig.h" +#if defined(HAVE_WS) && defined(HAVE_WS_HOST) +#include "ns_types.h" +#include "ns_trace.h" +#include "nsdynmemLIB.h" +#include "net_interface.h" +#include "eventOS_event.h" +#include "randLIB.h" +#include "common_functions.h" +#include "mac_common_defines.h" +#include "sw_mac.h" +#include "ccmLIB.h" +#include "Core/include/ns_monitor.h" +#include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan_interface.h" +#include "ipv6_stack/protocol_ipv6.h" +#include "ipv6_stack/ipv6_routing_table.h" +#include "6LoWPAN/MAC/mac_helper.h" +#include "6LoWPAN/MAC/mac_data_poll.h" +#include "6LoWPAN/MAC/mpx_api.h" +#include "6LoWPAN/MAC/mac_ie_lib.h" +#include "MPL/mpl.h" +#include "RPL/rpl_protocol.h" +#include "RPL/rpl_control.h" +#include "RPL/rpl_data.h" +#include "RPL/rpl_policy.h" +#include "Common_Protocols/icmpv6.h" +#include "Common_Protocols/icmpv6_radv.h" +#include "Common_Protocols/ipv6_constants.h" +#include "Common_Protocols/ip.h" +#include "Service_Libs/Trickle/trickle.h" +#include "Service_Libs/fhss/channel_list.h" +#include "Service_Libs/utils/ns_time.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_common.h" +#include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bbr_api_internal.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_llc.h" +#include "6LoWPAN/ws/ws_neighbor_class.h" +#include "6LoWPAN/ws/ws_ie_lib.h" +#include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/lowpan_adaptation_interface.h" +#include "Service_Libs/etx/etx.h" +#include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" +#include "Service_Libs/nd_proxy/nd_proxy.h" +#include "Service_Libs/blacklist/blacklist.h" +#include "platform/topo_trace.h" +#include "dhcp_service_api.h" +#include "libDHCPv6/libDHCPv6.h" +#include "libDHCPv6/libDHCPv6_vendordata.h" +#include "DHCPv6_client/dhcpv6_client_api.h" +#include "ws_management_api.h" +#include "net_rpl.h" +#include "mac_api.h" +#include "6LoWPAN/ws/ws_pae_controller.h" +#include "6LoWPAN/ws/ws_eapol_pdu.h" +#include "6LoWPAN/ws/ws_eapol_auth_relay.h" +#include "6LoWPAN/ws/ws_eapol_relay.h" +#include "libNET/src/net_dns_internal.h" +#include "Service_Libs/random_early_detection/random_early_detection_api.h" + +#define TRACE_GROUP "wsbs" + + +void ws_bootstrap_6ln_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type) +{ + (void)ie_ext; + // Store weakest heard packet RSSI + if (cur->ws_info->weakest_received_rssi > data->signal_dbm) { + cur->ws_info->weakest_received_rssi = data->signal_dbm; + } + + if (data->SrcAddrMode != MAC_ADDR_MODE_64_BIT) { + // Not from long address + return; + } + ws_stats_update(cur, STATS_WS_ASYNCH_RX, 1); + tr_warn("Wi-SUN LFN Mode received message id: %x", message_type); +} + +void ws_bootstrap_6ln_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message) +{ + (void)asynch_message; + ws_stats_update(interface, STATS_WS_ASYNCH_TX, 1); +} + +bool ws_bootstrap_6ln_eapol_relay_state_active(protocol_interface_info_entry_t *cur) +{ + (void) cur; + + return false; +} + +void ws_bootstrap_6ln_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event) +{ + (void)cur; + ws_bootsrap_event_type_e event_type; + event_type = (ws_bootsrap_event_type_e)event->event_type; + + switch (event_type) { + case WS_INIT_EVENT: + tr_debug("tasklet init"); + break; + /* case WS_DISCOVERY_START: + case WS_CONFIGURATION_START: + case WS_OPERATION_START: + case WS_ROUTING_READY: + case WS_FAST_DISCONNECT: + case WS_NORMAL_DISCONNECT: + */ + default: + tr_err("Invalid event received"); + break; + } +} + +void ws_bootstrap_6ln_state_machine(protocol_interface_info_entry_t *cur) +{ + + switch (cur->nwk_bootstrap_state) { + case ER_WAIT_RESTART: + tr_debug("WS SM:Wait for startup"); + break; + case ER_ACTIVE_SCAN: + tr_debug("WS SM:Active Scan"); + break; + case ER_SCAN: + tr_debug("WS SM:configuration Scan"); + break; + case ER_PANA_AUTH: + tr_info("authentication start"); + // Advertisements stopped during the EAPOL + break; + case ER_RPL_SCAN: + tr_debug("WS SM:Wait RPL to contact DODAG root"); + break; + case ER_BOOTSRAP_DONE: + tr_info("WS SM:Bootstrap Done"); + // Bootstrap_done event to application + break; + case ER_RPL_NETWORK_LEAVING: + tr_debug("WS SM:RPL Leaving ready trigger discovery"); + break; + default: + tr_warn("WS SM:Invalid state %d", cur->nwk_bootstrap_state); + } +} + +void ws_bootstrap_6ln_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) +{ + (void)cur; + (void)seconds; +} + +int8_t ws_bootstrap_6ln_up(protocol_interface_info_entry_t *cur) +{ + int8_t ret_val = -1; + + if (!cur) { + return -1; + } + + if ((cur->configure_flags & INTERFACE_SETUP_MASK) != INTERFACE_SETUP_READY) { + tr_error("Interface not yet fully configured"); + return -2; + } + if (ws_bootstrap_fhss_initialize(cur) != 0) { + tr_error("fhss initialization failed"); + return -3; + } + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //BBR init like NVM read + ws_bbr_init(cur); + } + // Save FHSS api + cur->ws_info->fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); + + ws_bootstrap_ll_address_validate(cur); + + addr_interface_set_ll64(cur, NULL); + cur->nwk_nd_re_scan_count = 0; + // Trigger discovery for bootstrap + ret_val = nwk_6lowpan_up(cur); + if (ret_val) { + goto cleanup; + } + + /* Wi-sun will trig event for stamechine this timer must be zero on init */ + cur->bootsrap_state_machine_cnt = 0; + /* Disable SLLAO send/mandatory receive with the ARO */ + cur->ipv6_neighbour_cache.use_eui64_as_slla_in_aro = true; + /* Omit sending of NA if ARO SUCCESS */ + cur->ipv6_neighbour_cache.omit_na_aro_success = true; + /* Omit sending of NA and consider ACK to be success */ + cur->ipv6_neighbour_cache.omit_na = true; + // do not process AROs from NA. This is overriden by Wi-SUN specific failure handling + cur->ipv6_neighbour_cache.recv_na_aro = false; + /* Disable NUD Probes */ + cur->ipv6_neighbour_cache.send_nud_probes = false; + cur->ipv6_neighbour_cache.probe_avoided_routers = true; + /*Replace NS handler to disable multicast address queries */ + cur->if_ns_transmit = ws_bootstrap_nd_ns_transmit; + + // Configure memory limits and garbage collection values; + ws_bootstrap_memory_configuration(); + ws_nud_table_reset(cur); + + ws_bootstrap_candidate_table_reset(cur); + // Zero uptime counters + cur->ws_info->uptime = 0; + cur->ws_info->authentication_time = 0; + cur->ws_info->connected_time = 0; + + blacklist_params_set( + WS_BLACKLIST_ENTRY_LIFETIME, + WS_BLACKLIST_TIMER_MAX_TIMEOUT, + WS_BLACKLIST_TIMER_TIMEOUT, + WS_BLACKLIST_ENTRY_MAX_NBR, + WS_BLACKLIST_PURGE_NBR, + WS_BLACKLIST_PURGE_TIMER_TIMEOUT); + + ws_bootstrap_event_discovery_start(cur); + + return 0; +cleanup: + return ret_val; +} + +int8_t ws_bootstrap_6ln_down(protocol_interface_info_entry_t *cur) +{ + if (!cur || !(cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { + return -1; + } + + tr_info("Wi-SUN ifdown"); + // Reset MAC for safe upper layer memory free + protocol_mac_reset(cur); + ns_sw_mac_fhss_unregister(cur->mac_api); + ns_fhss_delete(cur->ws_info->fhss_api); + cur->ws_info->fhss_api = NULL; + // Reset WS information + ws_bootstrap_asynch_trickle_stop(cur); + ws_llc_reset(cur); + if (nd_proxy_downstream_interface_unregister(cur->id) != 0) { + tr_warn("nd proxy unregister failed"); + } + ws_nud_table_reset(cur); + ws_pae_controller_stop(cur); + ws_bootstrap_candidate_table_reset(cur); + blacklist_clear(); + cur->if_common_forwarding_out_cb = NULL; + + return nwk_6lowpan_down(cur); +} + +#endif //HAVE_WS_BORDER_ROUTER && HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.h new file mode 100644 index 00000000000..0b9edeffdc9 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6ln.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_BOOTSTRAP_6LN_H_ +#define WS_BOOTSTRAP_6LN_H_ + +#if defined(HAVE_WS) && defined(HAVE_WS_HOST) + +void ws_bootstrap_6ln_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); +void ws_bootstrap_6ln_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); +bool ws_bootstrap_6ln_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6ln_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); +void ws_bootstrap_6ln_state_machine(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6ln_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); + +int8_t ws_bootstrap_6ln_up(protocol_interface_info_entry_t *cur); +int8_t ws_bootstrap_6ln_down(protocol_interface_info_entry_t *cur); + +#define wisun_mode_host(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_HOST) + +#else + +#define ws_bootstrap_6lr_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) +#define ws_bootstrap_6lr_asynch_confirm(interface, asynch_message) ((void) 0) +#define ws_bootstrap_6ln_eapol_relay_state_active(false) false +#define ws_bootstrap_6lr_event_handler(cur, event) ((void) 0) +#define ws_bootstrap_6ln_state_machine(cur) ((void) 0) +#define ws_bootstrap_6ln_seconds_timer(cur, seconds) ((void) 0) + +#define ws_bootstrap_6ln_up(cur) +#define ws_bootstrap_6ln_down(cur) + +#define wisun_mode_host(cur) (false) + +#endif //HAVE_WS + +#endif /* WS_BOOTSTRAP_6LN_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.c new file mode 100644 index 00000000000..d7a5cf8d812 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.c @@ -0,0 +1,1477 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "nsconfig.h" +#if defined(HAVE_WS) && defined(HAVE_WS_ROUTER) +#include "ns_types.h" +#include "ns_trace.h" +#include "nsdynmemLIB.h" +#include "net_interface.h" +#include "eventOS_event.h" +#include "randLIB.h" +#include "common_functions.h" +#include "mac_common_defines.h" +#include "sw_mac.h" +#include "ccmLIB.h" +#include "Core/include/ns_monitor.h" +#include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan_interface.h" +#include "ipv6_stack/protocol_ipv6.h" +#include "ipv6_stack/ipv6_routing_table.h" +#include "6LoWPAN/MAC/mac_helper.h" +#include "6LoWPAN/MAC/mac_data_poll.h" +#include "6LoWPAN/MAC/mpx_api.h" +#include "6LoWPAN/MAC/mac_ie_lib.h" +#include "MPL/mpl.h" +#include "RPL/rpl_protocol.h" +#include "RPL/rpl_control.h" +#include "RPL/rpl_data.h" +#include "RPL/rpl_policy.h" +#include "Common_Protocols/icmpv6.h" +#include "Common_Protocols/icmpv6_radv.h" +#include "Common_Protocols/ipv6_constants.h" +#include "Common_Protocols/ip.h" +#include "Service_Libs/Trickle/trickle.h" +#include "Service_Libs/fhss/channel_list.h" +#include "Service_Libs/utils/ns_time.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_common.h" +#include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bootstrap_6lr.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" +#include "6LoWPAN/ws/ws_bbr_api_internal.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_llc.h" +#include "6LoWPAN/ws/ws_neighbor_class.h" +#include "6LoWPAN/ws/ws_ie_lib.h" +#include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/lowpan_adaptation_interface.h" +#include "Service_Libs/etx/etx.h" +#include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" +#include "Service_Libs/nd_proxy/nd_proxy.h" +#include "Service_Libs/blacklist/blacklist.h" +#include "platform/topo_trace.h" +#include "dhcp_service_api.h" +#include "libDHCPv6/libDHCPv6.h" +#include "libDHCPv6/libDHCPv6_vendordata.h" +#include "DHCPv6_client/dhcpv6_client_api.h" +#include "ws_management_api.h" +#include "net_rpl.h" +#include "mac_api.h" +#include "6LoWPAN/ws/ws_pae_controller.h" +#include "6LoWPAN/ws/ws_eapol_pdu.h" +#include "6LoWPAN/ws/ws_eapol_auth_relay.h" +#include "6LoWPAN/ws/ws_eapol_relay.h" +#include "libNET/src/net_dns_internal.h" +#include "Service_Libs/random_early_detection/random_early_detection_api.h" + +#define TRACE_GROUP "wsbs" + +static void ws_bootstrap_6lr_address_update(protocol_interface_info_entry_t *interface); +static void ws_bootstrap_6lr_parent_confirm(protocol_interface_info_entry_t *cur, struct rpl_instance *instance); +static struct rpl_instance *ws_bootstrap_6lr_get_rpl_instance(protocol_interface_info_entry_t *cur); +static uint16_t ws_bootstrap_6lr_rank_get(protocol_interface_info_entry_t *cur); +static uint16_t ws_bootstrap_6lr_min_rank_inc_get(protocol_interface_info_entry_t *cur); + + +static void ws_bootstrap_6lr_set_fhss_hop(protocol_interface_info_entry_t *cur) +{ + uint16_t own_rank = ws_bootstrap_6lr_rank_get(cur); + uint16_t rank_inc = ws_bootstrap_6lr_min_rank_inc_get(cur); + if (own_rank == 0xffff || rank_inc == 0xffff) { + return; + } + // Calculate own hop count. This method gets inaccurate when hop count increases. + uint8_t own_hop = (own_rank - rank_inc) / rank_inc; + ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, own_hop); + if (own_hop == 1) { + // Allow transmitting unicast frames only on TX slots in normal mode and always in expedited forwarding mode for first hop + ns_fhss_ws_set_tx_allowance_level(cur->ws_info->fhss_api, WS_TX_SLOT, WS_TX_ALWAYS); + } else { + // Allow transmitting unicast frames only on TX slots in normal and expedited forwarding mode for other hops + ns_fhss_ws_set_tx_allowance_level(cur->ws_info->fhss_api, WS_TX_SLOT, WS_TX_SLOT); + } + tr_debug("own hop: %u, own rank: %u, rank inc: %u", own_hop, own_rank, rank_inc); +} + +static void ws_bootstrap_6lr_ip_stack_addr_clear(protocol_interface_info_entry_t *cur) +{ + tr_debug("ip stack address clear"); + ns_list_foreach_safe(if_address_entry_t, addr, &cur->ip_addresses) { + if (addr->source != ADDR_SOURCE_STATIC && + addr_ipv6_scope(addr->address, cur) > IPV6_SCOPE_LINK_LOCAL) { + // Remove all exept User set address + addr_delete_entry(cur, addr); + } + } +} + +static void ws_bootstrap_6lr_pan_information_store(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us, ws_pan_information_t *pan_information) +{ + + parent_info_t *new_entry; + /* Have List of 20 heard neighbours + * Order those as best based on pan cost + * In single pan order based on signal quality + * in single PAN limit the amount of devices to 5 + * If there is no advertisement heard for last hour Clear the neigbour. + */ + + // Discovery state processing + //tr_info("neighbour: addr:%s panid:%x signal:%d", trace_array(data->SrcAddr, 8), data->SrcPANId, data->signal_dbm); + + // Clean old entries + ws_bootstrap_candidate_list_clean(cur, WS_PARENT_LIST_MAX_PAN_IN_DISCOVERY, protocol_core_monotonic_time, data->SrcPANId); + + new_entry = ws_bootstrap_candidate_parent_get(cur, data->SrcAddr, true); + if (!new_entry) { + tr_warn("neighbour creation fail"); + return; + } + // Safe the information + ws_bootstrap_candidate_parent_store(new_entry, data, ws_utt, ws_us, pan_information); + if (!new_entry->link_acceptable) { + // This entry is either poor quality or changed to poor quality link so we will remove this + // Todo in future possibility to try poor link parents if we have not found any good link parents + tr_info("neighbour not accepted: addr:%s panid:%x rsl:%d device_min_sens: %d", trace_array(new_entry->addr, 8), new_entry->pan_id, ws_neighbor_class_rsl_from_dbm_calculate(new_entry->signal_dbm), DEVICE_MIN_SENS); + ns_list_remove(&cur->ws_info->parent_list_reserved, new_entry); + ns_list_add_to_end(&cur->ws_info->parent_list_free, new_entry); + return; + } + // set to the correct place in list + ws_bootstrap_candidate_parent_sort(cur, new_entry); + + return; +} + +static int8_t ws_bootstrap_6lr_fhss_configure(protocol_interface_info_entry_t *cur, bool discovery) +{ + // Read configuration of existing FHSS and start using the default values for any network + fhss_ws_configuration_t fhss_configuration = ws_common_get_current_fhss_configuration(cur); + ws_bootstrap_fhss_set_defaults(cur, &fhss_configuration); + ws_bootstrap_fhss_configure_channel_masks(cur, &fhss_configuration); + + // Discovery is done using fixed channel + if (discovery) { + fhss_configuration.ws_uc_channel_function = WS_FIXED_CHANNEL; + } else { + fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; + } + fhss_configuration.ws_bc_channel_function = WS_FIXED_CHANNEL; + fhss_configuration.fhss_broadcast_interval = 0; + uint8_t tmp_uc_fixed_channel = ws_bootstrap_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); + uint8_t tmp_bc_fixed_channel = ws_bootstrap_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels, fhss_configuration.channel_mask); + fhss_configuration.unicast_fixed_channel = tmp_uc_fixed_channel; + fhss_configuration.broadcast_fixed_channel = tmp_bc_fixed_channel; + ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); + ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, 0xff); + ws_bootstrap_llc_hopping_update(cur, &fhss_configuration); + + return 0; +} + +void ws_bootstrap_6lr_network_discovery_configure(protocol_interface_info_entry_t *cur) +{ + // Reset information to defaults + cur->ws_info->network_pan_id = 0xffff; + + ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); + ws_bootstrap_set_domain_rf_config(cur); + ws_bootstrap_6lr_fhss_configure(cur, true); + + //Set Network names, Pan information configure, hopping schedule & GTKHash + ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->cfg->gen.network_name, strlen(cur->ws_info->cfg->gen.network_name)); +} + +// Start network scan +static void ws_bootstrap_6lr_start_discovery(protocol_interface_info_entry_t *cur) +{ + tr_debug("router discovery start"); + // Remove network keys from MAC + ws_pae_controller_nw_keys_remove(cur); + ws_bootstrap_state_change(cur, ER_ACTIVE_SCAN); + cur->nwk_nd_re_scan_count = 0; + cur->ws_info->configuration_learned = false; + cur->ws_info->pan_timeout_timer = 0; + cur->ws_info->weakest_received_rssi = 0; + + // Clear learned candidate parents + ws_bootstrap_candidate_table_reset(cur); + + // Clear RPL information + rpl_control_free_domain_instances_from_interface(cur); + // Clear EAPOL relay address + ws_eapol_relay_delete(cur); + + // Clear ip stack from old information + ws_bootstrap_ip_stack_reset(cur); + // New network scan started old addresses not assumed valid anymore + ws_bootstrap_6lr_ip_stack_addr_clear(cur); + + if ((cur->lowpan_info & INTERFACE_NWK_BOOTSRAP_ACTIVE) != INTERFACE_NWK_BOOTSRAP_ACTIVE) { + // we have sent bootstrap ready event and now + // restarted discovery so bootstrap down event is sent + cur->lowpan_info |= INTERFACE_NWK_BOOTSRAP_ACTIVE; + ws_bootstrap_network_down(cur); + } + + // Start advertisement solicit trickle and calculate when we are checking the status + cur->ws_info->trickle_pas_running = true; + if (cur->ws_info->trickle_pan_advertisement_solicit.I != cur->ws_info->trickle_params_pan_discovery.Imin) { + // Trickle not reseted so starting a new interval + trickle_start(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); + } + + // Discovery statemachine is checkked after we have sent the Solicit + uint32_t time_to_solicit = 0; + if (cur->ws_info->trickle_pan_advertisement_solicit.t > cur->ws_info->trickle_pan_advertisement_solicit.now) { + time_to_solicit = cur->ws_info->trickle_pan_advertisement_solicit.t - cur->ws_info->trickle_pan_advertisement_solicit.now; + } + + tr_debug("Disc params imin %u, imax %u, expirations %u, k %u PAS Trickle I %u t %u, now %u, c %u", + cur->ws_info->trickle_params_pan_discovery.Imin, cur->ws_info->trickle_params_pan_discovery.Imax, cur->ws_info->trickle_params_pan_discovery.TimerExpirations, cur->ws_info->trickle_params_pan_discovery.k, + cur->ws_info->trickle_pan_advertisement_solicit.I, cur->ws_info->trickle_pan_advertisement_solicit.t, cur->ws_info->trickle_pan_advertisement_solicit.now, cur->ws_info->trickle_pan_advertisement_solicit.c); + + time_to_solicit += cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_random_in_range(0, cur->ws_info->trickle_params_pan_discovery.Imin); + + if (time_to_solicit > 0xffff) { + time_to_solicit = 0xffff; + } + cur->bootsrap_state_machine_cnt = time_to_solicit; + + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); +} + +// Start configuration learning +static void ws_bootstrap_6lr_start_configuration_learn(protocol_interface_info_entry_t *cur) +{ + tr_debug("router configuration learn start"); + ws_bootstrap_state_change(cur, ER_SCAN); + + cur->ws_info->configuration_learned = false; + + // Clear all temporary information + ws_bootstrap_ip_stack_reset(cur); + + cur->ws_info->pas_requests = 0; + //Calculate max time for config learn state + cur->ws_info->pan_config_sol_max_timeout = trickle_timer_max(&cur->ws_info->trickle_params_pan_discovery, PCS_MAX); + // Reset advertisement solicit trickle to start discovering network + cur->ws_info->trickle_pcs_running = true; + trickle_start(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery); + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery); +} + +static void ws_bootstrap_6lr_network_configuration_learn(protocol_interface_info_entry_t *cur) +{ + tr_debug("Start using PAN configuration"); + + // Timing information can be modified here + ws_llc_set_pan_information_pointer(cur, &cur->ws_info->pan_information); + uint8_t *gtkhash = ws_pae_controller_gtk_hash_ptr_get(cur); + ws_llc_set_gtkhash(cur, gtkhash); + // TODO update own fhss schedules we are starting to follow first parent + + return; +} + +static void ws_bootstrap_6lr_pan_advertisement_analyse_active(struct protocol_interface_info_entry *cur, ws_pan_information_t *pan_information) +{ + /* In Active state + * + * A consistent transmission is defined as a PAN Advertisement received by a node with PAN ID and + * NETNAME-IE / Network Name matching that of the receiving node, and with a PAN-IE / Routing Cost + * the same or worse than (bigger than or equal to) that of the receiving node. + * + * Inconsistent: + * + * Received Routing Cost is smaller than stored one + * + * A PAN Advertisement received by a node with PAN ID and NETNAME-IE / Network name matching + * that of the receiving node, and PAN-IE / Routing Cost better than (smaller than) that of the receiving node. + * + */ + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //Border router never set consistent that will guarantee that BR will send advertisment + return; + } +#ifdef WISUN_1_0_ERRATA_FIX + if (pan_information->pan_size == cur->ws_info->pan_information.pan_size) { + //If same pan size information then set consistent value + trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); + } +#else + // Wi-SUN 1.0 specified functionality, causes extra inconsistencies when we hear higher rank advertisements + if (pan_information->routing_cost >= ws_bootstrap_routing_cost_calculate(cur)) { + trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); + } else { + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); + } +#endif +} + +static void ws_bootstrap_6lr_pan_advertisement_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +{ + + //Validate Pan Conrfirmation is at packet + ws_pan_information_t pan_information; + if (!ws_wp_nested_pan_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &pan_information)) { + // Corrupted + tr_error("No pan information"); + return; + } + + if (ws_us->excluded_channel_ctrl) { + //Validate that we can storage data + if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK && ws_us->excluded_channels.mask.mask_len_inline > 32) { + return; + } + } + + // Check pan flags so that it is valid + if (!pan_information.rpl_routing_method) { + // NOT RPL routing + //tr_warn("Not supported routing"); + return; + } + + // Store heard pans and possible candidate parents + ws_bootstrap_6lr_pan_information_store(cur, data, ws_utt, ws_us, &pan_information); + + if (!(ws_bootstrap_state_active(cur) || + ws_bootstrap_state_wait_rpl(cur))) { + // During discovery/eapol/config learn we dont do further processing for advertisements + return; + } + // Active state processing + //tr_debug("Advertisement active"); + + // In active operation less neighbours per pan is allowed + ws_bootstrap_candidate_list_clean(cur, WS_PARENT_LIST_MAX_PAN_IN_ACTIVE, protocol_core_monotonic_time, data->SrcPANId); + + // Check if valid PAN + if (data->SrcPANId != cur->ws_info->network_pan_id) { + return; + } + + // Save route cost for all known neighbors + llc_neighbour_req_t neighbor_info; + neighbor_info.neighbor = NULL; + if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { + neighbor_info.ws_neighbor->routing_cost = pan_information.routing_cost; + //Store and search neighbour PCAP info + if (ws_version_1_1(cur)) { + ws_neighbor_class_pcap_ie_store(neighbor_info.ws_neighbor, ie_ext); + } + } + + ws_bootstrap_6lr_pan_advertisement_analyse_active(cur, &pan_information); + + // Learn latest network information + if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER && neighbor_info.neighbor) { + uint8_t ll_address[16]; + ws_common_create_ll_address(ll_address, neighbor_info.neighbor->mac64); + + if (rpl_control_is_dodag_parent(cur, ll_address)) { + cur->ws_info->pan_information.pan_size = pan_information.pan_size; + cur->ws_info->pan_information.routing_cost = pan_information.routing_cost; + cur->ws_info->pan_information.rpl_routing_method = pan_information.rpl_routing_method; + cur->ws_info->pan_information.use_parent_bs = pan_information.use_parent_bs; + } + } +} + +static void ws_bootstrap_6lr_pan_advertisement_solicit_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +{ + + (void)data; + (void)ws_utt; + (void)ws_us; + /* + * An inconsistent transmission is defined as: + * A PAN Advertisement Solicit with NETNAME-IE matching that of the receiving node. + */ + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); + /* + * A consistent transmission is defined as + * a PAN Advertisement Solicit with NETNAME-IE / Network Name matching that configured on the receiving node. + */ + trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit); + /* + * Optimized PAN discovery to select the parent faster if we hear solicit from someone else + */ + + if (ws_bootstrap_state_discovery(cur) && ws_cfg_network_config_get(cur) <= CONFIG_MEDIUM && + cur->bootsrap_state_machine_cnt > cur->ws_info->trickle_params_pan_discovery.Imin * 2) { + + cur->bootsrap_state_machine_cnt = cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_random_in_range(0, cur->ws_info->trickle_params_pan_discovery.Imin); + + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); + } + + if (ws_bootstrap_state_active(cur) && cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + mac_neighbor_table_entry_t *neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(cur), data->SrcAddr, ADDR_802_15_4_LONG); + if (neighbor && neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + ws_bootstrap_6lr_parent_confirm(cur, NULL); + } + } +} +#ifdef HAVE_WS_VERSION_1_1 +static void ws_bootstrap_6lr_pan_config_lfn_analyze(struct protocol_interface_info_entry *cur, const struct mcps_data_ie_list *ie_ext) +{ + if (!ws_version_1_1(cur) || cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + return; + } + + ws_lfnver_ie_t lfn_version; + if (!ws_wp_nested_lfn_version_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &lfn_version)) { + return; // LFN version + } + + //Read LFNGTKHASH + ws_lgtkhash_ie_t ws_lgtkhash; + if (!ws_wp_nested_lgtk_hash_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_lgtkhash)) { + return; + } + + if (!cur->ws_info->lfngtk.lfn_version_learned) { + if (!cur->ws_info->configuration_learned) { + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); + } + } else { + if (cur->ws_info->lfngtk.lfn_version == lfn_version.lfn_version) { + return; + } + + if (common_serial_number_greater_16(cur->ws_info->lfngtk.lfn_version, lfn_version.lfn_version)) { + // older version heard ignoring the message + return; + } + } + + cur->ws_info->lfngtk.lfn_version = lfn_version.lfn_version; + + //Clear HASH allways at new first or for first leaned one's + memset(cur->ws_info->lfngtk.lgtkhash, 0, 24); + cur->ws_info->lfngtk.lfn_version_learned = true; + + //Set Active key index and hash inline bits + cur->ws_info->lfngtk.active_key_index = ws_lgtkhash.active_lgtk_index; + cur->ws_info->lfngtk.active_hash_1 = ws_lgtkhash.lgtk0; + cur->ws_info->lfngtk.active_hash_2 = ws_lgtkhash.lgtk1; + cur->ws_info->lfngtk.active_hash_3 = ws_lgtkhash.lgtk2; + + if (cur->ws_info->lfngtk.active_hash_1) { + memcpy(cur->ws_info->lfngtk.lgtkhash, ws_lgtkhash.lgtk0_hash, 8); + } + + if (cur->ws_info->lfngtk.active_hash_2) { + memcpy(cur->ws_info->lfngtk.lgtkhash + 8, ws_lgtkhash.lgtk1_hash, 8); + } + + if (cur->ws_info->lfngtk.active_hash_3) { + memcpy(cur->ws_info->lfngtk.lgtkhash + 16, ws_lgtkhash.lgtk2_hash, 8); + } + //TODO Analyze HASH's and set LFN group key index +} +#endif + + +static void ws_bootstrap_6lr_pan_config_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +{ + + uint16_t pan_version; + ws_bs_ie_t ws_bs_ie; + uint8_t *gtkhash_ptr; + + if (data->SrcPANId != cur->ws_info->network_pan_id) { + return; + } + ws_bt_ie_t ws_bt_ie; + if (!ws_wh_bt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_bt_ie)) { + tr_warn("BT-IE"); + return; + } + + /* + * A consistent transmission is defined as a PAN Configuration with a PAN-ID matching that of the receiving node and + * a PANVER-IE / PAN Version greater than or equal to the receiving node’s current PAN version. + * + * A inconsistent transmission is defined as: + * + * A PAN Configuration with PAN-ID matching that of the receiving node and a + * PANVER-IE / PAN Version that is less than the receiving node’s current PAN version. + */ + + // TODO Add this to neighbor table + // TODO save all information from config message if version number has changed + + if (!ws_wp_nested_pan_version_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &pan_version)) { + // Corrupted + tr_warn("no version"); + return; + } + + gtkhash_ptr = ws_wp_nested_gtkhash_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength); + + if (!gtkhash_ptr) { + // Corrupted + tr_error("No gtk hash"); + return; + } + + if (!ws_wp_nested_bs_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_bs_ie)) { + // Corrupted + tr_error("No broadcast schedule"); + return; + } + + llc_neighbour_req_t neighbor_info; + bool neighbour_pointer_valid; + + //Validate BSI + if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + + if (cur->ws_info->ws_bsi_block.block_time && cur->ws_info->ws_bsi_block.old_bsi == ws_bs_ie.broadcast_schedule_identifier) { + tr_debug("Do not accept a old BSI: %u in time %"PRIu32, cur->ws_info->ws_bsi_block.old_bsi, cur->ws_info->ws_bsi_block.block_time); + //Refresh Block time when hear a old BSI + cur->ws_info->ws_bsi_block.block_time = cur->ws_info->cfg->timing.pan_timeout; + return; + } + + //When Config is learned and USE Parent BS is enabled compare is this new BSI + if (cur->ws_info->configuration_learned && cur->ws_info->pan_information.use_parent_bs && ws_bs_ie.broadcast_schedule_identifier != cur->ws_info->hopping_schdule.fhss_bsi) { + //Accept only next possible BSI number + if ((cur->ws_info->hopping_schdule.fhss_bsi + 1) != ws_bs_ie.broadcast_schedule_identifier) { + tr_debug("Do not accept a unknown BSI: %u", ws_bs_ie.broadcast_schedule_identifier); + } else { + tr_debug("NEW Brodcast Schedule %u...BR rebooted", ws_bs_ie.broadcast_schedule_identifier); + cur->ws_info->ws_bsi_block.block_time = cur->ws_info->cfg->timing.pan_timeout; + cur->ws_info->ws_bsi_block.old_bsi = cur->ws_info->hopping_schdule.fhss_bsi; + ws_bootstrap_event_disconnect(cur, WS_NORMAL_DISCONNECT); + } + return; + } + } + + + if (cur->ws_info->configuration_learned || cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //If we are border router or learned configuration we only update already learned neighbours. + neighbour_pointer_valid = ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false); + + } else { + neighbour_pointer_valid = ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, true); + if (!neighbour_pointer_valid) { + return; + } + ws_bootstrap_neighbor_set_stable(cur, data->SrcAddr); + } + + if (neighbour_pointer_valid) { + //Update Neighbor Broadcast and Unicast Parameters + ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp, (uint8_t *) data->SrcAddr); + ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us, &cur->ws_info->hopping_schdule); + ws_neighbor_class_neighbor_broadcast_time_info_update(neighbor_info.ws_neighbor, &ws_bt_ie, data->timestamp); + ws_neighbor_class_neighbor_broadcast_schedule_set(neighbor_info.ws_neighbor, &ws_bs_ie); + } + + if (cur->ws_info->configuration_learned) { + tr_info("PAN Config analyse own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); + if (cur->ws_info->pan_information.pan_version == pan_version) { + //Check if Trgigle have been resetted in short time skip this then + if (cur->ws_info->trickle_pc_consistency_block_period == 0) { + // Same version heard so it is consistent + trickle_consistent_heard(&cur->ws_info->trickle_pan_config); + } + + if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_SOFT_SYNCH); + } + // no need to process more +#ifdef HAVE_WS_VERSION_1_1 + ws_bootstrap_6lr_pan_config_lfn_analyze(cur, ie_ext); +#endif + return; + } else { + // received version is different so we need to reset the trickle + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); + if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_HARD_SYNCH); + } + if (common_serial_number_greater_16(cur->ws_info->pan_information.pan_version, pan_version)) { + // older version heard ignoring the message + return; + } + cur->ws_info->trickle_pc_consistency_block_period = WS_CONFIG_CONSISTENT_FILTER_PERIOD; + } + } + + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //Border router does not learn network information + return; + } + + /* + * Learn new information from neighbor + */ + tr_info("Updated PAN configuration own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); + + // restart PAN version timer + //Check Here Do we have a selected Primary parent + if (!cur->ws_info->configuration_learned || cur->ws_info->rpl_state == RPL_EVENT_DAO_DONE) { + ws_common_border_router_alive_update(cur); + } + + cur->ws_info->pan_information.pan_version = pan_version; + + ws_pae_controller_gtk_hash_update(cur, gtkhash_ptr); + + ws_pae_controller_nw_key_index_update(cur, data->Key.KeyIndex - 1); + +#ifdef HAVE_WS_VERSION_1_1 + ws_bootstrap_6lr_pan_config_lfn_analyze(cur, ie_ext); +#endif + + if (!cur->ws_info->configuration_learned) { + // Generate own hopping schedules Follow first parent broadcast and plans and also use same unicast dwell + tr_info("learn network configuration"); + cur->ws_info->configuration_learned = true; + // return to state machine after 1-2 s + cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(10, 20); + // enable frequency hopping for unicast channel and start listening first neighbour + ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_HARD_SYNCH); + // set neighbor as priority parent clear if there is others + protocol_6lowpan_neighbor_priority_clear_all(cur->id, PRIORITY_1ST); + neighbor_info.neighbor->link_role = PRIORITY_PARENT_NEIGHBOUR; + } +} + +static void ws_bootstrap_6lr_pan_config_solicit_analyse(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us) +{ + if (data->SrcPANId != cur->ws_info->network_pan_id) { + return; + } + + /* TODO smart neighbour process + * + * Unsecure packet we cant trust the device? + * + * Question mark in specification also present, now we create neighbour. + * this is moved in future to NS/ND processing triggered by RPL + * + */ + + llc_neighbour_req_t neighbor_info; + if (ws_bootstrap_neighbor_info_request(cur, data->SrcAddr, &neighbor_info, false)) { + ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, ws_utt, data->timestamp, (uint8_t *) data->SrcAddr); + ws_neighbor_class_neighbor_unicast_schedule_set(neighbor_info.ws_neighbor, ws_us, &cur->ws_info->hopping_schdule); + } + + if (ws_bootstrap_state_active(cur) && cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + mac_neighbor_table_entry_t *neighbor = mac_neighbor_table_address_discover(mac_neighbor_info(cur), data->SrcAddr, ADDR_802_15_4_LONG); + if (neighbor && neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { + ws_bootstrap_6lr_parent_confirm(cur, NULL); + } + } + + /* + * A consistent transmission is defined as a PAN Configuration Solicit with + * a PAN-ID matching that of the receiving node and a NETNAME-IE / Network Name + * matching that configured on the receiving node. + */ + trickle_consistent_heard(&cur->ws_info->trickle_pan_config_solicit); + /* + * inconsistent transmission is defined as either: + * A PAN Configuration Solicit with a PAN-ID matching that of the receiving node and + * a NETNAME-IE / Network Name matching the network name configured on the receiving + */ + trickle_inconsistent_heard(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); +} + + +void ws_bootstrap_6lr_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type) +{ + // Store weakest heard packet RSSI + if (cur->ws_info->weakest_received_rssi > data->signal_dbm) { + cur->ws_info->weakest_received_rssi = data->signal_dbm; + } + + if (data->SrcAddrMode != MAC_ADDR_MODE_64_BIT) { + // Not from long address + return; + } + ws_stats_update(cur, STATS_WS_ASYNCH_RX, 1); + //Validate network name + switch (message_type) { + case WS_FT_PAN_ADVERT: + case WS_FT_PAN_ADVERT_SOL: + case WS_FT_PAN_CONF_SOL: + //Check Network Name + if (!ws_bootstrap_network_name_matches(ie_ext, cur->ws_info->cfg->gen.network_name)) { + // Not in our network + return; + } + break; + case WS_FT_PAN_CONF: + break; + default: + return; + } + //UTT-IE and US-IE are mandatory for all Asynch Messages + ws_utt_ie_t ws_utt; + if (!ws_wh_utt_read(ie_ext->headerIeList, ie_ext->headerIeListLength, &ws_utt)) { + // Corrupted + return; + } + + ws_us_ie_t ws_us; + if (!ws_wp_nested_us_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_us)) { + // Corrupted + return; + } + + if (!ws_bootstrap_validate_channel_plan(&ws_us, cur) || + !ws_bootstrap_validate_channel_function(&ws_us, NULL)) { + return; + } + + //Handle Message's + switch (message_type) { + case WS_FT_PAN_ADVERT: + // Analyse Advertisement + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PA, 1); + tr_info("received ADVERT Src:%s panid:%x rssi:%d", trace_array(data->SrcAddr, 8), data->SrcPANId, data->signal_dbm); + ws_bootstrap_6lr_pan_advertisement_analyse(cur, data, ie_ext, &ws_utt, &ws_us); + break; + case WS_FT_PAN_ADVERT_SOL: + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PAS, 1); + tr_info("received ADVERT SOL Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); + ws_bootstrap_6lr_pan_advertisement_solicit_analyse(cur, data, &ws_utt, &ws_us); + break; + case WS_FT_PAN_CONF: + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PC, 1); + tr_info("received CONFIG Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); + ws_bootstrap_6lr_pan_config_analyse(cur, data, ie_ext, &ws_utt, &ws_us); + break; + case WS_FT_PAN_CONF_SOL: + ws_stats_update(cur, STATS_WS_ASYNCH_RX_PCS, 1); + tr_info("received CONFIG SOL Src:%s rssi:%d", trace_array(data->SrcAddr, 8), data->signal_dbm); + ws_bootstrap_6lr_pan_config_solicit_analyse(cur, data, &ws_utt, &ws_us); + default: + // Unknown message do not process + break; + } +} + +void ws_bootstrap_6lr_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message) +{ + (void)asynch_message; + ws_stats_update(interface, STATS_WS_ASYNCH_TX, 1); +} + +bool ws_bootstrap_6lr_eapol_relay_state_active(protocol_interface_info_entry_t *cur) +{ + if (cur->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { + return true; + } + + return false; +} + +static struct rpl_instance *ws_bootstrap_6lr_get_rpl_instance(protocol_interface_info_entry_t *cur) +{ + if (!cur || !cur->rpl_domain) { + return NULL; + } + struct rpl_instance *best_instance = NULL; + ns_list_foreach(struct rpl_instance, instance, &cur->rpl_domain->instances) { + best_instance = instance; + // Select best grounded and lowest rank? But there should be only one really + } + return best_instance; +} + +static uint16_t ws_bootstrap_6lr_rank_get(protocol_interface_info_entry_t *cur) +{ + struct rpl_instance *rpl_instance = ws_bootstrap_6lr_get_rpl_instance(cur); + if (!rpl_instance) { + return 0xffff; + } + return rpl_control_current_rank(rpl_instance); +} + +static uint16_t ws_bootstrap_6lr_min_rank_inc_get(protocol_interface_info_entry_t *cur) +{ + struct rpl_instance *rpl_instance = ws_bootstrap_6lr_get_rpl_instance(cur); + if (!rpl_instance) { + return 0xffff; + } + struct rpl_dodag_info_t dodag_info; + if (!rpl_control_read_dodag_info(rpl_instance, &dodag_info)) { + return 0xffff; + } + return dodag_info.dag_min_hop_rank_inc; +} + +void ws_bootstrap_6lr_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) +{ + rpl_control_register_address(interface, addr); + // Timer is used only to track full registrations + + if (addr != NULL && interface->ws_info->aro_registration_timer) { + // Single address update and timer is running + return; + } + + if (interface->ws_info->aro_registration_timer == 0) { + // Timer expired and check if we have valid address to register + ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { + if (!addr_is_ipv6_link_local(address->address)) { + // We have still valid addresses let the timer run for next period + tr_info("ARO registration timer start"); + interface->ws_info->aro_registration_timer = WS_NEIGHBOR_NUD_TIMEOUT; + return; + } + } + } +} + +static void ws_bootstrap_6lr_address_update(protocol_interface_info_entry_t *interface) +{ + tr_info("RPL parent update ... register ARO"); + ws_bootstrap_6lr_address_registration_update(interface, NULL); +} + +static void ws_bootstrap_6lr_parent_confirm(protocol_interface_info_entry_t *cur, struct rpl_instance *instance) +{ + /* Possible problem with the parent connection + * Give some time for parent to rejoin and confirm the connection with ARO and DAO + */ + const rpl_dodag_conf_int_t *config = NULL; + uint32_t Imin_secs = 0; + + if (!ws_bootstrap_state_active(cur)) { + // If we are not in Active state no need to confirm parent + return; + } + + tr_info("RPL parent confirm"); + + if (!instance) { + // If we dont have instance we take any available to get reference + instance = rpl_control_enumerate_instances(cur->rpl_domain, NULL); + } + + if (instance) { + config = rpl_control_get_dodag_config(instance); + } + + if (config) { + //dio imin Period caluclate in seconds + uint32_t Imin_ms = config->dio_interval_min < 32 ? (1ul << config->dio_interval_min) : 0xfffffffful; + //Covert to seconds and multiple by 2 so we give time to recovery so divide by 500 do that operation + Imin_secs = (Imin_ms + 499) / 500; + + if (Imin_secs > 0xffff) { + Imin_secs = 0xffff; + } + } + if (Imin_secs == 0) { + // If we dont have RPL configuration we assume conservative value + Imin_secs = 60; + } + + /*Speed up the ARO registration*/ + if (cur->ws_info->aro_registration_timer > Imin_secs) { + cur->ws_info->aro_registration_timer = Imin_secs; + } +} + + +void ws_bootstrap_6lr_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor) +{ + if (interface->ws_info) { + llc_neighbour_req_t neighbor_info; + neighbor_info.neighbor = neighbor; + neighbor_info.ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neighbor->index); + ws_bootstrap_primary_parent_set(interface, &neighbor_info, WS_PARENT_HARD_SYNCH); + uint8_t link_local_address[16]; + ws_common_create_ll_address(link_local_address, neighbor->mac64); + dhcp_client_server_address_update(interface->id, NULL, link_local_address); + + ws_bootstrap_6lr_secondary_parent_update(interface); + } +} + +void ws_bootstrap_6lr_secondary_parent_update(protocol_interface_info_entry_t *interface) +{ + if (interface->ws_info) { + ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { + if (!addr_is_ipv6_link_local(address->address)) { + ws_bootstrap_6lr_address_update(interface); + } + } + } +} + +static void ws_bootstrap_6lr_rpl_scan_start(protocol_interface_info_entry_t *cur) +{ + tr_debug("Start RPL learn"); + // Stop Trickle timers + ws_bootstrap_asynch_trickle_stop(cur); + + // routers wait until RPL root is contacted + ws_bootstrap_state_change(cur, ER_RPL_SCAN); + // Change state as the state is checked in state machine + cur->ws_info->rpl_state = RPL_EVENT_LOCAL_REPAIR_START; + //For Large network and medium should do passive scan + if (ws_cfg_network_config_get(cur) > CONFIG_SMALL) { + // Set timeout for check to 30 - 60 seconds + cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_INITIAL_TIMEOUT / 2, WS_RPL_DIS_INITIAL_TIMEOUT); + } +} + + +static void ws_bootstrap_6lr_rpl_callback(rpl_event_t event, void *handle) +{ + + protocol_interface_info_entry_t *cur = handle; + if (!cur->rpl_domain || cur->interface_mode != INTERFACE_UP) { + return; + } + + if (event == RPL_EVENT_POISON_FINISHED) { + //If we are waiting poison we will trig Discovery after couple seconds + if (cur->nwk_bootstrap_state == ER_RPL_NETWORK_LEAVING) { + cur->bootsrap_state_machine_cnt = 80; //Give 8 seconds time to send Poison + } + return; + } + + // if waiting for RPL and + if (event == RPL_EVENT_DAO_DONE) { + // Trigger statemachine check + cur->bootsrap_state_machine_cnt = 1; + rpl_dodag_info_t dodag_info; + struct rpl_instance *instance = rpl_control_enumerate_instances(cur->rpl_domain, NULL); + + if (instance && rpl_control_read_dodag_info(instance, &dodag_info)) { + tr_debug("Enable DHCPv6 relay"); + dhcp_relay_agent_enable(cur->id, dodag_info.dodag_id); + + tr_debug("Start EAPOL relay"); + // Set both own port and border router port to 10253 + ws_eapol_relay_start(cur, EAPOL_RELAY_SOCKET_PORT, dodag_info.dodag_id, EAPOL_RELAY_SOCKET_PORT); + // Set network information to PAE + ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->pan_information.pan_version, cur->ws_info->cfg->gen.network_name); + // Network key is valid, indicate border router IID to controller + ws_pae_controller_nw_key_valid(cur, &dodag_info.dodag_id[8]); + //Update here Suplikant target by validated Primary Parent + if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + mac_neighbor_table_entry_t *mac_neighbor = mac_neighbor_entry_get_priority(mac_neighbor_info(cur)); + if (mac_neighbor) { + ws_pae_controller_set_target(cur, cur->ws_info->network_pan_id, mac_neighbor->mac64); + } + } + + // After successful DAO ACK connection to border router is verified + ws_common_border_router_alive_update(cur); + } + + if (!cur->ws_info->trickle_pa_running || !cur->ws_info->trickle_pc_running) { + //Enable wi-sun asynch adverisment + ws_bootstrap_advertise_start(cur); + } + + ws_bootstrap_6lr_set_fhss_hop(cur); + // Set retry configuration for bootstrap ready state + ws_bootstrap_configure_max_retries(cur, WS_MAX_FRAME_RETRIES); + // Set TX failure request restart configuration + ws_bootstrap_configure_data_request_restart(cur, WS_CCA_REQUEST_RESTART_MAX, WS_TX_REQUEST_RESTART_MAX, WS_REQUEST_RESTART_BLACKLIST_MIN, WS_REQUEST_RESTART_BLACKLIST_MAX); + } else if (event == RPL_EVENT_LOCAL_REPAIR_NO_MORE_DIS) { + /* + * RPL goes to passive mode, but does not require any extra changed + * + * We could remove our current addresses learned from RPL + * We could send solicit for configuration and then select new parent when those arrive + * + */ + + } else if (event == RPL_EVENT_LOCAL_REPAIR_START) { + tr_debug("RPL local repair start"); + //Disable Async and go to state 4 to confirm parent connection + ws_bootstrap_6lr_parent_confirm(cur, NULL); + // Move to state 4 if we see issues with primary parent + if (ws_bootstrap_state_active(cur)) { + tr_info("Move state 4 to wait parent connection confirmation"); + ws_bootstrap_6lr_rpl_scan_start(cur); + ws_bootstrap_network_down(cur); + } + } else if (event == RPL_EVENT_DAO_PARENT_ADD) { + ws_bootstrap_6lr_address_update(cur); + } + cur->ws_info->rpl_state = event; + tr_info("RPL event %d", event); +} + +static void ws_bootstrap_6lr_rpl_prefix_callback(prefix_entry_t *prefix, void *handle, uint8_t *parent_link_local) +{ + protocol_interface_info_entry_t *cur = (protocol_interface_info_entry_t *) handle; + /* Check if A-Flag. + * A RPL node may use this option for the purpose of Stateless Address Autoconfiguration (SLAAC) + * from a prefix advertised by a parent. + */ + if (prefix->options & PIO_A) { + + if (parent_link_local) { + if (icmpv6_slaac_prefix_update(cur, prefix->prefix, prefix->prefix_len, prefix->lifetime, prefix->preftime) != 0) { + ipv6_interface_slaac_handler(cur, prefix->prefix, prefix->prefix_len, prefix->lifetime, prefix->preftime); + /* + * Give SLAAC addresses a different label and low precedence to indicate that + * they probably shouldn't be used for external traffic. SLAAC use in Wi-SUN is non-standard, + * and we use it for mesh-local traffic we should prefer any DHCP-assigned addresses + * for talking to the outside world + * + */ + addr_policy_table_add_entry(prefix->prefix, prefix->prefix_len, 2, WS_NON_PREFFRED_LABEL); + } + } else { + icmpv6_slaac_prefix_update(cur, prefix->prefix, prefix->prefix_len, 0, 0); + } + } else if (prefix->prefix_len) { + // Create new address using DHCP + if (parent_link_local) { + ws_dhcp_client_address_request(cur, prefix->prefix, parent_link_local); + } else { + /* Deprecate address and remove client */ + tr_debug("Prefix invalidation %s", trace_ipv6(prefix->prefix)); + dhcp_client_global_address_delete(cur->id, NULL, prefix->prefix); + } + } +} + +static bool ws_bootstrap_6lr_rpl_candidate_soft_filtering(protocol_interface_info_entry_t *cur, struct rpl_instance *instance) +{ + //Already many candidates + uint16_t candidate_list_size = rpl_control_candidate_list_size(cur, instance); + if (candidate_list_size >= cur->ws_info->cfg->gen.rpl_parent_candidate_max) { + return false; + } + + uint16_t selected_parents = rpl_control_selected_parent_count(cur, instance); + + //Already enough selected candidates + if (selected_parents >= cur->ws_info->cfg->gen.rpl_selected_parent_max) { + candidate_list_size -= selected_parents; + if (candidate_list_size >= 2) { + //We have more candidates than selected + return false; + } + } + + return true; +} + +static bool ws_bootstrap_6lr_rpl_new_parent_callback(uint8_t *ll_parent_address, void *handle, struct rpl_instance *instance, uint16_t candidate_rank) +{ + + protocol_interface_info_entry_t *cur = handle; + if (!cur->rpl_domain || cur->interface_mode != INTERFACE_UP) { + return false; + } + + if (blacklist_reject(ll_parent_address)) { + // Rejected by blacklist + return false; + } + + uint8_t mac64[10]; + //bool replace_ok = false; + //bool create_ok = false; + llc_neighbour_req_t neigh_buffer; + + //Discover neigh ready here for possible ETX validate + memcpy(mac64, ll_parent_address + 8, 8); + mac64[0] ^= 2; + + + ws_bootstrap_neighbor_info_request(cur, mac64, &neigh_buffer, false); + //Discover Multicast temporary entry for create neighbour table entry for new candidate + ws_neighbor_temp_class_t *entry = ws_llc_get_multicast_temp_entry(cur, mac64); + + if (!ws_bootstrap_6lr_rpl_candidate_soft_filtering(cur, instance)) { + + //Acept only better than own rank here + if (candidate_rank >= rpl_control_current_rank(instance)) { + //Do not accept no more siblings + return false; + } + + uint16_t candidate_list_size = rpl_control_candidate_list_size(cur, instance); + if (candidate_list_size > cur->ws_info->cfg->gen.rpl_parent_candidate_max + 1) { + //Accept only 1 better 1 time + return false; + } + + if (!neigh_buffer.neighbor) { + //Do not accept any new in that Place + return false; + } + + uint8_t replacing[16]; + //Accept Know neighbour if it is enough good + if (!rpl_control_find_worst_neighbor(cur, instance, replacing)) { + return false; + } + // +2 Is for PAN ID space + memcpy(mac64, replacing + 8, 8); + mac64[0] ^= 2; + + if (ws_local_etx_read(cur, ADDR_802_15_4_LONG, mac64) == 0xffff) { + //Not probed yet because ETX is 0xffff + return false; + } + + uint16_t etx = 0; + if (neigh_buffer.neighbor) { + etx = ws_local_etx_read(cur, ADDR_802_15_4_LONG, neigh_buffer.neighbor->mac64); + } + + // Accept now only better one's when max candidates selected and max candidate list size is reached + return rpl_possible_better_candidate(cur, instance, replacing, candidate_rank, etx); + } + + //Neighbour allready + if (neigh_buffer.neighbor) { + return true; + } + + if (!entry) { + //No Multicast Entry Available + return false; + } + + //Create entry + bool create_ok = ws_bootstrap_neighbor_info_request(cur, entry->mac64, &neigh_buffer, true); + if (create_ok) { + ws_neighbor_class_entry_t *ws_neigh = neigh_buffer.ws_neighbor; + ws_bootstrap_neighbor_set_stable(cur, entry->mac64); + //Copy fhss temporary data + *ws_neigh = entry->neigh_info_list; + mac_neighbor_table_trusted_neighbor(mac_neighbor_info(cur), neigh_buffer.neighbor, true); + } + ws_llc_free_multicast_temp_entry(cur, entry); + +#if 0 +neigh_create_ok: + + if (create_ok && replace_ok) { + //Try remove here when accepted new better one possible + tr_debug("Remove %s by %s", trace_ipv6(replacing), trace_ipv6(ll_parent_address)); + rpl_control_neighbor_delete_from_instance(cur, instance, replacing); + } +#endif + return create_ok; +} + +static void ws_bootstrap_6lr_rpl_parent_dis_callback(const uint8_t *ll_parent_address, void *handle, struct rpl_instance *instance) +{ + (void) ll_parent_address; + protocol_interface_info_entry_t *cur = handle; + if (!cur->rpl_domain || cur->interface_mode != INTERFACE_UP) { + return; + } + //Multicast DIS from parent indicate that Parent is not valid in short time window possible + ws_bootstrap_6lr_parent_confirm(cur, instance); +} + + +void ws_bootstrap_6lr_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event) +{ + ws_bootsrap_event_type_e event_type; + event_type = (ws_bootsrap_event_type_e)event->event_type; + + switch (event_type) { + case WS_INIT_EVENT: + tr_debug("tasklet init"); + break; + case WS_DISCOVERY_START: + tr_info("Discovery start"); + protocol_mac_reset(cur); + ws_llc_reset(cur); + lowpan_adaptation_interface_reset(cur->id); + //Clear Pending Key Index State + cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + cur->mac_parameters->mac_default_key_index = 0; + + ipv6_destination_cache_clean(cur->id); + + // Clear parent blacklist + blacklist_clear(); + + // All trickle timers stopped to allow entry from any state + ws_bootstrap_asynch_trickle_stop(cur); + //Init Packet congestion + ws_bootstrap_packet_congestion_init(cur); + + ws_pae_controller_supp_init(cur); + // Clear learned neighbours + ws_bootstrap_neighbor_list_clean(cur); + // Configure LLC for network discovery + ws_bootstrap_6lr_network_discovery_configure(cur); + ws_bootstrap_fhss_activate(cur); + // Set retry configuration for discovery state + ws_bootstrap_configure_max_retries(cur, WS_MAX_FRAME_RETRIES_BOOTSTRAP); + // Set TX failure request restart configuration for discovery state + ws_bootstrap_configure_data_request_restart(cur, WS_CCA_REQUEST_RESTART_MAX, WS_TX_REQUEST_RESTART_MAX_BOOTSTRAP, WS_REQUEST_RESTART_BLACKLIST_MIN, WS_REQUEST_RESTART_BLACKLIST_MAX); + // Set CSMA-CA backoff configuration + ws_bootstrap_configure_csma_ca_backoffs(cur, WS_MAX_CSMA_BACKOFFS, WS_MAC_MIN_BE, WS_MAC_MAX_BE); + // Start network scan + ws_bootstrap_6lr_start_discovery(cur); + break; + + case WS_CONFIGURATION_START: + tr_info("Configuration start"); + // Old configuration is considered invalid stopping all + ws_bootstrap_asynch_trickle_stop(cur); + + // Build list of possible neighbours and learn first broadcast schedule + + ws_bootstrap_6lr_start_configuration_learn(cur); + break; + case WS_OPERATION_START: + tr_info("operation start"); + // Advertisements stopped during the RPL scan + ws_bootstrap_asynch_trickle_stop(cur); + // Activate RPL + // Activate IPv6 stack + ws_bootstrap_ip_stack_activate(cur); + ws_bootstrap_ffn_rpl_configure(cur); + // Configure RPL for Node. + rpl_control_set_callback(protocol_6lowpan_rpl_domain, ws_bootstrap_6lr_rpl_callback, ws_bootstrap_6lr_rpl_prefix_callback, ws_bootstrap_6lr_rpl_new_parent_callback, ws_bootstrap_6lr_rpl_parent_dis_callback, cur); + rpl_control_set_memory_limits(WS_NODE_RPL_SOFT_MEM_LIMIT, WS_NODE_RPL_HARD_MEM_LIMIT); + + ws_bootstrap_network_start(cur); + // Wait for RPL start + ws_bootstrap_6lr_rpl_scan_start(cur); + /* While in Join State 4, if a non Border Router determines it has been unable to communicate with the PAN Border + * Router for an interval of PAN_TIMEOUT, a node MUST assume failure of the PAN Border Router and MUST + * Transition to Join State 1 + */ + ws_common_border_router_alive_update(cur); + break; + case WS_ROUTING_READY: + tr_info("Routing ready"); + // stopped all to make sure we can enter here from any state + ws_bootstrap_asynch_trickle_stop(cur); + + // Indicate PAE controller that bootstrap is ready + ws_pae_controller_bootstrap_done(cur); + + ws_bootstrap_advertise_start(cur); + ws_bootstrap_state_change(cur, ER_BOOTSRAP_DONE); + break; + case WS_FAST_DISCONNECT: + ws_bootstrap_state_disconnect(cur, WS_FAST_DISCONNECT); + break; + case WS_NORMAL_DISCONNECT: + ws_bootstrap_state_disconnect(cur, WS_NORMAL_DISCONNECT); + break; + + case WS_TEST_PROC_TRIGGER: + ws_bootstrap_test_procedure_trigger_exec(cur, (ws_bootsrap_procedure_t) event->data_ptr); + break; + + default: + tr_err("Invalid event received"); + break; + } +} + +/* + * Statemachine state functions + * */ + +static void ws_bootstrap_6lr_network_scan_process(protocol_interface_info_entry_t *cur) +{ + + parent_info_t *selected_parent_ptr; + + tr_debug("analyze network discovery result"); + +select_best_candidate: + selected_parent_ptr = ws_bootstrap_candidate_parent_get_best(cur); + + if (!selected_parent_ptr) { + // Configure LLC for network discovery + ws_bootstrap_6lr_network_discovery_configure(cur); + // randomize new channel and start MAC + ws_bootstrap_fhss_activate(cur); + // Next check will be after one trickle + uint32_t random_start = cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_random_in_range(0, cur->ws_info->trickle_params_pan_discovery.Imin); + if (random_start > 0xffff) { + random_start = 0xffff; + } + cur->bootsrap_state_machine_cnt = random_start; + + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); + return; + } + tr_info("selected parent:%s panid %u", trace_array(selected_parent_ptr->addr, 8), selected_parent_ptr->pan_id); + + if (ws_bootstrap_neighbor_set(cur, selected_parent_ptr, false) < 0) { + goto select_best_candidate; + } + + ws_pae_controller_set_target(cur, selected_parent_ptr->pan_id, selected_parent_ptr->addr); // temporary!!! store since auth + ws_bootstrap_event_authentication_start(cur); + return; +} + +static void ws_bootstrap_6lr_configure_process(protocol_interface_info_entry_t *cur) +{ + + if (cur->ws_info->configuration_learned) { + ws_bootstrap_6lr_network_configuration_learn(cur); + ws_bootstrap_event_operation_start(cur); + return; + } + return; +} + +void ws_bootstrap_6lr_rpl_wait_process(protocol_interface_info_entry_t *cur) +{ + + if (cur->ws_info->rpl_state == RPL_EVENT_DAO_DONE) { + // RPL routing is ready + cur->ws_info->connected_time = cur->ws_info->uptime; + ws_bootstrap_event_routing_ready(cur); + } else if (!rpl_control_have_dodag(cur->rpl_domain)) { + // RPL not ready send DIS message if possible + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_ROUTER) { + // TODO Multicast DIS should be sent only if no DIO heard for some time + rpl_control_transmit_dis(cur->rpl_domain, cur, 0, 0, NULL, 0, ADDR_LINK_LOCAL_ALL_RPL_NODES); + } + // set timer for next DIS + cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_TIMEOUT / 2, WS_RPL_DIS_TIMEOUT); + } + return; +} + + +/* + * State machine + */ + +void ws_bootstrap_6lr_state_machine(protocol_interface_info_entry_t *cur) +{ + + switch (cur->nwk_bootstrap_state) { + case ER_WAIT_RESTART: + tr_debug("WS SM:Wait for startup"); + ws_bootstrap_event_discovery_start(cur); + break; + case ER_ACTIVE_SCAN: + tr_debug("WS SM:Active Scan"); + ws_bootstrap_6lr_network_scan_process(cur); + break; + case ER_SCAN: + tr_debug("WS SM:configuration Scan"); + ws_bootstrap_6lr_configure_process(cur); + break; + case ER_PANA_AUTH: + tr_info("authentication start"); + // Advertisements stopped during the EAPOL + ws_bootstrap_asynch_trickle_stop(cur); + ws_bootstrap_6lr_fhss_configure(cur, false); + int8_t new_default = cur->ws_info->weakest_received_rssi - 1; + if ((new_default < CCA_DEFAULT_DBM) && (new_default >= CCA_LOW_LIMIT) && (new_default <= CCA_HIGH_LIMIT)) { + // Restart automatic CCA threshold using weakest received RSSI as new default + mac_helper_start_auto_cca_threshold(cur->id, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->weakest_received_rssi - 1, CCA_HIGH_LIMIT, CCA_LOW_LIMIT); + } + ws_bootstrap_start_authentication(cur); + break; + case ER_RPL_SCAN: + tr_debug("WS SM:Wait RPL to contact DODAG root"); + ws_bootstrap_6lr_rpl_wait_process(cur); + break; + case ER_BOOTSRAP_DONE: + tr_info("WS SM:Bootstrap Done"); + // Bootstrap_done event to application + nwk_bootsrap_state_update(ARM_NWK_BOOTSTRAP_READY, cur); + break; + case ER_RPL_NETWORK_LEAVING: + tr_debug("WS SM:RPL Leaving ready trigger discovery"); + ws_bootstrap_event_discovery_start(cur); + break; + default: + tr_warn("WS SM:Invalid state %d", cur->nwk_bootstrap_state); + } +} + +void ws_bootstrap_6lr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) +{ + /* Border router keep alive check + */ + if (cur->ws_info->pan_timeout_timer) { + // PAN version timer running + if (cur->ws_info->pan_timeout_timer > seconds) { + cur->ws_info->pan_timeout_timer -= seconds; + if (cur->ws_info->pan_timeout_timer < cur->ws_info->cfg->timing.pan_timeout / 10) { + /* pan timeout is closing need to verify that DAO is tested before the pan times out. + This will give some extra time for RPL to find better parents. + Border router liveliness can be checked from version number change or from successful DAO registrations + in this case there has not been any version number changes during this PAN lifetime. + */ + rpl_control_dao_timeout(cur->rpl_domain, 20); + } + } else { + // Border router has timed out + //Clear Timeout timer + cur->ws_info->pan_timeout_timer = 0; + tr_warn("Border router has timed out"); + ws_bootstrap_event_disconnect(cur, WS_FAST_DISCONNECT); + } + } + if (cur->ws_info->aro_registration_timer) { + if (cur->ws_info->aro_registration_timer > seconds) { + cur->ws_info->aro_registration_timer -= seconds; + } else { + // Update all addressess. This function will update the timer value if needed + cur->ws_info->aro_registration_timer = 0; + ws_bootstrap_6lr_address_registration_update(cur, NULL); + } + } + + if (cur->ws_info->ws_bsi_block.block_time) { + if (cur->ws_info->ws_bsi_block.block_time > seconds) { + cur->ws_info->ws_bsi_block.block_time -= seconds; + } else { + //Clear A BSI blokker + cur->ws_info->ws_bsi_block.block_time = 0; + cur->ws_info->ws_bsi_block.old_bsi = 0; + } + } +} + + +#endif //HAVE_WS_BORDER_ROUTER && HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.h new file mode 100644 index 00000000000..0facfa3d350 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_6lr.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_BOOTSTRAP_6LR_H_ +#define WS_BOOTSTRAP_6LR_H_ + +#if defined(HAVE_WS) && defined(HAVE_WS_ROUTER) + +void ws_bootstrap_6lr_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type); +void ws_bootstrap_6lr_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); +bool ws_bootstrap_6lr_eapol_relay_state_active(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6lr_event_handler(protocol_interface_info_entry_t *cur, arm_event_s *event); +void ws_bootstrap_6lr_state_machine(protocol_interface_info_entry_t *cur); +void ws_bootstrap_6lr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); + +void ws_bootstrap_6lr_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor); +void ws_bootstrap_6lr_secondary_parent_update(protocol_interface_info_entry_t *interface); +void ws_bootstrap_6lr_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]); + +#define wisun_mode_router(cur) (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_ROUTER) + +#else + +#define ws_bootstrap_6lr_asynch_ind(cur, data, ie_ext, message_type) ((void) 0) +#define ws_bootstrap_6lr_asynch_confirm(interface, asynch_message) ((void) 0) +#define ws_bootstrap_6lr_eapol_relay_state_active false +#define ws_bootstrap_6lr_event_handler(cur, event) ((void) 0) +#define ws_bootstrap_6lr_state_machine(cur) ((void) 0) +#define ws_bootstrap_6lr_seconds_timer(cur, seconds) ((void) 0) +#define ws_bootstrap_6lr_primary_parent_update(interface, neighbor) ((void) 0) +#define ws_bootstrap_6lr_secondary_parent_update(interface) ((void) 0) +#define ws_bootstrap_6lr_address_registration_update(interface, addr) ((void) 0) + +#define wisun_mode_router(cur) (false) + +#endif //HAVE_WS + +#endif /* WS_BOOTSTRAP_6LR_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.c new file mode 100644 index 00000000000..ae9dd1315f6 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.c @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "nsconfig.h" +#ifdef HAVE_WS +#include "ns_types.h" +#include "ns_trace.h" +#include "nsdynmemLIB.h" +#include "net_interface.h" +#include "eventOS_event.h" +#include "randLIB.h" +#include "common_functions.h" +#include "mac_common_defines.h" +#include "sw_mac.h" +#include "ccmLIB.h" +#include "Core/include/ns_monitor.h" +#include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan_interface.h" +#include "ipv6_stack/protocol_ipv6.h" +#include "ipv6_stack/ipv6_routing_table.h" +#include "6LoWPAN/MAC/mac_helper.h" +#include "6LoWPAN/MAC/mac_data_poll.h" +#include "6LoWPAN/MAC/mpx_api.h" +#include "6LoWPAN/MAC/mac_ie_lib.h" +#include "MPL/mpl.h" +#include "RPL/rpl_protocol.h" +#include "RPL/rpl_control.h" +#include "RPL/rpl_data.h" +#include "RPL/rpl_policy.h" +#include "Common_Protocols/icmpv6.h" +#include "Common_Protocols/icmpv6_radv.h" +#include "Common_Protocols/ipv6_constants.h" +#include "Common_Protocols/ip.h" +#include "Service_Libs/Trickle/trickle.h" +#include "Service_Libs/fhss/channel_list.h" +#include "Service_Libs/utils/ns_time.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_common.h" +#include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bbr_api_internal.h" +#include "6LoWPAN/ws/ws_common_defines.h" +#include "6LoWPAN/ws/ws_llc.h" +#include "6LoWPAN/ws/ws_neighbor_class.h" +#include "6LoWPAN/ws/ws_ie_lib.h" +#include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" +#include "6LoWPAN/ws/ws_bootstrap_6lbr.h" +#include "6LoWPAN/ws/ws_bootstrap_6lr.h" +#include "6LoWPAN/ws/ws_bootstrap_6ln.h" +#include "6LoWPAN/ws/ws_phy.h" +#include "6LoWPAN/lowpan_adaptation_interface.h" +#include "Service_Libs/etx/etx.h" +#include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" +#include "Service_Libs/nd_proxy/nd_proxy.h" +#include "Service_Libs/blacklist/blacklist.h" +#include "platform/topo_trace.h" +#include "dhcp_service_api.h" +#include "libDHCPv6/libDHCPv6.h" +#include "libDHCPv6/libDHCPv6_vendordata.h" +#include "DHCPv6_client/dhcpv6_client_api.h" +#include "ws_management_api.h" +#include "net_rpl.h" +#include "mac_api.h" +#include "6LoWPAN/ws/ws_pae_controller.h" +#include "6LoWPAN/ws/ws_eapol_pdu.h" +#include "6LoWPAN/ws/ws_eapol_auth_relay.h" +#include "6LoWPAN/ws/ws_eapol_relay.h" +#include "libNET/src/net_dns_internal.h" +#include "Service_Libs/random_early_detection/random_early_detection_api.h" + +#define TRACE_GROUP "wsbs" + +static void ws_bootstrap_ffn_dhcp_neighbour_update_cb(int8_t interface_id, uint8_t ll_addr[static 16]); +static void ws_bootstrap_ffn_dhcp_info_notify_cb(int8_t interface, dhcp_option_notify_t *options, dhcp_server_notify_info_t *server_info); + +int8_t ws_bootstrap_ffn_up(protocol_interface_info_entry_t *cur) +{ + int8_t ret_val = -1; + + if (!cur) { + return -1; + } + + if ((cur->configure_flags & INTERFACE_SETUP_MASK) != INTERFACE_SETUP_READY) { + tr_error("Interface not yet fully configured"); + return -2; + } + if (ws_bootstrap_fhss_initialize(cur) != 0) { + tr_error("fhss initialization failed"); + return -3; + } + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //BBR init like NVM read + ws_bbr_init(cur); + } + // Save FHSS api + cur->ws_info->fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); + + ws_bootstrap_ll_address_validate(cur); + + addr_interface_set_ll64(cur, NULL); + cur->nwk_nd_re_scan_count = 0; + // Trigger discovery for bootstrap + ret_val = nwk_6lowpan_up(cur); + if (ret_val) { + goto cleanup; + } + + /* Wi-sun will trig event for stamechine this timer must be zero on init */ + cur->bootsrap_state_machine_cnt = 0; + /* Disable SLLAO send/mandatory receive with the ARO */ + cur->ipv6_neighbour_cache.use_eui64_as_slla_in_aro = true; + /* Omit sending of NA if ARO SUCCESS */ + cur->ipv6_neighbour_cache.omit_na_aro_success = true; + /* Omit sending of NA and consider ACK to be success */ + cur->ipv6_neighbour_cache.omit_na = true; + // do not process AROs from NA. This is overriden by Wi-SUN specific failure handling + cur->ipv6_neighbour_cache.recv_na_aro = false; + /* Disable NUD Probes */ + cur->ipv6_neighbour_cache.send_nud_probes = false; + cur->ipv6_neighbour_cache.probe_avoided_routers = true; + /*Replace NS handler to disable multicast address queries */ + cur->if_ns_transmit = ws_bootstrap_nd_ns_transmit; + + dhcp_client_init(cur->id, DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE); + dhcp_service_link_local_rx_cb_set(cur->id, ws_bootstrap_ffn_dhcp_neighbour_update_cb); + dhcp_client_configure(cur->id, true, true, true); //RENEW uses SOLICIT, Interface will use 1 instance for address get, IAID address hint is not used. + + dhcp_client_solicit_timeout_set(cur->id, WS_DHCP_SOLICIT_TIMEOUT, WS_DHCP_SOLICIT_MAX_RT, WS_DHCP_SOLICIT_MAX_RC, WS_DHCP_SOLICIT_MAX_DELAY); + dhcp_client_option_notification_cb_set(cur->id, ws_bootstrap_ffn_dhcp_info_notify_cb); + + // Configure memory limits and garbage collection values; + ws_bootstrap_memory_configuration(); + ws_nud_table_reset(cur); + + ws_bootstrap_candidate_table_reset(cur); + // Zero uptime counters + cur->ws_info->uptime = 0; + cur->ws_info->authentication_time = 0; + cur->ws_info->connected_time = 0; + + blacklist_params_set( + WS_BLACKLIST_ENTRY_LIFETIME, + WS_BLACKLIST_TIMER_MAX_TIMEOUT, + WS_BLACKLIST_TIMER_TIMEOUT, + WS_BLACKLIST_ENTRY_MAX_NBR, + WS_BLACKLIST_PURGE_NBR, + WS_BLACKLIST_PURGE_TIMER_TIMEOUT); + + ws_bootstrap_event_discovery_start(cur); + + return 0; +cleanup: + return ret_val; +} + +int8_t ws_bootstrap_ffn_down(protocol_interface_info_entry_t *cur) +{ + if (!cur || !(cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { + return -1; + } + + tr_info("Wi-SUN ifdown"); + // Reset MAC for safe upper layer memory free + protocol_mac_reset(cur); + ns_sw_mac_fhss_unregister(cur->mac_api); + ns_fhss_delete(cur->ws_info->fhss_api); + cur->ws_info->fhss_api = NULL; + // Reset WS information + ws_bootstrap_asynch_trickle_stop(cur); + ws_llc_reset(cur); + if (nd_proxy_downstream_interface_unregister(cur->id) != 0) { + tr_warn("nd proxy unregister failed"); + } + ws_nud_table_reset(cur); + dhcp_client_delete(cur->id); + ws_eapol_relay_delete(cur); + ws_eapol_auth_relay_delete(cur); + ws_pae_controller_stop(cur); + ws_bootstrap_candidate_table_reset(cur); + blacklist_clear(); + cur->if_common_forwarding_out_cb = NULL; + + return nwk_6lowpan_down(cur); +} + +static void ws_bootstrap_ffn_dhcp_neighbour_update_cb(int8_t interface_id, uint8_t ll_addr[static 16]) +{ + if (memcmp(ll_addr, ADDR_LINK_LOCAL_PREFIX, 8)) { + return; + } + + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur) { + return; + } + + uint8_t mac64[8]; + memcpy(mac64, ll_addr + 8, 8); + mac64[0] ^= 2; + ws_bootstrap_mac_neighbor_short_time_set(cur, mac64, WS_NEIGHBOUR_DHCP_ENTRY_LIFETIME); +} + +static void ws_bootstrap_ffn_dhcp_info_notify_cb(int8_t interface, dhcp_option_notify_t *options, dhcp_server_notify_info_t *server_info) +{ + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface); + if (!cur) { + return; + } + uint8_t server_ll64[16]; + memcpy(server_ll64, ADDR_LINK_LOCAL_PREFIX, 8); + + if (server_info->duid_length == 8) { + memcpy(server_ll64 + 8, server_info->duid, 8); + } else { + server_ll64[8] = server_info->duid[0]; + server_ll64[9] = server_info->duid[1]; + server_ll64[10] = server_info->duid[2]; + server_ll64[11] = 0xff; + server_ll64[12] = 0xfe; + server_ll64[13] = server_info->duid[3]; + server_ll64[14] = server_info->duid[4]; + server_ll64[15] = server_info->duid[5]; + } + server_ll64[8] ^= 2; + + switch (options->option_type) { + case DHCPV6_OPTION_VENDOR_SPECIFIC_INFO: + if (options->option.vendor_spesific.enterprise_number != ARM_ENTERPRISE_NUMBER) { + break; + } + while (options->option.vendor_spesific.data_length) { + uint16_t option_type; + char *domain; + uint8_t *address; + uint16_t option_len; + option_len = net_dns_option_vendor_option_data_get_next(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &option_type); + tr_debug("DHCP vendor specific data type:%u length %d", option_type, option_len); + //tr_debug("DHCP vendor specific data %s", trace_array(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length)); + + if (option_len == 0) { + // Option fields were corrupted + break; + } + if (option_type == ARM_DHCP_VENDOR_DATA_DNS_QUERY_RESULT) { + // Process ARM DNS query result + domain = NULL; + address = NULL; + if (net_dns_option_vendor_option_data_dns_query_read(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &address, &domain) > 0 || + domain || address) { + // Valid ARM DNS query entry + net_dns_query_result_set(interface, address, domain, server_info->life_time); + } + } + if (option_type == ARM_DHCP_VENDOR_DATA_TIME_CONFIGURATION) { + timezone_info_t time_configuration; + if (net_vendor_option_time_configuration_read(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &time_configuration.timestamp, &time_configuration.timezone, &time_configuration.deviation, &time_configuration.status)) { + int ret = ns_time_system_timezone_info_notify(&time_configuration); + tr_info("Network Time configuration %s status:%"PRIu16" time stamp: %"PRIu64" deviation: %"PRId16" Time Zone: %"PRId16, ret == 0 ? "notified" : "notify FAILED", time_configuration.status, time_configuration.timestamp, time_configuration.deviation, time_configuration.timezone); + } + } + if (option_type == ARM_DHCP_VENDOR_DATA_NETWORK_TIME) { + // Process ARM Network Time + // Get Current time + // Get Round trip time of the DHCP request + // Estimated error is elapsed time of request + // If current time difference is larger than estimated error update current time + // set the time for server time + *.5 RTT + int32_t era; + uint32_t offset; + if (net_vendor_option_current_time_read(options->option.vendor_spesific.data, options->option.vendor_spesific.data_length, &era, &offset, NULL)) { + uint64_t current_time; + uint64_t network_time = (era * (uint64_t)(4294967296)) + offset - 2208988800; //Convert to First day of Unix (1 Jan 1970) + + tr_debug("Network Time option Era:%"PRId32" Offset:%"PRIu32" rtt: %"PRId32" time: %"PRIu64, era, offset, server_info->rtt, network_time); + if (0 == ns_time_system_time_read(¤t_time)) { + uint64_t difference; + // We only adjust clock if time has drifted more than 10 seconds to avoid constant changing of time + // If Round trip time is very high the accuracy is reduced. + uint32_t estimated_error = 10 + server_info->rtt / 10; + // Take into account the round trip time it took the response to arrive from the time server Write the time. + network_time += server_info->rtt / 20; + + if (current_time > network_time) { + difference = current_time - network_time; + } else { + difference = network_time - current_time; + } + if (difference > estimated_error) { + // Larger than 10 second difference update the time + int ret = ns_time_system_time_write(network_time); + tr_info("Network Time %s: Era:%"PRId32" Offset:%"PRIu32" old time: %"PRIu64" time: %"PRIu64, ret == 0 ? "updated" : "update FAILED", era, offset, current_time, network_time); + } + // System time has been acquired + ns_time_system_time_acquired_set(); + } + } + } + + options->option.vendor_spesific.data_length -= option_len; + options->option.vendor_spesific.data += option_len; + } + break; + + case DHCPV6_OPTION_DNS_SERVERS: + while (options->option.generic.data_length && options->option.generic.data_length >= 16 && options->option.generic.data_length % 16 == 0) { + // Validate payload to have full 16 byte length addresses without any extra bytes + net_dns_server_address_set(interface, server_ll64, options->option.generic.data, server_info->life_time); + options->option.generic.data_length -= 16; + options->option.generic.data += 16; + } + break; + case DHCPV6_OPTION_DOMAIN_LIST: + net_dns_server_search_list_set(interface, server_ll64, options->option.generic.data, options->option.generic.data_length, server_info->life_time); + break; + default: + break; + } + +} + +static void ws_dhcp_client_global_adress_cb(int8_t interface, uint8_t dhcp_addr[static 16], uint8_t prefix[static 16], bool register_status) +{ + (void)prefix; + (void)interface; + //TODO add handler for negative status + tr_debug("DHCPv6 %s status %u with link %s", trace_ipv6(prefix), register_status, trace_ipv6(dhcp_addr)); + if (register_status) { + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface); + if (cur) { + ws_address_reregister_trig(cur); + } + } else { + //Delete dhcpv6 client + dhcp_client_global_address_delete(interface, dhcp_addr, prefix); + } +} + + +void ws_dhcp_client_address_request(protocol_interface_info_entry_t *cur, uint8_t *prefix, uint8_t *parent_link_local) +{ + if (dhcp_client_get_global_address(cur->id, parent_link_local, prefix, ws_dhcp_client_global_adress_cb) != 0) { + tr_error("DHCPp client request fail"); + } +} + +void ws_dhcp_client_address_delete(protocol_interface_info_entry_t *cur, uint8_t *prefix) +{ + dhcp_client_global_address_delete(cur->id, NULL, prefix); +} + +void ws_bootstrap_ffn_rpl_configure(protocol_interface_info_entry_t *cur) +{ + tr_debug("RPL Activate"); +#ifdef HAVE_RPL + bool downstream = true; + bool leaf = false; +#endif + + addr_add_router_groups(cur); +#ifdef HAVE_RPL + rpl_control_set_domain_on_interface(cur, protocol_6lowpan_rpl_domain, downstream); + // If i am router I Do this + rpl_control_force_leaf(protocol_6lowpan_rpl_domain, leaf); + rpl_control_process_routes(protocol_6lowpan_rpl_domain, false); // Wi-SUN assumes that no default route needed + rpl_control_request_parent_link_confirmation(true); + rpl_control_set_dio_multicast_min_config_advertisment_count(WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT); + rpl_control_set_address_registration_timeout((WS_NEIGHBOR_LINK_TIMEOUT / 60) + 1); + rpl_control_set_dao_retry_count(WS_MAX_DAO_RETRIES); + rpl_control_set_initial_dao_ack_wait(WS_MAX_DAO_INITIAL_TIMEOUT); + rpl_control_set_mrhof_parent_set_size(WS_MAX_PARENT_SET_COUNT); + rpl_control_set_force_tunnel(true); + // Set RPL Link ETX Validation Threshold to 2.5 - 33.0 + // This setup will set ETX 0x800 to report ICMP error 18% probability + // When ETX start go over 0x280 forward dropping probability start increase linear to 100% at 0x2100 + rpl_policy_forward_link_etx_threshold_set(0x280, 0x2100); + + // Set the minimum target refresh to sen DAO registrations before pan timeout + rpl_control_set_minimum_dao_target_refresh(WS_RPL_DAO_MAX_TIMOUT); +#endif // HAVE_RPL + + cur->ws_info->rpl_state = 0xff; // Set invalid state and learn from event +} +#endif //HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h new file mode 100644 index 00000000000..b598b81479d --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap_ffn.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_BOOTSTRAP_FFN_H_ +#define WS_BOOTSTRAP_FFN_H_ + +#ifdef HAVE_WS + +int8_t ws_bootstrap_ffn_up(protocol_interface_info_entry_t *cur); +int8_t ws_bootstrap_ffn_down(protocol_interface_info_entry_t *cur); + +void ws_dhcp_client_address_request(protocol_interface_info_entry_t *cur, uint8_t *prefix, uint8_t *parent_link_local); + +void ws_bootstrap_ffn_rpl_configure(protocol_interface_info_entry_t *cur); + +#endif + +#endif /* WS_BOOTSTRAP_FFN_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.c index d01601da20c..312d41263a5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.c @@ -39,10 +39,8 @@ #define CFG_SETTINGS_OK 0 #define CFG_SETTINGS_CHANGED 1 -#define CFG_FLAGS_DISABLE_VAL_SET 0x01 -#define CFG_FLAGS_OVERRIDE_DISABLE_VAL_SET 0x02 -#define CFG_FLAGS_FORCE_INTERNAL_CONFIG 0x04 -#define CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE 0x08 +#define CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE 0x01 +#define CFG_FLAGS_BOOTSTRAP_SET_VALUES 0x02 #define TRICKLE_IMIN_60_SECS 60 #define TRICKLE_IMIN_30_SECS 30 @@ -58,8 +56,8 @@ typedef struct ws_cfg_nw_size_s { static uint32_t ws_test_temporary_entry_lifetime = 0; typedef int8_t (*ws_cfg_default_set)(void *cfg); -typedef int8_t (*ws_cfg_validate)(void *cfg, void *new_cfg); -typedef int8_t (*ws_cfg_set)(protocol_interface_info_entry_t *cur, void *cfg, void *new_cfg, uint8_t *flags); +typedef int8_t (*ws_cfg_validate)(void *new_cfg); +typedef int8_t (*ws_cfg_set)(protocol_interface_info_entry_t *cur, void *new_cfg, uint8_t flags); typedef struct { ws_cfg_default_set default_set; @@ -104,9 +102,6 @@ const cfg_devices_in_config_t devices_by_datarate[] = { { 2, 20, 50, 100}, // Configuration for 600kbs - 2400kbs }; - -static int8_t ws_cfg_to_get(ws_cfgs_t **cfg, ws_cfgs_t *new_cfg, ws_cfg_validate valid_cb, ws_cfgs_t *external_cfg, uint8_t *cfg_flags, uint8_t *flags); - static void ws_cfg_network_size_config_set_small(ws_cfg_nw_size_t *cfg); static void ws_cfg_network_size_config_set_medium(ws_cfg_nw_size_t *cfg); static void ws_cfg_network_size_config_set_large(ws_cfg_nw_size_t *cfg); @@ -146,55 +141,6 @@ static const ws_cfg_cb_t cfg_cb[] = { // Wisun configuration storage ws_cfg_t ws_cfg; -// If automatic network size mode; external configuration shown to towards users of external APIs -ws_cfg_nw_size_t *nw_size_external_cfg = NULL; - -static int8_t ws_cfg_to_get(ws_cfgs_t **cfg, ws_cfgs_t *new_cfg, ws_cfg_validate valid_cb, ws_cfgs_t *ws_cfg_ptr, uint8_t *cfg_flags, uint8_t *flags) -{ - // In case target configuration is not set, uses ws_cfg storage - if (*cfg == NULL) { - // In case external configuration is not same as internal - if (nw_size_external_cfg && (!flags || !(*flags & CFG_FLAGS_FORCE_INTERNAL_CONFIG))) { - if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.gen) { - *cfg = (ws_cfgs_t *) &nw_size_external_cfg->gen; - } else if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.timing) { - *cfg = (ws_cfgs_t *) &nw_size_external_cfg->timing; - } else if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.bbr) { - *cfg = (ws_cfgs_t *) &nw_size_external_cfg->bbr; - } else if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.sec_prot) { - *cfg = (ws_cfgs_t *) &nw_size_external_cfg->sec_prot; - } else if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.mpl) { - *cfg = (ws_cfgs_t *) &nw_size_external_cfg->mpl; - } else { - *cfg = ws_cfg_ptr; - } - } else { - *cfg = ws_cfg_ptr; - } - - if (valid_cb) { - int8_t ret = valid_cb(*cfg, new_cfg); - // On failure and if nothing is changed, returns - if (ret != CFG_SETTINGS_CHANGED) { - return ret; - } - } - } - - if (!cfg_flags) { - return CFG_SETTINGS_CHANGED; - } - *cfg_flags = 0; - if (flags) { - *cfg_flags |= *flags; - } - if (nw_size_external_cfg && !(*cfg_flags & CFG_FLAGS_OVERRIDE_DISABLE_VAL_SET)) { - *cfg_flags |= CFG_FLAGS_DISABLE_VAL_SET; - } - - return CFG_SETTINGS_CHANGED; -} - #ifdef FEA_TRACE_SUPPORT static void ws_cfg_trace(ws_cfgs_t *cfg, ws_cfgs_t *new_cfg, uint8_t size, char *name) { @@ -236,19 +182,15 @@ static int8_t ws_cfg_network_size_default_set(ws_gen_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_network_size_get(ws_gen_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_network_size_get(ws_gen_cfg_t *cfg) { - ws_gen_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.gen; return CFG_SETTINGS_OK; } -int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) +int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, 0); - + ws_gen_cfg_t *cfg = &ws_cfg.gen; if (cfg->network_size != new_cfg->network_size) { return CFG_SETTINGS_CHANGED; } @@ -258,29 +200,24 @@ int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) typedef void (*ws_cfg_network_size_config_set_size)(ws_cfg_nw_size_t *cfg); -int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *new_cfg, uint8_t flags) { - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_network_size_validate, (ws_cfgs_t *) &ws_cfg.gen, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { - return ret; - } - - uint8_t old_network_size = cfg->network_size; + (void) flags; - // If network size configuration has not changed, returns - if (cfg->network_size == new_cfg->network_size) { + if (ws_cfg_network_size_validate(new_cfg) != CFG_SETTINGS_CHANGED) { return CFG_SETTINGS_OK; } + ws_gen_cfg_t *cfg = &ws_cfg.gen; + cfg->network_size = new_cfg->network_size; ws_cfg_nw_size_t nw_size_cfg; - ws_cfg_gen_get(&nw_size_cfg.gen, NULL); - ws_cfg_timing_get(&nw_size_cfg.timing, NULL); - ws_cfg_bbr_get(&nw_size_cfg.bbr, NULL); - ws_cfg_sec_prot_get(&nw_size_cfg.sec_prot, NULL); - ws_cfg_mpl_get(&nw_size_cfg.mpl, NULL); + ws_cfg_gen_get(&nw_size_cfg.gen); + ws_cfg_timing_get(&nw_size_cfg.timing); + ws_cfg_bbr_get(&nw_size_cfg.bbr); + ws_cfg_sec_prot_get(&nw_size_cfg.sec_prot); + ws_cfg_mpl_get(&nw_size_cfg.mpl); ws_cfg_network_size_config_set_size set_function = NULL; @@ -301,46 +238,13 @@ int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_ set_function(&nw_size_cfg); } - uint8_t cfg_network_size = cfg->network_size; - - /* If no longer in an automatic network size mode, frees automatic configuration, - so that new configuration is set */ - if (nw_size_external_cfg && old_network_size == NETWORK_SIZE_AUTOMATIC) { - ns_dyn_mem_free(nw_size_external_cfg); - nw_size_external_cfg = NULL; - } + /* Sets values if changed */ + ws_cfg_gen_set(cur, &nw_size_cfg.gen, 0x00); + ws_cfg_timing_set(cur, &nw_size_cfg.timing, 0x00); + ws_cfg_bbr_set(cur, &nw_size_cfg.bbr, 0x00); + ws_cfg_sec_prot_set(cur, &nw_size_cfg.sec_prot, 0x00); + ws_cfg_mpl_set(cur, &nw_size_cfg.mpl, 0x00); - uint8_t set_flags = 0; - if (cfg_network_size == NETWORK_SIZE_AUTOMATIC) { - set_flags = CFG_FLAGS_DISABLE_VAL_SET; - } - /* Sets values if changed or network size has been previously automatic (to make sure - the settings are in sync */ - if (ws_cfg_gen_validate(&ws_cfg.gen, &nw_size_cfg.gen) == CFG_SETTINGS_CHANGED || - old_network_size == NETWORK_SIZE_AUTOMATIC) { - ws_cfg_gen_set(cur, &ws_cfg.gen, &nw_size_cfg.gen, &set_flags); - } - if (ws_cfg_timing_validate(&ws_cfg.timing, &nw_size_cfg.timing) == CFG_SETTINGS_CHANGED || - old_network_size == NETWORK_SIZE_AUTOMATIC) { - ws_cfg_timing_set(cur, &ws_cfg.timing, &nw_size_cfg.timing, &set_flags); - } - if (ws_cfg_bbr_validate(&ws_cfg.bbr, &nw_size_cfg.bbr) == CFG_SETTINGS_CHANGED || - old_network_size == NETWORK_SIZE_AUTOMATIC) { - ws_cfg_bbr_set(cur, &ws_cfg.bbr, &nw_size_cfg.bbr, &set_flags); - } - if (ws_cfg_sec_prot_validate(&ws_cfg.sec_prot, &nw_size_cfg.sec_prot) == CFG_SETTINGS_CHANGED || - old_network_size == NETWORK_SIZE_AUTOMATIC) { - ws_cfg_sec_prot_set(cur, &ws_cfg.sec_prot, &nw_size_cfg.sec_prot, &set_flags); - } - if (ws_cfg_mpl_validate(&ws_cfg.mpl, &nw_size_cfg.mpl) == CFG_SETTINGS_CHANGED || - old_network_size == NETWORK_SIZE_AUTOMATIC) { - ws_cfg_mpl_set(cur, &ws_cfg.mpl, &nw_size_cfg.mpl, &set_flags); - } - - // If is in an automatic network size mode, updates automatic configuration - if (cfg_network_size == NETWORK_SIZE_AUTOMATIC && cur) { - ws_cfg_network_size_configure(cur, cur->ws_info->pan_information.pan_size); - } return CFG_SETTINGS_OK; } @@ -349,7 +253,7 @@ static uint8_t ws_cfg_config_get_by_size(protocol_interface_info_entry_t *cur, u (void)cur; ws_phy_cfg_t phy_cfg; - if (ws_cfg_phy_get(&phy_cfg, NULL) < 0) { + if (ws_cfg_phy_get(&phy_cfg) < 0) { return CONFIG_SMALL; } uint32_t data_rate = ws_common_datarate_get_from_phy_mode(phy_cfg.phy_mode_id, phy_cfg.operating_mode); @@ -377,50 +281,6 @@ static uint8_t ws_cfg_config_get_by_size(protocol_interface_info_entry_t *cur, u return CONFIG_XLARGE; } -int8_t ws_cfg_network_size_configure(protocol_interface_info_entry_t *cur, uint16_t network_size) -{ - // Read settings that are affected by network size - ws_cfg_nw_size_t new_nw_size_cfg; - uint8_t flags = CFG_FLAGS_OVERRIDE_DISABLE_VAL_SET | CFG_FLAGS_FORCE_INTERNAL_CONFIG; - - ws_cfg_gen_get(&new_nw_size_cfg.gen, &flags); - ws_cfg_timing_get(&new_nw_size_cfg.timing, &flags); - ws_cfg_bbr_get(&new_nw_size_cfg.bbr, &flags); - ws_cfg_sec_prot_get(&new_nw_size_cfg.sec_prot, &flags); - ws_cfg_mpl_get(&new_nw_size_cfg.mpl, &flags); - - if (!nw_size_external_cfg) { - nw_size_external_cfg = ns_dyn_mem_alloc(sizeof(ws_cfg_nw_size_t)); - if (!nw_size_external_cfg) { - return -1; - } - memcpy(nw_size_external_cfg, &new_nw_size_cfg, sizeof(ws_cfg_nw_size_t)); - } - - network_size = network_size / 100; - if (network_size == 0) { - network_size = 1; - } - - if (ws_cfg_config_get_by_size(cur, network_size) == CONFIG_SMALL) { - ws_cfg_network_size_config_set_small(&new_nw_size_cfg); - } else if (ws_cfg_config_get_by_size(cur, network_size) == CONFIG_MEDIUM) { - ws_cfg_network_size_config_set_medium(&new_nw_size_cfg); - } else if (ws_cfg_config_get_by_size(cur, network_size) == CONFIG_LARGE) { - ws_cfg_network_size_config_set_large(&new_nw_size_cfg); - } else { - ws_cfg_network_size_config_set_xlarge(&new_nw_size_cfg); - } - - ws_cfg_gen_set(cur, NULL, &new_nw_size_cfg.gen, &flags); - ws_cfg_timing_set(cur, NULL, &new_nw_size_cfg.timing, &flags); - ws_cfg_bbr_set(cur, NULL, &new_nw_size_cfg.bbr, &flags); - ws_cfg_sec_prot_set(cur, NULL, &new_nw_size_cfg.sec_prot, &flags); - ws_cfg_mpl_set(cur, &ws_cfg.mpl, &new_nw_size_cfg.mpl, &flags); - - return CFG_SETTINGS_OK; -} - cfg_network_size_type_e ws_cfg_network_config_get(protocol_interface_info_entry_t *cur) { // Get size of the network Amount of devices in the network @@ -430,7 +290,7 @@ cfg_network_size_type_e ws_cfg_network_config_get(protocol_interface_info_entry_ (void)cur; ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { + if (ws_cfg_gen_get(&cfg) < 0) { return CONFIG_SMALL; } @@ -563,7 +423,6 @@ static void ws_cfg_network_size_config_set_large(ws_cfg_nw_size_t *cfg) cfg->mpl.mpl_trickle_k = MPL_LARGE_K; cfg->mpl.mpl_trickle_timer_exp = MPL_LARGE_EXPIRATIONS; cfg->mpl.seed_set_entry_lifetime = MPL_LARGE_SEED_LIFETIME; - } static void ws_cfg_network_size_config_set_xlarge(ws_cfg_nw_size_t *cfg) @@ -653,25 +512,21 @@ static void ws_cfg_network_size_config_set_certificate(ws_cfg_nw_size_t *cfg) static int8_t ws_cfg_gen_default_set(ws_gen_cfg_t *cfg) { memset(cfg->network_name, 0, sizeof(cfg->network_name)); - cfg->network_pan_id = 0xffff; cfg->rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; cfg->rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; return CFG_SETTINGS_OK; } -int8_t ws_cfg_gen_get(ws_gen_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_gen_get(ws_gen_cfg_t *cfg) { - ws_gen_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.gen; return CFG_SETTINGS_OK; } -int8_t ws_cfg_gen_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) +int8_t ws_cfg_gen_validate(ws_gen_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, 0); + ws_gen_cfg_t *cfg = &ws_cfg.gen; if (strlen(new_cfg->network_name) > 32) { return CFG_SETTINGS_ERROR_GEN_CONF; @@ -679,7 +534,6 @@ int8_t ws_cfg_gen_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) // Regulator domain, operating mode or class has changed if (strcmp(cfg->network_name, new_cfg->network_name) != 0 || - cfg->network_pan_id != new_cfg->network_pan_id || cfg->rpl_parent_candidate_max != new_cfg->rpl_parent_candidate_max || cfg->rpl_selected_parent_max != new_cfg->rpl_selected_parent_max) { return CFG_SETTINGS_CHANGED; @@ -688,30 +542,29 @@ int8_t ws_cfg_gen_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_gen_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_gen_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *new_cfg, uint8_t flags) { - (void) cur; - (void) flags; - - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_gen_validate, (ws_cfgs_t *) &ws_cfg.gen, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + int8_t ret = ws_cfg_gen_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (cfg == new_cfg) { + + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + + ws_gen_cfg_t *cfg = &ws_cfg.gen; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_gen_cfg_t), "gen"); cfg->network_size = new_cfg->network_size; if (&cfg->network_name != &new_cfg->network_name) { strncpy(cfg->network_name, new_cfg->network_name, 32); } - cfg->network_pan_id = new_cfg->network_pan_id; cfg->rpl_parent_candidate_max = new_cfg->rpl_parent_candidate_max; cfg->rpl_selected_parent_max = new_cfg->rpl_selected_parent_max; - if (cur && !(cfg_flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { + if (cur && !(flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { ws_bootstrap_restart_delayed(cur->id); } @@ -730,18 +583,15 @@ int8_t ws_cfg_phy_default_set(ws_phy_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_phy_get(ws_phy_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_phy_get(ws_phy_cfg_t *cfg) { - ws_phy_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.phy, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.phy; return CFG_SETTINGS_OK; } -int8_t ws_cfg_phy_validate(ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg) +int8_t ws_cfg_phy_validate(ws_phy_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.phy, 0, 0); + ws_phy_cfg_t *cfg = &ws_cfg.phy; // Regulator domain, operating mode or class has changed if (cfg->regulatory_domain != new_cfg->regulatory_domain || @@ -770,15 +620,14 @@ int8_t ws_cfg_phy_validate(ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *new_cfg, uint8_t flags) { - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_phy_validate, (ws_cfgs_t *) &ws_cfg.phy, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + int8_t ret = ws_cfg_phy_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } // Check settings and configure interface - if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + if (cur) { // Set operating mode for FSK if given with PHY mode ID if ((new_cfg->phy_mode_id == 1) || (new_cfg->phy_mode_id == 17)) { cur->ws_info->hopping_schdule.operating_mode = OPERATING_MODE_1a; @@ -809,15 +658,17 @@ int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *cfg, w } } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_phy_cfg_t *cfg = &ws_cfg.phy; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_phy_cfg_t), "phy"); *cfg = *new_cfg; - if (cur && !(cfg_flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { + if (cur && !(flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { ws_bootstrap_restart_delayed(cur->id); } @@ -837,18 +688,15 @@ int8_t ws_cfg_timing_default_set(ws_timing_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_timing_get(ws_timing_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_timing_get(ws_timing_cfg_t *cfg) { - ws_timing_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.timing, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.timing; return CFG_SETTINGS_OK; } -int8_t ws_cfg_timing_validate(ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg) +int8_t ws_cfg_timing_validate(ws_timing_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.timing, 0, 0); + ws_timing_cfg_t *cfg = &ws_cfg.timing; if (cfg->disc_trickle_imin != new_cfg->disc_trickle_imin || cfg->disc_trickle_imax != new_cfg->disc_trickle_imax || @@ -876,15 +724,16 @@ int8_t ws_cfg_timing_validate(ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t *new_cfg, uint8_t flags) { - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_timing_validate, (ws_cfgs_t *) &ws_cfg.timing, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + (void) flags; + + int8_t ret = ws_cfg_timing_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + if (cur) { cur->ws_info->trickle_params_pan_discovery.Imin = new_cfg->disc_trickle_imin * 10; cur->ws_info->trickle_params_pan_discovery.Imax = new_cfg->disc_trickle_imax * 10; cur->ws_info->trickle_params_pan_discovery.k = new_cfg->disc_trickle_k; @@ -892,10 +741,12 @@ int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t * ws_pae_controller_configure(cur, NULL, NULL, new_cfg); } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_timing_cfg_t *cfg = &ws_cfg.timing; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_timing_cfg_t), "timing"); *cfg = *new_cfg; @@ -922,19 +773,15 @@ static int8_t ws_cfg_bbr_default_set(ws_bbr_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_bbr_get(ws_bbr_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_bbr_get(ws_bbr_cfg_t *cfg) { - ws_bbr_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.bbr, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.bbr; return CFG_SETTINGS_OK; } -int8_t ws_cfg_bbr_validate(ws_bbr_cfg_t *cfg, ws_bbr_cfg_t *new_cfg) +int8_t ws_cfg_bbr_validate(ws_bbr_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.bbr, 0, 0); - + ws_bbr_cfg_t *cfg = &ws_cfg.bbr; if (cfg->dio_interval_min != new_cfg->dio_interval_min || cfg->dio_interval_doublings != new_cfg->dio_interval_doublings || cfg->dio_redundancy_constant != new_cfg->dio_redundancy_constant || @@ -945,21 +792,26 @@ int8_t ws_cfg_bbr_validate(ws_bbr_cfg_t *cfg, ws_bbr_cfg_t *new_cfg) return CFG_SETTINGS_CHANGED; } + if (cfg->dio_interval_min == 0 || + cfg->min_hop_rank_increase < 32 || + cfg->dhcp_address_lifetime < 60 || + cfg->rpl_default_lifetime < 60) { + return CFG_SETTINGS_ERROR_GEN_CONF; + } + return CFG_SETTINGS_OK; } -int8_t ws_cfg_bbr_set(protocol_interface_info_entry_t *cur, ws_bbr_cfg_t *cfg, ws_bbr_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_bbr_set(protocol_interface_info_entry_t *cur, ws_bbr_cfg_t *new_cfg, uint8_t flags) { - (void) cur; (void) flags; - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_bbr_validate, (ws_cfgs_t *) &ws_cfg.bbr, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + int8_t ret = ws_cfg_bbr_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (!(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + if (cur) { // cur is optional, default values are for Wi-SUN small network parameters, ws_bbr_rpl_config(cur, new_cfg->dio_interval_min, new_cfg->dio_interval_doublings, new_cfg->dio_redundancy_constant, new_cfg->dag_max_rank_increase, @@ -967,10 +819,12 @@ int8_t ws_cfg_bbr_set(protocol_interface_info_entry_t *cur, ws_bbr_cfg_t *cfg, w ws_bbr_dhcp_address_lifetime_set(cur, new_cfg->dhcp_address_lifetime); } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_bbr_cfg_t *cfg = &ws_cfg.bbr; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_bbr_cfg_t), "rpl"); *cfg = *new_cfg; @@ -990,18 +844,15 @@ static int8_t ws_cfg_mpl_default_set(ws_mpl_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_mpl_get(ws_mpl_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_mpl_get(ws_mpl_cfg_t *cfg) { - ws_mpl_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.mpl, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.mpl; return CFG_SETTINGS_OK; } -int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg) +int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.mpl, 0, 0); + ws_mpl_cfg_t *cfg = &ws_cfg.mpl; // MPL configuration has changed if (cfg->mpl_trickle_imin != new_cfg->mpl_trickle_imin || @@ -1015,9 +866,9 @@ int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *new_cfg, uint8_t flags) { - uint8_t cfg_flags; + (void) flags; // In Wi-SUN Border router will have modified settings to improve reliability if (cur && cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { @@ -1033,12 +884,12 @@ int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *cfg, w } } - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_mpl_validate, (ws_cfgs_t *) &ws_cfg.mpl, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + int8_t ret = ws_cfg_mpl_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + if (cur) { cur->mpl_data_trickle_params.Imin = MPL_MS_TO_TICKS(new_cfg->mpl_trickle_imin * 1000); cur->mpl_data_trickle_params.Imax = MPL_MS_TO_TICKS(new_cfg->mpl_trickle_imax * 1000); cur->mpl_data_trickle_params.k = new_cfg->mpl_trickle_k; @@ -1051,10 +902,12 @@ int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *cfg, w } } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_mpl_cfg_t *cfg = &ws_cfg.mpl; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_mpl_cfg_t), "mpl"); *cfg = *new_cfg; @@ -1080,18 +933,15 @@ int8_t ws_cfg_fhss_default_set(ws_fhss_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_fhss_get(ws_fhss_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_fhss_get(ws_fhss_cfg_t *cfg) { - ws_fhss_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.fhss, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.fhss; return CFG_SETTINGS_OK; } -int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg) +int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.fhss, 0, 0); + ws_fhss_cfg_t *cfg = &ws_cfg.fhss; if (memcmp(cfg->fhss_channel_mask, new_cfg->fhss_channel_mask, sizeof(uint32_t) * 8) != 0 || cfg->fhss_uc_dwell_interval != new_cfg->fhss_uc_dwell_interval || @@ -1123,20 +973,21 @@ int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *new_cfg, uint8_t flags) { (void) cur; - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_fhss_validate, (ws_cfgs_t *) &ws_cfg.fhss, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + int8_t ret = ws_cfg_fhss_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_fhss_cfg_t *cfg = &ws_cfg.fhss; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_fhss_cfg_t), "fhss"); *cfg = *new_cfg; @@ -1159,7 +1010,7 @@ int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *cfg, cfg->fhss_bc_fixed_channel = 0xffff; } - if (cur && !(cfg_flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { + if (cur && !(flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { ws_bootstrap_restart_delayed(cur->id); } @@ -1181,18 +1032,15 @@ static int8_t ws_cfg_sec_timer_default_set(ws_sec_timer_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_sec_timer_get(ws_sec_timer_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_sec_timer_get(ws_sec_timer_cfg_t *cfg) { - ws_sec_timer_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.sec_timer, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.sec_timer; return CFG_SETTINGS_OK; } -int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg) +int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.sec_timer, 0, 0); + ws_sec_timer_cfg_t *cfg = &ws_cfg.sec_timer; if (cfg->gtk_expire_offset != new_cfg->gtk_expire_offset || cfg->pmk_lifetime != new_cfg->pmk_lifetime || @@ -1210,22 +1058,25 @@ int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *ne return CFG_SETTINGS_OK; } -int8_t ws_cfg_sec_timer_set(protocol_interface_info_entry_t *cur, ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_sec_timer_set(protocol_interface_info_entry_t *cur, ws_sec_timer_cfg_t *new_cfg, uint8_t flags) { - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_sec_timer_validate, (ws_cfgs_t *) &ws_cfg.sec_timer, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + (void) flags; + + int8_t ret = ws_cfg_sec_timer_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + if (cur) { ws_pae_controller_configure(cur, new_cfg, NULL, NULL); } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_sec_timer_cfg_t *cfg = &ws_cfg.sec_timer; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_sec_timer_cfg_t), "sec_timer"); *cfg = *new_cfg; @@ -1249,18 +1100,15 @@ static int8_t ws_cfg_sec_prot_default_set(ws_sec_prot_cfg_t *cfg) return CFG_SETTINGS_OK; } -int8_t ws_cfg_sec_prot_get(ws_sec_prot_cfg_t *cfg, uint8_t *flags) +int8_t ws_cfg_sec_prot_get(ws_sec_prot_cfg_t *cfg) { - ws_sec_prot_cfg_t *get_cfg = NULL; - ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.sec_prot, 0, flags); - *cfg = *get_cfg; - + *cfg = ws_cfg.sec_prot; return CFG_SETTINGS_OK; } -int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg) +int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *new_cfg) { - ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.sec_prot, 0, 0); + ws_sec_prot_cfg_t *cfg = &ws_cfg.sec_prot; if (cfg->sec_prot_trickle_imin != new_cfg->sec_prot_trickle_imin || cfg->sec_prot_trickle_imax != new_cfg->sec_prot_trickle_imax || @@ -1279,22 +1127,25 @@ int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_c return CFG_SETTINGS_OK; } -int8_t ws_cfg_sec_prot_set(protocol_interface_info_entry_t *cur, ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg, uint8_t *flags) +int8_t ws_cfg_sec_prot_set(protocol_interface_info_entry_t *cur, ws_sec_prot_cfg_t *new_cfg, uint8_t flags) { - uint8_t cfg_flags; - int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_sec_prot_validate, (ws_cfgs_t *) &ws_cfg.sec_prot, &cfg_flags, flags); - if (ret != CFG_SETTINGS_CHANGED) { + (void) flags; + + int8_t ret = ws_cfg_sec_prot_validate(new_cfg); + if (!(flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) && ret != CFG_SETTINGS_CHANGED) { return ret; } - if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + if (cur) { ws_pae_controller_configure(cur, NULL, new_cfg, NULL); } - if (cfg == new_cfg) { + if (flags & CFG_FLAGS_BOOTSTRAP_SET_VALUES) { return CFG_SETTINGS_OK; } + ws_sec_prot_cfg_t *cfg = &ws_cfg.sec_prot; + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_sec_prot_cfg_t), "sec_prot"); *cfg = *new_cfg; @@ -1324,11 +1175,9 @@ int8_t ws_cfg_settings_default_set(void) // Set new configuration values for (uint8_t index = 0; index < CFG_CB_NUM; index++) { - uint8_t flags = 0; if (cfg_cb[index].set(NULL, ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, - ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, - &flags) < 0) { + 0x00) < 0) { tr_info("FATAL CONFIG FAILURE"); ret_value = CFG_SETTINGS_OTHER_ERROR; } @@ -1345,13 +1194,11 @@ int8_t ws_cfg_settings_interface_set(protocol_interface_info_entry_t *cur) // Set new configuration values for (uint8_t index = 0; index < CFG_CB_NUM; index++) { - uint8_t flags = CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE; // Validation if (cfg_cb[index].set) { if (cfg_cb[index].set(cur, ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, - ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, - &flags) < 0) { + CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE | CFG_FLAGS_BOOTSTRAP_SET_VALUES) < 0) { tr_info("FATAL CONFIG FAILURE"); ret_value = CFG_SETTINGS_OTHER_ERROR; } @@ -1361,30 +1208,19 @@ int8_t ws_cfg_settings_interface_set(protocol_interface_info_entry_t *cur) return ret_value; } -int8_t ws_cfg_settings_get(protocol_interface_info_entry_t *cur, ws_cfg_t *cfg) +int8_t ws_cfg_settings_get(ws_cfg_t *cfg) { - (void) cur; - *cfg = ws_cfg; - ws_cfg_gen_get(&cfg->gen, NULL); - ws_cfg_timing_get(&cfg->timing, NULL); - ws_cfg_bbr_get(&cfg->bbr, NULL); - ws_cfg_sec_prot_get(&cfg->sec_prot, NULL); - ws_cfg_mpl_get(&cfg->mpl, NULL); - return CFG_SETTINGS_OK; } -int8_t ws_cfg_settings_validate(protocol_interface_info_entry_t *cur, struct ws_cfg_s *new_cfg) +int8_t ws_cfg_settings_validate(struct ws_cfg_s *new_cfg) { - (void) cur; - // Validate new configuration values for (uint8_t index = 0; index < CFG_CB_NUM; index++) { if (cfg_cb[index].validate) { int8_t ret = cfg_cb[index].validate( - ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset); if (ret < 0) { // Validation failed @@ -1406,7 +1242,6 @@ int8_t ws_cfg_settings_set(protocol_interface_info_entry_t *cur, ws_cfg_t *new_c for (uint8_t index = 0; index < CFG_CB_NUM; index++) { if (cfg_cb[index].validate) { int8_t ret = cfg_cb[index].validate( - ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset); if (ret < 0) { @@ -1425,12 +1260,10 @@ int8_t ws_cfg_settings_set(protocol_interface_info_entry_t *cur, ws_cfg_t *new_c // Set new configuration values for (uint8_t index = 0; index < CFG_CB_NUM; index++) { - uint8_t flags = 0; // Validation if (call_cfg_set[index]) { if (cfg_cb[index].set(cur, - ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, - ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset, &flags) < 0) { + ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset, 0x00) < 0) { tr_info("FATAL CONFIG FAILURE"); ret_value = CFG_SETTINGS_OTHER_ERROR; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.h index 827b45aeff6..98f7b159058 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_cfg_settings.h @@ -26,7 +26,6 @@ typedef struct ws_gen_cfg_s { default values */ uint8_t network_size; /**< Network size selection; default medium (= 8) */ char network_name[33]; /**< Network name; max 32 octets + terminating 0 */ - uint16_t network_pan_id; /**< PAN identifier; PAN_ID; default 0xffff */ uint16_t rpl_parent_candidate_max; /**< RPL parent candidate maximum value; default 5 */ uint16_t rpl_selected_parent_max; /**< RPL selected parent maximum value; default 2 */ } ws_gen_cfg_t; @@ -163,48 +162,50 @@ typedef enum { int8_t ws_cfg_settings_init(void); int8_t ws_cfg_settings_default_set(void); int8_t ws_cfg_settings_interface_set(protocol_interface_info_entry_t *cur); -int8_t ws_cfg_network_size_configure(protocol_interface_info_entry_t *cur, uint16_t network_size); +int8_t ws_cfg_settings_get(ws_cfg_t *cfg); +int8_t ws_cfg_settings_validate(struct ws_cfg_s *new_cfg); +int8_t ws_cfg_settings_set(protocol_interface_info_entry_t *cur, ws_cfg_t *new_cfg); cfg_network_size_type_e ws_cfg_network_config_get(protocol_interface_info_entry_t *cur); -int8_t ws_cfg_network_size_get(ws_gen_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg); -int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_network_size_get(ws_gen_cfg_t *cfg); +int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *new_cfg); +int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *new_cfg, uint8_t flags); -int8_t ws_cfg_gen_get(ws_gen_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_gen_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg); -int8_t ws_cfg_gen_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_gen_get(ws_gen_cfg_t *cfg); +int8_t ws_cfg_gen_validate(ws_gen_cfg_t *new_cfg); +int8_t ws_cfg_gen_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *new_cfg, uint8_t flags); int8_t ws_cfg_phy_default_set(ws_phy_cfg_t *cfg); -int8_t ws_cfg_phy_get(ws_phy_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_phy_validate(ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg); -int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_phy_get(ws_phy_cfg_t *cfg); +int8_t ws_cfg_phy_validate(ws_phy_cfg_t *new_cfg); +int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *new_cfg, uint8_t flags); int8_t ws_cfg_timing_default_set(ws_timing_cfg_t *cfg); -int8_t ws_cfg_timing_get(ws_timing_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_timing_validate(ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg); -int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_timing_get(ws_timing_cfg_t *cfg); +int8_t ws_cfg_timing_validate(ws_timing_cfg_t *new_cfg); +int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t *new_cfg, uint8_t flags); -int8_t ws_cfg_bbr_get(ws_bbr_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_bbr_validate(ws_bbr_cfg_t *cfg, ws_bbr_cfg_t *new_cfg); -int8_t ws_cfg_bbr_set(protocol_interface_info_entry_t *cur, ws_bbr_cfg_t *cfg, ws_bbr_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_bbr_get(ws_bbr_cfg_t *cfg); +int8_t ws_cfg_bbr_validate(ws_bbr_cfg_t *new_cfg); +int8_t ws_cfg_bbr_set(protocol_interface_info_entry_t *cur, ws_bbr_cfg_t *new_cfg, uint8_t flags); -int8_t ws_cfg_mpl_get(ws_mpl_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg); -int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_mpl_get(ws_mpl_cfg_t *cfg); +int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *new_cfg); +int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *new_cfg, uint8_t flags); int8_t ws_cfg_fhss_default_set(ws_fhss_cfg_t *cfg); -int8_t ws_cfg_fhss_get(ws_fhss_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg); -int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_fhss_get(ws_fhss_cfg_t *cfg); +int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *new_cfg); +int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *new_cfg, uint8_t flags); -int8_t ws_cfg_sec_timer_get(ws_sec_timer_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg); -int8_t ws_cfg_sec_timer_set(protocol_interface_info_entry_t *cur, ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_sec_timer_get(ws_sec_timer_cfg_t *cfg); +int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *new_cfg); +int8_t ws_cfg_sec_timer_set(protocol_interface_info_entry_t *cur, ws_sec_timer_cfg_t *new_cfg, uint8_t flags); -int8_t ws_cfg_sec_prot_get(ws_sec_prot_cfg_t *cfg, uint8_t *flags); -int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg); -int8_t ws_cfg_sec_prot_set(protocol_interface_info_entry_t *cur, ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg, uint8_t *flags); +int8_t ws_cfg_sec_prot_get(ws_sec_prot_cfg_t *cfg); +int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *new_cfg); +int8_t ws_cfg_sec_prot_set(protocol_interface_info_entry_t *cur, ws_sec_prot_cfg_t *new_cfg, uint8_t flags); uint32_t ws_cfg_neighbour_temporary_lifetime_get(void); void ws_cfg_neighbour_temporary_lifetime_set(uint32_t lifetime); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c index 42a9ceb764b..f9c258aefd9 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c @@ -20,21 +20,29 @@ #include "ns_types.h" #include "ns_trace.h" #include "randLIB.h" +#include "common_functions.h" #include #include #include "Common_Protocols/icmpv6.h" #include "mac_common_defines.h" #include "net_interface.h" +#include "eventOS_event.h" #include "6LoWPAN/MAC/mpx_api.h" #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_common_defines.h" #include "6LoWPAN/ws/ws_llc.h" #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bootstrap_6ln.h" +#include "6LoWPAN/ws/ws_bootstrap_6lr.h" +#include "6LoWPAN/ws/ws_bootstrap_6lbr.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" #include "6LoWPAN/ws/ws_bbr_api_internal.h" #include "6LoWPAN/ws/ws_pae_controller.h" #include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_ie_lib.h" +#include "6LoWPAN/ws/ws_phy.h" #include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" #include "Service_Libs/blacklist/blacklist.h" @@ -58,13 +66,13 @@ static int8_t ws_disable_channels_in_range(uint32_t *channel_mask, uint16_t numb { for (uint16_t i = 0; i < number_of_channels; i++) { if (i >= range_start && i <= range_stop) { - channel_mask[0 + (i / 32)] &= ~(1 << (i % 32)); + channel_mask[i / 32] &= ~(1U << (i % 32)); } } return 0; } -int8_t ws_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_channels, uint8_t regulatory_domain, uint8_t operating_class, uint8_t channel_plan_id) +int8_t ws_common_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_channels, uint8_t regulatory_domain, uint8_t operating_class, uint8_t channel_plan_id) { // Clear channel mask for (uint8_t i = 0; i < 8; i++) { @@ -72,7 +80,7 @@ int8_t ws_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_chann } // Enable all channels for (uint16_t i = 0; i < number_of_channels; i++) { - channel_mask[0 + (i / 32)] |= (1 << (i % 32)); + channel_mask[i / 32] |= 1U << (i % 32); } // Disable unsupported channels per regional frequency bands if (regulatory_domain == REG_DOMAIN_BZ) { @@ -93,121 +101,38 @@ int8_t ws_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_chann ws_disable_channels_in_range(channel_mask, number_of_channels, 3, 10); } } + } else if (regulatory_domain == REG_DOMAIN_EU) { + if (channel_plan_id == 32) { + ws_disable_channels_in_range(channel_mask, number_of_channels, 55, 56); + ws_disable_channels_in_range(channel_mask, number_of_channels, 61, 63); + ws_disable_channels_in_range(channel_mask, number_of_channels, 65, 66); + } else if (channel_plan_id == 33) { + ws_disable_channels_in_range(channel_mask, number_of_channels, 27, 28); + ws_disable_channels_in_range(channel_mask, number_of_channels, 30, 33); + } else if (channel_plan_id == 36) { + ws_disable_channels_in_range(channel_mask, number_of_channels, 55, 56); + ws_disable_channels_in_range(channel_mask, number_of_channels, 61, 63); + ws_disable_channels_in_range(channel_mask, number_of_channels, 65, 66); + } else if (channel_plan_id == 37) { + ws_disable_channels_in_range(channel_mask, number_of_channels, 27, 28); + ws_disable_channels_in_range(channel_mask, number_of_channels, 30, 33); + } } return 0; } -uint16_t ws_active_channel_count(uint32_t *channel_mask, uint16_t number_of_channels) +uint16_t ws_common_active_channel_count(uint32_t *channel_mask, uint16_t number_of_channels) { uint16_t active_channels = 0; // Set channel maks outside excluded channels for (uint16_t i = 0; i < number_of_channels; i++) { - if (channel_mask[0 + (i / 32)] & (1 << (i % 32))) { + if (channel_mask[i / 32] & (1U << (i % 32))) { active_channels++; } } return active_channels; } -uint32_t ws_decode_channel_spacing(uint8_t channel_spacing) -{ - if (CHANNEL_SPACING_100 == channel_spacing) { - return 100000; - } else if (CHANNEL_SPACING_200 == channel_spacing) { - return 200000; - } else if (CHANNEL_SPACING_250 == channel_spacing) { - return 250000; - } else if (CHANNEL_SPACING_400 == channel_spacing) { - return 400000; - } else if (CHANNEL_SPACING_600 == channel_spacing) { - return 600000; - } else if (CHANNEL_SPACING_800 == channel_spacing) { - return 800000; - } else if (CHANNEL_SPACING_1200 == channel_spacing) { - return 1200000; - } - return 0; -} - -uint32_t ws_get_datarate_using_operating_mode(uint8_t operating_mode) -{ - if ((OPERATING_MODE_1a == operating_mode) || (OPERATING_MODE_1b == operating_mode)) { - return 50000; - } else if ((OPERATING_MODE_2a == operating_mode) || (OPERATING_MODE_2b == operating_mode)) { - return 100000; - } else if (OPERATING_MODE_3 == operating_mode) { - return 150000; - } else if ((OPERATING_MODE_4a == operating_mode) || (OPERATING_MODE_4b == operating_mode)) { - return 200000; - } else if (OPERATING_MODE_5 == operating_mode) { - return 300000; - } - return 0; -} - -uint32_t ws_get_datarate_using_phy_mode_id(uint8_t phy_mode_id) -{ - if (84 == phy_mode_id) { - return 150000; - } else if (85 == phy_mode_id) { - return 200000; - } else if ((68 == phy_mode_id) || (86 == phy_mode_id)) { - return 300000; - } else if ((34 == phy_mode_id) || (51 == phy_mode_id) || (69 == phy_mode_id)) { - return 400000; - } else if ((52 == phy_mode_id) || (70 == phy_mode_id)) { - return 600000; - } else if ((35 == phy_mode_id) || (53 == phy_mode_id)) { - return 800000; - } else if ((36 == phy_mode_id) || (54 == phy_mode_id)) { - return 1200000; - } else if (37 == phy_mode_id) { - return 1600000; - } else if (38 == phy_mode_id) { - return 2400000; - } - return 0; -} - -uint8_t ws_get_ofdm_option_using_phy_mode_id(uint8_t phy_mode_id) -{ - if ((phy_mode_id >= 34) && (phy_mode_id <= 38)) { - return OFDM_OPTION_1; - } else if ((phy_mode_id >= 51) && (phy_mode_id <= 54)) { - return OFDM_OPTION_2; - } else if ((phy_mode_id >= 68) && (phy_mode_id <= 70)) { - return OFDM_OPTION_3; - } else if ((phy_mode_id >= 84) && (phy_mode_id <= 86)) { - return OFDM_OPTION_4; - } - return 0; -} - -uint8_t ws_get_ofdm_mcs_using_phy_mode_id(uint8_t phy_mode_id) -{ - if (34 == phy_mode_id) { - return OFDM_MCS_2; - } else if ((35 == phy_mode_id) || (51 == phy_mode_id)) { - return OFDM_MCS_3; - } else if ((36 == phy_mode_id) || (52 == phy_mode_id) || (68 == phy_mode_id) || (84 == phy_mode_id)) { - return OFDM_MCS_4; - } else if ((37 == phy_mode_id) || (53 == phy_mode_id) || (69 == phy_mode_id) || (85 == phy_mode_id)) { - return OFDM_MCS_5; - } else if ((38 == phy_mode_id) || (54 == phy_mode_id) || (70 == phy_mode_id) || (86 == phy_mode_id)) { - return OFDM_MCS_6; - } - return 0; -} - -phy_modulation_index_e ws_get_modulation_index_using_operating_mode(uint8_t operating_mode) -{ - if ((OPERATING_MODE_1b == operating_mode) || (OPERATING_MODE_2b == operating_mode) || (OPERATING_MODE_4b == operating_mode)) { - return MODULATION_INDEX_1_0; - } else { - return MODULATION_INDEX_0_5; - } -} - int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur, ws_hopping_schedule_t *hopping_schdule) { (void)cur; @@ -229,23 +154,18 @@ int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur, if (phy_type >= 2 && phy_mode > 6) { return -1; } - // Skip if PHY mode is for FSK modulation - if (!phy_mode_id || ((phy_mode_id > 8) && (phy_mode_id < 17)) || phy_mode_id > 24) { + + if (M_OFDM == ws_phy_get_modulation_using_phy_mode_id(phy_mode_id)) { // Validate OFDM configurations - if (((phy_mode_id >= 34) && (phy_mode_id <= 38)) || - ((phy_mode_id >= 51) && (phy_mode_id <= 54)) || - ((phy_mode_id >= 68) && (phy_mode_id <= 70)) || - ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { - if (ws_get_datarate_using_phy_mode_id(phy_mode_id) == 0 || - ws_get_ofdm_option_using_phy_mode_id(phy_mode_id) == 0 || - ws_get_ofdm_mcs_using_phy_mode_id(phy_mode_id) == 0) { - //Unsupported PHY mode - return -1; - } - } else { - // Invalid PHY mode ID + if (!ws_phy_get_datarate_using_phy_mode_id(phy_mode_id) || + !ws_phy_get_ofdm_option_using_phy_mode_id(phy_mode_id) || + !ws_phy_get_ofdm_mcs_using_phy_mode_id(phy_mode_id)) { + //Unsupported PHY mode return -1; } + } else if (M_UNDEFINED == ws_phy_get_modulation_using_phy_mode_id(phy_mode_id)) { + // Invalid PHY mode ID + return -1; } } hopping_schdule->channel_plan = 0; @@ -261,20 +181,44 @@ int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur, return -1; } } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_EU) { - if (hopping_schdule->operating_class == 1) { - hopping_schdule->ch0_freq = 8631; - hopping_schdule->channel_spacing = CHANNEL_SPACING_100; - } else if (hopping_schdule->operating_class == 2) { - hopping_schdule->ch0_freq = 8631; - hopping_schdule->channel_spacing = CHANNEL_SPACING_200; - } else if (hopping_schdule->operating_class == 3) { - hopping_schdule->ch0_freq = 8701; - hopping_schdule->channel_spacing = CHANNEL_SPACING_100; - } else if (hopping_schdule->operating_class == 4) { - hopping_schdule->ch0_freq = 8702; - hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + if (hopping_schdule->channel_plan_id == 255) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->operating_class == 3) { + hopping_schdule->ch0_freq = 8701; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->operating_class == 4) { + hopping_schdule->ch0_freq = 8702; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else { + return -1; + } } else { - return -1; + if (hopping_schdule->channel_plan_id == 32) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->channel_plan_id == 33) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->channel_plan_id == 34) { + hopping_schdule->ch0_freq = 8701; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->channel_plan_id == 35) { + hopping_schdule->ch0_freq = 8702; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->channel_plan_id == 36) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->channel_plan_id == 37) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else { + return -1; + } } } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_IN) { if (hopping_schdule->operating_class == 1) { @@ -385,15 +329,10 @@ uint16_t ws_common_channel_number_calc(uint8_t regulatory_domain, uint8_t operat return 16; } } else if (regulatory_domain == REG_DOMAIN_EU) { - if (operating_class == 1) { - return 69; - } else if (operating_class == 2) { - return 35; - } else if (operating_class == 3) { - return 55; - } else if (operating_class == 4) { - return 27; + if (channel_plan_id == 255) { + channel_plan_id = ws_phy_convert_operating_class_to_channel_plan_id(operating_class, regulatory_domain); } + return ws_phy_get_number_of_channels_using_channel_plan_id(channel_plan_id); } else if (regulatory_domain == REG_DOMAIN_IN) { if (operating_class == 1) { return 19; @@ -402,22 +341,9 @@ uint16_t ws_common_channel_number_calc(uint8_t regulatory_domain, uint8_t operat } } else if (regulatory_domain == REG_DOMAIN_NA) { if (channel_plan_id == 255) { - if (operating_class == 1) { - return 129; - } else if (operating_class == 2) { - return 64; - } else if (operating_class == 3) { - return 42; - } - } else { - if (channel_plan_id == 1) { - return 129; - } else if (channel_plan_id == 2) { - return 64; - } else if (channel_plan_id == 5) { - return 21; - } + channel_plan_id = ws_phy_convert_operating_class_to_channel_plan_id(operating_class, regulatory_domain); } + return ws_phy_get_number_of_channels_using_channel_plan_id(channel_plan_id); } else if (regulatory_domain == REG_DOMAIN_JP) { if (operating_class == 1) { return 38; @@ -428,22 +354,9 @@ uint16_t ws_common_channel_number_calc(uint8_t regulatory_domain, uint8_t operat } } else if (regulatory_domain == REG_DOMAIN_BZ) { if (channel_plan_id == 255) { - if (operating_class == 1) { - return 129; - } else if (operating_class == 2) { - return 64; - } else if (operating_class == 3) { - return 42; - } - } else { - if (channel_plan_id == 1) { - return 129; - } else if (channel_plan_id == 2) { - return 64; - } else if (channel_plan_id == 5) { - return 21; - } + channel_plan_id = ws_phy_convert_operating_class_to_channel_plan_id(operating_class, regulatory_domain); } + return ws_phy_get_number_of_channels_using_channel_plan_id(channel_plan_id); } else if (regulatory_domain == REG_DOMAIN_WW) { if (operating_class == 1) { // TODO we dont support this yet, but it is used as test value @@ -472,12 +385,13 @@ int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur) ns_list_init(&cur->ws_info->parent_list_free); ns_list_init(&cur->ws_info->parent_list_reserved); + cur->ws_info->version = test_pan_version; + cur->ws_info->network_pan_id = 0xffff; cur->ws_info->pan_information.use_parent_bs = true; cur->ws_info->pan_information.rpl_routing_method = true; cur->ws_info->pan_information.pan_version_set = false; cur->ws_info->pan_information.version = WS_FAN_VERSION_1_0; - cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; cur->ws_info->hopping_schdule.regulatory_domain = REG_DOMAIN_EU; @@ -490,14 +404,40 @@ int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur) ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; - + // initialize for FAN 1.1 defaults + if (ws_version_1_1(cur)) { + cur->ws_info->pan_information.version = WS_FAN_VERSION_1_1; + } return 0; } +int ws_common_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) +{ + return ws_bootstrap_init(interface_id, bootstrap_mode); +} + +void ws_common_state_machine(protocol_interface_info_entry_t *cur) +{ + if (wisun_mode_host(cur)) { + // Configure for LFN device + ws_bootstrap_6ln_state_machine(cur); + } else if (wisun_mode_router(cur)) { + // Configure FFN device + ws_bootstrap_6lr_state_machine(cur); + } else if (wisun_mode_border_router(cur)) { + // Configure as Border router + ws_bootstrap_6lbr_state_machine(cur); + } + +} + void ws_common_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) { ws_bbr_seconds_timer(cur, seconds); ws_bootstrap_seconds_timer(cur, seconds); + ws_bootstrap_6lbr_seconds_timer(cur, seconds); + ws_bootstrap_6lr_seconds_timer(cur, seconds); + ws_bootstrap_6ln_seconds_timer(cur, seconds); blacklist_ttl_update(seconds); } @@ -508,6 +448,12 @@ void ws_common_fast_timer(protocol_interface_info_entry_t *cur, uint16_t ticks) ws_llc_fast_timer(cur, ticks); } +void ws_common_create_ll_address(uint8_t *ll_address, const uint8_t *mac64) +{ + memcpy(ll_address, ADDR_LINK_LOCAL_PREFIX, 8); + memcpy(ll_address + 8, mac64, 8); + ll_address[8] ^= 2; +} void ws_common_neighbor_update(protocol_interface_info_entry_t *cur, const uint8_t *ll_address) { @@ -652,13 +598,10 @@ uint32_t ws_common_latency_estimate_get(protocol_interface_info_entry_t *cur) uint32_t ws_common_datarate_get_from_phy_mode(uint8_t phy_mode_id, uint8_t operating_mode) { - if (((phy_mode_id >= 34) && (phy_mode_id <= 38)) || - ((phy_mode_id >= 51) && (phy_mode_id <= 54)) || - ((phy_mode_id >= 68) && (phy_mode_id <= 70)) || - ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { - return ws_get_datarate_using_phy_mode_id(phy_mode_id); + if (phy_mode_id == 255) { + phy_mode_id = ws_phy_convert_operating_mode_to_phy_mode_id(operating_mode); } - return ws_get_datarate_using_operating_mode(operating_mode); + return ws_phy_get_datarate_using_phy_mode_id(phy_mode_id); } uint32_t ws_common_datarate_get(protocol_interface_info_entry_t *cur) @@ -719,12 +662,12 @@ uint32_t ws_common_authentication_time_get(protocol_interface_info_entry_t *cur) void ws_common_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor) { - ws_bootstrap_primary_parent_update(interface, neighbor); + ws_bootstrap_6lr_primary_parent_update(interface, neighbor); } void ws_common_secondary_parent_update(protocol_interface_info_entry_t *interface) { - ws_bootstrap_secondary_parent_update(interface); + ws_bootstrap_6lr_secondary_parent_update(interface); } void ws_common_border_router_alive_update(protocol_interface_info_entry_t *interface) @@ -737,4 +680,16 @@ void ws_common_border_router_alive_update(protocol_interface_info_entry_t *inter interface->ws_info->pan_timeout_timer = interface->ws_info->cfg->timing.pan_timeout; } +fhss_ws_configuration_t ws_common_get_current_fhss_configuration(protocol_interface_info_entry_t *cur) +{ + fhss_ws_configuration_t fhss_configuration; + memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); + if (ns_fhss_ws_configuration_get(cur->ws_info->fhss_api)) { + memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); + } else { + tr_error("FHSS configuration could not be read"); + } + return fhss_configuration; +} + #endif // HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h index 40fbd0a16de..c7fb453e143 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.h @@ -37,6 +37,8 @@ struct ws_pan_information_s; struct ws_neighbor_class_s; struct ws_excluded_channel_data_s; struct ws_cfg_s; +struct ws_neighbor_class_entry; +struct mcps_data_ie_list; typedef struct parent_info_s { uint16_t pan_id; /**< PAN ID */ @@ -79,6 +81,30 @@ typedef struct { uint16_t old_bsi; } ws_bsi_block_t; +typedef struct { + uint16_t eapol_trigger_timer; + uint16_t pas_trigger_timer; + uint16_t pcs_trigger_timer; + uint16_t dis_trigger_timer; + uint16_t dis_trigger_timer_val; + uint16_t rpl_trigger_timer; + uint16_t rpl_trigger_timer_val; + uint8_t pas_trigger_count; + uint8_t pcs_trigger_count; + bool auto_trg_enabled; +} ws_test_proc_trg_t; + +typedef struct { + uint16_t lfn_version; + bool lfn_version_learned: 1; + bool active_hash_1: 1; + bool active_hash_2: 1; + bool active_hash_3: 1; + unsigned active_key_index: 2; + uint8_t lgtkhash[24]; +} ws_lfn_lgtk_t; + + typedef NS_LIST_HEAD(ws_nud_table_entry_t, link) ws_nud_table_list_t; typedef struct ws_info_s { @@ -87,6 +113,7 @@ typedef struct ws_info_s { trickle_t trickle_pan_advertisement_solicit; trickle_t trickle_pan_advertisement; trickle_params_t trickle_params_pan_discovery; + uint8_t version; // Wi-SUN version information 1 = 1.0 2 = 1.x uint8_t rpl_state; // state from rpl_event_t uint8_t pas_requests; // Amount of PAN solicits sent uint8_t device_min_sens; // Device min sensitivity set by the application @@ -114,6 +141,11 @@ typedef struct ws_info_s { ws_nud_table_entry_t nud_table_entrys[ACTIVE_NUD_PROCESS_MAX]; ws_nud_table_list_t active_nud_process; ws_nud_table_list_t free_nud_entries; + ws_test_proc_trg_t test_proc_trg; +#ifdef HAVE_WS_VERSION_1_1 + ws_lfn_lgtk_t lfngtk; + ws_phy_cap_info_t phy_cap_info; +#endif struct ws_cfg_s *cfg; /**< Wi-SUN configuration */ struct ws_pan_information_s pan_information; ws_hopping_schedule_t hopping_schdule; @@ -125,21 +157,9 @@ typedef struct ws_info_s { #ifdef HAVE_WS -int8_t ws_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_channels, uint8_t regulatory_domain, uint8_t operating_class, uint8_t channel_plan_id); - -uint16_t ws_active_channel_count(uint32_t *channel_mask, uint16_t number_of_channels); - -uint32_t ws_decode_channel_spacing(uint8_t channel_spacing); - -uint32_t ws_get_datarate_using_operating_mode(uint8_t operating_mode); - -uint32_t ws_get_datarate_using_phy_mode_id(uint8_t phy_mode_id); +int8_t ws_common_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_channels, uint8_t regulatory_domain, uint8_t operating_class, uint8_t channel_plan_id); -uint8_t ws_get_ofdm_option_using_phy_mode_id(uint8_t phy_mode_id); - -uint8_t ws_get_ofdm_mcs_using_phy_mode_id(uint8_t phy_mode_id); - -phy_modulation_index_e ws_get_modulation_index_using_operating_mode(uint8_t operating_mode); +uint16_t ws_common_active_channel_count(uint32_t *channel_mask, uint16_t number_of_channels); int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur, ws_hopping_schedule_t *hopping_schdule); @@ -151,6 +171,8 @@ void ws_common_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seco void ws_common_fast_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); +void ws_common_create_ll_address(uint8_t *ll_address, const uint8_t *mac64); + void ws_common_neighbor_update(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); void ws_common_black_list_neighbour(const uint8_t *ll_address, uint8_t nd_status); @@ -184,11 +206,35 @@ void ws_common_primary_parent_update(protocol_interface_info_entry_t *interface, void ws_common_secondary_parent_update(protocol_interface_info_entry_t *interface); uint8_t ws_common_temporary_entry_size(uint8_t mac_table_size); + void ws_common_border_router_alive_update(protocol_interface_info_entry_t *interface); +int ws_common_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode); + +void ws_common_state_machine(protocol_interface_info_entry_t *cur); + +fhss_ws_configuration_t ws_common_get_current_fhss_configuration(protocol_interface_info_entry_t *cur); + #define ws_info(cur) ((cur)->ws_info) +#ifdef HAVE_WS_VERSION_1_1 +#define ws_version_1_0(cur) (((cur)->ws_info) && ((cur)->ws_info)->version == 1) +#define ws_version_1_1(cur) (((cur)->ws_info) && ((cur)->ws_info)->version > 1) +#define ws_lfn_version_learned(cur) ((cur)->ws_info->lfngtk.lfn_version_learned == true) +#define ws_neighbour_cap_pointer(neighbour) (&neighbour->pcap_info) +#else +#define ws_version_1_1(cur) (false) +#define ws_version_1_0(cur) ((cur)->ws_info) +#define ws_lfn_version_learned(cur) (false) +#define ws_neighbour_cap_pointer(neighbour) NULL +#endif +#define ws_test_proc_auto_trg(cur) ((cur)->ws_info->test_proc_trg.auto_trg_enabled == true) #else #define ws_info(cur) ((ws_info_t *) NULL) +#define ws_version_1_1(cur) (false) +#define ws_version_1_0(cur) (false) +#define ws_lfn_version_learned(cur) (false) +#define ws_neighbour_cap_pointer(neighbour) NULL +#define ws_test_proc_auto_trg(cur) (false) #define ws_common_seconds_timer(cur, seconds) #define ws_common_neighbor_update(cur, ll_address) ((void) 0) #define ws_common_black_list_neighbour(ll_address, nd_status) ((void) 0) @@ -207,6 +253,8 @@ void ws_common_border_router_alive_update(protocol_interface_info_entry_t *inter #define ws_common_primary_parent_update(interface, neighbor) #define ws_common_secondary_parent_update(interface) #define ws_common_border_router_alive_update(interface) ((void) 0) +#define ws_common_init(interface_id, bootstrap_mode) 0 +#define ws_common_state_machine(cur) #endif //HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h index 8ea6ab3f068..fa73a96ef61 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common_defines.h @@ -28,19 +28,40 @@ #define WH_IE_MHDS_TYPE 5 /**< MHDS information for mesh routing */ #define WH_IE_VH_TYPE 6 /**< Vendor header information */ #define WH_IE_EA_TYPE 9 /**< Eapol Auhtenticator EUI-64 header information */ +/* Wi-SUN FAN dfinition 1.1 */ +#define WH_IE_LUTT_TYPE 10 /**< LFN Unicast Timing and Frame Type information */ +#define WH_IE_LBT_TYPE 11 /**< LFN Broadcast Timing information */ +#define WH_IE_NR_TYPE 12 /**< Node Role IE information */ +#define WH_IE_LUS_TYPE 13 /**< LFN Unicast Schedule information */ +#define WH_IE_FLUS_TYPE 14 /**< FFN for LFN unicast Schedule information */ +#define WH_IE_LBS_TYPE 15 /**< LFN Broadcast Schedule information */ +#define WH_IE_LND_TYPE 16 /**< LFN Network Discovery information */ +#define WH_IE_LTO_TYPE 17 /**< LFN Timing information */ +#define WH_IE_PANID_TYPE 18 /**< PAN Identifier information */ + #define WS_WP_NESTED_IE 4 /**< WS nested Payload IE element'selement could include mltiple sub payload IE */ #define WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH 2 /* Payload IE sub elements in side WS_WP_NESTED_IE */ -#define WP_PAYLOAD_IE_US_TYPE 1 /**< Unicast Schedule information */ -#define WP_PAYLOAD_IE_BS_TYPE 2 /**< Broadcast Schedule information */ -#define WP_PAYLOAD_IE_VP_TYPE 3 /**< Vendor Payload information */ +/* Long form subID's */ +#define WP_PAYLOAD_IE_US_TYPE 1 /**< Unicast Schedule information */ +#define WP_PAYLOAD_IE_BS_TYPE 2 /**< Broadcast Schedule information */ +#define WP_PAYLOAD_IE_VP_TYPE 3 /**< Vendor Payload information */ +/* Wi-SUN FAN definition 1.1 */ +#define WP_PAYLOAD_IE_LFN_CHANNEL_PLAN_TYPE 4 /**< LFN Channel Plan information*/ + +/* Short form subID's */ #define WP_PAYLOAD_IE_PAN_TYPE 4 /**< PAN Information */ #define WP_PAYLOAD_IE_NETNAME_TYPE 5 /**< Network Name information */ #define WP_PAYLOAD_IE_PAN_VER_TYPE 6 /**< Pan configuration version */ #define WP_PAYLOAD_IE_GTKHASH_TYPE 7 /**< GTK Hash information */ +/* Wi-SUN FAN definition 1.1 */ +#define WP_PAYLOAD_IE_PCAP_TYPE 8 /**< PHY Capability information */ +#define WP_PAYLOAD_IE_LFNVER_TYPE 9 /**< LFN Version information */ +#define WP_PAYLOAD_IE_LGTKHASH_TYPE 10 /**< LFN GTK Hash Information */ + /* WS frame types to WH_IE_UTT_TYPE */ #define WS_FT_PAN_ADVERT 0 /**< PAN Advert */ @@ -50,14 +71,25 @@ #define WS_FT_DATA 4 /**< data type inside MPX */ #define WS_FT_ACK 5 /**< Enhanced ACK */ #define WS_FT_EAPOL 6 /**< EAPOL message inside MPX */ +/* Wi-SUN FAN 1.1 */ +#define WS_FT_LPA 9 /**< LFN PAN Advert */ +#define WS_FT_LPAS 10 /**< LFN PAN Advert Solicit */ +#define WS_FT_LPC 11 /**< LFN PAN Config */ +#define WS_FT_LPCS 12 /**< LFN PAN Config Solicit */ + /* WS exluded channel Control */ #define WS_EXC_CHAN_CTRL_NONE 0 /**< No excluded channels */ #define WS_EXC_CHAN_CTRL_RANGE 1 /**< Excluded channels are in 1 or multiple channel range */ -#define WS_EXC_CHAN_CTRL_BITMASK 2 /**< Excluded channels are marked to bitmask which length based on configured channels */ +#define WS_EXC_CHAN_CTRL_BITMASK 2 /**< Excluded channels are marked to bitmask which length based on configured channels */ #define WS_EXCLUDED_MAX_RANGE_TO_SEND 3 + +#define WS_NR_ROLE_BR 0 +#define WS_NR_ROLE_ROUTER 1 +#define WS_NR_ROLE_LFN 2 + /** * @brief ws_pan_information_t PAN information */ @@ -68,6 +100,7 @@ typedef struct ws_pan_information_s { bool use_parent_bs: 1; /**< 1 for force to follow parent broadcast schedule. 0 node may define own schedule. */ bool rpl_routing_method: 1; /**< 1 when RPL routing is selected and 0 when L2 routing. */ bool pan_version_set: 1; /**< 1 PAN version is set. */ + bool lfn_window_style: 1; /**< 1 FFN management trasmission. */ unsigned version: 3; /**< Pan version support. */ } ws_pan_information_t; @@ -125,6 +158,101 @@ typedef struct ws_utt_ie { uint_fast24_t ufsi; } ws_utt_ie_t; +/** + * @brief ws_utt_ie_t WS LUTT-IE + */ +typedef struct ws_lutt_ie { + uint8_t message_type; + uint16_t slot_number; + uint_fast24_t interval_offset; +} ws_lutt_ie_t; + +/** + * @brief ws_lbt_ie_t WS LBT-IE + */ +typedef struct ws_lbt_ie { + uint16_t slot_number; + uint_fast24_t interval_offset; +} ws_lbt_ie_t; + + +/** + * @brief ws_nr_ie_t WS NR-IE + */ +typedef struct ws_nr_ie { + unsigned node_role: 3; + uint8_t clock_drift; + uint8_t timing_accurancy; + uint_fast24_t listen_interval_min; + uint_fast24_t listen_interval_max; +} ws_nr_ie_t; + + +/** + * @brief ws_lus_ie_t WS LUS-IE + */ +typedef struct ws_lus_ie { + uint8_t channel_plan_tag; + uint_fast24_t listen_interval; +} ws_lus_ie_t; + +/** + * @brief ws_lus_ie_t WS FLUS-IE + */ +typedef struct ws_flus_ie { + uint8_t channel_plan_tag; + uint8_t dwell_interval; +} ws_flus_ie_t; + +/** + * @brief ws_lnd_ie_t WS LND-IE + */ +typedef struct ws_lnd_ie { + uint8_t response_threshold; + uint8_t discovery_slot_time; + uint8_t discovery_slots; + uint16_t discovery_first_slot; + uint_fast24_t response_delay; +} ws_lnd_ie_t; + +/** + * @brief ws_lto_ie_t WS LTO-IE + */ +typedef struct ws_lto_ie { + uint_fast24_t offset; + uint_fast24_t adjusted_listening_interval; +} ws_lto_ie_t; + +/** + * @brief ws_lbs_ie_t WS LBS-IE + */ +typedef struct ws_lbs_ie { + uint8_t channel_plan_tag; + uint16_t broadcast_secheduler_id; + uint_fast24_t broadcast_interval; +} ws_lbs_ie_t; + + +/** + * @brief ws_panid_ie_t WS PANID-IE + */ +typedef struct ws_panid_ie { + uint16_t panid; +} ws_panid_ie_t; + +/** + * @brief ws_pcap_ie_t WS PCAB-IE + */ +typedef struct ws_pcap_ie { + unsigned phy_type: 3; + uint16_t operating_mode; +} ws_pcap_ie_t; + +typedef struct ws_phy_cap_info { + unsigned length_of_list: 3; + ws_pcap_ie_t pcap[7]; +} ws_phy_cap_info_t; + /** * @brief ws_bt_ie_t WS BT-IE read */ @@ -141,6 +269,26 @@ typedef struct ws_fc_ie { uint8_t rx_flow_ctrl; } ws_fc_ie_t; +/** + * @brief ws_lfnver_ie_t WS LFNVER-IE element + */ +typedef struct ws_lfnver_ie { + uint16_t lfn_version; +} ws_lfnver_ie_t; + +/** + * @brief ws_lgtkhash_ie_t WS LGTKHASH-IE element + */ +typedef struct ws_lgtkhash_ie { + bool lgtk0: 1; /**< 1= LGTK0 in line 0 = elided */ + bool lgtk1: 1; /**< 1= LGTK1 in line 0 = elided */ + bool lgtk2: 1; /**< 1= LGTK2 in line 0 = elided */ + unsigned active_lgtk_index: 2; /**< Indicate Active LGTK index 0-2 */ + uint8_t *lgtk0_hash; /**< LGTK0 64-bit Hash if lgtk0=1*/ + uint8_t *lgtk1_hash; /**< LGTK1 64-bit Hash if lgtk1=1*/ + uint8_t *lgtk2_hash; /**< LGTK2 64-bit Hash if lgtk2=1*/ +} ws_lgtkhash_ie_t; + /** * @brief ws_channel_plan_zero_t WS channel plan 0 define domain and class */ @@ -158,6 +306,14 @@ typedef struct ws_channel_plan_one { uint16_t number_of_channel; } ws_channel_plan_one_t; +/** + * @brief ws_channel_plan_two_t WS channel plan 2 define regulator domain and chanel plan 1 + */ +typedef struct ws_channel_plan_two { + uint8_t regulator_domain; + uint8_t channel_plan_id; +} ws_channel_plan_two_t; + /** * @brief ws_channel_function_zero_t WS function 0 fixed channel */ @@ -189,6 +345,43 @@ typedef struct ws_excluded_channel_mask { uint8_t mask_len_inline; } ws_excluded_channel_mask_t; + +typedef struct ws_excluded_channel_range_out { + unsigned excluded_range_length: 3; + ws_excluded_channel_range_data_t *exluded_range; +} ws_excluded_channel_range_out_t; + + +typedef struct ws_excluded_channel_mask_out { + uint16_t excluded_channel_count; + uint8_t channel_mask_bytes_inline; + uint32_t *channel_mask; +} ws_excluded_channel_mask_out_t; + +/** + * @brief ws_generic_channel_info_t Generic Channel Info + */ +typedef struct ws_generic_channel_info { + unsigned channel_plan: 3; + unsigned channel_function: 3; + unsigned excluded_channel_ctrl: 2; + union { + ws_channel_plan_zero_t zero; + ws_channel_plan_one_t one; + ws_channel_plan_two_t two; + } plan; + union { + ws_channel_function_zero_t zero; + ws_channel_function_three_t three; + } function; + union { + ws_excluded_channel_range_out_t range; + ws_excluded_channel_mask_out_t mask; + ws_excluded_channel_range_t range_in; + ws_excluded_channel_mask_t mask_in; + } excluded_channels; +} ws_generic_channel_info_t; + /** * @brief ws_us_ie_t WS US-IE read */ @@ -202,6 +395,7 @@ typedef struct ws_us_ie { union { ws_channel_plan_zero_t zero; ws_channel_plan_one_t one; + ws_channel_plan_two_t two; } plan; union { ws_channel_function_zero_t zero; @@ -228,6 +422,7 @@ typedef struct ws_bs_ie { union { ws_channel_plan_zero_t zero; ws_channel_plan_one_t one; + ws_channel_plan_two_t two; } plan; union { ws_channel_function_zero_t zero; @@ -247,6 +442,7 @@ typedef struct ws_bs_ie { #define WS_MPX_MAX_MTU 1576 #define WS_FAN_VERSION_1_0 1 +#define WS_FAN_VERSION_1_1 2 #define WS_NEIGHBOR_LINK_TIMEOUT 2200 @@ -381,9 +577,9 @@ typedef struct ws_bs_ie { /* Default FHSS timing information * */ -#define WS_FHSS_UC_DWELL_INTERVAL 255; -#define WS_FHSS_BC_INTERVAL 1020; -#define WS_FHSS_BC_DWELL_INTERVAL 255; +#define WS_FHSS_UC_DWELL_INTERVAL 255 +#define WS_FHSS_BC_INTERVAL 1020 +#define WS_FHSS_BC_DWELL_INTERVAL 255 /* * EAPOL relay and PAE authenticator socket settings diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h index 49723f009b4..d2715783a31 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h @@ -97,7 +97,7 @@ #define PAN_VERSION_SMALL_NETWORK_TIMEOUT 30*60 -#define PAN_VERSION_MEDIUM_NETWORK_TIMEOUT 60*60 +#define PAN_VERSION_MEDIUM_NETWORK_TIMEOUT 30*60 #define PAN_VERSION_LARGE_NETWORK_TIMEOUT 90*60 @@ -246,15 +246,21 @@ extern uint8_t DEVICE_MIN_SENS; * * Trickle is reset on start (inconsistent heard is set) */ +#define SEC_PROT_TIMER_EXPIRATIONS 4 // Number of retries +#define SEC_PROT_END_DELAY 30 // 30 seconds delay + #define SEC_PROT_SMALL_IMIN 60 // Retries done in 60 seconds #define SEC_PROT_SMALL_IMAX 120 // Largest value 120 seconds -#define SEC_PROT_RETRY_TIMEOUT_SMALL 450 // Retry timeout for small network additional 30 seconds for authenticator delay +// Retry timeout for small network; additional 30 seconds for authenticator delay +#define SEC_PROT_RETRY_TIMEOUT_SMALL (SEC_PROT_SMALL_IMAX * SEC_PROT_TIMER_EXPIRATIONS + SEC_PROT_END_DELAY) #define SEC_PROT_LARGE_IMIN 60 // Retries done in 60 seconds #define SEC_PROT_LARGE_IMAX 240 // Largest value 240 seconds -#define SEC_PROT_RETRY_TIMEOUT_LARGE 750 // Retry timeout for large network additional 30 seconds for authenticator delay +// Retry timeout for large network; additional 30 seconds for authenticator delay +#define SEC_PROT_RETRY_TIMEOUT_LARGE (SEC_PROT_LARGE_IMAX * SEC_PROT_TIMER_EXPIRATIONS + SEC_PROT_END_DELAY) -#define SEC_PROT_TIMER_EXPIRATIONS 4 // Number of retries +// Timeout for retrying side of the protocol (runs when trickle not running) +#define SEC_PROT_RETRYING_PROTOCOL_TIMEOUT (5 * 60 * 10) // 5 minutes in ticks // Maximum number of simultaneous security negotiations #define MAX_SIMULTANEOUS_SECURITY_NEGOTIATIONS_TX_QUEUE_MIN 64 diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c index f7e14fdb798..f070e20ac5e 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_empty_functions.c @@ -26,6 +26,7 @@ #include "ws_management_api.h" #include "ns_time_api.h" +#include "net_ws_test_ext.h" #ifndef HAVE_WS int ws_management_node_init( @@ -362,6 +363,12 @@ int ws_management_timing_parameters_validate( } /* ### test api ### */ +int ws_test_version_set(int8_t interface_id, uint8_t version) +{ + (void) interface_id; + (void) version; + return -1; +} int ws_test_pan_size_set(int8_t interface_id, uint16_t pan_size) { (void) interface_id; @@ -488,5 +495,22 @@ int8_t ws_test_drop_edfe_data_frames(int8_t interface_id, uint8_t number_of_dro return -1; } +int ws_test_procedure_trigger(int8_t interface_id, ws_test_proc_t procedure, void *parameters) +{ + (void) interface_id; + (void) procedure; + (void) parameters; + return -1; +} + +int ws_management_phy_capability_set( + int8_t interface_id, + ws_management_pcap_info_t *pcap_list) +{ + (void)interface_id; + (void)pcap_list; + return -1; +} + #endif // no HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c index 5edd436dbce..820ff86ed77 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.c @@ -25,6 +25,7 @@ #include "6LoWPAN/MAC/mac_ie_lib.h" #include "6LoWPAN/ws/ws_common_defines.h" #include "6LoWPAN/ws/ws_ie_lib.h" +#include "ws_management_api.h" static uint8_t *ws_wh_header_base_write(uint8_t *ptr, uint16_t length, uint8_t type) { @@ -42,6 +43,9 @@ static uint16_t ws_channel_plan_length(uint8_t channel_plan) case 1: //CHo, Channel spasing and number of channel's inline return 6; + case 2: + //Regulator domain and channel plan ID inline + return 2; default: return 0; @@ -66,29 +70,120 @@ static uint16_t ws_channel_function_length(uint8_t channel_function, uint16_t ho } } -uint16_t ws_wp_nested_hopping_schedule_length(struct ws_hopping_schedule_s *hopping_schedule, bool unicast_schedule) +static uint16_t ws_excluded_channel_length(ws_generic_channel_info_t *generic_channel_info) { uint16_t length; - uint8_t channel_function; + if (generic_channel_info->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + length = (generic_channel_info->excluded_channels.range.excluded_range_length * 4) + 1; + } else if (generic_channel_info->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { + length = generic_channel_info->excluded_channels.mask.channel_mask_bytes_inline; + } else { + length = 0; + } + return length; +} + +static void ws_generic_channel_info_init(struct ws_hopping_schedule_s *hopping_schedule, ws_generic_channel_info_t *generic_channel_info, bool unicast_schedule) +{ + generic_channel_info->channel_plan = hopping_schedule->channel_plan; if (unicast_schedule) { - length = 4; - channel_function = hopping_schedule->uc_channel_function; + generic_channel_info->channel_function = hopping_schedule->uc_channel_function; + generic_channel_info->excluded_channel_ctrl = hopping_schedule->excluded_channels.excuded_channel_ctrl; + if (generic_channel_info->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + generic_channel_info->excluded_channels.range.excluded_range_length = hopping_schedule->excluded_channels.excluded_range_length; + generic_channel_info->excluded_channels.range.exluded_range = hopping_schedule->excluded_channels.exluded_range; + } else if (generic_channel_info->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { + generic_channel_info->excluded_channels.mask.channel_mask_bytes_inline = hopping_schedule->excluded_channels.channel_mask_bytes_inline; + generic_channel_info->excluded_channels.mask.excluded_channel_count = hopping_schedule->excluded_channels.excluded_channel_count; + generic_channel_info->excluded_channels.mask.channel_mask = hopping_schedule->excluded_channels.channel_mask; + } } else { - length = 10; - channel_function = hopping_schedule->bc_channel_function; + generic_channel_info->channel_function = hopping_schedule->bc_channel_function; + generic_channel_info->excluded_channel_ctrl = WS_EXC_CHAN_CTRL_NONE; } +} - length += ws_channel_plan_length(hopping_schedule->channel_plan); +static void ws_wp_channel_plan_set(ws_generic_channel_info_t *generic_channel_info, struct ws_hopping_schedule_s *hopping_schedule) +{ + switch (generic_channel_info->channel_plan) { + case 0: + //Regulator domain and operationg class inline + generic_channel_info->plan.zero.regulator_domain = hopping_schedule->regulatory_domain; + generic_channel_info->plan.zero.operation_class = hopping_schedule->operating_class; + break; + case 1: + //CHo, Channel spasing and number of channel's inline + generic_channel_info->plan.one.ch0 = hopping_schedule->ch0_freq; + generic_channel_info->plan.one.channel_spacing = hopping_schedule->channel_spacing; + generic_channel_info->plan.one.number_of_channel = hopping_schedule->number_of_channels; + break; + case 2: + generic_channel_info->plan.two.regulator_domain = hopping_schedule->regulatory_domain; + generic_channel_info->plan.two.channel_plan_id = hopping_schedule->channel_plan_id; + break; + default: + break; + } +} - length += ws_channel_function_length(channel_function, 1); +static void ws_wp_channel_function_set(ws_generic_channel_info_t *generic_channel_info, struct ws_hopping_schedule_s *hopping_schedule, bool unicast_schedule) +{ + switch (generic_channel_info->channel_function) { + case 0: + //Fixed channel inline + if (unicast_schedule) { + generic_channel_info->function.zero.fixed_channel = hopping_schedule->uc_fixed_channel; + } else { + generic_channel_info->function.zero.fixed_channel = hopping_schedule->bc_fixed_channel; + } + break; + case 1: + case 2: + //No Inline + break; + case 3: + //TODO add list to possible to set + //Force 1 channel 0 + generic_channel_info->function.three.channel_hop_count = 1; + generic_channel_info->function.three.channel_list = NULL; + break; + default: + break; - if (unicast_schedule && hopping_schedule->excluded_channels.excuded_channel_ctrl) { - if (hopping_schedule->excluded_channels.excuded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { - length += (hopping_schedule->excluded_channels.excluded_range_length * 4) + 1; - } else { - length += hopping_schedule->excluded_channels.channel_mask_bytes_inline; - } } +} + +static uint16_t ws_wp_generic_shedule_length_get(ws_generic_channel_info_t *generic_channel_info) +{ + uint16_t length = 1; + + length += ws_channel_plan_length(generic_channel_info->channel_plan); + uint16_t number_of_channels = 1; + if (generic_channel_info->channel_plan == 3) { + number_of_channels = generic_channel_info->function.three.channel_hop_count; + } else { + number_of_channels = 1; + } + length += ws_channel_function_length(generic_channel_info->channel_function, number_of_channels); + + length += ws_excluded_channel_length(generic_channel_info); + + return length; +} + +uint16_t ws_wp_nested_hopping_schedule_length(struct ws_hopping_schedule_s *hopping_schedule, bool unicast_schedule) +{ + ws_generic_channel_info_t generic_channel_info; + + ws_generic_channel_info_init(hopping_schedule, &generic_channel_info, unicast_schedule); + ws_wp_channel_function_set(&generic_channel_info, hopping_schedule, unicast_schedule); + uint16_t length; + if (unicast_schedule) { + length = 3; + } else { + length = 9; + } + length += ws_wp_generic_shedule_length_get(&generic_channel_info); return length; } @@ -143,66 +238,152 @@ uint8_t *ws_wh_vh_write(uint8_t *ptr, uint8_t *vendor_header, uint8_t vendor_hea return ptr; } -uint8_t *ws_wp_base_write(uint8_t *ptr, uint16_t length) +uint8_t *ws_wh_lutt_write(uint8_t *ptr, uint8_t message_type) { - return mac_ie_payload_base_write(ptr, WS_WP_NESTED_IE, length); + ptr = ws_wh_header_base_write(ptr, ws_wh_lutt_length(), WH_IE_LUTT_TYPE); + *ptr++ = message_type; + //Set 0 for next 5 bytes which will be initializwed by FHSS + memset(ptr, 0, 5); /* Unicast Slot Number 2 bytes, UFSI 3 bytes */ + ptr += 5; + return ptr; } -uint8_t *ws_wp_nested_hopping_schedule_write(uint8_t *ptr, struct ws_hopping_schedule_s *hopping_schedule, bool unicast_schedule) +uint8_t *ws_wh_lus_write(uint8_t *ptr, struct ws_lus_ie *lus_ptr) { - //Calculate length - uint16_t length = ws_wp_nested_hopping_schedule_length(hopping_schedule, unicast_schedule); - if (!unicast_schedule) { - ptr = mac_ie_nested_ie_long_base_write(ptr, WP_PAYLOAD_IE_BS_TYPE, length); - ptr = common_write_32_bit_inverse(hopping_schedule->fhss_broadcast_interval, ptr); - ptr = common_write_16_bit_inverse(hopping_schedule->fhss_bsi, ptr); - *ptr++ = hopping_schedule->fhss_bc_dwell_interval; + ptr = ws_wh_header_base_write(ptr, ws_wh_lus_length(), WH_IE_LUS_TYPE); + ptr = common_write_24_bit_inverse(lus_ptr->listen_interval, ptr); + *ptr++ = lus_ptr->channel_plan_tag; + return ptr; +} + +uint8_t *ws_wh_flus_write(uint8_t *ptr, struct ws_flus_ie *flus_ptr) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_flus_length(), WH_IE_FLUS_TYPE); + *ptr++ = flus_ptr->dwell_interval; + *ptr++ = flus_ptr->channel_plan_tag; + return ptr; +} + +uint8_t *ws_wh_lbt_write(uint8_t *ptr) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_lbt_length(), WH_IE_LBT_TYPE); + //Set 0 for next 5 bytes which will be initializwed by FHSS + memset(ptr, 0, ws_wh_lbt_length()); /* LFN Broadcast Slot Number 2 bytes, LFN Broadcast Interval Offset 3 bytes */ + ptr += ws_wh_lbt_length(); + return ptr; + +} + +uint8_t *ws_wh_lbs_write(uint8_t *ptr, struct ws_lbs_ie *lbs_ptr) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_lbs_length(), WH_IE_LBS_TYPE); + ptr = common_write_24_bit_inverse(lbs_ptr->broadcast_interval, ptr); + ptr = common_write_16_bit_inverse(lbs_ptr->broadcast_secheduler_id, ptr); + *ptr++ = lbs_ptr->channel_plan_tag; + return ptr; +} + +uint16_t ws_wh_nr_length(struct ws_nr_ie *nr_ptr) +{ + uint16_t length; + if (nr_ptr->node_role == WS_NR_ROLE_LFN) { + length = 9; } else { - ptr = mac_ie_nested_ie_long_base_write(ptr, WP_PAYLOAD_IE_US_TYPE, length); - *ptr++ = hopping_schedule->fhss_uc_dwell_interval; + length = 3; } + return length; +} - *ptr++ = hopping_schedule->clock_drift; - *ptr++ = hopping_schedule->timing_accurancy; - uint8_t channel_info_base = 0; - channel_info_base = (hopping_schedule->channel_plan); - if (unicast_schedule) { - channel_info_base |= (hopping_schedule->uc_channel_function << 3); - //Set Excluded Channel control part - channel_info_base |= (hopping_schedule->excluded_channels.excuded_channel_ctrl << 6); - } else { - channel_info_base |= (hopping_schedule->bc_channel_function << 3); + +uint8_t *ws_wh_nr_write(uint8_t *ptr, struct ws_nr_ie *nr_ptr) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_nr_length(nr_ptr), WH_IE_NR_TYPE); + *ptr++ = nr_ptr->node_role; + *ptr++ = nr_ptr->clock_drift; + *ptr++ = nr_ptr->timing_accurancy; + if (nr_ptr->node_role == WS_NR_ROLE_LFN) { + ptr = common_write_24_bit_inverse(nr_ptr->listen_interval_min, ptr); + ptr = common_write_24_bit_inverse(nr_ptr->listen_interval_max, ptr); } + return ptr; +} + +uint8_t *ws_wh_lnd_write(uint8_t *ptr, struct ws_lnd_ie *lnd_ptr) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_lnd_length(), WH_IE_LND_TYPE); + *ptr++ = lnd_ptr->response_threshold; + ptr = common_write_24_bit_inverse(lnd_ptr->response_delay, ptr); + *ptr++ = lnd_ptr->discovery_slot_time; + *ptr++ = lnd_ptr->discovery_slots; + ptr = common_write_16_bit_inverse(lnd_ptr->discovery_first_slot, ptr); + return ptr; +} + +uint8_t *ws_wh_lto_write(uint8_t *ptr, struct ws_lto_ie *lto_ptr) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_lto_length(), WH_IE_LTO_TYPE); + ptr = common_write_24_bit_inverse(lto_ptr->offset, ptr); + ptr = common_write_24_bit_inverse(lto_ptr->adjusted_listening_interval, ptr); + return ptr; +} + + +uint8_t *ws_wh_panid_write(uint8_t *ptr, uint16_t pana_id) +{ + ptr = ws_wh_header_base_write(ptr, ws_wh_panid_length(), WH_IE_PANID_TYPE); + //TODO need to be check byte order + ptr = common_write_16_bit_inverse(pana_id, ptr); + return ptr; +} + + + +uint8_t *ws_wp_base_write(uint8_t *ptr, uint16_t length) +{ + return mac_ie_payload_base_write(ptr, WS_WP_NESTED_IE, length); +} + +static uint8_t ws_wp_channel_info_base_get(ws_generic_channel_info_t *generic_channel_info) +{ + uint8_t channel_info_base = 0; + channel_info_base = generic_channel_info->channel_plan; + channel_info_base |= (generic_channel_info->channel_function << 3); + //Set Excluded Channel control part + channel_info_base |= (generic_channel_info->excluded_channel_ctrl << 6); - *ptr++ = channel_info_base; + return channel_info_base; +} - switch (hopping_schedule->channel_plan) { +static uint8_t *ws_wp_channel_plan_write(uint8_t *ptr, ws_generic_channel_info_t *generic_channel_info) +{ + switch (generic_channel_info->channel_plan) { case 0: //Regulator domain and operationg class inline - *ptr++ = hopping_schedule->regulatory_domain; - *ptr++ = hopping_schedule->operating_class; + *ptr++ = generic_channel_info->plan.zero.regulator_domain; + *ptr++ = generic_channel_info->plan.zero.operation_class; break; case 1: //CHo, Channel spasing and number of channel's inline - ptr = common_write_24_bit_inverse(hopping_schedule->ch0_freq * 100, ptr); - *ptr++ = hopping_schedule->channel_spacing; - ptr = common_write_16_bit_inverse(hopping_schedule->number_of_channels, ptr); + ptr = common_write_24_bit_inverse(generic_channel_info->plan.one.ch0 * 100, ptr); + *ptr++ = generic_channel_info->plan.one.channel_spacing; + ptr = common_write_16_bit_inverse(generic_channel_info->plan.one.number_of_channel, ptr); + break; + case 2: + *ptr++ = generic_channel_info->plan.two.regulator_domain; + *ptr++ = generic_channel_info->plan.two.channel_plan_id; break; default: break; } - uint8_t cf = hopping_schedule->uc_channel_function; - uint16_t fixed_channel = hopping_schedule->uc_fixed_channel; - if (!unicast_schedule) { - cf = hopping_schedule->bc_channel_function; - } - switch (cf) { + return ptr; +} + +static uint8_t *ws_wp_channel_function_write(uint8_t *ptr, ws_generic_channel_info_t *generic_channel_info) +{ + switch (generic_channel_info->channel_function) { case 0: //Fixed channel inline - if (!unicast_schedule) { - fixed_channel = hopping_schedule->bc_fixed_channel; - } - ptr = common_write_16_bit_inverse(fixed_channel, ptr); + ptr = common_write_16_bit_inverse(generic_channel_info->function.zero.fixed_channel, ptr); break; case 1: case 2: @@ -211,50 +392,97 @@ uint8_t *ws_wp_nested_hopping_schedule_write(uint8_t *ptr, struct ws_hopping_sch case 3: //TODO do this properly //Hop count + channel hop list - *ptr++ = 1; - *ptr++ = 0; + if (generic_channel_info->function.three.channel_list && generic_channel_info->function.three.channel_hop_count) { + *ptr++ = generic_channel_info->function.three.channel_hop_count; + memcpy(ptr, generic_channel_info->function.three.channel_list, generic_channel_info->function.three.channel_hop_count); + ptr += generic_channel_info->function.three.channel_hop_count; + } else { + *ptr++ = 1; + *ptr++ = 0; + } + break; default: break; } + return ptr; +} - if (unicast_schedule && hopping_schedule->excluded_channels.excuded_channel_ctrl) { - if (hopping_schedule->excluded_channels.excuded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { - uint8_t range_length = hopping_schedule->excluded_channels.excluded_range_length; - ws_excluded_channel_range_data_t *range_ptr = hopping_schedule->excluded_channels.exluded_range; - *ptr++ = range_length; - while (range_length) { - ptr = common_write_16_bit_inverse(range_ptr->range_start, ptr); - ptr = common_write_16_bit_inverse(range_ptr->range_end, ptr); - range_length--; - range_ptr++; - } - } else if (hopping_schedule->excluded_channels.excuded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { - //Set Mask - uint16_t channel_mask_length = hopping_schedule->excluded_channels.channel_mask_bytes_inline * 8; - - for (uint8_t i = 0; i < 8; i++) { - uint32_t mask_value = hopping_schedule->excluded_channels.channel_mask[i]; - if (channel_mask_length >= 32) { - ptr = common_write_32_bit(mask_value, ptr); - channel_mask_length -= 32; - } else { - //Write MSB Bits from mask 24-8 top bits - uint8_t move_mask = 0; - while (channel_mask_length) { - *ptr++ = (uint8_t)(mask_value >> (24 - move_mask)); - channel_mask_length -= 8; - move_mask += 8; - } +static uint8_t *ws_wp_nested_excluded_channel_write(uint8_t *ptr, ws_generic_channel_info_t *generic_channel_info) +{ + if (generic_channel_info->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + uint8_t range_length = generic_channel_info->excluded_channels.range.excluded_range_length; + ws_excluded_channel_range_data_t *range_ptr = generic_channel_info->excluded_channels.range.exluded_range; + *ptr++ = range_length; + while (range_length) { + ptr = common_write_16_bit_inverse(range_ptr->range_start, ptr); + ptr = common_write_16_bit_inverse(range_ptr->range_end, ptr); + range_length--; + range_ptr++; + } + } else if (generic_channel_info->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { + //Set Mask + uint16_t channel_mask_length = generic_channel_info->excluded_channels.mask.channel_mask_bytes_inline * 8; + + for (uint8_t i = 0; i < 8; i++) { + uint32_t mask_value = generic_channel_info->excluded_channels.mask.channel_mask[i]; + if (channel_mask_length >= 32) { + ptr = common_write_32_bit(mask_value, ptr); + channel_mask_length -= 32; + } else { + //Write MSB Bits from mask 24-8 top bits + uint8_t move_mask = 0; + while (channel_mask_length) { + *ptr++ = (uint8_t)(mask_value >> (24 - move_mask)); + channel_mask_length -= 8; + move_mask += 8; } + } - if (channel_mask_length == 0) { - break; - } + if (channel_mask_length == 0) { + break; } } } + return ptr; +} + +uint8_t *ws_wp_nested_hopping_schedule_write(uint8_t *ptr, struct ws_hopping_schedule_s *hopping_schedule, bool unicast_schedule) +{ + //Calculate length + ws_generic_channel_info_t generic_channel_info; + + ws_generic_channel_info_init(hopping_schedule, &generic_channel_info, unicast_schedule); + ws_wp_channel_plan_set(&generic_channel_info, hopping_schedule); + ws_wp_channel_function_set(&generic_channel_info, hopping_schedule, unicast_schedule); + + uint16_t length; + if (unicast_schedule) { + length = 3; + } else { + length = 9; + } + length += ws_wp_generic_shedule_length_get(&generic_channel_info); + + if (!unicast_schedule) { + ptr = mac_ie_nested_ie_long_base_write(ptr, WP_PAYLOAD_IE_BS_TYPE, length); + ptr = common_write_32_bit_inverse(hopping_schedule->fhss_broadcast_interval, ptr); + ptr = common_write_16_bit_inverse(hopping_schedule->fhss_bsi, ptr); + *ptr++ = hopping_schedule->fhss_bc_dwell_interval; + } else { + ptr = mac_ie_nested_ie_long_base_write(ptr, WP_PAYLOAD_IE_US_TYPE, length); + *ptr++ = hopping_schedule->fhss_uc_dwell_interval; + } + + *ptr++ = hopping_schedule->clock_drift; + *ptr++ = hopping_schedule->timing_accurancy; + + // Write a generic part of shedule + *ptr++ = ws_wp_channel_info_base_get(&generic_channel_info); + ptr = ws_wp_channel_plan_write(ptr, &generic_channel_info); + ptr = ws_wp_channel_function_write(ptr, &generic_channel_info); + ptr = ws_wp_nested_excluded_channel_write(ptr, &generic_channel_info); return ptr; } @@ -280,7 +508,12 @@ uint8_t *ws_wp_nested_pan_info_write(uint8_t *ptr, struct ws_pan_information_s * uint8_t temp8 = 0; temp8 |= (pan_congiguration->use_parent_bs << 0); temp8 |= (pan_congiguration->rpl_routing_method << 1); + /* FAN 1.1 specific write */ + if (pan_congiguration->version > WS_FAN_VERSION_1_0) { + temp8 |= (pan_congiguration->lfn_window_style << 2); + } temp8 |= pan_congiguration->version << 5; + *ptr++ = temp8; return ptr; } @@ -315,11 +548,202 @@ uint8_t *ws_wp_nested_gtkhash_write(uint8_t *ptr, uint8_t *gtkhash, uint8_t gtkh return ptr; } +uint16_t ws_wp_nested_pcap_length(uint8_t list_length) +{ + uint16_t lenght = (list_length * 3) + 1; + return lenght; +} + +void ws_ie_lib_phy_cap_list_update(struct ws_phy_cap_info *phy_pap, struct ws_pcap_ie *pcap) +{ + for (int i = 0; i < phy_pap->length_of_list; i++) { + if (phy_pap->pcap[i].phy_type == pcap->phy_type) { + phy_pap->pcap[i].operating_mode |= pcap->operating_mode; + return; + } + } + + if (phy_pap->length_of_list == 7) { + return; + } + + phy_pap->pcap[phy_pap->length_of_list].phy_type = pcap->phy_type; + phy_pap->pcap[phy_pap->length_of_list].operating_mode |= pcap->operating_mode; + phy_pap->length_of_list++; +} + + +ws_pcap_ie_t ws_ie_lib_generate_phy_cap_from_phy_mode_id(uint8_t phy_mode_id) +{ + ws_pcap_ie_t pcap; + if (phy_mode_id > 96) { + pcap.operating_mode = 0; + return pcap; + } + + if (phy_mode_id < 16) { + pcap.phy_type = WS_PHY_TYPE_ID_FSK; + } else if (phy_mode_id < 32) { + phy_mode_id -= 16; + pcap.phy_type = WS_PHY_TYPE_ID_FSK_FEC; + } else if (phy_mode_id < 48) { + phy_mode_id -= 32; + pcap.phy_type = WS_PHY_TYPE_ID_OFDM1; + } else if (phy_mode_id < 64) { + phy_mode_id -= 48; + pcap.phy_type = WS_PHY_TYPE_ID_OFDM2; + } else if (phy_mode_id < 80) { + phy_mode_id -= 64; + pcap.phy_type = WS_PHY_TYPE_ID_OFDM3; + } else { + phy_mode_id -= 80; + pcap.phy_type = WS_PHY_TYPE_ID_OFDM4; + } + pcap.operating_mode = 1 << phy_mode_id; + return pcap; +} + +uint8_t ws_ie_lib_phy_mode_id_get_from_phy_cap(ws_pcap_ie_t *phy_cap) +{ + if (!phy_cap->operating_mode) { + return 0; + } + + uint8_t phy_mode_id = 0; + for (uint8_t i = 0; i < 16; i++) { + if (phy_cap->operating_mode & (1 << (15 - i))) { + phy_mode_id = 15 - i; + break; + } + } + + switch (phy_cap->phy_type) { + case WS_PHY_TYPE_ID_FSK: + break; + case WS_PHY_TYPE_ID_FSK_FEC: + phy_mode_id += 16; + break; + case WS_PHY_TYPE_ID_OFDM1: + phy_mode_id += 32; + break; + case WS_PHY_TYPE_ID_OFDM2: + phy_mode_id += 48; + break; + case WS_PHY_TYPE_ID_OFDM3: + phy_mode_id += 64; + break; + case WS_PHY_TYPE_ID_OFDM4: + phy_mode_id += 80; + break; + default: + break; + } + + return phy_mode_id; + +} + +uint8_t *ws_wp_nested_pcap_write(uint8_t *ptr, struct ws_phy_cap_info *pcap_list) +{ + uint16_t lenght = ws_wp_nested_pcap_length(pcap_list->length_of_list); + + ptr = mac_ie_nested_ie_short_base_write(ptr, WP_PAYLOAD_IE_PCAP_TYPE, lenght); + *ptr++ = pcap_list->length_of_list; + for (int i = 0; i < pcap_list->length_of_list; i++) { + *ptr++ = pcap_list->pcap[i].phy_type; + ptr = common_write_16_bit_inverse(pcap_list->pcap[i].operating_mode, ptr); + } + return ptr; +} + + +uint8_t *ws_wp_nested_lfn_version_write(uint8_t *ptr, struct ws_lfnver_ie *ws_lfnver) +{ + ptr = mac_ie_nested_ie_short_base_write(ptr, WP_PAYLOAD_IE_LFNVER_TYPE, ws_wp_nested_lfn_version_length()); + ptr = common_write_16_bit_inverse(ws_lfnver->lfn_version, ptr); + + return ptr; +} + + +uint16_t ws_wp_lgtk_hash_length(struct ws_lgtkhash_ie *ws_lgtkhash) +{ + uint16_t length = 1; + + if (ws_lgtkhash->lgtk0) { + length += 8; + } + + if (ws_lgtkhash->lgtk1) { + length += 8; + } + + if (ws_lgtkhash->lgtk2) { + length += 8; + } + return length; +} + +uint8_t *ws_wp_nested_lgtk_hash_write(uint8_t *ptr, struct ws_lgtkhash_ie *ws_lgtkhash) +{ + uint16_t length = ws_wp_lgtk_hash_length(ws_lgtkhash); + + ptr = mac_ie_nested_ie_short_base_write(ptr, WP_PAYLOAD_IE_LGTKHASH_TYPE, length); + + uint8_t temp8 = 0; + temp8 |= (ws_lgtkhash->lgtk0 << 0); + temp8 |= (ws_lgtkhash->lgtk1 << 1); + temp8 |= (ws_lgtkhash->lgtk2 << 2); + temp8 |= (ws_lgtkhash->active_lgtk_index << 3); + + *ptr++ = temp8; + if (ws_lgtkhash->lgtk0) { + memcpy(ptr, ws_lgtkhash->lgtk0_hash, 8); + ptr += 8; + } + + if (ws_lgtkhash->lgtk1) { + memcpy(ptr, ws_lgtkhash->lgtk1_hash, 8); + ptr += 8; + } + + if (ws_lgtkhash->lgtk2) { + memcpy(ptr, ws_lgtkhash->lgtk2_hash, 8); + ptr += 8; + } + + return ptr; +} + +uint16_t ws_wp_nested_lfn_channel_plan_length(ws_generic_channel_info_t *ws_lcp) +{ + uint16_t length = 1; //Channel Plan Tag + + length += ws_wp_generic_shedule_length_get(ws_lcp); + return length; +} + +uint8_t *ws_wp_nested_lfn_channel_plan_write(uint8_t *ptr, ws_generic_channel_info_t *ws_lcp, uint8_t plan_tag_id) +{ + uint16_t length = ws_wp_nested_lfn_channel_plan_length(ws_lcp); + + ptr = mac_ie_nested_ie_long_base_write(ptr, WP_PAYLOAD_IE_LFN_CHANNEL_PLAN_TYPE, length); + *ptr++ = plan_tag_id; + *ptr++ = ws_wp_channel_info_base_get(ws_lcp); + ptr = ws_wp_channel_plan_write(ptr, ws_lcp); + ptr = ws_wp_channel_function_write(ptr, ws_lcp); + ptr = ws_wp_nested_excluded_channel_write(ptr, ws_lcp); + return ptr; + +} + + + bool ws_wh_utt_read(uint8_t *data, uint16_t length, struct ws_utt_ie *utt_ie) { mac_header_IE_t utt_ie_data; utt_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; - if (4 != mac_ie_header_sub_id_discover(data, length, &utt_ie_data, WH_IE_UTT_TYPE)) { + if (4 > mac_ie_header_sub_id_discover(data, length, &utt_ie_data, WH_IE_UTT_TYPE)) { // NO UTT header return false; } @@ -333,7 +757,7 @@ bool ws_wh_bt_read(uint8_t *data, uint16_t length, struct ws_bt_ie *bt_ie) { mac_header_IE_t btt_ie_data; btt_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; - if (5 != mac_ie_header_sub_id_discover(data, length, &btt_ie_data, WH_IE_BT_TYPE)) { + if (5 > mac_ie_header_sub_id_discover(data, length, &btt_ie_data, WH_IE_BT_TYPE)) { return false; } data = btt_ie_data.content_ptr; @@ -346,7 +770,7 @@ bool ws_wh_fc_read(uint8_t *data, uint16_t length, struct ws_fc_ie *fc_ie) { mac_header_IE_t fc_ie_data; fc_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; - if (2 != mac_ie_header_sub_id_discover(data, length, &fc_ie_data, WH_IE_FC_TYPE)) { + if (2 > mac_ie_header_sub_id_discover(data, length, &fc_ie_data, WH_IE_FC_TYPE)) { return false; } data = fc_ie_data.content_ptr; @@ -359,7 +783,7 @@ bool ws_wh_rsl_read(uint8_t *data, uint16_t length, int8_t *rsl) { mac_header_IE_t rsl_ie_data; rsl_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; - if (1 != mac_ie_header_sub_id_discover(data, length, &rsl_ie_data, WH_IE_RSL_TYPE)) { + if (1 > mac_ie_header_sub_id_discover(data, length, &rsl_ie_data, WH_IE_RSL_TYPE)) { return false; } *rsl = *rsl_ie_data.content_ptr; @@ -371,7 +795,7 @@ bool ws_wh_ea_read(uint8_t *data, uint16_t length, uint8_t *eui64) { mac_header_IE_t rsl_ie_data; rsl_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; - if (8 != mac_ie_header_sub_id_discover(data, length, &rsl_ie_data, WH_IE_EA_TYPE)) { + if (8 > mac_ie_header_sub_id_discover(data, length, &rsl_ie_data, WH_IE_EA_TYPE)) { return false; } memcpy(eui64, rsl_ie_data.content_ptr, 8); @@ -379,6 +803,162 @@ bool ws_wh_ea_read(uint8_t *data, uint16_t length, uint8_t *eui64) return true; } +bool ws_wh_lutt_read(uint8_t *data, uint16_t length, struct ws_lutt_ie *ws_lutt) +{ + + mac_header_IE_t lutt_ie_data; + lutt_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_lutt_length() > mac_ie_header_sub_id_discover(data, length, &lutt_ie_data, WH_IE_LUTT_TYPE)) { + return false; + } + data = lutt_ie_data.content_ptr; + ws_lutt->message_type = *data++; + ws_lutt->slot_number = common_read_16_bit_inverse(data); + ws_lutt->interval_offset = common_read_24_bit_inverse(data + 2); + + return true; +} + +bool ws_wh_lus_read(uint8_t *data, uint16_t length, struct ws_lus_ie *lus_ptr) +{ + mac_header_IE_t lus_ie_data; + lus_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_lus_length() > mac_ie_header_sub_id_discover(data, length, &lus_ie_data, WH_IE_LUS_TYPE)) { + return false; + } + data = lus_ie_data.content_ptr; + lus_ptr->listen_interval = common_read_24_bit_inverse(data); + data += 3; + lus_ptr->channel_plan_tag = *data; + + return true; +} + +bool ws_wh_flus_read(uint8_t *data, uint16_t length, struct ws_flus_ie *flus_ptr) +{ + mac_header_IE_t flus_ie_data; + flus_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_flus_length() > mac_ie_header_sub_id_discover(data, length, &flus_ie_data, WH_IE_FLUS_TYPE)) { + return false; + } + data = flus_ie_data.content_ptr; + flus_ptr->dwell_interval = *data++; + flus_ptr->channel_plan_tag = *data; + + return true; +} + +bool ws_wh_lbt_read(uint8_t *data, uint16_t length, struct ws_lbt_ie *ws_lbt) +{ + mac_header_IE_t lbt_ie_data; + lbt_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_lbt_length() > mac_ie_header_sub_id_discover(data, length, &lbt_ie_data, WH_IE_LBT_TYPE)) { + return false; + } + data = lbt_ie_data.content_ptr; + ws_lbt->slot_number = common_read_16_bit_inverse(data); + ws_lbt->interval_offset = common_read_24_bit_inverse(data + 2); + + return true; +} + +bool ws_wh_lbs_read(uint8_t *data, uint16_t length, struct ws_lbs_ie *lbs_ptr) +{ + mac_header_IE_t lbs_ie_data; + lbs_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_lbs_length() > mac_ie_header_sub_id_discover(data, length, &lbs_ie_data, WH_IE_LBS_TYPE)) { + return false; + } + + data = lbs_ie_data.content_ptr; + lbs_ptr->broadcast_interval = common_read_24_bit_inverse(data); + data += 3; + lbs_ptr->broadcast_secheduler_id = common_read_16_bit_inverse(data); + data += 2; + lbs_ptr->channel_plan_tag = *data; + + return true; +} + +bool ws_wh_nr_read(uint8_t *data, uint16_t length, struct ws_nr_ie *nr_ptr) +{ + mac_header_IE_t nr_ie_data; + nr_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (3 > mac_ie_header_sub_id_discover(data, length, &nr_ie_data, WH_IE_NR_TYPE)) { + return false; + } + data = nr_ie_data.content_ptr; + nr_ptr->node_role = *data++ & 7; + nr_ptr->clock_drift = *data++; + nr_ptr->timing_accurancy = *data++; + switch (nr_ptr->node_role) { + case WS_NR_ROLE_BR: + break; + case WS_NR_ROLE_ROUTER: + break; + case WS_NR_ROLE_LFN: + if (9 > nr_ie_data.length) { + return false; + } + nr_ptr->listen_interval_min = common_read_24_bit_inverse(data); + nr_ptr->listen_interval_max = common_read_24_bit_inverse(data + 3); + break; + default: + return false; + } + + return true; +} + +bool ws_wh_lnd_read(uint8_t *data, uint16_t length, struct ws_lnd_ie *lnd_ptr) +{ + mac_header_IE_t lnd_ie_data; + lnd_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_lnd_length() > mac_ie_header_sub_id_discover(data, length, &lnd_ie_data, WH_IE_LND_TYPE)) { + return false; + } + + data = lnd_ie_data.content_ptr; + lnd_ptr->response_threshold = *data++; + lnd_ptr->response_delay = common_read_24_bit_inverse(data); + data += 3; + lnd_ptr->discovery_slot_time = *data++; + lnd_ptr->discovery_slots = *data++; + lnd_ptr->discovery_first_slot = common_read_16_bit_inverse(data); + + return true; +} + +bool ws_wh_lto_read(uint8_t *data, uint16_t length, struct ws_lto_ie *lto_ptr) +{ + mac_header_IE_t lto_ie_data; + lto_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_lto_length() > mac_ie_header_sub_id_discover(data, length, <o_ie_data, WH_IE_LTO_TYPE)) { + return false; + } + data = lto_ie_data.content_ptr; + + lto_ptr->offset = common_read_24_bit_inverse(data); + lto_ptr->adjusted_listening_interval = common_read_24_bit_inverse(data + 3); + + return true; +} + +bool ws_wh_panid_read(uint8_t *data, uint16_t length, struct ws_panid_ie *ws_panid) +{ + mac_header_IE_t panid_ie_data; + panid_ie_data.id = MAC_HEADER_ASSIGNED_EXTERNAL_ORG_IE_ID; + if (ws_wh_panid_length() > mac_ie_header_sub_id_discover(data, length, &panid_ie_data, WH_IE_PANID_TYPE)) { + return false; + } + + ws_panid->panid = common_read_16_bit_inverse(panid_ie_data.content_ptr); + + return true; +} + + + static uint8_t *ws_channel_plan_zero_read(uint8_t *ptr, ws_channel_plan_zero_t *plan) { plan->regulator_domain = *ptr++; @@ -397,6 +977,13 @@ static uint8_t *ws_channel_plan_one_read(uint8_t *ptr, ws_channel_plan_one_t *pl return ptr; } +static uint8_t *ws_channel_plan_two_read(uint8_t *ptr, ws_channel_plan_two_t *plan) +{ + plan->regulator_domain = *ptr++; + plan->channel_plan_id = *ptr++; + return ptr; +} + static uint8_t *ws_channel_function_zero_read(uint8_t *ptr, ws_channel_function_zero_t *plan) { plan->fixed_channel = common_read_16_bit_inverse(ptr); @@ -415,7 +1002,7 @@ bool ws_wp_nested_us_read(uint8_t *data, uint16_t length, struct ws_us_ie *us_ie mac_nested_payload_IE_t nested_payload_ie; nested_payload_ie.id = WP_PAYLOAD_IE_US_TYPE; nested_payload_ie.type_long = true; - if (mac_ie_nested_discover(data, length, &nested_payload_ie) < 4) { + if (4 > mac_ie_nested_discover(data, length, &nested_payload_ie)) { return false; } @@ -443,6 +1030,9 @@ bool ws_wp_nested_us_read(uint8_t *data, uint16_t length, struct ws_us_ie *us_ie case 1: data = ws_channel_plan_one_read(data, &us_ie->plan.one); break; + case 2: + data = ws_channel_plan_two_read(data, &us_ie->plan.two); + break; default: return false; @@ -517,7 +1107,7 @@ bool ws_wp_nested_bs_read(uint8_t *data, uint16_t length, struct ws_bs_ie *bs_ie mac_nested_payload_IE_t nested_payload_ie; nested_payload_ie.id = WP_PAYLOAD_IE_BS_TYPE; nested_payload_ie.type_long = true; - if (mac_ie_nested_discover(data, length, &nested_payload_ie) < 10) { + if (10 > mac_ie_nested_discover(data, length, &nested_payload_ie)) { return false; } data = nested_payload_ie.content_ptr; @@ -548,6 +1138,9 @@ bool ws_wp_nested_bs_read(uint8_t *data, uint16_t length, struct ws_bs_ie *bs_ie case 1: data = ws_channel_plan_one_read(data, &bs_ie->plan.one); break; + case 2: + data = ws_channel_plan_two_read(data, &bs_ie->plan.two); + break; default: return false; @@ -590,7 +1183,7 @@ bool ws_wp_nested_pan_read(uint8_t *data, uint16_t length, struct ws_pan_informa mac_nested_payload_IE_t nested_payload_ie; nested_payload_ie.id = WP_PAYLOAD_IE_PAN_TYPE; nested_payload_ie.type_long = false; - if (mac_ie_nested_discover(data, length, &nested_payload_ie) != 5) { + if (5 > mac_ie_nested_discover(data, length, &nested_payload_ie)) { return false; } @@ -599,6 +1192,12 @@ bool ws_wp_nested_pan_read(uint8_t *data, uint16_t length, struct ws_pan_informa pan_congiguration->use_parent_bs = (nested_payload_ie.content_ptr[4] & 0x01) == 0x01; pan_congiguration->rpl_routing_method = (nested_payload_ie.content_ptr[4] & 0x02) == 0x02; pan_congiguration->version = (nested_payload_ie.content_ptr[4] & 0xe0) >> 5; + if (pan_congiguration->version > WS_FAN_VERSION_1_0) { + /* FAN 1.1 specific read */ + pan_congiguration->lfn_window_style = (nested_payload_ie.content_ptr[4] & 0x04) == 0x04; + } else { + pan_congiguration->lfn_window_style = false; //Set false for FAN 1.0 + } return true; } @@ -608,7 +1207,7 @@ bool ws_wp_nested_pan_version_read(uint8_t *data, uint16_t length, uint16_t *pan mac_nested_payload_IE_t nested_payload_ie; nested_payload_ie.id = WP_PAYLOAD_IE_PAN_VER_TYPE; nested_payload_ie.type_long = false; - if (mac_ie_nested_discover(data, length, &nested_payload_ie) != 2) { + if (2 > mac_ie_nested_discover(data, length, &nested_payload_ie)) { return false; } *pan_version = common_read_16_bit_inverse(nested_payload_ie.content_ptr); @@ -646,3 +1245,204 @@ bool ws_wp_nested_network_name_read(uint8_t *data, uint16_t length, ws_wp_networ return true; } +bool ws_wp_nested_pcap_read(uint8_t *data, uint16_t length, struct ws_phy_cap_info *ws_pcap_list) +{ +#ifdef HAVE_WS_VERSION_1_1 + mac_nested_payload_IE_t nested_payload_ie; + nested_payload_ie.id = WP_PAYLOAD_IE_PCAP_TYPE; + nested_payload_ie.type_long = false; + if (4 > mac_ie_nested_discover(data, length, &nested_payload_ie)) { + return false; + } + //Read & Validate length + data = nested_payload_ie.content_ptr; + uint8_t length_of_cap = *data++ & 0x07; + + if (nested_payload_ie.length < length_of_cap * 3) { + return false; + } + ws_pcap_list->length_of_list = length_of_cap; + + for (uint8_t i = 0; i < length_of_cap; i++) { + ws_pcap_list->pcap[i].phy_type = *data++ & 7; + ws_pcap_list->pcap[i].operating_mode = common_read_16_bit_inverse(data); + data += 2; + } + + + return true; +#else + (void) data; + (void) length; + (void) ws_pcap_list; + return false; +#endif +} + + +bool ws_wp_nested_lfn_version_read(uint8_t *data, uint16_t length, struct ws_lfnver_ie *ws_lfnver) +{ + mac_nested_payload_IE_t nested_payload_ie; + nested_payload_ie.id = WP_PAYLOAD_IE_LFNVER_TYPE; + nested_payload_ie.type_long = false; + if (ws_wp_nested_lfn_version_length() > mac_ie_nested_discover(data, length, &nested_payload_ie)) { + return false; + } + + ws_lfnver->lfn_version = common_read_16_bit_inverse(nested_payload_ie.content_ptr); + return true; +} + + +bool ws_wp_nested_lgtk_hash_read(uint8_t *data, uint16_t length, struct ws_lgtkhash_ie *ws_lgtkhash) +{ + mac_nested_payload_IE_t nested_payload_ie; + nested_payload_ie.id = WP_PAYLOAD_IE_LGTKHASH_TYPE; + nested_payload_ie.type_long = false; + if (1 > mac_ie_nested_discover(data, length, &nested_payload_ie)) { + return false; + } + data = nested_payload_ie.content_ptr; + + ws_lgtkhash->lgtk0 = (*data & 0x01) == 0x01; + ws_lgtkhash->lgtk1 = (*data & 0x02) == 0x02; + ws_lgtkhash->lgtk2 = (*data & 0x04) == 0x04; + ws_lgtkhash->active_lgtk_index = (*data & 0x18) >> 3; + + if (ws_wp_lgtk_hash_length(ws_lgtkhash) > nested_payload_ie.length) { + return false; + } + + data++; + if (ws_lgtkhash->lgtk0) { + ws_lgtkhash->lgtk0_hash = data; + data += 8; + } else { + ws_lgtkhash->lgtk0_hash = NULL; + } + + if (ws_lgtkhash->lgtk1) { + ws_lgtkhash->lgtk1_hash = data; + data += 8; + } else { + ws_lgtkhash->lgtk1_hash = NULL; + } + + if (ws_lgtkhash->lgtk2) { + ws_lgtkhash->lgtk2_hash = data; + } else { + ws_lgtkhash->lgtk2_hash = NULL; + } + + return true; + +} + + + +bool ws_wp_nested_lfn_channel_plan_read(uint8_t *data, uint16_t length, ws_generic_channel_info_t *ws_lcp, uint8_t plan_tag_id) +{ + mac_nested_payload_IE_t nested_payload_ie; + nested_payload_ie.id = WP_PAYLOAD_IE_LFN_CHANNEL_PLAN_TYPE; + nested_payload_ie.type_long = true; + + if (1 < mac_ie_nested_tagged_discover(data, length, &nested_payload_ie, plan_tag_id)) { + return false; + } + //Parse Channel Plan, function and excluded channel + data = nested_payload_ie.content_ptr; + ws_lcp->channel_plan = (*data & 3); + ws_lcp->channel_function = (*data & 0x38) >> 3; + ws_lcp->excluded_channel_ctrl = (*data & 0xc0) >> 6; + data++; + nested_payload_ie.length--; + + uint16_t info_length = 0; + info_length = ws_channel_plan_length(ws_lcp->channel_plan); + if (nested_payload_ie.length < info_length) { + return false; + } + + nested_payload_ie.length -= info_length; + switch (ws_lcp->channel_plan) { + case 0: + data = ws_channel_plan_zero_read(data, &ws_lcp->plan.zero); + break; + + case 1: + data = ws_channel_plan_one_read(data, &ws_lcp->plan.one); + break; + case 2: + data = ws_channel_plan_two_read(data, &ws_lcp->plan.two); + break; + default: + return false; + + } + + info_length = ws_channel_function_length(ws_lcp->channel_function, 0); + + if (nested_payload_ie.length < info_length) { + return false; + } + nested_payload_ie.length -= info_length; + + + switch (ws_lcp->channel_function) { + case 0: + data = ws_channel_function_zero_read(data, &ws_lcp->function.zero); + break; + + case 1: + case 2: + break; + + case 3: + + data = ws_channel_function_three_read(data, &ws_lcp->function.three); + info_length = ws_lcp->function.three.channel_hop_count; + if (nested_payload_ie.length < info_length) { + return false; + } + nested_payload_ie.length -= info_length; + data += info_length; + break; + default: + return false; + + } + + switch (ws_lcp->excluded_channel_ctrl) { + case WS_EXC_CHAN_CTRL_NONE: + + break; + case WS_EXC_CHAN_CTRL_RANGE: + ws_lcp->excluded_channels.range_in.number_of_range = *data; + if (nested_payload_ie.length < (ws_lcp->excluded_channels.range_in.number_of_range * 4) + 1) { + return false; + } + //Set Range start after validation + ws_lcp->excluded_channels.range_in.range_start = data + 1; + break; + + case WS_EXC_CHAN_CTRL_BITMASK: + if (ws_lcp->channel_plan == 1) { + ws_lcp->excluded_channels.mask_in.mask_len_inline = ((ws_lcp->plan.one.number_of_channel + 7) / 8); + if (ws_lcp->excluded_channels.mask_in.mask_len_inline != nested_payload_ie.length) { + //Channel mask length is not correct + return false; + } + } else { + ws_lcp->excluded_channels.mask_in.mask_len_inline = nested_payload_ie.length; + } + + ws_lcp->excluded_channels.mask_in.channel_mask = data; + break; + default: + return false; + } + + return true; + +} + diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h index 3198763c07b..d6fb4907ab8 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_ie_lib.h @@ -24,6 +24,8 @@ struct ws_bt_ie; struct ws_us_ie; struct ws_hopping_schedule_s; struct ws_fc_ie; +struct ws_phy_cap_info; +struct ws_pcap_ie; /** * @brief ws_wp_network_name_t WS nested payload network name @@ -33,6 +35,16 @@ typedef struct ws_wp_network_name { uint8_t *network_name; } ws_wp_network_name_t; +#define ws_wp_nested_lfn_version_length() 2 +#define ws_wh_lutt_length() 6 +#define ws_wh_lus_length() 4 +#define ws_wh_flus_length() 2 +#define ws_wh_lbt_length() 5 +#define ws_wh_lbs_length() 6 +#define ws_wh_lnd_length() 8 +#define ws_wh_lto_length() 6 +#define ws_wh_panid_length() 2 + /* WS_WH HEADER IE */ uint8_t *ws_wh_utt_write(uint8_t *ptr, uint8_t message_type); uint8_t *ws_wh_bt_write(uint8_t *ptr); @@ -40,12 +52,34 @@ uint8_t *ws_wh_fc_write(uint8_t *ptr, struct ws_fc_ie *fc_ie); uint8_t *ws_wh_rsl_write(uint8_t *ptr, uint8_t rsl); uint8_t *ws_wh_vh_write(uint8_t *ptr, uint8_t *vendor_header, uint8_t vendor_header_length); uint8_t *ws_wh_ea_write(uint8_t *ptr, uint8_t *eui64); +/* Wi-SUN FAN 1.1 */ +uint8_t *ws_wh_lutt_write(uint8_t *ptr, uint8_t message_type); +uint8_t *ws_wh_lus_write(uint8_t *ptr, struct ws_lus_ie *lus_ptr); +uint8_t *ws_wh_flus_write(uint8_t *ptr, struct ws_flus_ie *flus_ptr); +uint8_t *ws_wh_lbt_write(uint8_t *ptr); +uint8_t *ws_wh_lbs_write(uint8_t *ptr, struct ws_lbs_ie *lbs_ptr); +uint8_t *ws_wh_nr_write(uint8_t *ptr, struct ws_nr_ie *nr_ptr); +uint16_t ws_wh_nr_length(struct ws_nr_ie *nr_ptr); +uint8_t *ws_wh_lnd_write(uint8_t *ptr, struct ws_lnd_ie *lnd_ptr); +uint8_t *ws_wh_lto_write(uint8_t *ptr, struct ws_lto_ie *lto_ptr); +uint8_t *ws_wh_panid_write(uint8_t *ptr, uint16_t pana_id); + bool ws_wh_utt_read(uint8_t *data, uint16_t length, struct ws_utt_ie *utt_ie); bool ws_wh_bt_read(uint8_t *data, uint16_t length, struct ws_bt_ie *bt_ie); bool ws_wh_fc_read(uint8_t *data, uint16_t length, struct ws_fc_ie *fc_ie); bool ws_wh_rsl_read(uint8_t *data, uint16_t length, int8_t *rsl); bool ws_wh_ea_read(uint8_t *data, uint16_t length, uint8_t *eui64); +/*Wi-SUN FAN 1.1 */ +bool ws_wh_lutt_read(uint8_t *data, uint16_t length, struct ws_lutt_ie *ws_lutt); +bool ws_wh_lus_read(uint8_t *data, uint16_t length, struct ws_lus_ie *lus_ptr); +bool ws_wh_flus_read(uint8_t *data, uint16_t length, struct ws_flus_ie *flus_ptr); +bool ws_wh_lbt_read(uint8_t *data, uint16_t length, struct ws_lbt_ie *ws_lbt); +bool ws_wh_lbs_read(uint8_t *data, uint16_t length, struct ws_lbs_ie *lbs_ptr); +bool ws_wh_nr_read(uint8_t *data, uint16_t length, struct ws_nr_ie *nr_ptr); +bool ws_wh_lnd_read(uint8_t *data, uint16_t length, struct ws_lnd_ie *lnd_ptr); +bool ws_wh_lto_read(uint8_t *data, uint16_t length, struct ws_lto_ie *lto_ptr); +bool ws_wh_panid_read(uint8_t *data, uint16_t length, struct ws_panid_ie *ws_panid); /* WS_WP_NESTED PAYLOD IE */ uint8_t *ws_wp_base_write(uint8_t *ptr, uint16_t length); @@ -56,6 +90,22 @@ uint8_t *ws_wp_nested_netname_write(uint8_t *ptr, uint8_t *network_name, uint8_t uint8_t *ws_wp_nested_pan_ver_write(uint8_t *ptr, struct ws_pan_information_s *pan_congiguration); uint8_t *ws_wp_nested_gtkhash_write(uint8_t *ptr, uint8_t *gtkhash, uint8_t gtkhash_length); uint16_t ws_wp_nested_hopping_schedule_length(struct ws_hopping_schedule_s *hopping_schedule, bool unicast_schedule); +/* Wi-SUN FAN 1.1 */ +/* WS PCAP */ +uint8_t *ws_wp_nested_pcap_write(uint8_t *ptr, struct ws_phy_cap_info *pcap_list); +uint16_t ws_wp_nested_pcap_length(uint8_t list_length); +struct ws_pcap_ie ws_ie_lib_generate_phy_cap_from_phy_mode_id(uint8_t phy_mode_id); +uint8_t ws_ie_lib_phy_mode_id_get_from_phy_cap(struct ws_pcap_ie *phy_cap); +void ws_ie_lib_phy_cap_list_update(struct ws_phy_cap_info *phy_pap, struct ws_pcap_ie *pcap); +/* WS LFN version */ +uint8_t *ws_wp_nested_lfn_version_write(uint8_t *ptr, struct ws_lfnver_ie *ws_lfnver); +/* WS LFN GTK HAS */ +uint8_t *ws_wp_nested_lgtk_hash_write(uint8_t *ptr, struct ws_lgtkhash_ie *ws_lgtkhash); +uint16_t ws_wp_lgtk_hash_length(struct ws_lgtkhash_ie *ws_lgtkhash); +/* WS LFN Channel plan */ +uint8_t *ws_wp_nested_lfn_channel_plan_write(uint8_t *ptr, struct ws_generic_channel_info *ws_lcp, uint8_t plan_tag_id); +uint16_t ws_wp_nested_lfn_channel_plan_length(struct ws_generic_channel_info *ws_lcp); + bool ws_wp_nested_us_read(uint8_t *data, uint16_t length, struct ws_us_ie *us_ie); bool ws_wp_nested_bs_read(uint8_t *data, uint16_t length, struct ws_bs_ie *bs_ie); @@ -63,6 +113,11 @@ bool ws_wp_nested_pan_read(uint8_t *data, uint16_t length, struct ws_pan_informa bool ws_wp_nested_pan_version_read(uint8_t *data, uint16_t length, uint16_t *pan_version); bool ws_wp_nested_network_name_read(uint8_t *data, uint16_t length, ws_wp_network_name_t *network_name); uint8_t *ws_wp_nested_gtkhash_read(uint8_t *data, uint16_t length); +/* Wi-SUN FAN 1.1 */ +bool ws_wp_nested_pcap_read(uint8_t *data, uint16_t length, struct ws_phy_cap_info *ws_pcap_list); +bool ws_wp_nested_lfn_version_read(uint8_t *data, uint16_t length, struct ws_lfnver_ie *ws_lfnver); +bool ws_wp_nested_lgtk_hash_read(uint8_t *data, uint16_t length, struct ws_lgtkhash_ie *ws_lgtkhash); +bool ws_wp_nested_lfn_channel_plan_read(uint8_t *data, uint16_t length, struct ws_generic_channel_info *ws_lcp, uint8_t plan_tag_id); #endif /* WS_IE_LIB_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h index 9e905b7bbc7..9b8e55f3807 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc.h @@ -49,13 +49,15 @@ typedef struct wh_ie_sub_list_s { * @brief wp_nested_ie_sub_list_t ws asynch Nested Payload sub IE element request list */ typedef struct wp_nested_ie_sub_list_s { - bool us_ie: 1; /**< Unicast Schedule information */ - bool bs_ie: 1; /**< Broadcast Schedule information */ - bool vp_ie: 1; /**< Vendor Payload information */ - bool pan_ie: 1; /**< PAN Information */ - bool net_name_ie: 1; /**< Network Name information */ - bool pan_version_ie: 1; /**< Pan configuration version */ - bool gtkhash_ie: 1; /**< GTK Hash information */ + bool us_ie: 1; /**< Unicast Schedule information */ + bool bs_ie: 1; /**< Broadcast Schedule information */ + bool vp_ie: 1; /**< Vendor Payload information */ + bool pan_ie: 1; /**< PAN Information */ + bool net_name_ie: 1; /**< Network Name information */ + bool pan_version_ie: 1; /**< Pan configuration version */ + bool gtkhash_ie: 1; /**< GTK Hash information */ + bool lfn_gtk_version_ie: 1; /**< LFN Version & GTK Hash */ + bool phy_cap_ie: 1; /** < Phy Cap information for MDR */ } wp_nested_ie_sub_list_t; /** @@ -115,7 +117,7 @@ typedef void ws_asynch_ind(struct protocol_interface_info_entry *interface, cons typedef void ws_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message); /** - * @brief ws_asynch_confirm ws asynch data confirmation to asynch message request + * @brief ws_neighbor_info_request neighbor info request * @param interface The interface pointer * @param mac_64 Neighbor 64-bit address * @param neighbor_buffer Buffer where neighbor infor is buffered @@ -124,17 +126,33 @@ typedef void ws_asynch_confirm(struct protocol_interface_info_entry *interface, * @return true when neighbor info is available * @return false when no neighbor info */ -typedef bool ws_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, llc_neighbour_req_t *neighbor_buffer, bool request_new); +typedef bool ws_neighbor_info_request(struct protocol_interface_info_entry *interface, const uint8_t *mac_64, struct llc_neighbour_req *neighbor_buffer, bool request_new); + +/** + * @brief ws_eapol_relay_active_check check if eapol relay is active + * @param interface The interface pointer + * + * @return true eapol relay is active + * @return false eapol relay is not active + */ +typedef bool ws_eapol_relay_active_check(struct protocol_interface_info_entry *cur); /** * @brief ws_llc_create ws LLC module create * @param interface Interface pointer * @param asynch_ind_cb Asynch indication + * @param asynch_cnf_cb Asynch confirm + * @param ws_neighbor_info_request_cb neighbor info request + * @param eapol_relay_active_cb check if eapol relay is active + * * @param ie_ext Information element list * * Function allocate and init LLC class and init it 2 supported 2 API: ws asynch and MPX user are internally registered. + * + * @return 0 on success + * @return < 0 on failure */ -int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ind *asynch_ind_cb, ws_asynch_confirm *asynch_cnf_cb, ws_neighbor_info_request *ws_neighbor_info_request_cb); +int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ind *asynch_ind_cb, ws_asynch_confirm *asynch_cnf_cb, ws_neighbor_info_request *ws_neighbor_info_request_cb, ws_eapol_relay_active_check *eapol_relay_active_cb); /** * @brief ws_llc_reset Reset ws LLC parametrs and clean messages diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c index 35e87582e77..665a16b8c8b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_llc_data_service.c @@ -32,8 +32,11 @@ #include "6LoWPAN/ws/ws_common_defines.h" #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_bootstrap_ffn.h" #include "6LoWPAN/ws/ws_ie_lib.h" #include "6LoWPAN/ws/ws_llc.h" +#include "6LoWPAN/ws/ws_neighbor_class.h" +#include "6LoWPAN/ws/ws_ie_lib.h" #include "6LoWPAN/ws/ws_mpx_header.h" #include "6LoWPAN/ws/ws_pae_controller.h" #include "6LoWPAN/ws/ws_cfg_settings.h" @@ -42,6 +45,7 @@ #include "Service_Libs/etx/etx.h" #include "fhss_ws_extension.h" #include "Service_Libs/random_early_detection/random_early_detection_api.h" +#include "ws_management_api.h" #ifdef HAVE_WS @@ -150,6 +154,7 @@ typedef struct { ws_asynch_ind *asynch_ind; /**< LLC Asynch data indication call back configured by user */ ws_asynch_confirm *asynch_confirm; /**< LLC Asynch data confirmation call back configured by user */ ws_neighbor_info_request *ws_neighbor_info_request_cb; /**< LLC Neighbour discover API*/ + ws_eapol_relay_active_check *eapol_relay_active_cb; /**< EAPOL relay active check callback */ uint8_t ws_enhanced_response_elements[ENHANCED_FRAME_RESPONSE]; ns_ie_iovec_t ws_header_vector; bool high_priority_mode; @@ -158,7 +163,7 @@ typedef struct { static NS_LIST_DEFINE(llc_data_base_list, llc_data_base_t, link); -static uint16_t ws_wp_nested_message_length(wp_nested_ie_sub_list_t requested_list, llc_ie_params_t *params); +static uint16_t ws_wp_nested_message_length(wp_nested_ie_sub_list_t requested_list, llc_data_base_t *llc_base); static uint16_t ws_wh_headers_length(wh_ie_sub_list_t requested_list, llc_ie_params_t *params); /** LLC message local functions */ @@ -378,9 +383,10 @@ static uint16_t ws_wh_headers_length(wh_ie_sub_list_t requested_list, llc_ie_par return length; } -static uint16_t ws_wp_nested_message_length(wp_nested_ie_sub_list_t requested_list, llc_ie_params_t *params) +static uint16_t ws_wp_nested_message_length(wp_nested_ie_sub_list_t requested_list, llc_data_base_t *llc_base) { uint16_t length = 0; + llc_ie_params_t *params = &llc_base->ie_params; if (requested_list.gtkhash_ie) { //Static 32 bytes allways length += WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH + params->gtkhash_length; @@ -411,6 +417,23 @@ static uint16_t ws_wp_nested_message_length(wp_nested_ie_sub_list_t requested_li length += 2; } } +#ifdef HAVE_WS_VERSION_1_1 + if (ws_version_1_1(llc_base->interface_ptr)) { + if (requested_list.lfn_gtk_version_ie) { + + length += WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH + ws_wp_nested_lfn_version_length(); + ws_lgtkhash_ie_t ws_lgtkhash; + ws_lgtkhash.lgtk0 = llc_base->interface_ptr->ws_info->lfngtk.active_hash_1; + ws_lgtkhash.lgtk1 = llc_base->interface_ptr->ws_info->lfngtk.active_hash_2; + ws_lgtkhash.lgtk2 = llc_base->interface_ptr->ws_info->lfngtk.active_hash_3; + length += WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH + ws_wp_lgtk_hash_length(&ws_lgtkhash); + } + + if (requested_list.phy_cap_ie) { + length += WS_WP_SUB_IE_ELEMENT_HEADER_LENGTH + ws_wp_nested_pcap_length(llc_base->interface_ptr->ws_info->phy_cap_info.length_of_list); + } + } +#endif if (requested_list.bs_ie) { ///Dynamic length @@ -774,6 +797,11 @@ static void ws_llc_data_indication_cb(const mac_api_t *api, const mcps_data_ind_ //SET trusted state mac_neighbor_table_trusted_neighbor(mac_neighbor_info(interface), neighbor_info.neighbor, true); } + // + //Phy CAP info read and store + if (ws_version_1_1(interface)) { + ws_neighbor_class_pcap_ie_store(neighbor_info.ws_neighbor, ie_ext); + } } mcps_data_ind_t data_ind = *data; @@ -966,9 +994,9 @@ static uint16_t ws_mpx_header_size_get(llc_data_base_t *base, uint16_t user_id) return header_size; } -static bool ws_eapol_handshake_first_msg(uint8_t *pdu, uint16_t length, protocol_interface_info_entry_t *cur) +static bool ws_eapol_handshake_first_msg(llc_data_base_t *base, uint8_t *pdu, uint16_t length, protocol_interface_info_entry_t *cur) { - if (!ws_eapol_relay_state_active(cur)) { + if (!base->eapol_relay_active_cb(cur)) { return false; } @@ -1010,6 +1038,26 @@ static void ws_llc_lowpan_mpx_header_set(llc_message_t *message, uint16_t user_i message->ie_vector_list[1].iovLen = ptr - (uint8_t *)message->ie_vector_list[1].ieBase; } +#ifdef HAVE_WS_VERSION_1_1 +uint8_t ws_llc_mdr_phy_mode_get(llc_data_base_t *base, const struct mcps_data_req_s *data) +{ + + if (!ws_version_1_1(base->interface_ptr) || !data->TxAckReq || data->msduLength < 500) { + return 0; + } + + llc_neighbour_req_t neighbor_info; + + if (!base->ws_neighbor_info_request_cb(base->interface_ptr, data->DstAddr, &neighbor_info, false)) { + return 0; + } + + return neighbor_info.ws_neighbor->phy_mode_id; +} +#else +#define ws_llc_mdr_phy_mode_get(base, data) 0 +#endif + static void ws_llc_lowpan_mpx_data_request(llc_data_base_t *base, mpx_user_t *user_cb, const struct mcps_data_req_s *data, mac_data_priority_t priority) { wh_ie_sub_list_t ie_header_mask; @@ -1038,7 +1086,7 @@ static void ws_llc_lowpan_mpx_data_request(llc_data_base_t *base, mpx_user_t *us nested_wp_id.us_ie = true; uint16_t ie_header_length = ws_wh_headers_length(ie_header_mask, &base->ie_params); - uint16_t nested_ie_length = ws_wp_nested_message_length(nested_wp_id, &base->ie_params); + uint16_t nested_ie_length = ws_wp_nested_message_length(nested_wp_id, base); uint16_t over_head_size = ie_header_length; if (nested_ie_length) { @@ -1066,6 +1114,7 @@ static void ws_llc_lowpan_mpx_data_request(llc_data_base_t *base, mpx_user_t *us ns_list_add_to_end(&base->llc_message_list, message); mcps_data_req_t data_req; + uint8_t phy_mode_id = ws_llc_mdr_phy_mode_get(base, data); message->mpx_user_handle = data->msduHandle; message->ack_requested = data->TxAckReq; if (data->TxAckReq) { @@ -1140,7 +1189,7 @@ static void ws_llc_lowpan_mpx_data_request(llc_data_base_t *base, mpx_user_t *us message->ie_ext.payloadIovLength = 0; //Set Back 2 at response handler } - base->interface_ptr->mac_api->mcps_data_req_ext(base->interface_ptr->mac_api, &data_req, &message->ie_ext, NULL, message->priority); + base->interface_ptr->mac_api->mcps_data_req_ext(base->interface_ptr->mac_api, &data_req, &message->ie_ext, NULL, message->priority, phy_mode_id); } static void ws_llc_eapol_data_req_init(mcps_data_req_t *data_req, llc_message_t *message) @@ -1187,7 +1236,7 @@ static void ws_llc_mpx_eapol_send(llc_data_base_t *base, llc_message_t *message) ns_list_add_to_end(&base->llc_message_list, message); ws_llc_eapol_data_req_init(&data_req, message); base->temp_entries->active_eapol_session = true; - base->interface_ptr->mac_api->mcps_data_req_ext(base->interface_ptr->mac_api, &data_req, &message->ie_ext, NULL, message->priority); + base->interface_ptr->mac_api->mcps_data_req_ext(base->interface_ptr->mac_api, &data_req, &message->ie_ext, NULL, message->priority, 0); } @@ -1199,15 +1248,15 @@ static void ws_llc_mpx_eapol_request(llc_data_base_t *base, mpx_user_t *user_cb, wp_nested_ie_sub_list_t nested_wp_id; memset(&nested_wp_id, 0, sizeof(wp_nested_ie_sub_list_t)); ie_header_mask.utt_ie = true; - ie_header_mask.bt_ie = ws_eapol_relay_state_active(base->interface_ptr); - ie_header_mask.ea_ie = ws_eapol_handshake_first_msg(data->msdu, data->msduLength, base->interface_ptr); + ie_header_mask.bt_ie = base->eapol_relay_active_cb(base->interface_ptr); /* Broadcast timing information */ + ie_header_mask.ea_ie = ws_eapol_handshake_first_msg(base, data->msdu, data->msduLength, base->interface_ptr); nested_wp_id.bs_ie = ie_header_mask.ea_ie; nested_wp_id.us_ie = true; uint16_t ie_header_length = ws_wh_headers_length(ie_header_mask, &base->ie_params); - uint16_t nested_ie_length = ws_wp_nested_message_length(nested_wp_id, &base->ie_params); + uint16_t nested_ie_length = ws_wp_nested_message_length(nested_wp_id, base); uint16_t over_head_size = ie_header_length; if (nested_ie_length) { @@ -1699,7 +1748,7 @@ static uint16_t ws_llc_calculate_dynamic_entries_max(uint16_t min_entry, uint16_ } -int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ind *asynch_ind_cb, ws_asynch_confirm *asynch_cnf_cb, ws_neighbor_info_request *ws_neighbor_info_request_cb) +int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ind *asynch_ind_cb, ws_asynch_confirm *asynch_cnf_cb, ws_neighbor_info_request *ws_neighbor_info_request_cb, ws_eapol_relay_active_check eapol_relay_active_cb) { llc_data_base_t *base = ws_llc_discover_by_interface(interface); if (base) { @@ -1718,6 +1767,7 @@ int8_t ws_llc_create(struct protocol_interface_info_entry *interface, ws_asynch_ base->asynch_ind = asynch_ind_cb; base->asynch_confirm = asynch_cnf_cb; base->ws_neighbor_info_request_cb = ws_neighbor_info_request_cb; + base->eapol_relay_active_cb = eapol_relay_active_cb; //Register MAC Extensions base->interface_ptr->mac_api->mac_mcps_extension_enable(base->interface_ptr->mac_api, &ws_llc_mac_indication_cb, &ws_llc_mac_confirm_cb, &ws_llc_ack_data_req_ext); base->interface_ptr->mac_api->mac_mcps_edfe_enable(base->interface_ptr->mac_api, &ws_llc_mcps_edfe_handler); @@ -1764,6 +1814,31 @@ mpx_api_t *ws_llc_mpx_api_get(struct protocol_interface_info_entry *interface) } return &base->mpx_data_base.mpx_api; } +#ifdef HAVE_WS_VERSION_1_1 + +static void ws_llc_phy_cab_list_generate(struct protocol_interface_info_entry *interface, ws_phy_cap_info_t *phy_cap) +{ + + memset(phy_cap, 0, sizeof(ws_phy_cap_info_t)); + + ws_phy_cap_info_t *prefedd_list = &interface->ws_info->phy_cap_info; + + if (!prefedd_list->length_of_list) { + return; + } + + + for (int i = 0; i < prefedd_list->length_of_list; i++) { + ws_ie_lib_phy_cap_list_update(phy_cap, &prefedd_list->pcap[i]); + } + + //Add base support + ws_pcap_ie_t base_cap = ws_ie_lib_generate_phy_cap_from_phy_mode_id(interface->ws_info->hopping_schdule.phy_mode_id); + if (base_cap.operating_mode) { + ws_ie_lib_phy_cap_list_update(phy_cap, &base_cap); + } +} +#endif int8_t ws_llc_asynch_request(struct protocol_interface_info_entry *interface, asynch_request_t *request) { @@ -1783,7 +1858,7 @@ int8_t ws_llc_asynch_request(struct protocol_interface_info_entry *interface, as request->wh_requested_ie_list.rsl_ie = false; //Never should not be a part Asynch message request->wh_requested_ie_list.vh_ie = false; uint16_t header_buffer_length = ws_wh_headers_length(request->wh_requested_ie_list, &base->ie_params); - uint16_t wp_nested_payload_length = ws_wp_nested_message_length(request->wp_requested_nested_ie_list, &base->ie_params); + uint16_t wp_nested_payload_length = ws_wp_nested_message_length(request->wp_requested_nested_ie_list, base); //Allocated uint16_t total_length = header_buffer_length; @@ -1880,9 +1955,37 @@ int8_t ws_llc_asynch_request(struct protocol_interface_info_entry *interface, as //Write Vendor spesific payload ptr = ws_wp_nested_vp_write(ptr, base->ie_params.vendor_payload, base->ie_params.vendor_payload_length); } + +#ifdef HAVE_WS_VERSION_1_1 + if (ws_version_1_1(interface)) { + if (request->wp_requested_nested_ie_list.lfn_gtk_version_ie) { + ws_lfnver_ie_t lfn_ver; + ws_lgtkhash_ie_t ws_lgtkhash; + //Write LFN Version + lfn_ver.lfn_version = interface->ws_info->lfngtk.lfn_version; + ptr = ws_wp_nested_lfn_version_write(ptr, &lfn_ver); + //Write LFN GTK Hash info + ws_lgtkhash.lgtk0 = base->interface_ptr->ws_info->lfngtk.active_hash_1; + ws_lgtkhash.lgtk1 = base->interface_ptr->ws_info->lfngtk.active_hash_2; + ws_lgtkhash.lgtk2 = base->interface_ptr->ws_info->lfngtk.active_hash_3; + ws_lgtkhash.active_lgtk_index = base->interface_ptr->ws_info->lfngtk.active_key_index; + ws_lgtkhash.lgtk0_hash = base->interface_ptr->ws_info->lfngtk.lgtkhash; + ws_lgtkhash.lgtk1_hash = base->interface_ptr->ws_info->lfngtk.lgtkhash + 8; + ws_lgtkhash.lgtk2_hash = base->interface_ptr->ws_info->lfngtk.lgtkhash + 16; + ptr = ws_wp_nested_lgtk_hash_write(ptr, &ws_lgtkhash); + } + + if (request->wp_requested_nested_ie_list.phy_cap_ie) { + ws_phy_cap_info_t phy_cap; + ws_llc_phy_cab_list_generate(base->interface_ptr, &phy_cap); + ptr = ws_wp_nested_pcap_write(ptr, &phy_cap); + } + } +#endif + } - base->interface_ptr->mac_api->mcps_data_req_ext(base->interface_ptr->mac_api, &data_req, &message->ie_ext, &request->channel_list, message->priority); + base->interface_ptr->mac_api->mcps_data_req_ext(base->interface_ptr->mac_api, &data_req, &message->ie_ext, &request->channel_list, message->priority, 0); return 0; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c index 61c9e4b6e55..92e280d1b1f 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_management_api.c @@ -51,24 +51,24 @@ int ws_management_node_init( } ws_phy_cfg_t phy_cfg; - if (ws_cfg_phy_get(&phy_cfg, NULL) < 0) { + if (ws_cfg_phy_get(&phy_cfg) < 0) { return -3; } phy_cfg.regulatory_domain = regulatory_domain; - if (ws_cfg_phy_set(cur, NULL, &phy_cfg, 0) < 0) { + if (ws_cfg_phy_set(cur, &phy_cfg, 0) < 0) { return -4; } ws_gen_cfg_t gen_cfg; - if (ws_cfg_gen_get(&gen_cfg, NULL) < 0) { + if (ws_cfg_gen_get(&gen_cfg) < 0) { return -3; } strncpy(gen_cfg.network_name, network_name_ptr, 32); - if (ws_cfg_gen_set(cur, NULL, &gen_cfg, 0) < 0) { + if (ws_cfg_gen_set(cur, &gen_cfg, 0) < 0) { return -4; } @@ -93,13 +93,13 @@ int ws_management_network_name_set( } ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { + if (ws_cfg_gen_get(&cfg) < 0) { return -3; } strncpy(cfg.network_name, network_name_ptr, 32); - if (ws_cfg_gen_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_gen_set(cur, &cfg, 0) < 0) { return -4; } @@ -120,7 +120,7 @@ int ws_management_network_name_get( } ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { + if (ws_cfg_gen_get(&cfg) < 0) { return -3; } @@ -143,13 +143,13 @@ int ws_management_network_name_validate( } ws_gen_cfg_t cfg; - if (ws_cfg_gen_get(&cfg, NULL) < 0) { + if (ws_cfg_gen_get(&cfg) < 0) { return -3; } strncpy(cfg.network_name, network_name_ptr, 32); - if (ws_cfg_gen_validate(NULL, &cfg) < 0) { + if (ws_cfg_gen_validate(&cfg) < 0) { return -4; } @@ -170,7 +170,7 @@ int ws_management_domain_configuration_set( ws_phy_cfg_t cfg; ws_phy_cfg_t cfg_default; - if (ws_cfg_phy_get(&cfg, NULL) < 0) { + if (ws_cfg_phy_get(&cfg) < 0) { return -3; } @@ -196,7 +196,7 @@ int ws_management_domain_configuration_set( cfg.channel_plan_id = channel_plan_id; } - if (ws_cfg_phy_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_phy_set(cur, &cfg, 0) < 0) { return -4; } @@ -216,7 +216,7 @@ int ws_management_domain_configuration_get( } ws_phy_cfg_t cfg; - if (ws_cfg_phy_get(&cfg, NULL) < 0) { + if (ws_cfg_phy_get(&cfg) < 0) { return -2; } @@ -246,7 +246,7 @@ int ws_management_domain_configuration_validate( } ws_phy_cfg_t cfg; - if (ws_cfg_phy_get(&cfg, NULL) < 0) { + if (ws_cfg_phy_get(&cfg) < 0) { return -3; } @@ -254,7 +254,7 @@ int ws_management_domain_configuration_validate( cfg.phy_mode_id = phy_mode_id; cfg.channel_plan_id = channel_plan_id; - if (ws_cfg_phy_validate(NULL, &cfg) < 0) { + if (ws_cfg_phy_validate(&cfg) < 0) { return -4; } @@ -276,7 +276,7 @@ int ws_management_regulatory_domain_set( ws_phy_cfg_t cfg; ws_phy_cfg_t cfg_default; - if (ws_cfg_phy_get(&cfg, NULL) < 0) { + if (ws_cfg_phy_get(&cfg) < 0) { return -3; } @@ -300,7 +300,7 @@ int ws_management_regulatory_domain_set( cfg.operating_class = cfg_default.operating_class; } - if (ws_cfg_phy_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_phy_set(cur, &cfg, 0) < 0) { return -4; } @@ -323,13 +323,30 @@ int ws_management_regulatory_domain_get( } ws_phy_cfg_t cfg; - if (ws_cfg_phy_get(&cfg, NULL) < 0) { + if (ws_cfg_phy_get(&cfg) < 0) { return -3; } - *regulatory_domain = cfg.regulatory_domain; - *operating_class = cfg.operating_class; - *operating_mode = cfg.operating_mode; + if (regulatory_domain) { + *regulatory_domain = cfg.regulatory_domain; + } + + // If phy_mode_id is set the new configuration mode is used and class and mode return invalid value + if (operating_class) { + if (cfg.phy_mode_id == 0xff) { + *operating_class = cfg.operating_class; + } else { + *operating_class = 0xff; + } + } + + if (operating_mode) { + if (cfg.phy_mode_id == 0xff) { + *operating_mode = cfg.operating_mode; + } else { + *operating_mode = 0xff; + } + } return 0; } @@ -347,7 +364,7 @@ int ws_management_regulatory_domain_validate( } ws_phy_cfg_t cfg; - if (ws_cfg_phy_get(&cfg, NULL) < 0) { + if (ws_cfg_phy_get(&cfg) < 0) { return -3; } @@ -355,7 +372,7 @@ int ws_management_regulatory_domain_validate( cfg.operating_class = operating_class; cfg.operating_mode = operating_mode; - if (ws_cfg_phy_validate(NULL, &cfg) < 0) { + if (ws_cfg_phy_validate(&cfg) < 0) { return -4; } @@ -374,13 +391,13 @@ int ws_management_network_size_set( } ws_gen_cfg_t cfg; - if (ws_cfg_network_size_get(&cfg, NULL) < 0) { + if (ws_cfg_network_size_get(&cfg) < 0) { return -3; } cfg.network_size = network_size; - if (ws_cfg_network_size_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_network_size_set(cur, &cfg, 0) < 0) { return -3; } @@ -401,7 +418,7 @@ int ws_management_network_size_get( } ws_gen_cfg_t cfg; - if (ws_cfg_network_size_get(&cfg, NULL) < 0) { + if (ws_cfg_network_size_get(&cfg) < 0) { return -3; } @@ -421,13 +438,13 @@ int ws_management_network_size_validate( } ws_gen_cfg_t cfg; - if (ws_cfg_network_size_get(&cfg, NULL) < 0) { + if (ws_cfg_network_size_get(&cfg) < 0) { return -3; } cfg.network_size = network_size; - if (ws_cfg_network_size_validate(NULL, &cfg) < 0) { + if (ws_cfg_network_size_validate(&cfg) < 0) { return -4; } @@ -446,7 +463,7 @@ int ws_management_channel_mask_set( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -463,7 +480,7 @@ int ws_management_channel_mask_set( } - if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_fhss_set(cur, &cfg, 0) < 0) { return -3; } @@ -484,7 +501,7 @@ int ws_management_channel_mask_get( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -504,13 +521,13 @@ int ws_management_channel_mask_validate( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } memcpy(cfg.fhss_channel_mask, channel_mask, sizeof(uint32_t) * 8); - if (ws_cfg_fhss_validate(NULL, &cfg) < 0) { + if (ws_cfg_fhss_validate(&cfg) < 0) { return -4; } @@ -557,7 +574,7 @@ int ws_management_fhss_timing_configure( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -584,7 +601,7 @@ int ws_management_fhss_timing_configure( cfg.fhss_bc_dwell_interval = fhss_bc_dwell_interval; } - if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_fhss_set(cur, &cfg, 0) < 0) { return -3; } @@ -605,7 +622,7 @@ int ws_management_fhss_unicast_channel_function_configure( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -631,7 +648,7 @@ int ws_management_fhss_unicast_channel_function_configure( cfg.fhss_uc_fixed_channel = cfg_default.fhss_uc_fixed_channel; } - if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_fhss_set(cur, &cfg, 0) < 0) { return -3; } @@ -654,7 +671,7 @@ int ws_management_fhss_unicast_channel_function_get( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -678,7 +695,7 @@ int ws_management_fhss_unicast_channel_function_validate( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -686,7 +703,7 @@ int ws_management_fhss_unicast_channel_function_validate( cfg.fhss_uc_channel_function = channel_function; cfg.fhss_uc_fixed_channel = fixed_channel; - if (ws_cfg_fhss_validate(NULL, &cfg) < 0) { + if (ws_cfg_fhss_validate(&cfg) < 0) { return -4; } @@ -708,7 +725,7 @@ int ws_management_fhss_broadcast_channel_function_configure( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } ws_fhss_cfg_t cfg_default; @@ -740,7 +757,7 @@ int ws_management_fhss_broadcast_channel_function_configure( cfg.fhss_bc_fixed_channel = cfg_default.fhss_bc_fixed_channel; } - if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_fhss_set(cur, &cfg, 0) < 0) { return -3; } @@ -764,7 +781,7 @@ int ws_management_fhss_broadcast_channel_function_get( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -790,7 +807,7 @@ int ws_management_fhss_broadcast_channel_function_validate( } ws_fhss_cfg_t cfg; - if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + if (ws_cfg_fhss_get(&cfg) < 0) { return -2; } @@ -799,7 +816,7 @@ int ws_management_fhss_broadcast_channel_function_validate( cfg.fhss_bc_channel_function = channel_function; cfg.fhss_bc_fixed_channel = fixed_channel; - if (ws_cfg_fhss_validate(NULL, &cfg) < 0) { + if (ws_cfg_fhss_validate(&cfg) < 0) { return -4; } @@ -821,7 +838,7 @@ int ws_management_timing_parameters_set( } ws_timing_cfg_t cfg; - if (ws_cfg_timing_get(&cfg, NULL) < 0) { + if (ws_cfg_timing_get(&cfg) < 0) { return -2; } @@ -854,7 +871,7 @@ int ws_management_timing_parameters_set( cfg.pan_timeout = cfg_default.pan_timeout;; } - if (ws_cfg_timing_set(cur, NULL, &cfg, 0) < 0) { + if (ws_cfg_timing_set(cur, &cfg, 0) < 0) { return -3; } @@ -878,7 +895,7 @@ int ws_management_timing_parameters_get( } ws_timing_cfg_t cfg; - if (ws_cfg_timing_get(&cfg, NULL) < 0) { + if (ws_cfg_timing_get(&cfg) < 0) { return -2; } @@ -904,7 +921,7 @@ int ws_management_timing_parameters_validate( } ws_timing_cfg_t cfg; - if (ws_cfg_timing_get(&cfg, NULL) < 0) { + if (ws_cfg_timing_get(&cfg) < 0) { return -2; } @@ -913,7 +930,7 @@ int ws_management_timing_parameters_validate( cfg.disc_trickle_k = disc_trickle_k; cfg.pan_timeout = pan_timeout; - if (ws_cfg_timing_validate(NULL, &cfg) < 0) { + if (ws_cfg_timing_validate(&cfg) < 0) { return -4; } @@ -957,4 +974,33 @@ int ws_device_min_sens_set( return 0; } +int ws_management_phy_capability_set( + int8_t interface_id, + ws_management_pcap_info_t *pcap_list) +{ +#ifdef HAVE_WS_VERSION_1_1 + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !ws_info(cur) || pcap_list->length_of_list > 7) { + return -1; + } + + //Set supported configure for MDR + //TODO add validation for Phy_type and operation modes + cur->ws_info->phy_cap_info.length_of_list = pcap_list->length_of_list; + for (int i = 0; i < pcap_list->length_of_list; i++) { + cur->ws_info->phy_cap_info.pcap[i].phy_type = pcap_list->pcap[i].phy_type; + cur->ws_info->phy_cap_info.pcap[i].operating_mode = pcap_list->pcap[i].operating_mode; + } + + return 0; + +#else + (void)interface_id; + (void)pcap_list; + return -1; +#endif +} + + #endif // HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c index 20d29cbc4d2..3cd07e5e5f2 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.c @@ -26,7 +26,9 @@ #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_neighbor_class.h" #include "6LoWPAN/ws/ws_common.h" +#include "6LoWPAN/ws/ws_ie_lib.h" #include "ws_management_api.h" +#include "mac_api.h" #ifdef HAVE_WS @@ -168,7 +170,7 @@ static void ws_neighbour_excluded_mask_by_range(ws_channel_mask_t *channel_info, if (channel >= range_start && channel <= range_stop) { //Cut channel - compare_mask_bit = 1 << (channel % 32); + compare_mask_bit = 1U << (channel % 32); mask_index = 0 + (channel / 32); if (channel_info->channel_mask[mask_index] & compare_mask_bit) { @@ -187,7 +189,7 @@ static uint32_t ws_reserve_order_32_bit(uint32_t value) uint32_t ret_val = 0; for (uint8_t i = 0; i < 32; i++) { if ((value & (1 << i))) { - ret_val |= 1 << ((32 - 1) - i); + ret_val |= 1U << ((32 - 1) - i); } } return ret_val; @@ -258,21 +260,23 @@ void ws_neighbor_class_neighbor_unicast_schedule_set(ws_neighbor_class_entry_t * } else if (ws_us->channel_plan == 1) { ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels = ws_us->plan.one.number_of_channel; + } else if (ws_us->channel_plan == 2) { + //TODO add Channel plan 2 channel count function call here } //Handle excluded channel and generate activate channel list if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { - ws_generate_channel_list(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels, own_shedule->regulatory_domain, own_shedule->operating_class, own_shedule->channel_plan_id); - ws_neighbor->fhss_data.uc_channel_list.channel_count = ws_active_channel_count(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + ws_common_generate_channel_list(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels, own_shedule->regulatory_domain, own_shedule->operating_class, own_shedule->channel_plan_id); + ws_neighbor->fhss_data.uc_channel_list.channel_count = ws_common_active_channel_count(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); ws_neighbour_excluded_mask_by_range(&ws_neighbor->fhss_data.uc_channel_list, &ws_us->excluded_channels.range, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); } else if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { - ws_generate_channel_list(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels, own_shedule->regulatory_domain, own_shedule->operating_class, own_shedule->channel_plan_id); - ws_neighbor->fhss_data.uc_channel_list.channel_count = ws_active_channel_count(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + ws_common_generate_channel_list(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels, own_shedule->regulatory_domain, own_shedule->operating_class, own_shedule->channel_plan_id); + ws_neighbor->fhss_data.uc_channel_list.channel_count = ws_common_active_channel_count(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); ws_neighbour_excluded_mask_by_mask(&ws_neighbor->fhss_data.uc_channel_list, &ws_us->excluded_channels.mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); } else if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_NONE) { if (ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels != ws_neighbor->fhss_data.uc_channel_list.channel_count) { - ws_generate_channel_list(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels, own_shedule->regulatory_domain, own_shedule->operating_class, own_shedule->channel_plan_id); - ws_neighbor->fhss_data.uc_channel_list.channel_count = ws_active_channel_count(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + ws_common_generate_channel_list(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels, own_shedule->regulatory_domain, own_shedule->operating_class, own_shedule->channel_plan_id); + ws_neighbor->fhss_data.uc_channel_list.channel_count = ws_common_active_channel_count(ws_neighbor->fhss_data.uc_channel_list.channel_mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); } } @@ -391,6 +395,13 @@ bool ws_neighbor_class_neighbor_duplicate_packet_check(ws_neighbor_class_entry_t return true; } +#ifdef HAVE_WS_VERSION_1_1 +void ws_neighbor_class_pcap_ie_store(struct ws_neighbor_class_entry *ws_neighbor, const struct mcps_data_ie_list *ie_ext) +{ + ws_wp_nested_pcap_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &ws_neighbor->pcap_info); +} +#endif + #endif /* HAVE_WS */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h index 1bb82adb28c..5fe7c19b67f 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_neighbor_class.h @@ -21,6 +21,8 @@ #include "fhss_ws_extension.h" #include "6LoWPAN/ws/ws_common_defines.h" +struct mcps_data_ie_list; + #define RSL_UNITITIALIZED 0x7fff typedef struct ws_neighbor_class_entry { @@ -34,6 +36,10 @@ typedef struct ws_neighbor_class_entry { bool broadcast_shedule_info_stored: 1; bool synch_done : 1; bool unicast_data_rx : 1; +#ifdef HAVE_WS_VERSION_1_1 + uint8_t phy_mode_id; /*!< Bootstrap configured Preference Phy mode for MDR */ + ws_phy_cap_info_t pcap_info; +#endif } ws_neighbor_class_entry_t; /** @@ -182,5 +188,10 @@ void ws_neighbor_class_rsl_in_calculate(ws_neighbor_class_entry_t *ws_neighbor, void ws_neighbor_class_rsl_out_calculate(ws_neighbor_class_entry_t *ws_neighbor, uint8_t rsl_reported); bool ws_neighbor_class_neighbor_duplicate_packet_check(ws_neighbor_class_entry_t *ws_neighbor, uint8_t mac_dsn, uint32_t rx_timestamp); +#ifdef HAVE_WS_VERSION_1_1 +void ws_neighbor_class_pcap_ie_store(ws_neighbor_class_entry_t *ws_neighbor, const struct mcps_data_ie_list *ie_ext); +#else +#define ws_neighbor_class_pcap_ie_store(ws_neighbor, ie_ext) ((void)0) +#endif #endif /* WS_NEIGHBOR_CLASS_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c index da2c3cf104d..fa6b66da4b1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c @@ -80,6 +80,13 @@ // Short GTK lifetime value, for GTK install check #define SHORT_GTK_LIFETIME 10 * 3600 // 10 hours +// Frame counter exhaust check timer +#define FRAME_CNT_TIMER 3600 + +#define SECONDS_IN_DAY (3600 * 24) +#define TIME_MINIMUM_DIFFERENCE 5 +#define TIME_DIFFERENCE_THRESHOLD 3600 + typedef struct { ns_list_link_t link; /**< Link */ uint16_t pan_id; /**< PAN ID */ @@ -93,6 +100,7 @@ typedef struct { ws_pae_auth_nw_info_updated *nw_info_updated; /**< Security keys network info updated callback */ ws_pae_auth_ip_addr_get *ip_addr_get; /**< IP address get callback */ ws_pae_auth_congestion_get *congestion_get; /**< Congestion get callback */ + ws_pae_auth_nw_frame_counter_read *nw_frame_cnt_read; /**< Network frame counter read callback */ supp_list_t active_supp_list; /**< List of active supplicants */ supp_list_t waiting_supp_list; /**< List of waiting supplicants */ shared_comp_list_t shared_comp_list; /**< Shared component list */ @@ -101,13 +109,20 @@ typedef struct { const sec_prot_certs_t *certs; /**< Certificates */ sec_prot_keys_nw_info_t *sec_keys_nw_info; /**< Security keys network information */ sec_cfg_t *sec_cfg; /**< Security configuration */ + frame_counters_t *frame_counters; /**< Frame counters */ + uint64_t prev_system_time; /**< Previous system time */ + uint64_t system_time_diff; /**< System time diffence */ + uint32_t prev_frame_cnt; /**< Previous frame counter */ + uint16_t prev_frame_cnt_timer; /**< Previous frame counter timer */ uint16_t supp_max_number; /**< Max number of stored supplicants */ uint16_t waiting_supp_list_size; /**< Waiting supplicants list size */ uint8_t relay_socked_msg_if_instance_id; /**< Relay socket message interface instance identifier */ uint8_t radius_socked_msg_if_instance_id; /**< Radius socket message interface instance identifier */ bool timer_running : 1; /**< Timer is running */ bool gtk_new_inst_req_exp : 1; /**< GTK new install required timer expired */ - bool gtk_new_act_time_exp: 1; /**< GTK new activation time expired */ + bool gtk_new_act_time_exp : 1; /**< GTK new activation time expired */ + bool prev_system_time_set : 1; /**< Previous system time set */ + bool prev_frame_cnt_set : 1; /**< Previous frame counter set */ } pae_auth_t; static int8_t ws_pae_auth_network_keys_from_gtks_set(pae_auth_t *pae_auth, bool force_install); @@ -118,6 +133,8 @@ static pae_auth_t *ws_pae_auth_get(protocol_interface_info_entry_t *interface_pt static pae_auth_t *ws_pae_auth_by_kmp_service_get(kmp_service_t *service); static int8_t ws_pae_auth_event_send(kmp_service_t *service, void *data); static void ws_pae_auth_tasklet_handler(arm_event_s *event); +static uint32_t ws_pae_auth_lifetime_key_frame_cnt_check(pae_auth_t *pae_auth, uint8_t gtk_index, uint16_t seconds); +static uint32_t ws_pae_auth_lifetime_system_time_check(pae_auth_t *pae_auth, int8_t gtk_index, uint16_t seconds, uint32_t dec_extra_seconds); static void ws_pae_auth_gtk_key_insert(pae_auth_t *pae_auth); static int8_t ws_pae_auth_new_gtk_activate(pae_auth_t *pae_auth); static int8_t ws_pae_auth_timer_if_start(kmp_service_t *service, kmp_api_t *kmp); @@ -145,9 +162,9 @@ static void ws_pae_auth_waiting_supp_deleted(void *pae_auth); static int8_t tasklet_id = -1; static NS_LIST_DEFINE(pae_auth_list, pae_auth_t, link); -int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, sec_cfg_t *sec_cfg, sec_prot_keys_nw_info_t *sec_keys_nw_info) +int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, sec_cfg_t *sec_cfg, sec_prot_keys_nw_info_t *sec_keys_nw_info, frame_counters_t *frame_counters) { - if (!interface_ptr || !next_gtks || !certs || !sec_cfg || !sec_keys_nw_info) { + if (!interface_ptr || !next_gtks || !certs || !sec_cfg || !sec_keys_nw_info || !frame_counters) { return -1; } @@ -175,16 +192,24 @@ int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot pae_auth->nw_info_updated = NULL; pae_auth->ip_addr_get = NULL; pae_auth->congestion_get = NULL; + pae_auth->nw_frame_cnt_read = NULL; pae_auth->next_gtks = next_gtks; pae_auth->certs = certs; pae_auth->sec_keys_nw_info = sec_keys_nw_info; pae_auth->sec_cfg = sec_cfg; + pae_auth->frame_counters = frame_counters; + pae_auth->prev_system_time = 0; + pae_auth->system_time_diff = 0; + pae_auth->prev_frame_cnt = 0; + pae_auth->prev_frame_cnt_timer = FRAME_CNT_TIMER; pae_auth->supp_max_number = SUPPLICANT_MAX_NUMBER; pae_auth->waiting_supp_list_size = 0; pae_auth->gtk_new_inst_req_exp = false; pae_auth->gtk_new_act_time_exp = false; + pae_auth->prev_frame_cnt_set = false; + pae_auth->prev_system_time_set = false; pae_auth->relay_socked_msg_if_instance_id = 0; pae_auth->radius_socked_msg_if_instance_id = 0; @@ -316,7 +341,7 @@ int8_t ws_pae_auth_delete(protocol_interface_info_entry_t *interface_ptr) return 0; } -void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_auth_gtk_hash_set *hash_set, ws_pae_auth_nw_key_insert *nw_key_insert, ws_pae_auth_nw_key_index_set *nw_key_index_set, ws_pae_auth_nw_info_updated *nw_info_updated, ws_pae_auth_ip_addr_get *ip_addr_get, ws_pae_auth_congestion_get *congestion_get) +void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_auth_gtk_hash_set *hash_set, ws_pae_auth_nw_key_insert *nw_key_insert, ws_pae_auth_nw_key_index_set *nw_key_index_set, ws_pae_auth_nw_info_updated *nw_info_updated, ws_pae_auth_ip_addr_get *ip_addr_get, ws_pae_auth_congestion_get *congestion_get, ws_pae_auth_nw_frame_counter_read *nw_frame_cnt_read) { if (!interface_ptr) { return; @@ -333,6 +358,7 @@ void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ pae_auth->nw_info_updated = nw_info_updated; pae_auth->ip_addr_get = ip_addr_get; pae_auth->congestion_get = congestion_get; + pae_auth->nw_frame_cnt_read = nw_frame_cnt_read; } void ws_pae_auth_start(protocol_interface_info_entry_t *interface_ptr) @@ -364,6 +390,9 @@ void ws_pae_auth_start(protocol_interface_info_entry_t *interface_ptr) // Sets active key index ws_pae_auth_network_key_index_set(pae_auth, index); + + pae_auth->prev_system_time = ws_pae_current_time_get(); + pae_auth->prev_system_time_set = true; } void ws_pae_auth_gtks_updated(protocol_interface_info_entry_t *interface_ptr) @@ -734,7 +763,12 @@ void ws_pae_auth_slow_timer(uint16_t seconds) if (!sec_prot_keys_gtk_is_set(pae_auth->sec_keys_nw_info->gtks, i)) { continue; } - uint32_t timer_seconds = sec_prot_keys_gtk_lifetime_decrement(pae_auth->sec_keys_nw_info->gtks, i, current_time, seconds, true); + uint32_t gtk_lifetime_dec_extra_seconds = 0; + if (active_index == i) { + gtk_lifetime_dec_extra_seconds = ws_pae_auth_lifetime_key_frame_cnt_check(pae_auth, i, seconds); + gtk_lifetime_dec_extra_seconds = ws_pae_auth_lifetime_system_time_check(pae_auth, i, seconds, gtk_lifetime_dec_extra_seconds); + } + uint32_t timer_seconds = sec_prot_keys_gtk_lifetime_decrement(pae_auth->sec_keys_nw_info->gtks, i, current_time, seconds + gtk_lifetime_dec_extra_seconds, true); if (active_index == i) { if (!pae_auth->gtk_new_inst_req_exp) { pae_auth->gtk_new_inst_req_exp = ws_pae_timers_gtk_new_install_required(pae_auth->sec_cfg, timer_seconds); @@ -766,6 +800,10 @@ void ws_pae_auth_slow_timer(uint16_t seconds) pae_auth->nw_info_updated(pae_auth->interface_ptr); } } + if (gtk_lifetime_dec_extra_seconds != 0) { + // Update keys to NVM as needed + pae_auth->nw_info_updated(pae_auth->interface_ptr); + } } if (timer_seconds == 0) { @@ -786,6 +824,159 @@ void ws_pae_auth_slow_timer(uint16_t seconds) ws_pae_key_storage_timer(seconds); } +static uint32_t ws_pae_auth_lifetime_key_frame_cnt_check(pae_auth_t *pae_auth, uint8_t gtk_index, uint16_t seconds) +{ + uint32_t decrement_seconds = 0; + + if (pae_auth->prev_frame_cnt_timer > seconds) { + pae_auth->prev_frame_cnt_timer -= seconds; + return 0; + } + pae_auth->prev_frame_cnt_timer = FRAME_CNT_TIMER; + + uint32_t frame_cnt = 0; + if (pae_auth->nw_frame_cnt_read(pae_auth->interface_ptr, &frame_cnt, gtk_index) < 0) { + return 0; + } + + sec_timer_cfg_t *timer_cfg = &pae_auth->sec_cfg->timer_cfg; + + // For GTK lifetime and frame counter space calculate the percent that has been used + uint32_t gtk_lifetime_left = sec_prot_keys_gtk_lifetime_get(pae_auth->sec_keys_nw_info->gtks, gtk_index); + uint32_t gtk_lifetime = timer_cfg->gtk_expire_offset; + uint32_t gtk_lifetime_left_percent = gtk_lifetime_left * 100 / gtk_lifetime; + + uint32_t frame_cnt_left_percent = ((uint64_t)((UINT32_MAX - frame_cnt))) * 100 / UINT32_MAX; + + tr_info("Active GTK lifetime %"PRIu32", frame counter %"PRIu32" percent, counter %"PRIu32, gtk_lifetime_left_percent, frame_cnt_left_percent, frame_cnt); + + /* If frame counter space has been exhausted faster than should be based on GTK lifetime + * decrements GTK lifetime. Do not check until 20% of the frame counter space has been used + * so that we have data from longer time period. As sanity check, validate that GTK lifetime + * is not more than 105% of the GTK lifetime. + */ + uint32_t gtk_new_install_req_seconds = timer_cfg->gtk_expire_offset - timer_cfg->gtk_new_install_req * timer_cfg->gtk_expire_offset / 100; + if ((frame_cnt_left_percent < gtk_lifetime_left_percent && frame_cnt_left_percent < 80) || + gtk_lifetime_left_percent > 105) { + // If not yet on GTK update period + if (gtk_lifetime_left > (gtk_new_install_req_seconds + SECONDS_IN_DAY)) { + uint32_t diff = gtk_lifetime_left_percent - frame_cnt_left_percent; + decrement_seconds = gtk_lifetime * diff / 100 + SECONDS_IN_DAY; + if (decrement_seconds > gtk_lifetime_left - gtk_new_install_req_seconds) { + decrement_seconds = gtk_lifetime_left - gtk_new_install_req_seconds; + } + tr_info("Decrement GTK lifetime percent, seconds %"PRIu32, decrement_seconds); + } + } + + // Calculate how much frame counters have changed and store maximum if larger than previous maximum + uint32_t frame_cnt_diff = 0; + if (pae_auth->prev_frame_cnt_set && frame_cnt > pae_auth->prev_frame_cnt) { + frame_cnt_diff = frame_cnt - pae_auth->prev_frame_cnt; + if (frame_cnt_diff > pae_auth->frame_counters->counter[gtk_index].max_frame_counter_chg) { + pae_auth->frame_counters->counter[gtk_index].max_frame_counter_chg = frame_cnt_diff; + } + } + + tr_info("Frame counter change %"PRIu32", max %"PRIu32, frame_cnt_diff, pae_auth->frame_counters->counter[gtk_index].max_frame_counter_chg); + + /* Calculates an estimate for how much free frame counter space is needed for the GTK update and + * initiates it faster if needed (default length of GTK update is 6 days). + */ + uint32_t max_needed_frame_counters = + pae_auth->frame_counters->counter[gtk_index].max_frame_counter_chg * gtk_new_install_req_seconds / 3600; + // Adds 20% to calculated value + max_needed_frame_counters = max_needed_frame_counters * 120 / 100; + // If estimated value is more than is left starts GTK update right away (if not already started) + if (max_needed_frame_counters >= (UINT32_MAX - frame_cnt)) { + if (gtk_lifetime_left > gtk_new_install_req_seconds) { + decrement_seconds = gtk_lifetime_left - gtk_new_install_req_seconds; + tr_info("Decrement GTK lifetime update, seconds %"PRIu32, decrement_seconds); + } + } + + /* Calculates an estimate for how much free frame counter space is needed for the GTK activation and + * initiates it faster if needed (default length of GTK activation is 60 minutes). + */ + uint32_t gtk_new_activation_time_seconds = timer_cfg->gtk_expire_offset / timer_cfg->gtk_new_act_time; + // Calculates the estimated maximum value for frame counter during GTK update + max_needed_frame_counters = + pae_auth->frame_counters->counter[gtk_index].max_frame_counter_chg * gtk_new_activation_time_seconds / 3600; + // Adds 200% to calculated value + max_needed_frame_counters = max_needed_frame_counters * 300 / 100; + // If estimated value is more than is left starts GTK update right away (if not already started) + if (max_needed_frame_counters >= (UINT32_MAX - frame_cnt)) { + if (gtk_lifetime_left > gtk_new_activation_time_seconds) { + decrement_seconds = gtk_lifetime_left - gtk_new_activation_time_seconds; + tr_info("Decrement GTK lifetime activation, seconds %"PRIu32, decrement_seconds); + } + } + + pae_auth->prev_frame_cnt = frame_cnt; + pae_auth->prev_frame_cnt_set = true; + + return decrement_seconds; +} + +static uint32_t ws_pae_auth_lifetime_system_time_check(pae_auth_t *pae_auth, int8_t gtk_index, uint16_t seconds, uint32_t dec_extra_seconds) +{ + // Read current system time and compare it to previous time + uint64_t current_time = ws_pae_current_time_get(); + if (pae_auth->prev_system_time_set) { + if (current_time > pae_auth->prev_system_time + TIME_MINIMUM_DIFFERENCE) { + pae_auth->system_time_diff += current_time - pae_auth->prev_system_time; + } + } + pae_auth->prev_system_time = current_time; + pae_auth->prev_system_time_set = true; + + uint64_t time_diff = 0; + // Update lifetimes only if time difference is more than hour + if (pae_auth->system_time_diff > TIME_DIFFERENCE_THRESHOLD + seconds + dec_extra_seconds) { + time_diff = pae_auth->system_time_diff - seconds - dec_extra_seconds; + } else { + return dec_extra_seconds; + } + pae_auth->system_time_diff = 0; + + uint32_t new_dec_extra_seconds = dec_extra_seconds; + + if (time_diff > 0) { + /* If the system time has made a large jump then use the stored time to calculate the lifetime + (this implies e.g. that new time has been received from NTP and old time was not valid) */ + if (!ws_pae_time_old_and_new_validate(current_time, current_time + time_diff)) { + // Allow one jump without invalidating active GTK + if (pae_auth->sec_keys_nw_info->system_time_changed == SYSTEM_TIME_NOT_CHANGED) { + pae_auth->sec_keys_nw_info->system_time_changed = SYSTEM_TIME_CHANGED; + tr_info("System time large change ignored; difference: %"PRIu64, time_diff); + time_diff = 0; + } + } + + uint32_t gtk_lifetime_left = sec_prot_keys_gtk_lifetime_get(pae_auth->sec_keys_nw_info->gtks, gtk_index); + sec_timer_cfg_t *timer_cfg = &pae_auth->sec_cfg->timer_cfg; + uint32_t gtk_new_activation_time_seconds = timer_cfg->gtk_expire_offset / timer_cfg->gtk_new_act_time; + + // If there is GTK lifetime left + if (gtk_lifetime_left > (seconds + dec_extra_seconds + time_diff)) { + // If GTK lifetime would be less than new activation time sets decrements time to activation time + if (gtk_lifetime_left - seconds - dec_extra_seconds - time_diff < gtk_new_activation_time_seconds) { + new_dec_extra_seconds = gtk_lifetime_left - gtk_new_activation_time_seconds; + } else { + // Decrements GTK lifetime + new_dec_extra_seconds = dec_extra_seconds + time_diff; + } + } else { + // If there is no GTK lifetime left decrements time to activation time + new_dec_extra_seconds = gtk_lifetime_left - gtk_new_activation_time_seconds; + } + + tr_info("System change difference: %"PRIu64" decrement extra: %"PRIu32" (seconds: %"PRIu16" previous extra %"PRIu32")", time_diff, new_dec_extra_seconds, seconds, dec_extra_seconds); + } + + return new_dec_extra_seconds; +} + static void ws_pae_auth_gtk_key_insert(pae_auth_t *pae_auth) { // Gets index to install the key @@ -962,27 +1153,36 @@ static bool ws_pae_auth_active_limit_reached(uint16_t active_supp, pae_auth_t *p return pae_auth->congestion_get(pae_auth->interface_ptr, active_supp); } +static void ws_pae_auth_waiting_supp_remove_oldest(pae_auth_t *pae_auth, const kmp_addr_t *addr) +{ + supp_entry_t *delete_supp = ns_list_get_last(&pae_auth->waiting_supp_list); + if (!delete_supp) { + return; + } + tr_info("PAE: waiting list full, eui-64: %s, deleted eui-64: %s", trace_array(addr->eui_64, 8), trace_array(delete_supp->addr.eui_64, 8)); + // Create new instance + kmp_api_t *new_kmp = ws_pae_auth_kmp_create_and_start(pae_auth->kmp_service, MSG_PROT, pae_auth->relay_socked_msg_if_instance_id, delete_supp, pae_auth->sec_cfg); + if (!new_kmp) { + return; + } + kmp_api_create_request(new_kmp, MSG_PROT, &delete_supp->addr, &delete_supp->sec_keys); + (void) ws_pae_lib_supp_list_remove(pae_auth, &pae_auth->waiting_supp_list, delete_supp, ws_pae_auth_waiting_supp_deleted); +} + static supp_entry_t *ws_pae_auth_waiting_supp_list_add(pae_auth_t *pae_auth, supp_entry_t *supp_entry, const kmp_addr_t *addr) { // Entry is already allocated if (supp_entry) { + // If the waiting list if full removes the oldest entry from the list + if (pae_auth->waiting_supp_list_size >= WAITING_SUPPLICANT_LIST_MAX_SIZE) { + ws_pae_auth_waiting_supp_remove_oldest(pae_auth, addr); + } ns_list_add_to_start(&pae_auth->waiting_supp_list, supp_entry); pae_auth->waiting_supp_list_size++; } else { // If the waiting list if full removes the oldest entry from the list if (pae_auth->waiting_supp_list_size >= WAITING_SUPPLICANT_LIST_MAX_SIZE) { - supp_entry_t *delete_supp = ns_list_get_last(&pae_auth->waiting_supp_list); - if (!delete_supp) { - return NULL; - } - tr_info("PAE: waiting list full, eui-64: %s, deleted eui-64: %s", trace_array(addr->eui_64, 8), trace_array(delete_supp->addr.eui_64, 8)); - // Create new instance - kmp_api_t *new_kmp = ws_pae_auth_kmp_create_and_start(pae_auth->kmp_service, MSG_PROT, pae_auth->relay_socked_msg_if_instance_id, delete_supp, pae_auth->sec_cfg); - if (!new_kmp) { - return NULL; - } - kmp_api_create_request(new_kmp, MSG_PROT, &delete_supp->addr, &delete_supp->sec_keys); - (void) ws_pae_lib_supp_list_remove(pae_auth, &pae_auth->waiting_supp_list, delete_supp, ws_pae_auth_waiting_supp_deleted); + ws_pae_auth_waiting_supp_remove_oldest(pae_auth, addr); } supp_entry = ws_pae_lib_supp_list_add(&pae_auth->waiting_supp_list, addr); if (!supp_entry) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h index 4b6dd074323..79df0315863 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.h @@ -48,12 +48,13 @@ * \param timer_settings timer settings * \param sec_cfg security configuration * \param sec_keys_nw_info security keys network information + * \param frame_counters frame counters * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, sec_cfg_t *sec_cfg, sec_prot_keys_nw_info_t *sec_keys_nw_info); +int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, sec_cfg_t *sec_cfg, sec_prot_keys_nw_info_t *sec_keys_nw_info, frame_counters_t *frame_counters); /** * ws_pae_auth_addresses_set set relay addresses @@ -260,6 +261,19 @@ typedef void ws_pae_auth_ip_addr_get(protocol_interface_info_entry_t *interface_ */ typedef bool ws_pae_auth_congestion_get(protocol_interface_info_entry_t *interface_ptr, uint16_t active_supp); +/** + * ws_pae_auth_nw_frame_counter_read network frame counter read callback + * + * \param interface_ptr interface + * \param counter frame counter + * \param gtk_index GTK index + * + * \return < 0 failure + * \return >= 0 success + * + */ +typedef int8_t ws_pae_auth_nw_frame_counter_read(protocol_interface_info_entry_t *interface_ptr, uint32_t *counter, uint8_t gtk_index); + /** * ws_pae_auth_cb_register register PAE authenticator callbacks * @@ -270,17 +284,18 @@ typedef bool ws_pae_auth_congestion_get(protocol_interface_info_entry_t *interfa * \param nw_info_updated network keys updated callback * \param ip_addr_get IP addressing information callback * \param congestion_get congestion get callback + * \param nw_frame_cnt_read network frame counter read callback * */ -void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_auth_gtk_hash_set *hash_set, ws_pae_auth_nw_key_insert *nw_key_insert, ws_pae_auth_nw_key_index_set *nw_key_index_set, ws_pae_auth_nw_info_updated *nw_info_updated, ws_pae_auth_ip_addr_get *ip_addr_get, ws_pae_auth_congestion_get *congestion_get); +void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_auth_gtk_hash_set *hash_set, ws_pae_auth_nw_key_insert *nw_key_insert, ws_pae_auth_nw_key_index_set *nw_key_index_set, ws_pae_auth_nw_info_updated *nw_info_updated, ws_pae_auth_ip_addr_get *ip_addr_get, ws_pae_auth_congestion_get *congestion_get, ws_pae_auth_nw_frame_counter_read *nw_frame_cnt_read); #else -#define ws_pae_auth_init(interface_ptr, next_gtks, certs, sec_cfg, sec_keys_nw_info) 1 +#define ws_pae_auth_init(interface_ptr, next_gtks, certs, sec_cfg, sec_keys_nw_info, frame_counters) 1 #define ws_pae_auth_timing_adjust(timing) #define ws_pae_auth_addresses_set(interface_ptr, local_port, remote_addr, remote_port) 1 #define ws_pae_auth_delete NULL -#define ws_pae_auth_cb_register(interface_ptr, hash_set, nw_key_insert, nw_key_index_set, nw_info_updated, ip_addr_get, congestion_get) {(void) hash_set;} +#define ws_pae_auth_cb_register(interface_ptr, hash_set, nw_key_insert, nw_key_index_set, nw_info_updated, ip_addr_get, congestion_get, nw_frame_cnt_read) #define ws_pae_auth_start(interface_ptr) #define ws_pae_auth_gtks_updated NULL #define ws_pae_auth_nw_key_index_update NULL diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c index 805cb07d8bc..fdc0dbfd0a3 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c @@ -26,6 +26,7 @@ #include "ws_management_api.h" #include "ws_bbr_api.h" #include "Service_Libs/utils/ns_file.h" +#include "Service_Libs/utils/ns_time.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_cfg_settings.h" @@ -51,7 +52,7 @@ typedef void ws_pae_timer(uint16_t ticks); typedef int8_t ws_pae_br_addr_write(protocol_interface_info_entry_t *interface_ptr, const uint8_t *eui_64); typedef int8_t ws_pae_br_addr_read(protocol_interface_info_entry_t *interface_ptr, uint8_t *eui_64); typedef void ws_pae_gtks_updated(protocol_interface_info_entry_t *interface_ptr); -typedef int8_t ws_pae_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash); +typedef int8_t ws_pae_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash, bool del_gtk_on_mismatch); typedef int8_t ws_pae_nw_key_index_update(protocol_interface_info_entry_t *interface_ptr, uint8_t index); typedef int8_t ws_pae_nw_info_set(protocol_interface_info_entry_t *interface_ptr, uint16_t pan_id, char *network_name, bool updated); @@ -63,11 +64,15 @@ typedef struct { typedef struct { ns_list_link_t link; /**< Link */ +#ifdef HAVE_PAE_SUPP uint8_t target_eui_64[8]; /**< EAPOL target */ uint16_t target_pan_id; /**< EAPOL target PAN ID */ +#endif uint8_t br_eui_64[8]; /**< Border router EUI-64 */ sec_prot_gtk_keys_t gtks; /**< GTKs */ +#ifdef HAVE_PAE_AUTH sec_prot_gtk_keys_t next_gtks; /**< Next GTKs */ +#endif sec_prot_keys_nw_info_t sec_keys_nw_info; /**< Security keys network information */ int8_t gtk_index; /**< GTK index */ uint8_t gtkhash[32]; /**< GTK hashes */ @@ -79,17 +84,21 @@ typedef struct { sec_cfg_t sec_cfg; /**< Security configuration (configuration set values) */ uint32_t restart_cnt; /**< Re-start counter */ protocol_interface_info_entry_t *interface_ptr; /**< List link entry */ - ws_pae_controller_auth_completed *auth_completed; /**< Authentication completed callback, continue bootstrap */ ws_pae_controller_nw_key_set *nw_key_set; /**< Key set callback */ ws_pae_controller_nw_key_clear *nw_key_clear; /**< Key clear callback */ ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set; /**< Send key index set callback */ ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set; /**< Frame counter set callback */ ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read; /**< Frame counter read callback */ +#ifdef HAVE_PAE_SUPP + ws_pae_controller_auth_completed *auth_completed; /**< Authentication completed callback, continue bootstrap */ + ws_pae_controller_auth_next_target *auth_next_target; /**< Authentication next target callback */ +#endif +#ifdef HAVE_PAE_AUTH ws_pae_controller_pan_ver_increment *pan_ver_increment; /**< PAN version increment callback */ ws_pae_controller_nw_info_updated *nw_info_updated; /**< Network information updated callback */ - ws_pae_controller_auth_next_target *auth_next_target; /**< Authentication next target callback */ ws_pae_controller_congestion_get *congestion_get; /**< Congestion get callback */ ws_pae_controller_ip_addr_get *ip_addr_get; /**< IP address get callback */ +#endif ws_pae_delete *pae_delete; /**< PAE delete callback */ ws_pae_timer *pae_fast_timer; /**< PAE fast timer callback */ ws_pae_timer *pae_slow_timer; /**< PAE slow timer callback */ @@ -119,6 +128,7 @@ static void ws_pae_controller_nw_info_updated_check(protocol_interface_info_entr #ifdef HAVE_PAE_AUTH static void ws_pae_controller_auth_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address); static bool ws_pae_controller_auth_congestion_get(protocol_interface_info_entry_t *interface_ptr, uint16_t active_supp); +static int8_t ws_pae_controller_auth_nw_frame_counter_read(protocol_interface_info_entry_t *interface_ptr, uint32_t *counter, uint8_t gtk_index); #endif static pae_controller_t *ws_pae_controller_get(protocol_interface_info_entry_t *interface_ptr); static void ws_pae_controller_frame_counter_timer(uint16_t seconds, pae_controller_t *entry); @@ -126,10 +136,14 @@ static void ws_pae_controller_frame_counter_store(pae_controller_t *entry, bool static void ws_pae_controller_nvm_frame_counter_write(frame_cnt_nvm_tlv_t *tlv_entry); static int8_t ws_pae_controller_nvm_frame_counter_read(uint32_t *restart_cnt, uint64_t *stored_time, uint16_t *pan_version, frame_counters_t *counters); static pae_controller_t *ws_pae_controller_get_or_create(int8_t interface_id); +#ifdef HAVE_PAE_AUTH static void ws_pae_controller_gtk_hash_set(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash); +#endif static int8_t ws_pae_controller_nw_key_check_and_insert(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks, bool force_install); static void ws_pae_controller_active_nw_key_clear(nw_key_t *nw_key); +#ifdef HAVE_PAE_SUPP static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t *cur, uint8_t index); +#endif static int8_t ws_pae_controller_gak_from_gtk(uint8_t *gak, uint8_t *gtk, char *network_name); static void ws_pae_controller_frame_counter_store_and_nw_keys_remove(protocol_interface_info_entry_t *interface_ptr, pae_controller_t *controller, bool use_threshold); #ifdef HAVE_PAE_AUTH @@ -140,8 +154,8 @@ static int8_t ws_pae_controller_frame_counter_read(pae_controller_t *controller) static void ws_pae_controller_frame_counter_reset(frame_counters_t *frame_counters); static void ws_pae_controller_frame_counter_index_reset(frame_counters_t *frame_counters, uint8_t index); static int8_t ws_pae_controller_nw_info_read(pae_controller_t *controller, sec_prot_gtk_keys_t *gtks); -static int8_t ws_pae_controller_nvm_nw_info_write(protocol_interface_info_entry_t *interface_ptr, uint16_t pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks); -static int8_t ws_pae_controller_nvm_nw_info_read(protocol_interface_info_entry_t *interface_ptr, uint16_t *pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks); +static int8_t ws_pae_controller_nvm_nw_info_write(protocol_interface_info_entry_t *interface_ptr, uint16_t pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t stored_time, uint8_t time_changed); +static int8_t ws_pae_controller_nvm_nw_info_read(protocol_interface_info_entry_t *interface_ptr, uint16_t *pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t current_time, uint8_t *time_changed); static const char *FRAME_COUNTER_FILE = FRAME_COUNTER_FILE_NAME; @@ -196,7 +210,7 @@ int8_t ws_pae_controller_bootstrap_done(protocol_interface_info_entry_t *interfa /* Trigger GTK hash update to supplicant, so it can check whether keys have been updated during bootstrap. Does nothing if GTKs are up to date. */ - ws_pae_supp_gtk_hash_update(interface_ptr, controller->gtkhash); + ws_pae_supp_gtk_hash_update(interface_ptr, controller->gtkhash, false); #endif return 0; @@ -239,7 +253,7 @@ int8_t ws_pae_controller_authenticator_start(protocol_interface_info_entry_t *in ws_pae_auth_node_limit_set(controller->interface_ptr, pae_controller_config.node_limit); } - ws_pae_auth_cb_register(interface_ptr, ws_pae_controller_gtk_hash_set, ws_pae_controller_nw_key_check_and_insert, ws_pae_controller_nw_key_index_check_and_set, ws_pae_controller_nw_info_updated_check, ws_pae_controller_auth_ip_addr_get, ws_pae_controller_auth_congestion_get); + ws_pae_auth_cb_register(interface_ptr, ws_pae_controller_gtk_hash_set, ws_pae_controller_nw_key_check_and_insert, ws_pae_controller_nw_key_index_check_and_set, ws_pae_controller_nw_info_updated_check, ws_pae_controller_auth_ip_addr_get, ws_pae_controller_auth_congestion_get, ws_pae_controller_auth_nw_frame_counter_read); controller->auth_started = true; @@ -248,7 +262,7 @@ int8_t ws_pae_controller_authenticator_start(protocol_interface_info_entry_t *in return 0; } -int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_auth_next_target *auth_next_target, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read, ws_pae_controller_pan_ver_increment *pan_ver_increment, ws_pae_controller_nw_info_updated *nw_info_updated, ws_pae_controller_congestion_get *congestion_get) +int8_t ws_pae_controller_nw_key_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read) { if (!interface_ptr) { return -1; @@ -259,21 +273,40 @@ int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ return -1; } - controller->auth_completed = completed; controller->nw_key_set = nw_key_set; controller->nw_key_clear = nw_key_clear; controller->nw_send_key_index_set = nw_send_key_index_set; controller->nw_frame_counter_set = nw_frame_counter_set; controller->nw_frame_counter_read = nw_frame_counter_read; - controller->pan_ver_increment = pan_ver_increment; - controller->nw_info_updated = nw_info_updated; + return 0; +} + +int8_t ws_pae_controller_authentication_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_auth_next_target *auth_next_target) +{ +#ifdef HAVE_PAE_SUPP + if (!interface_ptr) { + return -1; + } + + pae_controller_t *controller = ws_pae_controller_get(interface_ptr); + if (!controller) { + return -1; + } + + controller->auth_completed = completed; controller->auth_next_target = auth_next_target; - controller->congestion_get = congestion_get; return 0; +#else + (void) interface_ptr; + (void) completed; + (void) auth_next_target; + return 0; +#endif } -int8_t ws_pae_controller_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_ip_addr_get *ip_addr_get) +int8_t ws_pae_controller_information_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_ip_addr_get *ip_addr_get, ws_pae_controller_nw_info_updated *nw_info_updated, ws_pae_controller_congestion_get *congestion_get) { +#ifdef HAVE_PAE_AUTH if (!interface_ptr) { return -1; } @@ -284,11 +317,42 @@ int8_t ws_pae_controller_auth_cb_register(protocol_interface_info_entry_t *inter } controller->ip_addr_get = ip_addr_get; + controller->nw_info_updated = nw_info_updated; + controller->congestion_get = congestion_get; + return 0; +#else + (void) interface_ptr; + (void) ip_addr_get; + (void) nw_info_updated; + (void) congestion_get; + return 0; +#endif +} + +int8_t ws_pae_controller_pan_version_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_pan_ver_increment *pan_ver_increment) +{ +#ifdef HAVE_PAE_AUTH + if (!interface_ptr) { + return -1; + } + + pae_controller_t *controller = ws_pae_controller_get(interface_ptr); + if (!controller) { + return -1; + } + + controller->pan_ver_increment = pan_ver_increment; return 0; +#else + (void) interface_ptr; + (void) pan_ver_increment; + return 0; +#endif } int8_t ws_pae_controller_set_target(protocol_interface_info_entry_t *interface_ptr, uint16_t target_pan_id, uint8_t *target_eui_64) { +#ifdef HAVE_PAE_SUPP if (!interface_ptr) { return -1; } @@ -302,6 +366,12 @@ int8_t ws_pae_controller_set_target(protocol_interface_info_entry_t *interface_p memcpy(controller->target_eui_64, target_eui_64, 8); return 0; +#else + (void) interface_ptr; + (void) target_pan_id; + (void) target_eui_64; + return -1; +#endif } static void ws_pae_controller_keys_nw_info_init(sec_prot_keys_nw_info_t *sec_keys_nw_info, sec_prot_gtk_keys_t *gtks) @@ -376,7 +446,8 @@ static void ws_pae_controller_nw_info_updated_check(protocol_interface_info_entr if (arm_nwk_mac_address_read(interface_ptr->id, &mac_params) >= 0) { memcpy(gtk_eui64, mac_params.mac_long, 8); } - ws_pae_controller_nvm_nw_info_write(interface_ptr, controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.network_name, gtk_eui64, controller->sec_keys_nw_info.gtks); + uint64_t system_time = ws_pae_current_time_get(); + ws_pae_controller_nvm_nw_info_write(interface_ptr, controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.network_name, gtk_eui64, controller->sec_keys_nw_info.gtks, system_time, controller->sec_keys_nw_info.system_time_changed); controller->sec_keys_nw_info.updated = false; sec_prot_keys_gtks_updated_reset(controller->sec_keys_nw_info.gtks); } @@ -410,10 +481,27 @@ static bool ws_pae_controller_auth_congestion_get(protocol_interface_info_entry_ return controller->congestion_get(interface_ptr, active_supp); } + +static int8_t ws_pae_controller_auth_nw_frame_counter_read(protocol_interface_info_entry_t *interface_ptr, uint32_t *counter, uint8_t gtk_index) +{ + if (!interface_ptr) { + return -1; + } + + pae_controller_t *controller = ws_pae_controller_get(interface_ptr); + if (!controller) { + return -1; + } + + controller->nw_frame_counter_read(interface_ptr, counter, gtk_index); + return 0; +} #endif int8_t ws_pae_controller_nw_key_valid(protocol_interface_info_entry_t *interface_ptr, uint8_t *br_iid) { + (void) br_iid; + if (!interface_ptr) { return -1; } @@ -546,19 +634,31 @@ static int8_t ws_pae_controller_gak_from_gtk(uint8_t *gak, uint8_t *gtk, char *n mbedtls_sha256_init(&ctx); +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_starts(&ctx, 0) != 0) { +#else if (mbedtls_sha256_starts_ret(&ctx, 0) != 0) { +#endif ret_val = -1; goto error; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_update(&ctx, input, network_name_len + GTK_LEN) != 0) { +#else if (mbedtls_sha256_update_ret(&ctx, input, network_name_len + GTK_LEN) != 0) { +#endif ret_val = -1; goto error; } uint8_t output[32]; +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_finish(&ctx, output) != 0) { +#else if (mbedtls_sha256_finish_ret(&ctx, output) != 0) { +#endif ret_val = -1; goto error; } @@ -653,6 +753,7 @@ static void ws_pae_controller_nw_key_index_check_and_set(protocol_interface_info } #endif +#ifdef HAVE_PAE_SUPP static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t *cur, uint8_t index) { pae_controller_t *controller = ws_pae_controller_get(cur); @@ -671,6 +772,7 @@ static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t } } +#endif int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr) { @@ -690,15 +792,21 @@ int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr) } controller->interface_ptr = interface_ptr; - controller->auth_completed = NULL; controller->nw_key_set = NULL; controller->nw_key_clear = NULL; controller->nw_send_key_index_set = NULL; controller->nw_frame_counter_set = NULL; + controller->nw_frame_counter_read = NULL; +#ifdef HAVE_PAE_SUPP + controller->auth_completed = NULL; + controller->auth_next_target = NULL; +#endif +#ifdef HAVE_PAE_AUTH controller->pan_ver_increment = NULL; controller->nw_info_updated = NULL; - controller->auth_next_target = NULL; controller->congestion_get = NULL; + controller->ip_addr_get = NULL; +#endif memset(&controller->sec_cfg, 0, sizeof(sec_cfg_t)); @@ -743,7 +851,9 @@ int8_t ws_pae_controller_configure(protocol_interface_info_entry_t *interface_pt static void ws_pae_controller_data_init(pae_controller_t *controller) { +#ifdef HAVE_PAE_SUPP memset(controller->target_eui_64, 0, 8); +#endif memset(controller->br_eui_64, 0, 8); memset(controller->gtkhash, 0, 32); @@ -752,7 +862,9 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) ws_pae_controller_active_nw_key_clear(&controller->nw_key[2]); ws_pae_controller_active_nw_key_clear(&controller->nw_key[3]); +#ifdef HAVE_PAE_SUPP controller->target_pan_id = 0xffff; +#endif controller->pae_delete = NULL; controller->pae_fast_timer = NULL; controller->pae_slow_timer = NULL; @@ -773,7 +885,9 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) controller->auth_started = false; ws_pae_controller_frame_counter_reset(&controller->frame_counters); sec_prot_keys_gtks_init(&controller->gtks); +#ifdef HAVE_PAE_AUTH sec_prot_keys_gtks_init(&controller->next_gtks); +#endif sec_prot_certs_init(&controller->certs); sec_prot_certs_ext_certificate_validation_set(&controller->certs, pae_controller_config.ext_cert_valid_enabled); ws_pae_controller_keys_nw_info_init(&controller->sec_keys_nw_info, &controller->gtks); @@ -792,8 +906,8 @@ static int8_t ws_pae_controller_frame_counter_read(pae_controller_t *controller) // Read frame counters if (ws_pae_controller_nvm_frame_counter_read(&controller->restart_cnt, &stored_time, &controller->sec_keys_nw_info.pan_version, &controller->frame_counters) >= 0) { - // Current time is not valid - if (ws_pae_current_time_set(stored_time) < 0) { + // Check if stored time is not valid + if (ws_pae_stored_time_check_and_set(stored_time) < 0) { ret_value = -1; } // This is used to ensure that PMK replay counters are fresh after each re-start. @@ -837,16 +951,23 @@ static void ws_pae_controller_frame_counter_index_reset(frame_counters_t *frame_ memset(frame_counters->counter[index].gtk, 0, GTK_LEN); frame_counters->counter[index].frame_counter = 0; frame_counters->counter[index].stored_frame_counter = 0; + frame_counters->counter[index].max_frame_counter_chg = 0; frame_counters->counter[index].set = false; } static int8_t ws_pae_controller_nw_info_read(pae_controller_t *controller, sec_prot_gtk_keys_t *gtks) { uint8_t nvm_gtk_eui64[8]; - if (ws_pae_controller_nvm_nw_info_read(controller->interface_ptr, &controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.network_name, nvm_gtk_eui64, gtks) < 0) { + uint64_t system_time = ws_pae_current_time_get(); + + uint8_t system_time_changed = controller->sec_keys_nw_info.system_time_changed; + if (ws_pae_controller_nvm_nw_info_read(controller->interface_ptr, &controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.network_name, nvm_gtk_eui64, gtks, system_time, &controller->sec_keys_nw_info.system_time_changed) < 0) { // If no stored GTKs and network info (pan_id and network name) exits return -1; } + if (system_time_changed != controller->sec_keys_nw_info.system_time_changed) { + controller->sec_keys_nw_info.updated = true; + } /* Get own EUI-64 and compare to the one read from the NVM. In case of mismatch delete GTKs and make full authentication to update keys with new EUI-64 and in case of authenticator to update new @@ -867,21 +988,21 @@ static int8_t ws_pae_controller_nw_info_read(pae_controller_t *controller, sec_p return 0; } -static int8_t ws_pae_controller_nvm_nw_info_write(protocol_interface_info_entry_t *interface_ptr, uint16_t pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks) +static int8_t ws_pae_controller_nvm_nw_info_write(protocol_interface_info_entry_t *interface_ptr, uint16_t pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t stored_time, uint8_t time_changed) { nw_info_nvm_tlv_t *tlv = (nw_info_nvm_tlv_t *) ws_pae_controller_nvm_tlv_get(interface_ptr); if (!tlv) { return -1; } - ws_pae_nvm_store_nw_info_tlv_create(tlv, pan_id, network_name, gtk_eui64, gtks); + ws_pae_nvm_store_nw_info_tlv_create(tlv, pan_id, network_name, gtk_eui64, gtks, stored_time, time_changed); ws_pae_nvm_store_tlv_file_write(NW_INFO_FILE, (nvm_tlv_t *) tlv); return 0; } -static int8_t ws_pae_controller_nvm_nw_info_read(protocol_interface_info_entry_t *interface_ptr, uint16_t *pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks) +static int8_t ws_pae_controller_nvm_nw_info_read(protocol_interface_info_entry_t *interface_ptr, uint16_t *pan_id, char *network_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t current_time, uint8_t *time_changed) { nw_info_nvm_tlv_t *tlv_entry = (nw_info_nvm_tlv_t *) ws_pae_controller_nvm_tlv_get(interface_ptr); if (!tlv_entry) { @@ -894,7 +1015,7 @@ static int8_t ws_pae_controller_nvm_nw_info_read(protocol_interface_info_entry_t return -1; } - if (ws_pae_nvm_store_nw_info_tlv_read(tlv_entry, pan_id, network_name, gtk_eui64, gtks) < 0) { + if (ws_pae_nvm_store_nw_info_tlv_read(tlv_entry, pan_id, network_name, gtk_eui64, gtks, current_time, time_changed) < 0) { return -1; } @@ -939,10 +1060,13 @@ int8_t ws_pae_controller_auth_init(protocol_interface_info_entry_t *interface_pt return -1; } - if (ws_pae_auth_init(controller->interface_ptr, &controller->next_gtks, &controller->certs, &controller->sec_cfg, &controller->sec_keys_nw_info) < 0) { + if (ws_pae_auth_init(controller->interface_ptr, &controller->next_gtks, &controller->certs, &controller->sec_cfg, &controller->sec_keys_nw_info, &controller->frame_counters) < 0) { return -1; } + // For Border Router enable the time acquired as default + ns_time_system_time_acquired_set(); + controller->pae_delete = ws_pae_auth_delete; controller->pae_fast_timer = ws_pae_auth_fast_timer; controller->pae_slow_timer = ws_pae_auth_slow_timer; @@ -966,22 +1090,22 @@ int8_t ws_pae_controller_auth_init(protocol_interface_info_entry_t *interface_pt } sec_prot_keys_gtks_updated_reset(&controller->gtks); } -#endif - - if (ws_pae_controller_nw_info_read(controller, read_gtks_to) >= 0) { + if (read_gtks_to && ws_pae_controller_nw_info_read(controller, read_gtks_to) >= 0) { /* If network information i.e pan_id and network name exists updates bootstrap with it, (in case already configured by application then no changes are made) */ if (controller->nw_info_updated) { controller->nw_info_updated(interface_ptr, controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.pan_version, controller->sec_keys_nw_info.network_name); } - if (!read_gtks_to || sec_prot_keys_gtk_count(read_gtks_to) == 0) { + if (sec_prot_keys_gtk_count(read_gtks_to) == 0) { // Key material invalid or GTKs are expired, delete GTKs from NVM uint8_t gtk_eui64[8] = {0}; // Set GTK EUI-64 to zero - ws_pae_controller_nvm_nw_info_write(controller->interface_ptr, controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.network_name, gtk_eui64, NULL); + uint64_t system_time = ws_pae_current_time_get(); + ws_pae_controller_nvm_nw_info_write(controller->interface_ptr, controller->sec_keys_nw_info.key_pan_id, controller->sec_keys_nw_info.network_name, gtk_eui64, NULL, system_time, controller->sec_keys_nw_info.system_time_changed); } } - +#endif ws_pae_key_storage_init(); + if (read_gtks_to) { ws_pae_key_storage_read(controller->restart_cnt); } else { @@ -1499,6 +1623,7 @@ int8_t ws_pae_controller_gtk_update(int8_t interface_id, uint8_t *gtk[GTK_NUM]) int8_t ws_pae_controller_next_gtk_update(int8_t interface_id, uint8_t *gtk[GTK_NUM]) { +#ifdef HAVE_PAE_AUTH if (!gtk) { return -1; } @@ -1518,6 +1643,11 @@ int8_t ws_pae_controller_next_gtk_update(int8_t interface_id, uint8_t *gtk[GTK_N } return 0; +#else + (void) interface_id; + (void) gtk; + return -1; +#endif } int8_t ws_pae_controller_active_key_update(int8_t interface_id, uint8_t index) @@ -1617,6 +1747,7 @@ void ws_pae_controller_forced_gc(bool full_gc) } } +#ifdef HAVE_PAE_AUTH static void ws_pae_controller_gtk_hash_set(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash) { pae_controller_t *controller = ws_pae_controller_get(interface_ptr); @@ -1641,6 +1772,7 @@ static void ws_pae_controller_gtk_hash_set(protocol_interface_info_entry_t *inte controller->gtkhash_set = true; } } +#endif uint8_t *ws_pae_controller_gtk_hash_ptr_get(protocol_interface_info_entry_t *interface_ptr) { @@ -1662,7 +1794,7 @@ int8_t ws_pae_controller_gtk_hash_update(protocol_interface_info_entry_t *interf memcpy(controller->gtkhash, gtkhash, 32); if (controller->pae_gtk_hash_update) { - return controller->pae_gtk_hash_update(interface_ptr, controller->gtkhash); + return controller->pae_gtk_hash_update(interface_ptr, controller->gtkhash, true); } return 0; @@ -1731,9 +1863,12 @@ static void ws_pae_controller_frame_counter_store(pae_controller_t *entry, bool } uint32_t frame_counter = entry->frame_counters.counter[i].frame_counter; - // If threshold check is disabled or frame counter has advanced for the threshold value, stores the new value - if (!use_threshold || - frame_counter > entry->frame_counters.counter[i].stored_frame_counter + FRAME_COUNTER_STORE_THRESHOLD) { + /* If threshold check is disabled or frame counter has advanced for the threshold value, stores the new value. + If frame counter is at maximum at storage, do not initiate storing */ + if (!use_threshold || ( + (frame_counter > entry->frame_counters.counter[i].stored_frame_counter + FRAME_COUNTER_STORE_THRESHOLD) && + !(entry->frame_counters.counter[i].stored_frame_counter == UINT32_MAX && + frame_counter >= UINT32_MAX - FRAME_COUNTER_STORE_THRESHOLD))) { entry->frame_counters.counter[i].stored_frame_counter = frame_counter; update_needed = true; tr_debug("Stored updated frame counter: index %i value %"PRIu32"", i, frame_counter); @@ -1761,8 +1896,9 @@ static void ws_pae_controller_frame_counter_store(pae_controller_t *entry, bool if (update_needed || entry->frame_cnt_store_force_timer == 0) { tr_debug("Write frame counters: system time %"PRIu32"", protocol_core_monotonic_time / 10); + uint64_t system_time = ws_pae_current_time_get(); // Writes modified frame counters - ws_pae_nvm_store_frame_counter_tlv_create((frame_cnt_nvm_tlv_t *) &entry->pae_nvm_buffer, entry->restart_cnt, entry->sec_keys_nw_info.pan_version, &entry->frame_counters); + ws_pae_nvm_store_frame_counter_tlv_create((frame_cnt_nvm_tlv_t *) &entry->pae_nvm_buffer, entry->restart_cnt, entry->sec_keys_nw_info.pan_version, &entry->frame_counters, system_time); ws_pae_controller_nvm_frame_counter_write((frame_cnt_nvm_tlv_t *) &entry->pae_nvm_buffer); // Reset force interval when ever values are stored diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h index 40cd01fb0b9..ab31a7c75a2 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h @@ -573,6 +573,22 @@ typedef void ws_pae_controller_nw_frame_counter_set(protocol_interface_info_entr */ typedef void ws_pae_controller_nw_frame_counter_read(protocol_interface_info_entry_t *interface_ptr, uint32_t *counter, uint8_t slot); +/** + * ws_pae_controller_nw_key_cb_register register network key control callbacks + * + * \param interface_ptr interface + * \param nw_key_set network key set callback + * \param nw_key_clear network key clear callback + * \param nw_send_key_index_set network send key index set callback + * \param nw_frame_counter_set network frame counter set callback + * \param nw_frame_counter_read network frame counter read callback + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_nw_key_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read); + /** * ws_pae_controller_auth_completed authentication completed callback * @@ -596,12 +612,29 @@ typedef void ws_pae_controller_auth_completed(protocol_interface_info_entry_t *i typedef const uint8_t *ws_pae_controller_auth_next_target(protocol_interface_info_entry_t *interface_ptr, const uint8_t *previous_eui_64, uint16_t *pan_id); /** - * ws_pae_controller_pan_ver_increment PAN version increment callback + * ws_pae_controller_authentication_cb_register register supplicant authentication control callbacks * * \param interface_ptr interface + * \param completed authentication completed callback + * \param next_target authentication next target callback + * + * \return < 0 failure + * \return >= 0 success * */ -typedef void ws_pae_controller_pan_ver_increment(protocol_interface_info_entry_t *interface_ptr); +int8_t ws_pae_controller_authentication_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_auth_next_target *auth_next_target); + +/** + * ws_pae_controller_ip_addr_get gets IP addressing information + * + * \param interface_ptr interface + * \param address IP address + * + * \return < 0 failure + * \return >= 0 success + * + */ +typedef int8_t ws_pae_controller_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address); /** * ws_pae_controller_nw_info_updated network information is updated (read from memory) @@ -626,17 +659,10 @@ typedef void ws_pae_controller_nw_info_updated(protocol_interface_info_entry_t * typedef bool ws_pae_controller_congestion_get(protocol_interface_info_entry_t *interface_ptr, uint16_t active_supp); /** - * ws_pae_controller_cb_register register controller callbacks + * ws_pae_controller_information_cb_register register information callbacks * * \param interface_ptr interface - * \param completed authentication completed callback - * \param next_target authentication next target callback - * \param nw_key_set network key set callback - * \param nw_key_clear network key clear callback - * \param nw_send_key_index_set network send key index set callback - * \param nw_frame_counter_set network frame counter set callback - * \param nw_frame_counter_read network frame counter read callback - * \param pan_ver_increment PAN version increment callback + * \param ip_addr_get IP address get callback * \param nw_info_updated network information updated callback * \param congestion_get congestion get callback * @@ -644,31 +670,27 @@ typedef bool ws_pae_controller_congestion_get(protocol_interface_info_entry_t *i * \return >= 0 success * */ -int8_t ws_pae_controller_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_auth_completed *completed, ws_pae_controller_auth_next_target *auth_next_target, ws_pae_controller_nw_key_set *nw_key_set, ws_pae_controller_nw_key_clear *nw_key_clear, ws_pae_controller_nw_send_key_index_set *nw_send_key_index_set, ws_pae_controller_nw_frame_counter_set *nw_frame_counter_set, ws_pae_controller_nw_frame_counter_read *nw_frame_counter_read, ws_pae_controller_pan_ver_increment *pan_ver_increment, ws_pae_controller_nw_info_updated *nw_info_updated, ws_pae_controller_congestion_get *congestion_get); +int8_t ws_pae_controller_information_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_ip_addr_get *ip_addr_get, ws_pae_controller_nw_info_updated *nw_info_updated, ws_pae_controller_congestion_get *congestion_get); /** - * ws_pae_controller_ip_addr_get gets IP addressing information + * ws_pae_controller_pan_ver_increment PAN version increment callback * * \param interface_ptr interface - * \param address IP address - * - * \return < 0 failure - * \return >= 0 success * */ -typedef int8_t ws_pae_controller_ip_addr_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *address); +typedef void ws_pae_controller_pan_ver_increment(protocol_interface_info_entry_t *interface_ptr); /** - * ws_pae_controller_auth_cb_register register authenticator callbacks + * ws_pae_controller_bbr_control_cb_register register PAN version control callbacks * * \param interface_ptr interface - * \param ip_addr_get IP address get callback + * \param pan_ver_increment PAN version increment callback * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_controller_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_ip_addr_get *ip_addr_get); +int8_t ws_pae_controller_pan_version_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_controller_pan_ver_increment *pan_ver_increment); /** * ws_pae_controller_fast_timer PAE controller fast timer call diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.c index 373f2c0619f..04fd4d47578 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.c @@ -42,6 +42,7 @@ #include "6LoWPAN/ws/ws_pae_key_storage.h" #ifdef HAVE_WS +#ifdef HAVE_PAE_AUTH #define TRACE_GROUP "wsks" @@ -944,7 +945,7 @@ static int8_t ws_pae_key_storage_array_time_update_entry(uint64_t time_differenc #endif } - if (storage_array_entry->pmk_lifetime_set) { + if (storage_array_entry->ptk_lifetime_set) { #ifdef EXTRA_DEBUG_INFO tr_debug("KeyS time update diff: %"PRIi64" PTK OLD t: %i %i eui64: %s", time_difference, STIME_TIME_GET(storage_array_entry->ptk_lifetime), STIME_FORMAT_GET(storage_array_entry->ptk_lifetime), tr_array(storage_array_entry->ptk_eui_64, 8)); #endif @@ -1081,5 +1082,6 @@ static void ws_pae_key_storage_array_ptk_invalid(sec_prot_keys_storage_t *storag storage_array->ptk_lifetime = 0; } +#endif /* HAVE_PAE_AUTH */ #endif /* HAVE_WS */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h index 39e6df60e03..7c170b63318 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_key_storage.h @@ -18,6 +18,8 @@ #ifndef WS_PAE_KEY_STORAGE_H_ #define WS_PAE_KEY_STORAGE_H_ +#ifdef HAVE_PAE_AUTH + /* * Port access entity key storage functions. * @@ -169,4 +171,22 @@ void ws_pae_key_storage_fast_timer(uint16_t ticks); */ uint16_t ws_pae_key_storage_storing_interval_get(void); +#else + +#define ws_pae_key_storage_memory_set(key_storages_number, key_storage_size, key_storages) +#define ws_pae_key_storage_settings_set(alloc_max_number, alloc_size, storing_interval) +#define ws_pae_key_storage_init() +#define ws_pae_key_storage_delete() +#define ws_pae_key_storage_store() +#define ws_pae_key_storage_read(restart_cnt) +#define ws_pae_key_storage_remove() +#define ws_pae_key_storage_supp_write(instance, pae_supp) +#define ws_pae_key_storage_supp_read(instance, eui_64, gtks, certs) +#define ws_pae_key_storage_supp_delete(instance, eui64) +#define ws_pae_key_storage_timer(seconds) +#define ws_pae_key_storage_fast_timer(ticks) +#define ws_pae_key_storage_storing_interval_get() 0 + +#endif + #endif /* WS_PAE_KEY_STORAGE_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c index bc14ba93ab9..e833dc3019c 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c @@ -374,9 +374,6 @@ void ws_pae_lib_supp_list_to_inactive(void *instance, supp_list_t *active_supp_l // Remove supplicant entry ws_pae_lib_supp_list_remove(instance, active_supp_list, entry, supp_deleted); - if (supp_deleted) { - supp_deleted(instance); - } } void ws_pae_lib_supp_list_purge(void *instance, supp_list_t *active_supp_list, uint16_t max_number, uint8_t max_purge, ws_pae_lib_supp_deleted supp_deleted) diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c index 27eacbc45f0..fe5e00d09e0 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.c @@ -40,34 +40,7 @@ #define PAE_NVM_FIELD_NOT_SET 0 // Field is not present #define PAE_NVM_FIELD_SET 1 // Field is present -void ws_pae_nvm_store_generic_tlv_create(nvm_tlv_t *tlv_entry, uint16_t tag, uint16_t length) -{ - tlv_entry->tag = tag; - tlv_entry->len = length; -} - -nvm_tlv_t *ws_pae_nvm_store_generic_tlv_allocate_and_create(uint16_t tag, uint16_t length) -{ - nvm_tlv_t *tlv_entry = ns_dyn_mem_alloc(length + sizeof(nvm_tlv_t)); - if (!tlv_entry) { - return NULL; - } - tlv_entry->tag = tag; - tlv_entry->len = length; - - return tlv_entry; -} - -void ws_pae_nvm_store_generic_tlv_free(nvm_tlv_t *tlv_entry) -{ - if (!tlv_entry) { - return; - } - - ns_dyn_mem_free(tlv_entry); -} - -void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks) +void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t stored_time, uint8_t time_changed) { int len; tlv_entry->tag = PAE_NVM_NW_INFO_TAG; @@ -90,13 +63,14 @@ void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t memcpy((char *)tlv, gtk_eui64, 8); tlv += 8; - uint64_t current_time = ws_pae_current_time_get(); + *tlv++ = time_changed; + tlv = common_write_64_bit(stored_time, tlv); for (uint8_t i = 0; i < GTK_NUM; i++) { if (gtks && sec_prot_keys_gtk_is_set(gtks, i)) { *tlv++ = PAE_NVM_FIELD_SET; // GTK is set - uint64_t expirytime = sec_prot_keys_gtk_exptime_from_lifetime_get(gtks, i, current_time); + uint64_t expirytime = sec_prot_keys_gtk_exptime_from_lifetime_get(gtks, i, stored_time); // Sets stored expiration time to GTKs; no need to update anymore to NVM if not changed sec_prot_keys_gtk_expirytime_set(gtks, i, expirytime); @@ -118,11 +92,11 @@ void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t } } - tr_debug("NVM NW_INFO write PAN ID %i name: %s", pan_id, nw_name); + tr_info("NVM NW_INFO write PAN ID: %i name: %s stored time: %"PRIu64, pan_id, nw_name, stored_time); } -int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t *pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks) +int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t *pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t current_time, uint8_t *time_changed) { if (!tlv_entry || !pan_id || !nw_name) { return -1; @@ -150,9 +124,20 @@ int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t memcpy(gtk_eui64, (char *)tlv, 8); tlv += 8; - uint64_t current_time = ws_pae_current_time_get(); + *time_changed = *tlv++; + uint64_t stored_time = common_read_64_bit(tlv); + tlv += 8; + // Use either stored time or current time as reference when calculating lifetimes + current_time = ws_pae_time_old_or_new_select(stored_time, current_time); + /* If the selected time has made a large jump then use the stored time to calculate the lifetime + (this implies e.g. that new time has been received from NTP and old time was not valid) */ + if (*time_changed == SYSTEM_TIME_NOT_CHANGED && !ws_pae_time_old_and_new_validate(stored_time, current_time)) { + *time_changed = SYSTEM_TIME_CHANGED; + current_time = stored_time; + tr_info("NVM NW_INFO system time change"); + } - tr_debug("NVM NW_INFO current time: %"PRIi64, current_time); + tr_info("NVM NW_INFO current time: %"PRIi64" stored time: %"PRIi64, current_time, stored_time); if (gtks && sec_prot_keys_gtk_count(gtks) == 0) { // If application has not set GTKs read them from NVM @@ -160,9 +145,10 @@ int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t if (*tlv++ == PAE_NVM_FIELD_SET) { /* GTK is set */ uint64_t expirytime = common_read_64_bit(tlv); uint32_t lifetime = 0; + // Calculate lifetime if (ws_pae_time_diff_calc(current_time, expirytime, &lifetime, true) < 0) { tlv += 8 + 1 + 1 + GTK_LEN; - tr_debug("GTK index %i, expired expiry time: %"PRIi64", lifetime: %"PRIi32, i, expirytime, lifetime); + tr_info("GTK index %i, expired expiry time: %"PRIi64", lifetime: %"PRIi32, i, expirytime, lifetime); continue; } tlv += 8; @@ -171,7 +157,7 @@ int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t uint8_t install_order = *tlv++; - tr_debug("GTK index: %i, status: %i, install order %i, expiry time: %"PRIi64", lifetime: %"PRIi32, i, status, install_order, expirytime, lifetime); + tr_info("GTK index: %i, status: %i, install order %i, expiry time: %"PRIi64", lifetime: %"PRIi32, i, status, install_order, expirytime, lifetime); sec_prot_keys_gtk_set(gtks, i, tlv, lifetime); sec_prot_keys_gtk_expirytime_set(gtks, i, expirytime); @@ -185,7 +171,7 @@ int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t sec_prot_keys_gtks_updated_reset(gtks); } - tr_debug("NVM NW_INFO read PAN ID %i name: %s", *pan_id, nw_name); + tr_info("NVM NW_INFO read PAN ID %i name: %s", *pan_id, nw_name); return 0; } @@ -234,7 +220,7 @@ void ws_pae_nvm_store_keys_tlv_create(keys_nvm_tlv_t *tlv_entry, sec_prot_keys_t } tlv += PTK_LEN; - tr_debug("NVM KEYS write"); + tr_info("NVM KEYS write"); } int8_t ws_pae_nvm_store_keys_tlv_read(keys_nvm_tlv_t *tlv_entry, sec_prot_keys_t *sec_keys) @@ -282,12 +268,12 @@ int8_t ws_pae_nvm_store_keys_tlv_read(keys_nvm_tlv_t *tlv_entry, sec_prot_keys_t sec_prot_keys_updated_reset(sec_keys); - tr_debug("NVM KEYS read"); + tr_info("NVM KEYS read"); return 0; } -void ws_pae_nvm_store_frame_counter_tlv_create(frame_cnt_nvm_tlv_t *tlv_entry, uint32_t restart_cnt, uint16_t pan_version, frame_counters_t *counters) +void ws_pae_nvm_store_frame_counter_tlv_create(frame_cnt_nvm_tlv_t *tlv_entry, uint32_t restart_cnt, uint16_t pan_version, frame_counters_t *counters, uint64_t stored_time) { tlv_entry->tag = PAE_NVM_FRAME_COUNTER_TAG; tlv_entry->len = PAE_NVM_FRAME_COUNTER_LEN; @@ -296,7 +282,6 @@ void ws_pae_nvm_store_frame_counter_tlv_create(frame_cnt_nvm_tlv_t *tlv_entry, u tlv = common_write_32_bit(restart_cnt, tlv); - uint64_t stored_time = ws_pae_current_time_get(); tlv = common_write_64_bit(stored_time, tlv); tlv = common_write_16_bit(pan_version, tlv); @@ -304,17 +289,18 @@ void ws_pae_nvm_store_frame_counter_tlv_create(frame_cnt_nvm_tlv_t *tlv_entry, u for (uint8_t index = 0; index < GTK_NUM; index++) { if (!counters->counter[index].set) { *tlv++ = PAE_NVM_FIELD_NOT_SET; - memset(tlv, 0, GTK_LEN + 4); - tlv += GTK_LEN + 4; + memset(tlv, 0, GTK_LEN + 4 + 4); + tlv += GTK_LEN + 4 + 4; continue; } *tlv++ = PAE_NVM_FIELD_SET; memcpy(tlv, counters->counter[index].gtk, GTK_LEN); tlv += GTK_LEN; tlv = common_write_32_bit(counters->counter[index].frame_counter, tlv); + tlv = common_write_32_bit(counters->counter[index].max_frame_counter_chg, tlv); } - tr_debug("NVM FRAME COUNTER write"); + tr_info("NVM FRAME COUNTER write; stored time: %"PRIu64, stored_time); } int8_t ws_pae_nvm_store_frame_counter_tlv_read(frame_cnt_nvm_tlv_t *tlv_entry, uint32_t *restart_cnt, uint64_t *stored_time, uint16_t *pan_version, frame_counters_t *counters) @@ -342,7 +328,7 @@ int8_t ws_pae_nvm_store_frame_counter_tlv_read(frame_cnt_nvm_tlv_t *tlv_entry, u // Frame counter not set if (*tlv++ == PAE_NVM_FIELD_NOT_SET) { counters->counter[index].set = false; - tlv += GTK_LEN + 4; + tlv += GTK_LEN + 4 + 4; continue; } // Frame counter is set, read GTK key and counter values @@ -351,9 +337,11 @@ int8_t ws_pae_nvm_store_frame_counter_tlv_read(frame_cnt_nvm_tlv_t *tlv_entry, u tlv += GTK_LEN; counters->counter[index].frame_counter = common_read_32_bit(tlv); tlv += 4; + counters->counter[index].max_frame_counter_chg = common_read_32_bit(tlv); + tlv += 4; } - tr_debug("NVM FRAME COUNTER read"); + tr_info("NVM FRAME COUNTER read; stored time: %"PRIu64, *stored_time); return 0; } @@ -367,7 +355,7 @@ void ws_pae_nvm_store_key_storage_index_tlv_create(nvm_tlv_t *tlv_entry, uint64_ tlv = common_write_64_bit(bitfield, tlv); - tr_debug("NVM KEY STORAGE INDEX write"); + tr_info("NVM KEY STORAGE INDEX write"); } int8_t ws_pae_nvm_store_key_storage_index_tlv_read(nvm_tlv_t *tlv_entry, uint64_t *bitfield) @@ -384,7 +372,7 @@ int8_t ws_pae_nvm_store_key_storage_index_tlv_read(nvm_tlv_t *tlv_entry, uint64_ *bitfield = common_read_64_bit(tlv); tlv += 8; - tr_debug("NVM KEY STORAGE INDEX read"); + tr_info("NVM KEY STORAGE INDEX read"); return 0; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h index 9194e2b5b98..1e0f0f3214f 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_data.h @@ -35,16 +35,24 @@ #define PAE_NVM_KEY_STORAGE_INDEX_TAG 4 #define PAE_NVM_KEY_STORAGE_TAG 5 -// pan_id (2) + network name (33) + GTK EUI-64 (own EUI-64) (8) + (GTK set (1) + GTK expiry timestamp (8) + status (1) + install order (1) + GTK (16)) * 4 -#define PAE_NVM_NW_INFO_LEN 2 + 33 + 8 + (1 + 8 + 1 + 1 + GTK_LEN) * GTK_NUM +// pan_id (2) + network name (33) + GTK EUI-64 (own EUI-64) (8) + stored time (8) + time changed (1) + (GTK set (1) + GTK expiry timestamp (8) + status (1) + install order (1) + GTK (16)) * 4 +#define PAE_NVM_NW_INFO_LEN 2 + 33 + 8 + 8 + 1 + (1 + 8 + 1 + 1 + GTK_LEN) * GTK_NUM // PTK EUI-64 set (1) + PTK EUI-64 (8) + PMK set (1) + PMK lifetime (4) + PMK (32) + PMK replay counter (8) + PTK set (1) + PTK lifetime (4) + PTK (48) #define PAE_NVM_KEYS_LEN 1 + 8 + 1 + 4 + PMK_LEN + 8 + 1 + 4 + PTK_LEN -// restart counter + stored time + pan version + (frame counter set (1) + GTK (16) + frame counter (4)) * 4 -#define PAE_NVM_FRAME_COUNTER_LEN 4 + 8 + 2 + (1 + GTK_LEN + 4) * GTK_NUM +// restart counter + stored time + pan version + (frame counter set (1) + GTK (16) + frame counter (4) + max frame counter change (4)) * 4 +#define PAE_NVM_FRAME_COUNTER_LEN 4 + 8 + 2 + (1 + GTK_LEN + 4 + 4) * GTK_NUM -#define PAE_NVM_DEFAULT_BUFFER_SIZE sizeof(nvm_tlv_t) + PAE_NVM_NW_INFO_LEN +#if (PAE_NVM_NW_INFO_LEN >= PAE_NVM_KEYS_LEN) && (PAE_NVM_NW_INFO_LEN >= PAE_NVM_FRAME_COUNTER_LEN) +#define PAE_NVM_LARGEST_FILE PAE_NVM_NW_INFO_LEN +#elif (PAE_NVM_KEYS_LEN >= PAE_NVM_NW_INFO_LEN) && (PAE_NVM_KEYS_LEN >= PAE_NVM_FRAME_COUNTER_LEN) +#define PAE_NVM_LARGEST_FILE PAE_NVM_KEYS_LEN +#else +#define PAE_NVM_LARGEST_FILE PAE_NVM_FRAME_COUNTER_LEN +#endif + +#define PAE_NVM_DEFAULT_BUFFER_SIZE sizeof(nvm_tlv_t) + PAE_NVM_LARGEST_FILE // key storage index bitfield (8) #define PAE_NVM_KEY_STORAGE_INDEX_LEN 8 @@ -91,11 +99,13 @@ void ws_pae_nvm_store_generic_tlv_free(nvm_tlv_t *tlv_entry); * \param pan_id PAN ID * \param nw_name network name * \param gtks GTK keys + * \param stored_time stored timestampt + * \param time_changed stored time has changed * * \return TLV entry or NULL * */ -void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks); +void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t stored_time, uint8_t time_changed); /** * ws_pae_nvm_store_nw_info_tlv_read read from NVM network info TLV @@ -104,12 +114,14 @@ void ws_pae_nvm_store_nw_info_tlv_create(nw_info_nvm_tlv_t *tlv_entry, uint16_t * \param pan_id PAN ID * \param nw_name network name * \param gtks GTK keys + * \param current_time current timestampt + * \param time_changed stored time has changed * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t *pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks); +int8_t ws_pae_nvm_store_nw_info_tlv_read(nw_info_nvm_tlv_t *tlv_entry, uint16_t *pan_id, char *nw_name, uint8_t *gtk_eui64, sec_prot_gtk_keys_t *gtks, uint64_t current_time, uint8_t *time_changed); /** * ws_pae_nvm_store_keys_tlv_create create NVM keys TLV @@ -139,9 +151,10 @@ int8_t ws_pae_nvm_store_keys_tlv_read(keys_nvm_tlv_t *tlv_entry, sec_prot_keys_t * \param restart_cnt re-start counter * \param pan_version PAN version * \param counters frame counters + * \param stored_time stored timestampt * */ -void ws_pae_nvm_store_frame_counter_tlv_create(frame_cnt_nvm_tlv_t *tlv_entry, uint32_t restart_cnt, uint16_t pan_version, frame_counters_t *counters); +void ws_pae_nvm_store_frame_counter_tlv_create(frame_cnt_nvm_tlv_t *tlv_entry, uint32_t restart_cnt, uint16_t pan_version, frame_counters_t *counters, uint64_t stored_time); /** * ws_pae_nvm_store_frame_counter_tlv_read read from NVM frame counter TLV diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c index 065d9d0598f..e30a1caad73 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.c @@ -43,6 +43,33 @@ static int8_t ws_pae_nvm_store_create_path(char *fast_data_path, const char *fil static int8_t ws_pae_nvm_store_write(const char *file_name, nvm_tlv_t *tlv); static int8_t ws_pae_nvm_store_read(const char *file_name, nvm_tlv_t *tlv); +void ws_pae_nvm_store_generic_tlv_create(nvm_tlv_t *tlv_entry, uint16_t tag, uint16_t length) +{ + tlv_entry->tag = tag; + tlv_entry->len = length; +} + +nvm_tlv_t *ws_pae_nvm_store_generic_tlv_allocate_and_create(uint16_t tag, uint16_t length) +{ + nvm_tlv_t *tlv_entry = ns_dyn_mem_alloc(length + sizeof(nvm_tlv_t)); + if (!tlv_entry) { + return NULL; + } + tlv_entry->tag = tag; + tlv_entry->len = length; + + return tlv_entry; +} + +void ws_pae_nvm_store_generic_tlv_free(nvm_tlv_t *tlv_entry) +{ + if (!tlv_entry) { + return; + } + + ns_dyn_mem_free(tlv_entry); +} + int8_t ws_pae_nvm_store_tlv_file_write(const char *file, nvm_tlv_t *tlv) { if (!ws_pae_nvm_store_root_path_valid()) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h index 32fd0bafdec..412c57a6dfc 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_nvm_store.h @@ -47,6 +47,38 @@ typedef struct { // tag + length #define NVM_TLV_FIXED_LEN sizeof(nvm_tlv_t) +/** + * ws_pae_nvm_store_generic_tlv_create create NVM generic storage TLV + * + * \param tlv_entry TLV entry + * \param tag tag + * \param length length of the (whole) entry + * + * \return < 0 failure + * \return >= 0 success + * + */ +void ws_pae_nvm_store_generic_tlv_create(nvm_tlv_t *tlv_entry, uint16_t tag, uint16_t length); + +/** + * ws_pae_nvm_store_generic_tlv_allocate_and_create allocate and create NVM generic storage TLV + * + * \param tag tag + * \param length length of the (whole) entry + * + * \return TLV entry or NULL + * + */ +nvm_tlv_t *ws_pae_nvm_store_generic_tlv_allocate_and_create(uint16_t tag, uint16_t length); + +/** + * ws_pae_nvm_store_generic_tlv_free free NVM generic storage TLV + * + * \param tlv_entry TLV entry + * + */ +void ws_pae_nvm_store_generic_tlv_free(nvm_tlv_t *tlv_entry); + /** * ws_pae_nvm_store_tlv_file_write write a list of TLVs to file * diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c index 6aab0d9cae4..8c6cefdb787 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c @@ -294,7 +294,7 @@ static int8_t ws_pae_supp_gtk_hash_mismatch_check(pae_supp_t *pae_supp) } // Check GTK hashes and initiate EAPOL procedure if mismatch is detected */ - gtk_mismatch_e mismatch = sec_prot_keys_gtks_hash_update(pae_supp->sec_keys_nw_info->gtks, gtkhash); + gtk_mismatch_e mismatch = sec_prot_keys_gtks_hash_update(pae_supp->sec_keys_nw_info->gtks, gtkhash, false); if (mismatch != GTK_NO_MISMATCH) { return -1; } @@ -303,7 +303,7 @@ static int8_t ws_pae_supp_gtk_hash_mismatch_check(pae_supp_t *pae_supp) return 0; } -int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash) +int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash, bool del_gtk_on_mismatch) { pae_supp_t *pae_supp = ws_pae_supp_get(interface_ptr); if (!pae_supp) { @@ -311,7 +311,7 @@ int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_pt } // Check GTK hashes and initiate EAPOL procedure if mismatch is detected */ - gtk_mismatch_e mismatch = sec_prot_keys_gtks_hash_update(pae_supp->sec_keys_nw_info->gtks, gtkhash); + gtk_mismatch_e mismatch = sec_prot_keys_gtks_hash_update(pae_supp->sec_keys_nw_info->gtks, gtkhash, del_gtk_on_mismatch); if (mismatch > GTK_NO_MISMATCH) { tr_info("GTK hash update %s %s %s %s", trace_array(>khash[0], 8), @@ -1007,6 +1007,7 @@ static int8_t ws_pae_supp_eapol_pdu_address_check(protocol_interface_info_entry_ static int8_t ws_pae_supp_parent_eui_64_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *eui_64) { rpl_dodag_info_t dodag_info; + (void) dodag_info; // avoid unused warning in ws_host mode if (!interface_ptr->rpl_domain) { return -1; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h index 1ccd78c21ea..377c78ec76f 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.h @@ -130,12 +130,13 @@ int8_t ws_pae_supp_nw_key_valid(protocol_interface_info_entry_t *interface_ptr, * * \param interface_ptr interface * \param gtkhash GTK hash, 32 bytes + * \param del_gtk_on_mismatch Delete GTK in case of mismatch * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash); +int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash, bool del_gtk_on_mismatch); /** * ws_pae_supp_nw_key_index_update key index been updated (on PAN configuration) @@ -264,8 +265,8 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #define ws_pae_supp_init(interface_ptr, certs, sec_timer_cfg, sec_prot_cfg) 1 #define ws_pae_supp_delete NULL #define ws_pae_supp_timing_adjust(timing) 1 -#define ws_pae_supp_cb_register(interface_ptr, completed, nw_key_insert, nw_key_index_set) -#define ws_pae_supp_nw_key_valid(interface_ptr) -1 +#define ws_pae_supp_cb_register(interface_ptr, completed, auth_next_target,nw_key_insert, nw_key_index_set, gtk_hash_ptr_get, nw_info_updated) +#define ws_pae_supp_nw_key_valid(interface_ptr, br_iid) -1 #define ws_pae_supp_fast_timer NULL #define ws_pae_supp_slow_timer NULL #define ws_pae_supp_authenticate(interface_ptr, dest_pan_id, dest_eui_64) PAE_SUPP_NOT_ENABLED @@ -275,6 +276,7 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #define ws_pae_supp_nw_key_index_update NULL #define ws_pae_supp_gtks_set(interface_ptr, gtks) #define ws_pae_supp_eapol_target_remove(interface_ptr) +#define ws_pae_supp_nw_info_set NULL #endif diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.c index 55a3e8b5c68..be7bf77597d 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.c @@ -34,7 +34,9 @@ // Wednesday, January 1, 2020 0:00:00 GMT #define CURRENT_TIME_INIT_VALUE 1577836800 -static uint64_t current_time = CURRENT_TIME_INIT_VALUE; +#define SECONDS_IN_WEEK (7 * 24 * 60 * 60) + +static uint64_t ws_pae_current_time = CURRENT_TIME_INIT_VALUE; uint16_t ws_pae_time_to_short_convert(uint32_t time) { @@ -146,36 +148,76 @@ int8_t ws_pae_time_diff_calc(uint64_t curr_time, uint64_t comp_time, uint32_t *t return 0; } +uint64_t ws_pae_time_old_or_new_select(uint64_t old_time, uint64_t new_time) +{ + // If current time is more than one week in the past use the stored time + if (old_time > SECONDS_IN_WEEK && new_time < old_time - SECONDS_IN_WEEK) { + return old_time; + } + + return new_time; +} + +bool ws_pae_time_old_and_new_validate(uint64_t old_time, uint64_t new_time) +{ + /* If new time is more than one week in the past or more than a month in the + future the old time is not valid */ + if ((old_time > SECONDS_IN_WEEK && new_time < old_time - SECONDS_IN_WEEK) || + new_time > (old_time + SYSTEM_TIME_MAXIMUM_DIFF)) { + return false; + } + + return true; +} + uint64_t ws_pae_current_time_get(void) { + if (!ns_time_system_time_acquired_get()) { + return ws_pae_current_time; + } + uint64_t new_time; if (ns_time_system_time_read(&new_time) == 0) { + new_time = ws_pae_time_old_or_new_select(ws_pae_current_time, new_time); return new_time; } - return current_time; + return ws_pae_current_time; } void ws_pae_current_time_update(uint16_t seconds) { - current_time += seconds; + ws_pae_current_time += seconds; } -int8_t ws_pae_current_time_set(uint64_t time) +int8_t ws_pae_stored_time_check_and_set(uint64_t stored_time) { uint64_t new_system_time; - current_time = time; - tr_debug("Current time set: %"PRIi64, time); + tr_debug("Stored time check and set: %"PRIi64, stored_time); + + if (!ns_time_system_time_acquired_get()) { + ws_pae_current_time = stored_time; + return stored_time; + } if (ns_time_system_time_read(&new_system_time) == 0) { - // System time has gone backwards - if (new_system_time < current_time || new_system_time > current_time + SYSTEM_TIME_MAXIMUM_DIFF) { - tr_error("FATAL: system time less than reference time or more than 12 months in future: %"PRIi64" reference time: %"PRIi64, new_system_time, current_time); - return -1; - } + // Use either stored time or current time as reference when calculating lifetimes + ws_pae_current_time = ws_pae_time_old_or_new_select(stored_time, new_system_time); } + return 0; +} +int8_t ws_pae_current_time_check_and_set(uint64_t current_time) +{ + uint64_t new_system_time; + + tr_debug("Current time check and set: %"PRIi64, current_time); + + if (ns_time_system_time_read(&new_system_time) == 0) { + // Use either stored time or current time as reference when calculating lifetimes + ws_pae_current_time = ws_pae_time_old_or_new_select(current_time, new_system_time); + } return 0; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.h index 41f77ef9fe7..4fb6181ef51 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_time.h @@ -38,7 +38,7 @@ typedef enum { #define STIME_TIME_GET(stime) (stime & STIME_TIME_MASK) // Maximum difference in stored and indicated system time -#define SYSTEM_TIME_MAXIMUM_DIFF (60 * 60 * 24 * 30 * 12) +#define SYSTEM_TIME_MAXIMUM_DIFF (60 * 60 * 24 * 30) // One month /** * ws_pae_time_to_short_convert convert time to short format @@ -87,6 +87,28 @@ bool ws_pae_time_from_short_time_compare(uint16_t short_time1, uint16_t short_ti */ int8_t ws_pae_time_diff_calc(uint64_t curr_time, uint64_t comp_time, uint32_t *time_diff, bool future); +/** + * ws_pae_time_old_or_new_select selected old or new time (based on difference) + * + * \param old_time old time + * \param new_time new time + * + * \return old or new time + * + */ +uint64_t ws_pae_time_old_or_new_select(uint64_t old_time, uint64_t new_time); + +/** + * ws_pae_time_old_and_new_validate validate old and new time (based on difference) + * + * \param old_time old time + * \param new_time new time + * + * \return TRUE old time is valid, FALSE old time is not valid + * + */ +bool ws_pae_time_old_and_new_validate(uint64_t old_time, uint64_t new_time); + /** * ws_pae_current_time_get gets current time * @@ -96,7 +118,7 @@ int8_t ws_pae_time_diff_calc(uint64_t curr_time, uint64_t comp_time, uint32_t *t uint64_t ws_pae_current_time_get(void); /** - * ws_pae_current_time_get updates current time + * ws_pae_current_time_update updates current time * * \param seconds seconds to be added to current time * @@ -104,13 +126,13 @@ uint64_t ws_pae_current_time_get(void); void ws_pae_current_time_update(uint16_t seconds); /** - * ws_pae_current_time_set sets current time + * ws_pae_stored_time_check_and_set stored time check and set current time * - * \param time new time + * \param stored_time stored time * * \return < 0 failure * \return >= 0 success */ -int8_t ws_pae_current_time_set(uint64_t time); +int8_t ws_pae_stored_time_check_and_set(uint64_t stored_time); #endif /* WS_PAE_KEY_STORAGE_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_phy.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_phy.c new file mode 100644 index 00000000000..d6d84709a74 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_phy.c @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "nsconfig.h" +#include "ns_types.h" +#include "ns_trace.h" +#include "ws_management_api.h" + +#ifdef HAVE_WS +#define TRACE_GROUP "wsph" + +uint32_t ws_phy_decode_channel_spacing(uint8_t channel_spacing) +{ + if (CHANNEL_SPACING_100 == channel_spacing) { + return 100000; + } else if (CHANNEL_SPACING_200 == channel_spacing) { + return 200000; + } else if (CHANNEL_SPACING_250 == channel_spacing) { + return 250000; + } else if (CHANNEL_SPACING_400 == channel_spacing) { + return 400000; + } else if (CHANNEL_SPACING_600 == channel_spacing) { + return 600000; + } else if (CHANNEL_SPACING_800 == channel_spacing) { + return 800000; + } else if (CHANNEL_SPACING_1200 == channel_spacing) { + return 1200000; + } + return 0; +} + +uint32_t ws_phy_get_datarate_using_operating_mode(uint8_t operating_mode) +{ + if ((OPERATING_MODE_1a == operating_mode) || (OPERATING_MODE_1b == operating_mode)) { + return 50000; + } else if ((OPERATING_MODE_2a == operating_mode) || (OPERATING_MODE_2b == operating_mode)) { + return 100000; + } else if (OPERATING_MODE_3 == operating_mode) { + return 150000; + } else if ((OPERATING_MODE_4a == operating_mode) || (OPERATING_MODE_4b == operating_mode)) { + return 200000; + } else if (OPERATING_MODE_5 == operating_mode) { + return 300000; + } + return 0; +} + +uint8_t ws_phy_convert_operating_class_to_channel_plan_id(uint8_t operating_class, uint8_t regulatory_domain) +{ + if (regulatory_domain == REG_DOMAIN_KR) { + + } else if (regulatory_domain == REG_DOMAIN_EU) { + if ((operating_class == 1) || (operating_class == 2) || (operating_class == 3) || (operating_class == 4)) { + return operating_class + 31; + } + } else if (regulatory_domain == REG_DOMAIN_IN) { + + } else if ((regulatory_domain == REG_DOMAIN_NA) || (regulatory_domain == REG_DOMAIN_BZ)) { + if ((operating_class == 1) || (operating_class == 2) || (operating_class == 3)) { + return operating_class; + } + } else if (regulatory_domain == REG_DOMAIN_JP) { + + } else if (regulatory_domain == REG_DOMAIN_WW) { + + } + + return 0; +} + +uint8_t ws_phy_convert_operating_mode_to_phy_mode_id(uint8_t operating_mode) +{ + if (OPERATING_MODE_1a == operating_mode) { + return 1; + } else if (OPERATING_MODE_1b == operating_mode) { + return 2; + } else if (OPERATING_MODE_2a == operating_mode) { + return 3; + } else if (OPERATING_MODE_2b == operating_mode) { + return 4; + } else if (OPERATING_MODE_3 == operating_mode) { + return 5; + } else if (OPERATING_MODE_4a == operating_mode) { + return 6; + } else if (OPERATING_MODE_4b == operating_mode) { + return 7; + } else if (OPERATING_MODE_5 == operating_mode) { + return 8; + } + return 0; +} + +uint32_t ws_phy_get_datarate_using_phy_mode_id(uint8_t phy_mode_id) +{ + if (84 == phy_mode_id) { + return 150000; + } else if (85 == phy_mode_id) { + return 200000; + } else if ((68 == phy_mode_id) || (86 == phy_mode_id)) { + return 300000; + } else if ((34 == phy_mode_id) || (51 == phy_mode_id) || (69 == phy_mode_id)) { + return 400000; + } else if ((52 == phy_mode_id) || (70 == phy_mode_id)) { + return 600000; + } else if ((35 == phy_mode_id) || (53 == phy_mode_id)) { + return 800000; + } else if ((36 == phy_mode_id) || (54 == phy_mode_id)) { + return 1200000; + } else if (37 == phy_mode_id) { + return 1600000; + } else if (38 == phy_mode_id) { + return 2400000; + } else if ((1 == phy_mode_id) || (2 == phy_mode_id) || (17 == phy_mode_id) || (18 == phy_mode_id)) { + return 50000; + } else if ((3 == phy_mode_id) || (4 == phy_mode_id) || (19 == phy_mode_id) || (20 == phy_mode_id)) { + return 100000; + } else if ((5 == phy_mode_id) || (21 == phy_mode_id)) { + return 150000; + } else if ((6 == phy_mode_id) || (7 == phy_mode_id) || (22 == phy_mode_id) || (23 == phy_mode_id)) { + return 200000; + } else if ((8 == phy_mode_id) || (24 == phy_mode_id)) { + return 300000; + } + return 0; +} + +uint8_t ws_phy_get_ofdm_option_using_phy_mode_id(uint8_t phy_mode_id) +{ + if ((phy_mode_id >= 34) && (phy_mode_id <= 38)) { + return OFDM_OPTION_1; + } else if ((phy_mode_id >= 51) && (phy_mode_id <= 54)) { + return OFDM_OPTION_2; + } else if ((phy_mode_id >= 68) && (phy_mode_id <= 70)) { + return OFDM_OPTION_3; + } else if ((phy_mode_id >= 84) && (phy_mode_id <= 86)) { + return OFDM_OPTION_4; + } + return 0; +} + +uint8_t ws_phy_get_ofdm_mcs_using_phy_mode_id(uint8_t phy_mode_id) +{ + if (34 == phy_mode_id) { + return OFDM_MCS_2; + } else if ((35 == phy_mode_id) || (51 == phy_mode_id)) { + return OFDM_MCS_3; + } else if ((36 == phy_mode_id) || (52 == phy_mode_id) || (68 == phy_mode_id) || (84 == phy_mode_id)) { + return OFDM_MCS_4; + } else if ((37 == phy_mode_id) || (53 == phy_mode_id) || (69 == phy_mode_id) || (85 == phy_mode_id)) { + return OFDM_MCS_5; + } else if ((38 == phy_mode_id) || (54 == phy_mode_id) || (70 == phy_mode_id) || (86 == phy_mode_id)) { + return OFDM_MCS_6; + } + return 0; +} + +uint8_t ws_phy_get_channel_plan_id_using_phy_mode_id(uint8_t phy_mode_id, uint8_t regulatory_domain, uint8_t base_channel_plan_id) +{ + if (regulatory_domain == REG_DOMAIN_KR) { + + } else if (regulatory_domain == REG_DOMAIN_EU) { + // As on EU domain the PHY mode ID cannot unambiguously define the used channel plan id, use the one which best matches to the base channel plan id + if ((base_channel_plan_id == 32) || (base_channel_plan_id == 33)) { + if ((phy_mode_id == 1) || (phy_mode_id == 17)) { + return 32; + } else if ((phy_mode_id == 3) || (phy_mode_id == 5) || (phy_mode_id == 19) || (phy_mode_id == 21) || ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { + return 33; + } + } else if ((base_channel_plan_id == 36) || (base_channel_plan_id == 37)) { + if ((phy_mode_id == 1) || (phy_mode_id == 17)) { + return 36; + } else if ((phy_mode_id == 3) || (phy_mode_id == 5) || (phy_mode_id == 19) || (phy_mode_id == 21) || ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { + return 37; + } + } else if ((base_channel_plan_id == 34) || (base_channel_plan_id == 35)) { + if ((phy_mode_id == 1) || (phy_mode_id == 17)) { + return 34; + } else if ((phy_mode_id == 3) || (phy_mode_id == 5) || (phy_mode_id == 19) || (phy_mode_id == 21) || ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { + return 35; + } + } + } else if (regulatory_domain == REG_DOMAIN_IN) { + + } else if ((regulatory_domain == REG_DOMAIN_NA) || (regulatory_domain == REG_DOMAIN_BZ)) { + if ((phy_mode_id == 2) || (phy_mode_id == 3) || (phy_mode_id == 18) || (phy_mode_id == 19) || ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { + return 1; + } else if ((phy_mode_id == 5) || (phy_mode_id == 6) || (phy_mode_id == 21) || (phy_mode_id == 22) || ((phy_mode_id >= 68) && (phy_mode_id <= 70))) { + return 2; + } else if ((phy_mode_id == 8) || (phy_mode_id == 24)) { + return 3; + } else if ((phy_mode_id >= 51) && (phy_mode_id <= 54)) { + return 4; + } else if ((phy_mode_id >= 34) && (phy_mode_id <= 38)) { + return 5; + } + } else if (regulatory_domain == REG_DOMAIN_JP) { + + } else if (regulatory_domain == REG_DOMAIN_WW) { + + } + + return 0; +} + +uint16_t ws_phy_get_number_of_channels_using_channel_plan_id(uint8_t channel_plan_id) +{ + if (channel_plan_id == 1) { + return 129; + } else if (channel_plan_id == 2) { + return 64; + } else if (channel_plan_id == 3) { + return 42; + } else if (channel_plan_id == 4) { + return 32; + } else if (channel_plan_id == 5) { + return 21; + } else if (channel_plan_id == 32) { + return 69; + } else if (channel_plan_id == 33) { + return 35; + } else if (channel_plan_id == 34) { + return 55; + } else if (channel_plan_id == 35) { + return 27; + } else if (channel_plan_id == 36) { + return 125; + } else if (channel_plan_id == 37) { + return 62; + } + + return 0; +} + +uint32_t ws_phy_get_channel_spacing_using_channel_plan_id(uint8_t channel_plan_id) +{ + if (channel_plan_id == 1) { + return 200000; + } else if (channel_plan_id == 2) { + return 400000; + } else if (channel_plan_id == 3) { + return 600000; + } else if (channel_plan_id == 4) { + return 800000; + } else if (channel_plan_id == 5) { + return 1200000; + } else if (channel_plan_id == 32) { + return 100000; + } else if (channel_plan_id == 33) { + return 200000; + } else if (channel_plan_id == 34) { + return 100000; + } else if (channel_plan_id == 35) { + return 200000; + } else if (channel_plan_id == 36) { + return 100000; + } else if (channel_plan_id == 37) { + return 200000; + } + + return 0; +} + +uint32_t ws_phy_get_channel_0_frequency_using_channel_plan_id(uint8_t channel_plan_id) +{ + if (channel_plan_id == 1) { + return 902200000; + } else if (channel_plan_id == 2) { + return 902400000; + } else if (channel_plan_id == 3) { + return 902600000; + } else if (channel_plan_id == 4) { + return 902800000; + } else if (channel_plan_id == 5) { + return 903200000; + } else if (channel_plan_id == 32) { + return 863100000; + } else if (channel_plan_id == 33) { + return 863100000; + } else if (channel_plan_id == 34) { + return 870100000; + } else if (channel_plan_id == 35) { + return 870200000; + } else if (channel_plan_id == 36) { + return 863100000; + } else if (channel_plan_id == 37) { + return 863100000; + } + + return 0; +} + +bool ws_phy_get_fsk_fec_enabled_using_phy_mode_id(uint8_t phy_mode_id) +{ + if ((phy_mode_id >= 17) && (phy_mode_id <= 24)) { + return true; + } + return false; +} + +phy_modulation_e ws_phy_get_modulation_using_phy_mode_id(uint8_t phy_mode_id) +{ + if (((phy_mode_id >= 34) && (phy_mode_id <= 38)) || + ((phy_mode_id >= 51) && (phy_mode_id <= 54)) || + ((phy_mode_id >= 68) && (phy_mode_id <= 70)) || + ((phy_mode_id >= 84) && (phy_mode_id <= 86))) { + return M_OFDM; + } else if (((phy_mode_id >= 1) && (phy_mode_id <= 8)) || ((phy_mode_id >= 17) && (phy_mode_id <= 24))) { + return M_2FSK; + } else { + return M_UNDEFINED; + } +} + +phy_modulation_index_e ws_phy_get_modulation_index_using_phy_mode_id(uint8_t phy_mode_id) +{ + if (ws_phy_get_modulation_using_phy_mode_id(phy_mode_id) != M_2FSK) { + return MODULATION_INDEX_UNDEFINED; + } + + if ((2 == phy_mode_id) || (18 == phy_mode_id) || + (4 == phy_mode_id) || (20 == phy_mode_id) || + (7 == phy_mode_id) || (23 == phy_mode_id)) { + return MODULATION_INDEX_1_0; + } + return MODULATION_INDEX_0_5; +} + +phy_modulation_index_e ws_phy_get_modulation_index_using_operating_mode(uint8_t operating_mode) +{ + if ((OPERATING_MODE_1b == operating_mode) || (OPERATING_MODE_2b == operating_mode) || (OPERATING_MODE_4b == operating_mode)) { + return MODULATION_INDEX_1_0; + } else { + return MODULATION_INDEX_0_5; + } +} + + +#endif //HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_phy.h b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_phy.h new file mode 100644 index 00000000000..5b4603e7203 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_phy.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_PHY_H_ +#define WS_PHY_H_ + +uint32_t ws_phy_decode_channel_spacing(uint8_t channel_spacing); + +uint32_t ws_phy_get_datarate_using_operating_mode(uint8_t operating_mode); + +uint8_t ws_phy_convert_operating_class_to_channel_plan_id(uint8_t operating_class, uint8_t regulatory_domain); + +uint8_t ws_phy_convert_operating_mode_to_phy_mode_id(uint8_t operating_mode); + +uint8_t ws_phy_get_channel_plan_id_using_phy_mode_id(uint8_t phy_mode_id, uint8_t regulatory_domain, uint8_t base_channel_plan_id); + +uint32_t ws_phy_get_datarate_using_phy_mode_id(uint8_t phy_mode_id); + +uint8_t ws_phy_get_ofdm_option_using_phy_mode_id(uint8_t phy_mode_id); + +uint8_t ws_phy_get_ofdm_mcs_using_phy_mode_id(uint8_t phy_mode_id); + +uint16_t ws_phy_get_number_of_channels_using_channel_plan_id(uint8_t channel_plan_id); + +uint32_t ws_phy_get_channel_spacing_using_channel_plan_id(uint8_t channel_plan_id); + +uint32_t ws_phy_get_channel_0_frequency_using_channel_plan_id(uint8_t channel_plan_id); + +bool ws_phy_get_fsk_fec_enabled_using_phy_mode_id(uint8_t phy_mode_id); + +phy_modulation_e ws_phy_get_modulation_using_phy_mode_id(uint8_t phy_mode_id); + +phy_modulation_index_e ws_phy_get_modulation_index_using_phy_mode_id(uint8_t phy_mode_id); + +phy_modulation_index_e ws_phy_get_modulation_index_using_operating_mode(uint8_t operating_mode); + +#endif //WS_PHY_H_ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_test_api.c b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_test_api.c index 9dd322a752f..902cc352b69 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_test_api.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_test_api.c @@ -21,6 +21,7 @@ #include "ns_list.h" #include "nsdynmemLIB.h" #include "net_ws_test.h" +#include "net_ws_test_ext.h" #include "fhss_config.h" #include "ws_management_api.h" #include "mac_api.h" @@ -32,6 +33,7 @@ #include "6LoWPAN/ws/ws_bbr_api_internal.h" #include "6LoWPAN/ws/ws_pae_controller.h" #include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/ws/ws_bootstrap.h" #include "randLIB.h" #include "ns_trace.h" @@ -41,6 +43,25 @@ #ifdef HAVE_WS +int ws_test_version_set(int8_t interface_id, uint8_t version) +{ + test_pan_version = version; + + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (cur) { + if (!ws_info(cur)) { + return -1; + } + cur->ws_info->version = version; + if (ws_version_1_0(cur)) { + cur->ws_info->pan_information.version = WS_FAN_VERSION_1_0; + } else if (ws_version_1_1(cur)) { + cur->ws_info->pan_information.version = WS_FAN_VERSION_1_1; + } + } + return 0; +} + int ws_test_pan_size_set(int8_t interface_id, uint16_t pan_size) { @@ -88,7 +109,7 @@ int ws_test_key_lifetime_set(int8_t interface_id, uint32_t gtk_lifetime, uint32_ } ws_sec_timer_cfg_t cfg; - if (ws_cfg_sec_timer_get(&cfg, NULL) < 0) { + if (ws_cfg_sec_timer_get(&cfg) < 0) { return -2; } @@ -102,7 +123,7 @@ int ws_test_key_lifetime_set(int8_t interface_id, uint32_t gtk_lifetime, uint32_ cfg.ptk_lifetime = ptk_lifetime; } - if (ws_cfg_sec_timer_set(cur, NULL, &cfg, NULL) < 0) { + if (ws_cfg_sec_timer_set(cur, &cfg, 0x00) < 0) { return -3; } @@ -119,7 +140,7 @@ int ws_test_gtk_time_settings_set(int8_t interface_id, uint8_t revocat_lifetime_ } ws_sec_timer_cfg_t cfg; - if (ws_cfg_sec_timer_get(&cfg, NULL) < 0) { + if (ws_cfg_sec_timer_get(&cfg) < 0) { return -2; } @@ -136,7 +157,7 @@ int ws_test_gtk_time_settings_set(int8_t interface_id, uint8_t revocat_lifetime_ cfg.gtk_max_mismatch = max_mismatch; } - if (ws_cfg_sec_timer_set(cur, NULL, &cfg, NULL) < 0) { + if (ws_cfg_sec_timer_set(cur, &cfg, 0x00) < 0) { return -3; } @@ -177,4 +198,27 @@ int ws_test_neighbour_temporary_lifetime_set(int8_t interface_id, uint32_t tempo return 0; } +int ws_test_procedure_trigger(int8_t interface_id, ws_test_proc_t procedure, void *parameters) +{ + (void) parameters; + + protocol_interface_info_entry_t *cur = NULL;; + + if (interface_id > 0) { + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !ws_info(cur)) { + return -1; + } + } else { + cur = protocol_stack_interface_info_get_wisun_mesh(); + if (!cur) { + if (procedure != PROC_AUTO_ON && procedure != PROC_AUTO_OFF) { + return -1; + } + } + } + + return ws_bootstrap_test_procedure_trigger(cur, (ws_bootsrap_procedure_t) procedure); +} + #endif // HAVE_WS diff --git a/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/CMakeLists.txt index 74cb0490de9..3f0d5fafce8 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/border_router.c b/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/border_router.c index 02836da0d85..00964f3a197 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/border_router.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/BorderRouter/border_router.c @@ -114,7 +114,7 @@ void nd_border_router_setup_refresh(nwk_interface_id id, bool fresh_abro) nd_router_object->life_time = nd_configure->life_time; if (!ns_list_is_empty(&nd_router_object->prefix_list)) { - tr_debug("Release Prefix\n"); + tr_debug("Release Prefix"); icmpv6_prefix_list_free(&nd_router_object->prefix_list); } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/CMakeLists.txt index 7cd6f34eac2..31bcdffc227 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6_radv.c b/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6_radv.c index 9ad0544322d..f49f7303bb3 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6_radv.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6_radv.c @@ -326,6 +326,7 @@ void icmpv6_stop_router_advertisements(protocol_interface_info_entry_t *cur, con static void icmpv6_send_ra(protocol_interface_info_entry_t *cur, const uint8_t *dest, const uint8_t *abro) { #ifndef HAVE_RPL + (void) dest; (void) abro; #endif if (cur->nwk_id == IF_6LoWPAN) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Core/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/Core/CMakeLists.txt index aa1aebd641f..ae8903fe3ff 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Core/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/Core/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c b/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c index c7c69d2d39e..023ce2880e0 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_address_internal.c @@ -371,7 +371,7 @@ void addr_policy_table_print(void) ns_list_foreach(addr_policy_table_entry_t, entry, &addr_policy_table) { char addr[40]; ip6tos(entry->prefix, addr); - tr_debug("%3d %3d %s/%u\n", entry->precedence, entry->label, addr, entry->prefix_len); + tr_debug("%3d %3d %s/%u", entry->precedence, entry->label, addr, entry->prefix_len); } } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c b/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c index 77dade5ccf4..c520c20279b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Core/ns_socket.c @@ -834,12 +834,12 @@ void socket_list_print(route_print_fn_t *print_fn, char sep) /* Chuck in a consistency check */ for (int i = 0; i < SOCKETS_MAX; i++) { if (socket_instance[i] && socket_instance[i]->id != i) { - tr_err("ID %d points to %p with id %d\n", i, (void *)socket_instance[i], socket_instance[i]->id); + tr_err("ID %d points to %p with id %d", i, (void *)socket_instance[i], socket_instance[i]->id); } } ns_list_foreach(socket_t, socket, &socket_list) { if (socket->id != -1 && socket_pointer_get(socket->id) != socket) { - tr_err("Socket %p has invalid ID %d\n", (void *)socket, socket->id); + tr_err("Socket %p has invalid ID %d", (void *)socket, socket->id); } sockbuf_check(&socket->rcvq); sockbuf_check(&socket->sndq); @@ -1438,6 +1438,10 @@ buffer_t *socket_tx_buffer_event(buffer_t *buf, uint8_t status) if (buf->ack_receive_cb) { buf->ack_receive_cb(buf, status); } + if (status == SOCKET_BUSY) { + //SOCKET_BUSY shuold not be forward further and switched back orginal behaviour + status = SOCKET_TX_FAIL; + } /* Suppress events once socket orphaned */ if (!buf->socket || (buf->socket->flags & (SOCKET_FLAG_PENDING | SOCKET_FLAG_CLOSED))) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_Server/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_Server/CMakeLists.txt index 82e65cea29b..f62037f1219 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_Server/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_Server/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/CMakeLists.txt index 8a37141a160..1838ab01534 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c b/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c index 15b2dbe4cc9..6000e854454 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c @@ -212,7 +212,7 @@ void dhcp_client_delete(int8_t interface) do { srv_data_ptr = libdhcpv6_nonTemporal_entry_get_by_instance(dhcp_client->libDhcp_instance); if (srv_data_ptr != NULL) { - tr_debug("Free DHCPv6 Client\n"); + tr_debug("Free DHCPv6 Client"); memcpy(temporary_address, srv_data_ptr->iaNontemporalAddress.addressPrefix, 16); dhcp_service_req_remove_all(srv_data_ptr);// remove all pending retransmissions libdhcvp6_nontemporalAddress_server_data_free(srv_data_ptr); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/MAC/CMakeLists.txt index 2e67a768106..6dec6f74a7d 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack @@ -19,6 +19,7 @@ target_sources(mbed-nanostack-sal_stack IEEE802_15_4/mac_indirect_data.c IEEE802_15_4/mac_mcps_sap.c IEEE802_15_4/mac_mlme.c + IEEE802_15_4/mac_mode_switch.c IEEE802_15_4/mac_pd_sap.c IEEE802_15_4/mac_security_mib.c IEEE802_15_4/mac_timer.c diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_cca_threshold.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_cca_threshold.c index 1b3a94253b6..f4ce92fbe47 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_cca_threshold.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_cca_threshold.c @@ -137,7 +137,7 @@ int8_t mac_cca_threshold_update(protocol_interface_rf_mac_setup_s *rf_ptr, uint8 return -1; } } - tr_debug("Channel %u CCA threshold to %i", channel, rf_ptr->cca_threshold->ch_thresholds[channel]); + tr_info("Channel %u CCA threshold to %i", channel, rf_ptr->cca_threshold->ch_thresholds[channel]); return 0; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_data_buffer.h b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_data_buffer.h index a76016cb4d5..f3d97a04a05 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_data_buffer.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_data_buffer.h @@ -96,6 +96,7 @@ typedef struct mac_pre_build_frame { uint8_t cca_request_restart_cnt; uint8_t tx_request_restart_cnt; uint8_t priority; + uint8_t phy_mode_id; uint32_t blacklist_start_time_us; uint16_t blacklist_period_ms; uint16_t initial_tx_channel; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h index c55b5085f40..ee76ad67ada 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h @@ -43,7 +43,8 @@ typedef enum mac_event_t { MAC_ACK_SECURITY_FAIL, MAC_UNKNOWN_DESTINATION, MAC_TX_PRECOND_FAIL, - MAC_RETURN_TO_QUEUE + MAC_RETURN_TO_QUEUE, + MAC_MODE_SWITCH_TIMEOUT } mac_event_t; typedef enum mac_tx_status_type_t { @@ -95,11 +96,21 @@ typedef enum arm_nwk_mlme_event_type { ARM_NWK_MAC_MLME_INDIRECT_DATA_POLL_AFTER_DATA = 5, } arm_nwk_mlme_event_type_e; +typedef enum mac_mode_switch_states { + MAC_MS_IDLE = 0, + MAC_MS_PHR_SEND_READY, + MAC_MS_DATA_SEND_READY, + MAC_MS_PHR_RECEIVED, + MAC_MS_DATA_RECEIVED, + MAC_MS_TIMEOUT +} mac_mode_switch_states_e; + #define ENHANCED_ACK_MAX_LENGTH 255 typedef struct dev_driver_tx_buffer { uint8_t *buf; uint8_t *enhanced_ack_buf; + uint8_t mode_switch_phr_buf[2]; uint16_t ack_len; uint16_t len; unsigned priority: 2; @@ -180,6 +191,7 @@ typedef struct protocol_interface_rf_mac_setup { bool mac_ack_tx_active: 1; bool mac_edfe_tx_active: 1; bool mac_edfe_response_tx_active: 1; + bool mac_mode_switch_phr_tx_active: 1; bool mac_frame_pending: 1; /* MAC Capability Information */ bool macCapRxOnIdle: 1; @@ -228,6 +240,8 @@ typedef struct protocol_interface_rf_mac_setup { uint8_t mac_channel; uint8_t mac_tx_start_channel; + uint8_t base_phy_mode; + mac_mode_switch_states_e mode_switch_state; //uint8_t cca_failure; /* MAC TX Queue */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c index 6e952174f45..145d43bf10e 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c @@ -48,6 +48,7 @@ #include "MAC/IEEE802_15_4/mac_header_helper_functions.h" #include "MAC/IEEE802_15_4/mac_indirect_data.h" #include "MAC/IEEE802_15_4/mac_cca_threshold.h" +#include "MAC/IEEE802_15_4/mac_mode_switch.h" #include "MAC/rf_driver_storage.h" #include "sw_mac.h" @@ -156,7 +157,7 @@ void mcps_sap_data_req_handler(protocol_interface_rf_mac_setup_s *rf_mac_setup, { mcps_data_req_ie_list_t ie_list; memset(&ie_list, 0, sizeof(mcps_data_req_ie_list_t)); - mcps_sap_data_req_handler_ext(rf_mac_setup, data_req, &ie_list, NULL, MAC_DATA_NORMAL_PRIORITY); + mcps_sap_data_req_handler_ext(rf_mac_setup, data_req, &ie_list, NULL, MAC_DATA_NORMAL_PRIORITY, 0); } static bool mac_ie_vector_length_validate(ns_ie_iovec_t *ie_vector, uint16_t iov_length, uint16_t *length_out) @@ -195,8 +196,9 @@ static bool mac_ie_vector_length_validate(ns_ie_iovec_t *ie_vector, uint16_t iov } -void mcps_sap_data_req_handler_ext(protocol_interface_rf_mac_setup_s *rf_mac_setup, const mcps_data_req_t *data_req, const mcps_data_req_ie_list_t *ie_list, const channel_list_s *asynch_channel_list, mac_data_priority_t priority) +void mcps_sap_data_req_handler_ext(protocol_interface_rf_mac_setup_s *rf_mac_setup, const mcps_data_req_t *data_req, const mcps_data_req_ie_list_t *ie_list, const channel_list_s *asynch_channel_list, mac_data_priority_t priority, uint8_t phy_mode_id) { + (void) phy_mode_id; uint8_t status = MLME_SUCCESS; mac_pre_build_frame_t *buffer = NULL; @@ -292,6 +294,7 @@ void mcps_sap_data_req_handler_ext(protocol_interface_rf_mac_setup_s *rf_mac_set buffer->fcf_dsn.frametype = FC_DATA_FRAME; buffer->ExtendedFrameExchange = data_req->ExtendedFrameExchange; buffer->WaitResponse = data_req->TxAckReq; + buffer->phy_mode_id = phy_mode_id; if (data_req->ExtendedFrameExchange) { buffer->fcf_dsn.ackRequested = false; } else { @@ -1106,6 +1109,10 @@ static void mac_mcps_asynch_finish(protocol_interface_rf_mac_setup_s *rf_mac_set static bool mcps_sap_check_buffer_timeout(protocol_interface_rf_mac_setup_s *rf_mac_setup, mac_pre_build_frame_t *buffer) { + // Timestamp is not implemented by virtual RF driver. Do not check buffer age. + if (rf_mac_setup->dev_driver->phy_driver->arm_net_virtual_tx_cb) { + return false; + } // Convert from 1us slots to seconds uint32_t buffer_age_s = (mac_mcps_sap_get_phy_timestamp(rf_mac_setup) - buffer->request_start_time_us) / 1000000; // Do not timeout broadcast frames. Broadcast interval could be very long. @@ -1834,6 +1841,12 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt mac_security_authentication_data_params_set(&ccm_ptr, mhr_start, (buffer->mac_header_length_with_security + open_payload)); ccm_process_run(&ccm_ptr); } + // Packet is sent using mode switch. Build mode switch PHR + if (buffer->phy_mode_id) { + if (mac_build_mode_switch_phr(rf_ptr, tx_buf->mode_switch_phr_buf, buffer->phy_mode_id)) { + return -1; + } + } return 0; } @@ -2083,6 +2096,7 @@ int8_t mcps_generic_ack_build(protocol_interface_rf_mac_setup_s *rf_ptr, bool in phy_csma_params_t csma_params; csma_params.backoff_time = 0; csma_params.cca_enabled = false; + csma_params.mode_switch_phr = false; rf_ptr->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_CSMA_PARAMETERS, (uint8_t *) &csma_params); if (rf_ptr->active_pd_data_request) { timer_mac_stop(rf_ptr); @@ -2197,8 +2211,10 @@ static int8_t mcps_pd_data_cca_trig(protocol_interface_rf_mac_setup_s *rf_ptr, m rf_ptr->mac_edfe_tx_active = true; } + } else if (buffer->phy_mode_id) { + rf_ptr->mac_mode_switch_phr_tx_active = true; + cca_enabled = true; } else { - if (rf_ptr->mac_ack_tx_active) { mac_csma_backoff_start(rf_ptr); platform_exit_critical(); @@ -2209,13 +2225,13 @@ static int8_t mcps_pd_data_cca_trig(protocol_interface_rf_mac_setup_s *rf_ptr, m } // Use double CCA check with FHSS for data packets only - if (rf_ptr->fhss_api && !rf_ptr->mac_ack_tx_active && !rf_ptr->mac_edfe_tx_active && !rf_ptr->active_pd_data_request->asynch_request) { + if (rf_ptr->fhss_api && !rf_ptr->mac_ack_tx_active && !rf_ptr->mac_edfe_tx_active && !rf_ptr->active_pd_data_request->asynch_request && !rf_ptr->mac_mode_switch_phr_tx_active) { if ((buffer->tx_time - (rf_ptr->multi_cca_interval * (rf_ptr->number_of_csma_ca_periods - 1))) > mac_mcps_sap_get_phy_timestamp(rf_ptr)) { buffer->csma_periods_left = rf_ptr->number_of_csma_ca_periods - 1; buffer->tx_time -= (rf_ptr->multi_cca_interval * (rf_ptr->number_of_csma_ca_periods - 1)); } } - mac_pd_sap_set_phy_tx_time(rf_ptr, buffer->tx_time, cca_enabled); + mac_pd_sap_set_phy_tx_time(rf_ptr, buffer->tx_time, cca_enabled, rf_ptr->mac_mode_switch_phr_tx_active); if (mac_plme_cca_req(rf_ptr) != 0) { if (buffer->fcf_dsn.frametype == MAC_FRAME_ACK || (buffer->ExtendedFrameExchange && rf_ptr->mac_edfe_response_tx_active)) { //ACK or EFDE Response diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h index 94247d58b87..db986d26eeb 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h @@ -123,7 +123,7 @@ int8_t mac_virtual_sap_data_cb(void *identifier, struct arm_phy_sap_msg_s *messa void mcps_sap_data_req_handler(struct protocol_interface_rf_mac_setup *rf_mac_setup, const struct mcps_data_req_s *data_req); -void mcps_sap_data_req_handler_ext(struct protocol_interface_rf_mac_setup *rf_mac_setup, const struct mcps_data_req_s *data_req, const struct mcps_data_req_ie_list *ie_list, const channel_list_s *asynch_channel_list, mac_data_priority_t priority); +void mcps_sap_data_req_handler_ext(struct protocol_interface_rf_mac_setup *rf_mac_setup, const struct mcps_data_req_s *data_req, const struct mcps_data_req_ie_list *ie_list, const channel_list_s *asynch_channel_list, mac_data_priority_t priority, uint8_t phy_mode_id); void mac_mcps_trig_buffer_from_queue(struct protocol_interface_rf_mac_setup *rf_mac_setup); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c index 9d39b35202e..0e6e7c6c501 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c @@ -71,6 +71,7 @@ static void mac_mlme_start_confirm_handler(protocol_interface_rf_mac_setup_s *rf static void mac_mlme_scan_confirm_handler(protocol_interface_rf_mac_setup_s *rf_ptr, const mlme_scan_conf_t *conf); static int mac_mlme_set_symbol_rate(protocol_interface_rf_mac_setup_s *rf_mac_setup); static int mac_mlme_allocate_tx_buffers(protocol_interface_rf_mac_setup_s *rf_mac_setup, arm_device_driver_list_s *dev_driver, uint16_t mtu_size); +static int mac_mlme_allocate_beacon_payload_buffer(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint16_t mtu_size); static void mac_mlme_energy_scan_start(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint8_t channel) { @@ -826,7 +827,7 @@ int8_t mac_mlme_set_req(protocol_interface_rf_mac_setup_s *rf_mac_setup, const m case macCCAThreshold: pu8 = (uint8_t *) set_req->value_pointer; rf_mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_CCA_THRESHOLD, pu8); - tr_debug("Set CCA threshold to %u%%", *pu8); + tr_info("Set CCA threshold to %u%%", *pu8); return 0; case macMultiCSMAParameters: return mac_mlme_set_multi_csma_parameters(rf_mac_setup, set_req); @@ -1133,7 +1134,6 @@ static int mac_mlme_set_symbol_rate(protocol_interface_rf_mac_setup_s *rf_mac_se static int mac_mlme_allocate_tx_buffers(protocol_interface_rf_mac_setup_s *rf_mac_setup, arm_device_driver_list_s *dev_driver, uint16_t mtu_size) { ns_dyn_mem_free(rf_mac_setup->dev_driver_tx_buffer.buf); - ns_dyn_mem_free(rf_mac_setup->mac_beacon_payload); uint16_t total_length = 0; //Allocate tx buffer by given MTU + header + tail total_length = mtu_size; @@ -1142,15 +1142,26 @@ static int mac_mlme_allocate_tx_buffers(protocol_interface_rf_mac_setup_s *rf_ma if (!rf_mac_setup->dev_driver_tx_buffer.buf) { return -1; } - //allocate Beacon Payload buffer - rf_mac_setup->max_beacon_payload_length = mtu_size - MAC_IEEE_802_15_4_MAX_BEACON_OVERHEAD; - rf_mac_setup->mac_beacon_payload = ns_dyn_mem_alloc(rf_mac_setup->max_beacon_payload_length); + + return 0; +} + +static int mac_mlme_allocate_beacon_payload_buffer(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint16_t mtu_size) +{ + + rf_mac_setup->mac_beacon_payload = ns_dyn_mem_alloc(mtu_size); if (!rf_mac_setup->mac_beacon_payload) { return -1; } + + rf_mac_setup->max_beacon_payload_length = mtu_size; + rf_mac_setup->mac_beacon_payload_size = 0; + memset(rf_mac_setup->mac_beacon_payload, 0, rf_mac_setup->max_beacon_payload_length); return 0; } + + protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, arm_device_driver_list_s *dev_driver, mac_description_storage_size_t *storage_sizes, uint16_t mtu_size) { //allocate security @@ -1191,6 +1202,11 @@ protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, a mac_mlme_data_base_deallocate(entry); return NULL; } + //Allocate Default Beacon pyload data + if (mac_mlme_allocate_beacon_payload_buffer(entry, MAC_IEEE_802_15_4_MAX_BEACON_PAYLOAD_LENGTH)) { + mac_mlme_data_base_deallocate(entry); + return NULL; + } entry->mac_tasklet_id = mac_mcps_sap_tasklet_init(); if (entry->mac_tasklet_id < 0) { @@ -1213,7 +1229,6 @@ protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, a entry->mac_mlme_retry_max = MAC_DEFAULT_MAX_FRAME_RETRIES; memset(entry->mac_default_key_source, 0xff, 8); memset(entry->mac_auto_request.Keysource, 0xff, 8); - memset(entry->mac_beacon_payload, 0, entry->max_beacon_payload_length); entry->mac_auto_request.SecurityLevel = 6; entry->mac_auto_request.KeyIndex = 0xff; mac_pd_sap_rf_low_level_function_set(entry, entry->dev_driver); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mode_switch.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mode_switch.c new file mode 100644 index 00000000000..4fe09637027 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mode_switch.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "string.h" +#include "nsconfig.h" +#include "ns_types.h" +#include "ns_trace.h" +#include "common_functions.h" +#include "mac_api.h" +#include "MAC/IEEE802_15_4/sw_mac_internal.h" +#include "MAC/IEEE802_15_4/mac_defines.h" +#include "MAC/IEEE802_15_4/mac_mode_switch.h" +#include "MAC/IEEE802_15_4/mac_mcps_sap.h" +#include "MAC/IEEE802_15_4/mac_timer.h" +#include "MAC/rf_driver_storage.h" + +#define TRACE_GROUP "mswc" + +static uint8_t mac_calculate_mode_switch_parity(uint16_t mode_switch_phr) +{ + uint8_t counter = 0; + // Calculate number of 1-bits in (15-bit) input and return modulo-2 of the sum + for (int i = 0; i < 15; i++) { + if (mode_switch_phr & (1 << i)) { + counter++; + } + } + return counter % 2; +} +/* + * 11-bit input must be padded with 4 leading zeroes. + * Reverse the 15-bit result and divide with polynomial X⁴ + X + 1 -> 10011 + * Return remainder as checksum + * + * Example: + * Input: xxxxx01000000001 + * Padded input: x000001000000001 + * Reversed and padded input: 100000000100000x + * Calculated checksum: 0x0f (00001111) + * + * Division: + * + * 10011010101 <- Result + * ----------------- + * 10011 | 100000000100000 <- Highest bit (10000) is 1, add 1 in result + * 10011 <- 10011 * 1 + * ----- + * 00110 <- Highest bit (00110) is 0, add 0 in result + * 00000 <- 10011 * 0 + * ----- + * . + * . + * . + * ----- + * 11100 + * 10011 + * ---- + * 1111 <- Remainder + * + */ +static uint8_t mac_calculate_mode_switch_checksum(uint16_t mode_switch_phr) +{ + // X⁴ + X + 1 -> 0b10011 -> 0x13 + uint8_t polynomial = 0x13; + // Pad input with four leading zeroes + mode_switch_phr &= ~0x7800; + // Reverse input + uint16_t phr_reversed = 0; + for (int i = 0; i < 16; i++) { + if (mode_switch_phr & (1 << i)) { + phr_reversed |= 1 << (15 - i); + } + } + // Divide 15-bit padded and reversed input, use polynomial 10011 as the divider + uint8_t shift = 11; + uint8_t remainder = phr_reversed >> shift; + for (int i = 0; i < 11; i++) { + // Check highest bit + if (remainder & (1 << 4)) { + remainder ^= polynomial; + } else { + remainder ^= 0; + } + // Division ready, return remainder as checksum + if (!(--shift)) { + return remainder; + } + remainder <<= 1; + if (phr_reversed & (1 << shift)) { + remainder |= 1; + } + } + // Shouldn't go here + return 0; +} + +/* + * Mode switch PHR format: + * + * | 0 | 1-2 | 3-10 | 11-14 | 15 | + * |Mode Switch|Reserved|New Phy Mode ID|Checksum|Parity| + * + */ +int8_t mac_build_mode_switch_phr(protocol_interface_rf_mac_setup_s *rf_ptr, uint8_t *data_ptr, uint8_t phy_mode_id) +{ + (void) rf_ptr; + if (!data_ptr) { + return -1; + } + // - Write mode switch and PHY mode id fields + uint16_t mode_switch_phr = 1 << SHIFT_MODE_SWITCH; + mode_switch_phr |= phy_mode_id << SHIFT_MODE_SWITCH_PHY_MODE; + // - Calculate checksum + mode_switch_phr |= mac_calculate_mode_switch_checksum(mode_switch_phr) << SHIFT_MODE_SWITCH_CHECKSUM; + // - Calculate parity + mode_switch_phr |= mac_calculate_mode_switch_parity(mode_switch_phr) << SHIFT_MODE_SWITCH_PARITY; + + common_write_16_bit_inverse(mode_switch_phr, data_ptr); + + // - With successful return value, MAC should start CSMA-CA for a mode switch PHR + return 0; +} + +static int8_t mac_change_mode_switch_configuration(protocol_interface_rf_mac_setup_s *rf_ptr, uint8_t phy_mode_id, mac_mode_switch_states_e new_state) +{ + mac_api_t *mac_api = get_sw_mac_api(rf_ptr); + if (mac_api->mode_resolver_cb) { + phy_rf_channel_configuration_s rf_config; + memset(&rf_config, 0, sizeof(phy_rf_channel_configuration_s)); + if (!mac_api->mode_resolver_cb(mac_api, phy_mode_id, &rf_config)) { + rf_ptr->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_RF_CONFIGURATION, (uint8_t *) &rf_config); + rf_ptr->mode_switch_state = new_state; + return 0; + } else { + tr_error("Mode switch could not resolve PHY mode ID %u", phy_mode_id); + } + } + return -1; +} + +static uint32_t mac_calculate_timeout(protocol_interface_rf_mac_setup_s *rf_ptr, uint8_t phy_mode_id) +{ + mac_api_t *mac_api = get_sw_mac_api(rf_ptr); + if (mac_api->mode_resolver_cb) { + phy_rf_channel_configuration_s rf_config; + memset(&rf_config, 0, sizeof(phy_rf_channel_configuration_s)); + if (!mac_api->mode_resolver_cb(mac_api, phy_mode_id, &rf_config)) { + // Calculate transmission time of max size packet + Ack size + max settling time + Tack + return ((uint64_t)(1200 + 100) * 8000000 / rf_config.datarate + 1500 + 5000); + } + } + // If could not resolve configuration, use 300ms as default timeout + return 300000; +} + +int8_t mac_parse_mode_switch_phr(protocol_interface_rf_mac_setup_s *rf_ptr, const uint8_t *data_ptr, uint16_t data_len) +{ + if (data_len != PHR_LEN) { + return -1; + } + if (!data_ptr) { + return -1; + } + + uint16_t mode_switch_phr = common_read_16_bit_inverse(data_ptr); + if (!(mode_switch_phr & MASK_MODE_SWITCH)) { + // Mode switch not enabled + return -1; + } + + // - Validate checksum + if (mac_calculate_mode_switch_checksum(mode_switch_phr) != ((mode_switch_phr & MASK_MODE_SWITCH_CHECKSUM) >> SHIFT_MODE_SWITCH_CHECKSUM)) { + // Invalid checksum, TODO: error correction + return -1; + } + // - Validate parity + if (mac_calculate_mode_switch_parity(mode_switch_phr) != (mode_switch_phr & MASK_MODE_SWITCH_PARITY) >> SHIFT_MODE_SWITCH_PARITY) { + // Invalid parity + return -1; + } + // - Read PHY mode id + uint8_t phy_mode_id = (mode_switch_phr & MASK_MODE_SWITCH_PHY_MODE) >> SHIFT_MODE_SWITCH_PHY_MODE; + + // When mode switch PHR was received, change new configuration here to wait data packet and set mode switch state machine to 'PHR received' + if (mac_change_mode_switch_configuration(rf_ptr, phy_mode_id, MAC_MS_PHR_RECEIVED)) { + return -1; + } + // Backup timer, if reception of data packet fails + timer_mac_start(rf_ptr, MAC_MODE_SWITCH_TIMEOUT, mac_calculate_timeout(rf_ptr, phy_mode_id) / 50); + return 0; +} + +int8_t mac_update_mode_switch_state(protocol_interface_rf_mac_setup_s *rf_ptr, mac_mode_switch_states_e state, uint8_t phy_mode_id) +{ + switch (state) { + case MAC_MS_PHR_SEND_READY: + // When mode switch PHR was sent, change new configuration here before transmitting data packet and set mode switch state machine to 'PHR send ready' + if (!mac_change_mode_switch_configuration(rf_ptr, phy_mode_id, MAC_MS_PHR_SEND_READY)) { + return 0; + } + break; + case MAC_MS_DATA_SEND_READY: + // When data packet was sent, switch back to base configuration and set mode switch state machine to 'idle' + if ((rf_ptr->mode_switch_state == MAC_MS_PHR_SEND_READY) && !mac_change_mode_switch_configuration(rf_ptr, phy_mode_id, MAC_MS_IDLE)) { + return 0; + } + break; + case MAC_MS_DATA_RECEIVED: + // When packet was received in new configuration, switch back to base configuration and set mode switch state machine to 'idle' + if ((rf_ptr->mode_switch_state == MAC_MS_PHR_RECEIVED) && !mac_change_mode_switch_configuration(rf_ptr, phy_mode_id, MAC_MS_IDLE)) { + // Packet was received, stop backup timer to not cause timeout event + timer_mac_stop(rf_ptr); + return 0; + } + break; + case MAC_MS_TIMEOUT: + // When reception timeout occurs, switch back to base configuration and set mode switch state machine to 'idle' + if ((rf_ptr->mode_switch_state == MAC_MS_PHR_RECEIVED) && !mac_change_mode_switch_configuration(rf_ptr, phy_mode_id, MAC_MS_IDLE)) { + return 0; + } + break; + default: + break; + } + return -1; +} diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mode_switch.h b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mode_switch.h new file mode 100644 index 00000000000..8efa146cf08 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mode_switch.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MAC_MODE_SWITCH_H_ +#define MAC_MODE_SWITCH_H_ + +#define PHR_LEN 2 + +#define SHIFT_MODE_SWITCH_PARITY (15) +#define SHIFT_MODE_SWITCH_CHECKSUM (11) +#define SHIFT_MODE_SWITCH_PHY_MODE (3) +#define SHIFT_MODE_SWITCH (0) +#define MASK_MODE_SWITCH_PARITY (0x8000) +#define MASK_MODE_SWITCH_CHECKSUM (0x7800) +#define MASK_MODE_SWITCH_PHY_MODE (0x07F8) +#define MASK_MODE_SWITCH (0x0001) + +/** + * @brief Build mode switch PHR. + * @param rf_ptr Pointer to MAC instance. + * @param data_ptr Pointer to data buffer. + * @param phy_mode_id Used PHY mode id. + * @return 0 - success, -1 - failure. + */ +int8_t mac_build_mode_switch_phr(protocol_interface_rf_mac_setup_s *rf_ptr, uint8_t *data_ptr, uint8_t phy_mode_id); + +/** + * @brief Parse mode switch PHR. + * @param rf_ptr Pointer to MAC instance. + * @param data_ptr Pointer to data buffer. + * @param data_len Data length. + * @return 0 - mode switch PHR found, -1 - mode switch PHR not found. + */ +int8_t mac_parse_mode_switch_phr(protocol_interface_rf_mac_setup_s *rf_ptr, const uint8_t *data_ptr, uint16_t data_len); + +/** + * @brief Update mode switch state. + * @param rf_ptr Pointer to MAC instance. + */ +int8_t mac_update_mode_switch_state(protocol_interface_rf_mac_setup_s *rf_ptr, mac_mode_switch_states_e state, uint8_t phy_mode_id); + +#endif /* MAC_MODE_SWITCH_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c index da3b6b7a538..f4956b896c1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c @@ -35,6 +35,7 @@ #include "MAC/IEEE802_15_4/mac_filter.h" #include "MAC/IEEE802_15_4/mac_mcps_sap.h" #include "MAC/IEEE802_15_4/mac_cca_threshold.h" +#include "MAC/IEEE802_15_4/mac_mode_switch.h" #include "MAC/rf_driver_storage.h" #include "Core/include/ns_monitor.h" #include "ns_trace.h" @@ -49,6 +50,10 @@ // MAC should learn and make this dynamic by sending first few packets with predefined CSMA period. #define MIN_FHSS_CSMA_PERIOD_US 5000 +// Add extra CSMA-CA delay for packets using mode switch. The delay between mode switch PHR and data packet equals to MDR_SETTLING_TIME_US +// Must be between 510 and 1500 us +#define MDR_SETTLING_TIME_US 510 + static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *rf_ptr, phy_link_tx_status_e status, uint8_t cca_retry, uint8_t tx_retry); static void mac_sap_cca_fail_cb(protocol_interface_rf_mac_setup_s *rf_ptr, uint16_t failed_channel); @@ -106,6 +111,9 @@ uint32_t mac_csma_backoff_get(protocol_interface_rf_mac_setup_s *rf_mac_setup) backoff_in_us = 1; } if (rf_mac_setup->fhss_api) { + if (rf_mac_setup->active_pd_data_request->phy_mode_id) { + backoff_in_us += MDR_SETTLING_TIME_US; + } // Synchronization error when backoff time is shorter than allowed. // TODO: Make this dynamic. if (backoff_in_us < MIN_FHSS_CSMA_PERIOD_US) { @@ -184,6 +192,9 @@ int8_t mac_plme_cca_req(protocol_interface_rf_mac_setup_s *rf_mac_setup) if (rf_mac_setup->mac_ack_tx_active || (rf_mac_setup->mac_edfe_tx_active && rf_mac_setup->mac_edfe_response_tx_active)) { buffer = tx_buf->enhanced_ack_buf; length = tx_buf->ack_len; + } else if (rf_mac_setup->mac_mode_switch_phr_tx_active) { + buffer = tx_buf->mode_switch_phr_buf; + length = sizeof(tx_buf->mode_switch_phr_buf); } else { buffer = tx_buf->buf; length = tx_buf->len; @@ -232,6 +243,7 @@ void mac_pd_abort_active_tx(protocol_interface_rf_mac_setup_s *rf_mac_setup) phy_csma_params_t csma_params; // Set TX time to 0 to abort current transmission csma_params.backoff_time = 0; + csma_params.mode_switch_phr = false; rf_mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_CSMA_PARAMETERS, (uint8_t *) &csma_params); } @@ -242,8 +254,12 @@ void mac_pd_abort_active_tx(protocol_interface_rf_mac_setup_s *rf_mac_setup) * \param tx_time TX timestamp to be set. * */ -void mac_pd_sap_set_phy_tx_time(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint32_t tx_time, bool cca_enabled) +void mac_pd_sap_set_phy_tx_time(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint32_t tx_time, bool cca_enabled, bool mode_switch) { + // Given tx_time is for the actual data packet. Mode switch PHR must be sent with the offset of MDR settling time. + if (mode_switch) { + tx_time -= MDR_SETTLING_TIME_US; + } // With TX time set to zero, PHY sends immediately if (!tx_time) { tx_time++; @@ -251,6 +267,7 @@ void mac_pd_sap_set_phy_tx_time(protocol_interface_rf_mac_setup_s *rf_mac_setup, phy_csma_params_t csma_params; csma_params.backoff_time = tx_time; csma_params.cca_enabled = cca_enabled; + csma_params.mode_switch_phr = mode_switch; rf_mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_CSMA_PARAMETERS, (uint8_t *) &csma_params); } @@ -300,7 +317,7 @@ void mac_pd_sap_state_machine(protocol_interface_rf_mac_setup_s *rf_mac_setup) cca_enabled = true; } - mac_pd_sap_set_phy_tx_time(rf_mac_setup, active_buf->tx_time, cca_enabled); + mac_pd_sap_set_phy_tx_time(rf_mac_setup, active_buf->tx_time, cca_enabled, rf_mac_setup->mac_mode_switch_phr_tx_active); if (active_buf->fcf_dsn.frametype == FC_BEACON_FRAME) { // FHSS synchronization info is written in the end of transmitted (Beacon) buffer dev_driver_tx_buffer_s *tx_buf = &rf_mac_setup->dev_driver_tx_buffer; @@ -335,6 +352,10 @@ void mac_pd_sap_state_machine(protocol_interface_rf_mac_setup_s *rf_mac_setup) } else if (rf_mac_setup->mac_tx_result == MAC_TIMER_ACK) { mac_data_interface_tx_done_cb(rf_mac_setup, PHY_LINK_TX_FAIL, 0, 0); } + } else { + if (rf_mac_setup->mac_tx_result == MAC_MODE_SWITCH_TIMEOUT) { + mac_update_mode_switch_state(rf_mac_setup, MAC_MS_TIMEOUT, rf_mac_setup->base_phy_mode); + } } } @@ -424,6 +445,7 @@ static bool mac_data_asynch_channel_switch(protocol_interface_rf_mac_setup_s *rf static void mac_data_ack_tx_finish(protocol_interface_rf_mac_setup_s *rf_ptr) { rf_ptr->mac_ack_tx_active = false; + mac_update_mode_switch_state(rf_ptr, MAC_MS_DATA_RECEIVED, rf_ptr->base_phy_mode); if (rf_ptr->fhss_api) { //SET tx completed false because ack isnot never queued rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, false, false, 0xff); @@ -449,7 +471,6 @@ int8_t mac_data_edfe_force_stop(protocol_interface_rf_mac_setup_s *rf_ptr) static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *rf_ptr, phy_link_tx_status_e status, uint8_t cca_retry, uint8_t tx_retry) { - if (!rf_ptr->macRfRadioTxActive) { return -1; } @@ -513,7 +534,7 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r if (active_buf->csma_periods_left > 0) { active_buf->csma_periods_left--; active_buf->tx_time += rf_ptr->multi_cca_interval; - mac_pd_sap_set_phy_tx_time(rf_ptr, active_buf->tx_time, true); + mac_pd_sap_set_phy_tx_time(rf_ptr, active_buf->tx_time, true, false); #ifdef TIMING_TOOL_TRACES tr_info("%u CSMA_start", mac_mcps_sap_get_phy_timestamp(rf_ptr)); #endif @@ -555,6 +576,23 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r mac_data_ack_tx_finish(rf_ptr); return 0; } + } else if (rf_ptr->mac_mode_switch_phr_tx_active) { +#ifdef TIMING_TOOL_TRACES + tr_info("%u TX_done", mac_mcps_sap_get_phy_timestamp(rf_ptr)); +#endif + rf_ptr->mac_mode_switch_phr_tx_active = false; + if (rf_ptr->fhss_api) { + rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, false, true, rf_ptr->active_pd_data_request->msduHandle); + } + if (!mac_update_mode_switch_state(rf_ptr, MAC_MS_PHR_SEND_READY, rf_ptr->active_pd_data_request->phy_mode_id)) { + mac_pd_sap_set_phy_tx_time(rf_ptr, rf_ptr->active_pd_data_request->tx_time, true, rf_ptr->mac_mode_switch_phr_tx_active); + if (mac_plme_cca_req(rf_ptr) != 0) { + mac_sap_no_ack_cb(rf_ptr); + } + return 0; + } + // Failed to start data transmission after mode switch PHR was sent + status = PHY_LINK_TX_FAIL; } // Do not update CCA count when Ack is received, it was already updated with PHY_LINK_TX_SUCCESS event @@ -580,7 +618,7 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r timer_mac_stop(rf_ptr); } uint16_t failed_channel = rf_ptr->mac_channel; - if (rf_ptr->fhss_api && rf_ptr->active_pd_data_request->asynch_request == false) { + if (rf_ptr->active_pd_data_request && rf_ptr->active_pd_data_request->asynch_request == false) { /* waiting_ack == false allows FHSS to change back to RX channel after transmission * tx_completed == true allows FHSS to delete stored failure handles */ @@ -610,7 +648,12 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r waiting_ack = false; tx_completed = true; } - rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, waiting_ack, tx_completed, rf_ptr->active_pd_data_request->msduHandle); + if (waiting_ack == false) { + mac_update_mode_switch_state(rf_ptr, MAC_MS_DATA_SEND_READY, rf_ptr->base_phy_mode); + } + if (rf_ptr->fhss_api) { + rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, waiting_ack, tx_completed, rf_ptr->active_pd_data_request->msduHandle); + } } switch (status) { @@ -674,7 +717,7 @@ static int8_t mac_data_interface_tx_done_by_ack_cb(protocol_interface_rf_mac_set if (mcps_sap_pd_ack(rf_ptr, buf) != 0) { mcps_sap_pre_parsed_frame_buffer_free(buf); } - + mac_update_mode_switch_state(rf_ptr, MAC_MS_DATA_SEND_READY, rf_ptr->base_phy_mode); if (rf_ptr->fhss_api) { rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, false, true, rf_ptr->active_pd_data_request->msduHandle); } @@ -1040,19 +1083,27 @@ int8_t mac_pd_sap_data_cb(void *identifier, arm_phy_sap_msg_t *message) goto ERROR_HANDLER; } - if (pd_data_ind->data_len < 3) { - return -1; - } #ifdef TIMING_TOOL_TRACES tr_info("%u RX_start", mac_pd_sap_get_phy_rx_time(rf_ptr)); tr_info("%u RX_done", mac_mcps_sap_get_phy_timestamp(rf_ptr)); #endif + + if (!mac_parse_mode_switch_phr(rf_ptr, pd_data_ind->data_ptr, pd_data_ind->data_len)) { + // TODO: mode switch returned 0, needs some logic to wait frame with new mode + goto ERROR_HANDLER; + } + + if (pd_data_ind->data_len < 3) { + return -1; + } + mac_cca_threshold_event_send(rf_ptr, rf_ptr->mac_channel, pd_data_ind->dbm); mac_fcf_sequence_t fcf_read; const uint8_t *ptr = mac_header_parse_fcf_dsn(&fcf_read, pd_data_ind->data_ptr); // No need to send Ack - Check if RX channel needs to be updated if (fcf_read.ackRequested == false) { + mac_update_mode_switch_state(rf_ptr, MAC_MS_DATA_RECEIVED, rf_ptr->base_phy_mode); if (rf_ptr->fhss_api) { rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, false, false, 0); } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.h b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.h index 730c9b0e3ee..79b959312d4 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.h @@ -43,7 +43,7 @@ int8_t mac_plme_cca_req(struct protocol_interface_rf_mac_setup *rf_mac_setup); void mac_pd_abort_active_tx(struct protocol_interface_rf_mac_setup *rf_mac_setup); -void mac_pd_sap_set_phy_tx_time(struct protocol_interface_rf_mac_setup *rf_mac_setup, uint32_t tx_time, bool cca_enabled); +void mac_pd_sap_set_phy_tx_time(struct protocol_interface_rf_mac_setup *rf_mac_setup, uint32_t tx_time, bool cca_enabled, bool mode_switch); void mac_pd_sap_rf_low_level_function_set(void *mac_ptr, void *driver); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_timer.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_timer.c index 764cd25a736..187ae44c1c1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_timer.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_timer.c @@ -23,7 +23,7 @@ #include "MAC/IEEE802_15_4/mac_pd_sap.h" #include "MAC/IEEE802_15_4/mac_timer.h" #include "sw_mac.h" - +#define TRACE_GROUP "mTim" /*-------------------MAC TIMER FUNCTIONS--------------------------*/ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c index 675eda3b5cb..1decacba218 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c @@ -55,10 +55,11 @@ static int8_t ns_sw_mac_initialize(mac_api_t *api, mcps_data_confirm *mcps_data_ mlme_confirm *mlme_conf_callback, mlme_indication *mlme_ind_callback, int8_t parent_id); static int8_t ns_sw_mac_api_enable_mcps_ext(mac_api_t *api, mcps_data_indication_ext *data_ind_cb, mcps_data_confirm_ext *data_cnf_cb, mcps_ack_data_req_ext *ack_data_req_cb); static int8_t ns_sw_mac_api_enable_edfe_ext(mac_api_t *api, mcps_edfe_handler *edfe_ind_cb); +static int8_t ns_sw_mac_api_mode_switch_resolver_set(mac_api_t *api, mode_switch_resolver *mode_resolver_cb, uint8_t base_phy_mode); static void mlme_req(const mac_api_t *api, mlme_primitive id, const void *data); static void mcps_req(const mac_api_t *api, const mcps_data_req_t *data); -static void mcps_req_ext(const mac_api_t *api, const mcps_data_req_t *data, const mcps_data_req_ie_list_t *ie_ext, const channel_list_s *asynch_channel_list, mac_data_priority_t priority); +static void mcps_req_ext(const mac_api_t *api, const mcps_data_req_t *data, const mcps_data_req_ie_list_t *ie_ext, const channel_list_s *asynch_channel_list, mac_data_priority_t priority, uint8_t phy_mode_id); static uint8_t purge_req(const mac_api_t *api, const mcps_purge_t *data); static int8_t macext_mac64_address_set(const mac_api_t *api, const uint8_t *mac64); static int8_t macext_mac64_address_get(const mac_api_t *api, mac_extended_address_type type, uint8_t *mac64_buf); @@ -130,6 +131,7 @@ mac_api_t *ns_sw_mac_create(int8_t rf_driver_id, mac_description_storage_size_t this->mac_initialize = &ns_sw_mac_initialize; this->mac_mcps_extension_enable = &ns_sw_mac_api_enable_mcps_ext; this->mac_mcps_edfe_enable = &ns_sw_mac_api_enable_edfe_ext; + this->mac_mode_switch_resolver_set = &ns_sw_mac_api_mode_switch_resolver_set; this->mlme_req = &mlme_req; this->mcps_data_req = &mcps_req; this->mcps_data_req_ext = &mcps_req_ext; @@ -344,6 +346,19 @@ static int8_t ns_sw_mac_api_enable_edfe_ext(mac_api_t *api, mcps_edfe_handler *e return 0; } +static int8_t ns_sw_mac_api_mode_switch_resolver_set(mac_api_t *api, mode_switch_resolver *mode_resolver_cb, uint8_t base_phy_mode) +{ + if (api != mac_store.mac_api) { + return -1; + } + if (!mac_store.setup->mac_extension_enabled) { + return -1; + } + mac_store.setup->base_phy_mode = base_phy_mode; + mac_store.mac_api->mode_resolver_cb = mode_resolver_cb; + return 0; +} + mac_api_t *get_sw_mac_api(protocol_interface_rf_mac_setup_s *setup) { if (!mac_store.mac_api || mac_store.mac_api->parent_id == -1 || mac_store.setup != setup) { @@ -582,15 +597,15 @@ static void mcps_req(const mac_api_t *api, const mcps_data_req_t *data) /* Call direct new API but without IE extensions */ mcps_data_req_ie_list_t ie_list; memset(&ie_list, 0, sizeof(mcps_data_req_ie_list_t)); - mcps_sap_data_req_handler_ext(mac_store.setup, data, &ie_list, NULL, MAC_DATA_NORMAL_PRIORITY); + mcps_sap_data_req_handler_ext(mac_store.setup, data, &ie_list, NULL, MAC_DATA_NORMAL_PRIORITY, 0); } } -static void mcps_req_ext(const mac_api_t *api, const mcps_data_req_t *data, const mcps_data_req_ie_list_t *ie_ext, const channel_list_s *asynch_channel_list, mac_data_priority_t priority) +static void mcps_req_ext(const mac_api_t *api, const mcps_data_req_t *data, const mcps_data_req_ie_list_t *ie_ext, const channel_list_s *asynch_channel_list, mac_data_priority_t priority, uint8_t phy_mode_id) { //TODO: Populate linked list when present if (mac_store.mac_api == api) { - mcps_sap_data_req_handler_ext(mac_store.setup, data, ie_ext, asynch_channel_list, priority); + mcps_sap_data_req_handler_ext(mac_store.setup, data, ie_ext, asynch_channel_list, priority, phy_mode_id); } } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MLE/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/MLE/CMakeLists.txt index f5990904a2d..da8a5f3d37e 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MLE/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/MLE/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MPL/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/MPL/CMakeLists.txt index 1f59b31ecaa..805ae78d202 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MPL/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/MPL/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/MPL/mpl.c b/connectivity/nanostack/sal-stack-nanostack/source/MPL/mpl.c index face25a0f32..52453fbd063 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/MPL/mpl.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/MPL/mpl.c @@ -501,7 +501,7 @@ static void mpl_buffer_transmit(mpl_domain_t *domain, mpl_buffered_message_t *me memcpy(buf->src_sa.address, message->message + IPV6_HDROFF_SRC_ADDR, 16); ipv6_transmit_multicast_on_interface(buf, domain->interface); - tr_debug("MPL transmit %u", mpl_buffer_sequence(message)); + tr_info("MPL transmit %u", mpl_buffer_sequence(message)); } static void mpl_buffer_inconsistent(const mpl_domain_t *domain, mpl_buffered_message_t *message) diff --git a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/CMakeLists.txt index a38a8fac430..50445aeffe5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h index a3a845ffba7..e2a71fee20a 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol.h @@ -91,12 +91,10 @@ typedef enum icmp_state { ER_SCAN = 2, ER_ADDRESS_REQ = 3, ER_BIND_COMP = 4, -#ifdef HAVE_RPL ER_RPL_MC = 5, ER_RPL_SCAN = 6, ER_RPL_UNICAST = 7, ER_DAO_TX = 8, -#endif ER_PANA_AUTH = 9, ER_PANA_AUTH_DONE = 10, ER_PANA_AUTH_ERROR = 11, @@ -104,9 +102,7 @@ typedef enum icmp_state { ER_MLE_LINK_REQ = 13, ER_MLE_LINK_SHORT_SYNCH = 14, ER_MLE_LINK_ADDRESS_SYNCH = 15, -#ifdef HAVE_RPL ER_ROUTER_SYNCH = 17, -#endif ER_PANA_PING = 18, ER_PARENT_SYNCH_LOST = 19, ER_MLE_SCAN = 20, diff --git a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol_abstract.h b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol_abstract.h index f59ca2bf9e8..87452877a59 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol_abstract.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/Include/protocol_abstract.h @@ -45,5 +45,6 @@ protocol_interface_info_entry_t *protocol_stack_interface_info_get_by_id(int8_t protocol_interface_info_entry_t *protocol_stack_interface_info_get_by_bootstrap_id(int8_t id); protocol_interface_info_entry_t *protocol_stack_interface_info_get_by_rpl_domain(const struct rpl_domain *domain, int8_t last_id); protocol_interface_info_entry_t *protocol_stack_interface_info_get_by_fhss_api(const struct fhss_api *fhss_api); +protocol_interface_info_entry_t *protocol_stack_interface_info_get_wisun_mesh(void); #endif /* NWK_INTERFACE_INCLUDE_PROTOCOL_ABSTRACT_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c index cab954193b9..3a46c05b4a0 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_core.c @@ -65,7 +65,6 @@ #include "6LoWPAN/Thread/thread_bootstrap.h" #include "6LoWPAN/Thread/thread_routing.h" #include "6LoWPAN/Thread/thread_management_internal.h" -#include "6LoWPAN/ws/ws_bootstrap.h" #include "6LoWPAN/ws/ws_common.h" #ifdef HAVE_WS #include "6LoWPAN/ws/ws_pae_controller.h" @@ -806,6 +805,18 @@ protocol_interface_info_entry_t *protocol_stack_interface_info_get_by_fhss_api(c return NULL; } +protocol_interface_info_entry_t *protocol_stack_interface_info_get_wisun_mesh(void) +{ +#ifdef HAVE_WS + ns_list_foreach(protocol_interface_info_entry_t, cur, &protocol_interface_info_list) { + if (cur->ws_info) { + return cur; + } + } +#endif //HAVE_WS + return NULL; +} + protocol_interface_info_entry_t *protocol_stack_interface_sleep_possibility(void) { ns_list_foreach(protocol_interface_info_entry_t, cur, &protocol_interface_info_list) { @@ -1148,7 +1159,7 @@ void net_bootsrap_cb_run(uint8_t event) if (thread_info(cur)) { thread_bootstrap_state_machine(cur); } else if (ws_info(cur)) { - ws_bootstrap_state_machine(cur); + ws_common_state_machine(cur); } else { protocol_6lowpan_bootstrap(cur); } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_timer.c b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_timer.c index 0c518ecf5d7..15c2869adfa 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_timer.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/NWK_INTERFACE/protocol_timer.c @@ -70,7 +70,7 @@ void protocol_timer_start(protocol_timer_id_t id, void (*passed_fptr)(uint16_t), protocol_timer[id].fptr = passed_fptr; platform_exit_critical(); } else { - tr_debug("Do Not use Null pointer for fptr!!!\n"); + tr_debug("Do Not use Null pointer for fptr!!!"); } } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/RPL/CMakeLists.txt index 6ce125fe30e..98616d90bee 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c index 282eea4f6e5..59f573a087a 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c @@ -132,6 +132,19 @@ void rpl_control_event(struct rpl_domain *domain, rpl_event_t event) } } +static void rpl_control_convert_internal_config(rpl_dodag_conf_int_t *conf, const rpl_dodag_conf_t *external_conf) +{ + conf->dio_interval_min = external_conf->dio_interval_min; + conf->dio_interval_doublings = external_conf->dio_interval_doublings; + conf->dio_redundancy_constant = external_conf->dio_redundancy_constant; + conf->default_lifetime = external_conf->default_lifetime; + conf->dag_max_rank_increase = external_conf->dag_max_rank_increase; + conf->min_hop_rank_increase = external_conf->min_hop_rank_increase; + conf->objective_code_point = external_conf->objective_code_point; + conf->lifetime_unit = external_conf->lifetime_unit; + conf->options = rpl_conf_options(external_conf->authentication, external_conf->path_control_size); + conf->reserved = 0; +} /* When we join a new instance, we need to publish existing addresses. * Later addresses additions/removals are handled by rpl_control_addr_notifier. @@ -660,7 +673,9 @@ rpl_dodag_t *rpl_control_create_dodag_root(rpl_domain_t *domain, uint8_t instanc return NULL; } - rpl_dodag_update_config(dodag, conf, NULL, NULL); + rpl_dodag_conf_int_t internal_conf; + rpl_control_convert_internal_config(&internal_conf, conf); + rpl_dodag_update_config(dodag, &internal_conf, NULL, NULL); rpl_dodag_set_root(dodag, true); rpl_dodag_version_t *version = rpl_create_dodag_version(dodag, rpl_seq_init()); if (!version) { @@ -717,11 +732,12 @@ void rpl_control_update_dodag_config(struct rpl_dodag *dodag, const rpl_dodag_co { if (rpl_dodag_am_root(dodag)) { - rpl_dodag_update_config(dodag, conf, NULL, NULL); + rpl_dodag_conf_int_t internal_conf; + rpl_control_convert_internal_config(&internal_conf, conf); + rpl_dodag_update_config(dodag, &internal_conf, NULL, NULL); } } - void rpl_control_set_dodag_pref(rpl_dodag_t *dodag, uint8_t pref) { if (rpl_dodag_am_root(dodag)) { @@ -839,34 +855,33 @@ static const uint8_t *rpl_control_find_option_in_buffer(const buffer_t *buf, uin * * Figure 24: Format of the DODAG Configuration Option */ -static const uint8_t *rpl_control_read_conf(rpl_dodag_conf_t *conf_out, const uint8_t *opt) +static const uint8_t *rpl_control_read_conf(rpl_dodag_conf_int_t *conf_out, const uint8_t *opt) { - conf_out->authentication = opt[2] & 0x08; - conf_out->path_control_size = opt[2] & 0x07; + conf_out->options = opt[2]; conf_out->dio_interval_doublings = opt[3]; conf_out->dio_interval_min = opt[4]; conf_out->dio_redundancy_constant = opt[5]; conf_out->dag_max_rank_increase = common_read_16_bit(opt + 6); conf_out->min_hop_rank_increase = common_read_16_bit(opt + 8); conf_out->objective_code_point = common_read_16_bit(opt + 10); + conf_out->reserved = opt[12]; conf_out->default_lifetime = opt[13]; conf_out->lifetime_unit = common_read_16_bit(opt + 14); return opt + 16; } -static uint8_t *rpl_control_write_conf(uint8_t *opt_out, const rpl_dodag_conf_t *conf) +static uint8_t *rpl_control_write_conf(uint8_t *opt_out, const rpl_dodag_conf_int_t *conf) { opt_out[0] = RPL_DODAG_CONF_OPTION; opt_out[1] = 14; - opt_out[2] = conf->authentication ? RPL_CONF_FLAG_AUTH : 0; - opt_out[2] |= conf->path_control_size; + opt_out[2] = conf->options; opt_out[3] = conf->dio_interval_doublings; opt_out[4] = conf->dio_interval_min; opt_out[5] = conf->dio_redundancy_constant; common_write_16_bit(conf->dag_max_rank_increase, opt_out + 6); common_write_16_bit(conf->min_hop_rank_increase, opt_out + 8); common_write_16_bit(conf->objective_code_point, opt_out + 10); - opt_out[12] = 0; // reserved + opt_out[12] = conf->reserved; opt_out[13] = conf->default_lifetime; common_write_16_bit(conf->lifetime_unit, opt_out + 14); return opt_out + 16; @@ -1174,7 +1189,7 @@ static buffer_t *rpl_control_dio_handler(protocol_interface_info_entry_t *cur, r /* Update DODAG config information, if option present, and either we don't have it or version is newer */ const uint8_t *dodag_conf_ptr = rpl_control_find_option_in_buffer(buf, 24, RPL_DODAG_CONF_OPTION, 14); if (dodag_conf_ptr) { - rpl_dodag_conf_t conf_buf; + rpl_dodag_conf_int_t conf_buf; rpl_control_read_conf(&conf_buf, dodag_conf_ptr); if (!rpl_dodag_update_config(dodag, &conf_buf, buf->src_sa.address, &become_leaf)) { goto invalid_parent; @@ -1182,7 +1197,7 @@ static buffer_t *rpl_control_dio_handler(protocol_interface_info_entry_t *cur, r } /* If we don't have any DODAG config information, ask by unicast DIS */ - const rpl_dodag_conf_t *conf = rpl_dodag_get_config(dodag); + const rpl_dodag_conf_int_t *conf = rpl_dodag_get_config(dodag); if (!conf) { /* TODO - rate limit DIS? */ if (domain->new_parent_add && !domain->new_parent_add(buf->src_sa.address, domain->cb_handle, instance, rank)) { @@ -1361,7 +1376,7 @@ void rpl_control_transmit(rpl_domain_t *domain, protocol_interface_info_entry_t /* Transmit a DIO (unicast or multicast); cur may be NULL if multicast */ -void rpl_control_transmit_dio(rpl_domain_t *domain, protocol_interface_info_entry_t *cur, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, rpl_dodag_t *dodag, const uint8_t dodagid[16], const rpl_dodag_conf_t *conf, const uint8_t *dst) +void rpl_control_transmit_dio(rpl_domain_t *domain, protocol_interface_info_entry_t *cur, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, rpl_dodag_t *dodag, const uint8_t dodagid[16], const rpl_dodag_conf_int_t *conf, const uint8_t *dst) { uint16_t length; @@ -1549,6 +1564,20 @@ static buffer_t *rpl_control_dis_handler(protocol_interface_info_entry_t *cur, r return buffer_free(buf); } +void rpl_control_transmit_dio_trigger(protocol_interface_info_entry_t *cur, struct rpl_domain *domain) +{ + ns_list_foreach(rpl_instance_t, instance, &domain->instances) { + rpl_instance_dio_trigger(instance, cur, NULL); + } +} + +void rpl_control_parent_selection_trigger(struct rpl_domain *domain) +{ + ns_list_foreach(rpl_instance_t, instance, &domain->instances) { + rpl_instance_run_parent_selection(instance); + } +} + void rpl_control_transmit_dis(rpl_domain_t *domain, protocol_interface_info_entry_t *cur, uint8_t pred, uint8_t instance_id, const uint8_t *dodagid, const uint8_t version, const uint8_t *dst) { uint16_t length = 2; @@ -1917,7 +1946,7 @@ bool rpl_control_read_dodag_info(const rpl_instance_t *instance, rpl_dodag_info_ return rpl_upward_read_dodag_info(instance, dodag_info); } -const rpl_dodag_conf_t *rpl_control_get_dodag_config(const rpl_instance_t *instance) +const rpl_dodag_conf_int_t *rpl_control_get_dodag_config(const rpl_instance_t *instance) { rpl_dodag_t *dodag = rpl_instance_current_dodag(instance); if (!dodag) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h index e5381afefd7..ce8a1d16659 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h @@ -18,8 +18,6 @@ #ifndef RPL_CONTROL_H_ #define RPL_CONTROL_H_ -#ifdef HAVE_RPL - #include "ns_list.h" #include "ipv6_stack/ipv6_routing_table.h" @@ -85,6 +83,29 @@ typedef struct rpl_dodag_conf { uint16_t lifetime_unit; /* seconds */ } rpl_dodag_conf_t; +/* Internally used configuration parameters for a DODAG, obtained through DIO DODAG Configuration options + * + * This structure has all the fields that are in the configuration + * to allow forwarding new bits that are added in future specifications. + */ +typedef struct rpl_dodag_conf_int { + uint8_t options; /* Flags|A|PCS */ + uint8_t reserved; /* Reserved fields in options (byte 12)*/ + uint8_t dio_interval_min; /* log2 milliseconds */ + uint8_t dio_interval_doublings; + uint8_t dio_redundancy_constant; + uint8_t default_lifetime; /* lifetime units */ + uint16_t dag_max_rank_increase; + uint16_t min_hop_rank_increase; + uint16_t objective_code_point; + uint16_t lifetime_unit; /* seconds */ +} rpl_dodag_conf_int_t; + +/* Helpers to handle configuration option bits*/ +#define rpl_conf_options(security, path_control_size) ((security ? 1:0) << 4) | (path_control_size & 0x07) +#define rpl_conf_option_security(conf) (bool)((conf)->options & 0x08) +#define rpl_conf_option_path_control_size(conf) ((conf)->options & 0x07) + /* Descriptor for a route from a DIO Route Information option. * Used to hold the "master copy" in the DODAG structure - the table for the * current DODAG is used to populate routes in our system routing table, and to @@ -104,6 +125,8 @@ typedef struct rpl_dio_route { uint8_t prefix[]; /* Variable-length prefix */ } rpl_dio_route_t; +#ifdef HAVE_RPL + typedef NS_LIST_HEAD(rpl_dio_route_t, link) rpl_dio_route_list_t; /******************************* RPL internal API ****************************/ @@ -112,7 +135,7 @@ void *rpl_realloc(void *p, uint16_t old_size, uint16_t new_size); void rpl_free(void *p, uint16_t size); void rpl_control_transmit(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t code, struct buffer *buf, const uint8_t *dst); void rpl_control_transmit_multicast_dio(struct rpl_domain *domain, struct rpl_instance *instance, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, const uint8_t dodagid[16], const struct rpl_dodag_conf *conf); -void rpl_control_transmit_dio(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, struct rpl_dodag *dodag, const uint8_t dodagid[16], const struct rpl_dodag_conf *conf, const uint8_t *dst); +void rpl_control_transmit_dio(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t instance_id, uint8_t dodag_version, uint16_t rank, uint8_t g_mop_prf, uint8_t dtsn, struct rpl_dodag *dodag, const uint8_t dodagid[16], const struct rpl_dodag_conf_int *conf, const uint8_t *dst); bool rpl_control_transmit_dao(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, struct rpl_instance *instance, uint8_t instance_id, uint8_t dao_sequence, const uint8_t dodagid[16], const uint8_t *opts, uint16_t opts_size, const uint8_t *dst); void rpl_control_disable_ra_routes(struct rpl_domain *domain); void rpl_control_event(struct rpl_domain *domain, rpl_event_t event); @@ -133,6 +156,11 @@ struct buffer *rpl_control_source_route_error_handler(struct buffer *buf, struct /* Manually send DIS packets for bootstrap */ void rpl_control_transmit_dis(struct rpl_domain *domain, struct protocol_interface_info_entry *cur, uint8_t pred, uint8_t instance_id, const uint8_t *dodagid, const uint8_t version, const uint8_t *dst); +/* Manually send DIO packets for bootstrap */ +void rpl_control_transmit_dio_trigger(struct protocol_interface_info_entry *cur, struct rpl_domain *domain); +/* Manually trigger RPL parent selection */ +void rpl_control_parent_selection_trigger(struct rpl_domain *domain); + bool rpl_control_have_dodag(struct rpl_domain *domain); /* APIs used to manipulate configuration at the root */ @@ -202,7 +230,7 @@ struct rpl_instance *rpl_control_enumerate_instances(rpl_domain_t *domain, struc struct rpl_instance *rpl_control_lookup_instance(rpl_domain_t *domain, uint8_t instance_id, const uint8_t *dodagid); bool rpl_control_get_instance_dao_target_count(rpl_domain_t *domain, uint8_t instance_id, const uint8_t *dodagid, const uint8_t *prefix, uint16_t *target_count); bool rpl_control_read_dodag_info(const struct rpl_instance *instance, struct rpl_dodag_info_t *dodag_info); -const rpl_dodag_conf_t *rpl_control_get_dodag_config(const struct rpl_instance *instance); +const rpl_dodag_conf_int_t *rpl_control_get_dodag_config(const struct rpl_instance *instance); const uint8_t *rpl_control_preferred_parent_addr(const struct rpl_instance *instance, bool global); uint16_t rpl_control_current_rank(const struct rpl_instance *instance); uint8_t rpl_policy_mrhof_parent_set_size_get(const rpl_domain_t *domain); @@ -210,15 +238,39 @@ void rpl_control_instant_poison(struct protocol_interface_info_entry *cur, rpl_d #else /* HAVE_RPL */ +#define rpl_control_set_memory_limits(soft_limit, hard_limit) #define rpl_control_fast_timer(ticks) ((void) 0) #define rpl_control_slow_timer(seconds) ((void) 0) +#define rpl_control_transmit_dis(domain, cur, pred, instance_id, dodagid, version, dst) ((void) 0) +#define rpl_control_transmit_dio_trigger(cur, domain) ((void) 0) +#define rpl_control_parent_selection_trigger(domain) ((void) 0) +#define rpl_control_force_leaf(domain, leaf) ((void) 0) +#define rpl_control_poison(domain, poison_count) ((void) 0) +#define rpl_control_dao_timeout(domain, seconds) ((void) 0) +#define rpl_control_set_domain_on_interface(cur, domain, downstream) ((void) 0) #define rpl_control_remove_domain_from_interface(cur) ((void) 0) #define rpl_control_free_domain_instances_from_interface(cur) ((void) 0) +#define rpl_control_set_callback(domain, callback, prefix_learn_cb, new_parent_add, parent_dis, cb_handle) ((void) 0) +#define rpl_control_is_dodag_parent(interface, ll_addr) (false) +#define rpl_control_is_dodag_parent_candidate(interface, ll_addr, candidate_cmp_limiter) (false) +#define rpl_control_probe_parent_candidate(interface, ll_addr) (false) +#define rpl_control_neighbor_info_get(interface, ll_addr, global_address) (0xffff) +#define rpl_possible_better_candidate(interface, rpl_instance, ll_addr, candidate_rank, etx) (false) +#define rpl_control_parent_candidate_list_size(interface, parent_list) (0) +#define rpl_control_candidate_list_size(interface, rpl_instance) (0) +#define rpl_control_selected_parent_count(interface, rpl_instance) (0) +#define rpl_control_neighbor_delete(interface, ll_addr) ((void) 0) +#define rpl_control_find_worst_neighbor(interface, rpl_instance, ll_addr) (false) #define rpl_control_register_address(interface, addr) ((void) 0) #define rpl_control_address_register_done(interface, ll_addr, status) (false) +#define rpl_control_enumerate_instances(domain, instance) (NULL) +#define rpl_control_read_dodag_info(instance, dodag_info) (false) +#define rpl_control_get_dodag_config(instance) (NULL) +#define rpl_control_preferred_parent_addr(instance, global) (NULL) +#define rpl_control_current_rank(instance) (RPL_RANK_INFINITE) #define rpl_policy_mrhof_parent_set_size_get(domain) (0) -#define rpl_control_set_mrhof_parent_set_size(parent_set_size) #define rpl_control_instant_poison(cur, domain) ((void) 0) + #endif /* HAVE_RPL */ #endif /* RPL_CONTROL_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c index 984c24953ef..628b3440521 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c @@ -134,7 +134,7 @@ void rpl_downward_convert_dodag_preferences_to_dao_path_control(rpl_dodag_t *dod } rpl_instance_t *instance = dodag->instance; - uint8_t pcs = dodag->config.path_control_size; + uint8_t pcs = rpl_conf_option_path_control_size(&dodag->config); uint_fast8_t bit = 0; rpl_neighbour_t *last = NULL; @@ -477,14 +477,14 @@ static uint8_t *rpl_downward_write_target(uint8_t *ptr, rpl_dao_target_t *target * Figure 26: Format of the Transit Information Option * */ -static uint8_t *rpl_downward_write_transit(uint8_t *ptr, rpl_dao_target_t *target, uint8_t path_control, const uint8_t *parent, bool no_path) +static uint8_t *rpl_downward_write_transit(uint8_t *ptr, rpl_dao_target_t *target, uint8_t path_control, const uint8_t *parent, uint8_t path_lifetime) { *ptr++ = RPL_TRANSIT_OPTION; *ptr++ = parent ? 16 + 4 : 4; *ptr++ = target->external ? TRANSIT_FLAG_EXTERNAL : 0; *ptr++ = path_control; *ptr++ = target->path_sequence; - *ptr++ = no_path ? 0 : target->info.non_root.path_lifetime; + *ptr++ = path_lifetime; if (parent) { ptr = (uint8_t *) memcpy(ptr, parent, 16) + 16; } @@ -770,7 +770,11 @@ void rpl_instance_send_dao_update(rpl_instance_t *instance) * (^ Repeat if more targets with different transit info/parents) */ - + const rpl_dodag_conf_int_t *conf = rpl_dodag_get_config(dodag); + if (!conf) { + rpl_instance_dao_trigger(instance, 0); + return; + } uint8_t *opts = ns_dyn_mem_temporary_alloc(1280); if (!opts) { rpl_instance_dao_trigger(instance, 0); @@ -778,13 +782,13 @@ void rpl_instance_send_dao_update(rpl_instance_t *instance) } uint8_t *ptr = opts; - rpl_downward_reset_assigning(instance, PCSMASK(dodag->config.path_control_size)); + rpl_downward_reset_assigning(instance, PCSMASK(rpl_conf_option_path_control_size(&dodag->config))); ns_list_foreach(rpl_dao_target_t, t, &instance->dao_targets) { /* Self-published targets can defer path lifetime choice */ if (t->info.non_root.path_lifetime == 0) { uint32_t lifetime = t->lifetime; - const rpl_dodag_conf_t *conf = rpl_dodag_get_config(dodag); + uint16_t unit = conf->lifetime_unit; uint8_t def = conf->default_lifetime; if (lifetime != 0xFFFFFFFF) { @@ -835,20 +839,31 @@ void rpl_instance_send_dao_update(rpl_instance_t *instance) ptr = rpl_downward_write_target(ptr, t2); } + + uint8_t path_lifetime; + uint8_t path_life_adjust_t_default = conf->default_lifetime - (conf->default_lifetime / 8); + if (target->info.non_root.path_lifetime < path_life_adjust_t_default || target->info.non_root.path_lifetime >= conf->default_lifetime) { + path_lifetime = target->info.non_root.path_lifetime; + } else { + //Adjust from 7/8-0.99 to 1*default + //to pass conformance tests that expect to see exactly the default lifetime in a smoothly-running system + path_lifetime = conf->default_lifetime; + } + /* Then output the transit information for the original target */ if (storing) { /* Just one transit info */ - ptr = rpl_downward_write_transit(ptr, target, path_control, NULL, false); + ptr = rpl_downward_write_transit(ptr, target, path_control, NULL, path_lifetime); } else if (target->own) { /* One transit info for each DAO parent */ ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { if (neighbour->dao_path_control & path_control) { - ptr = rpl_downward_write_transit(ptr, target, neighbour->dao_path_control & path_control, neighbour->global_address, false); + ptr = rpl_downward_write_transit(ptr, target, neighbour->dao_path_control & path_control, neighbour->global_address, path_lifetime); } } } else { /* Attached host - single transit is us */ - ptr = rpl_downward_write_transit(ptr, target, path_control, our_addr, false); + ptr = rpl_downward_write_transit(ptr, target, path_control, our_addr, path_lifetime); } } @@ -1601,7 +1616,7 @@ void rpl_instance_dao_acked(rpl_instance_t *instance, const uint8_t src[16], int } rpl_dodag_t *dodag = rpl_instance_current_dodag(instance); - const rpl_dodag_conf_t *conf = dodag ? rpl_dodag_get_config(dodag) : NULL; + const rpl_dodag_conf_int_t *conf = dodag ? rpl_dodag_get_config(dodag) : NULL; instance->dao_in_transit = false; instance->dao_retry_timer = 0; if (!retry) { @@ -1917,11 +1932,11 @@ static void rpl_instance_address_registration_cancel(rpl_instance_t *instance) instance->pending_neighbour_confirmation = false; } -static void rpl_instance_address_registration_retry(rpl_dao_target_t *dao_target) +static void rpl_instance_address_registration_retry(rpl_dao_target_t *dao_target, uint8_t response_wait_time) { dao_target->active_confirmation_state = true; // Active timer is set true so the response_wait_time runs out dao_target->trig_confirmation_state = true; - dao_target->response_wait_time = 20; // Wait 20 seconds before retry + dao_target->response_wait_time = response_wait_time; // Wait 20 seconds before retry } void rpl_instance_parent_address_reg_timer_update(rpl_instance_t *instance, uint16_t seconds) @@ -2003,28 +2018,36 @@ bool rpl_instance_address_registration_done(protocol_interface_info_entry_t *int tr_debug("Address %s register to %s", trace_ipv6(dao_target->prefix), trace_ipv6(neighbour->ll_address)); - if (status != SOCKET_TX_DONE) { - if (neighbour->addr_reg_failures > 0) { - // Neighbor should be blacklisted after this. - tr_error("Address registration failed delete neighbor"); - rpl_instance_address_registration_cancel(instance); - rpl_delete_neighbour(instance, neighbour); - return true; + if (status == SOCKET_TX_DONE) { + /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ + if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); + if (address && address->source != ADDR_SOURCE_DHCP) { + address->state_timer = (address->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); } - tr_warn("Address registration ACK fail retry selection"); - neighbour->addr_reg_failures++; - rpl_instance_address_registration_retry(dao_target); + neighbour->addr_reg_failures = 0; + neighbour->confirmed = true; + dao_target->response_wait_time = 6; return false; } - /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ - if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); - if (address && address->source != ADDR_SOURCE_DHCP) { - address->state_timer = (address->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); + + if (status == SOCKET_BUSY) { + tr_warn("Address registration CCA fail retry selection"); + rpl_instance_address_registration_retry(dao_target, 4); + return false; } - neighbour->addr_reg_failures = 0; - neighbour->confirmed = true; - dao_target->response_wait_time = 6; + + if (neighbour->addr_reg_failures > 0) { + // Neighbor should be blacklisted after this. + tr_error("Address registration failed delete neighbor"); + rpl_instance_address_registration_cancel(instance); + rpl_delete_neighbour(instance, neighbour); + return true; + } + tr_warn("Address registration ACK fail retry selection"); + neighbour->addr_reg_failures++; + rpl_instance_address_registration_retry(dao_target, 20); return false; + } #endif /* HAVE_RPL */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c index 5f669c591c7..c0ee1171172 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c @@ -87,7 +87,7 @@ bool rpl_policy_join_dodag(rpl_domain_t *domain, uint8_t g_mop_prf, uint8_t inst return true; } -bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_t *conf, bool *leaf_only) +bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_int_t *conf, bool *leaf_only) { (void)domain; (void)conf; @@ -99,7 +99,7 @@ bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_t *conf, } /* We don't support authentication */ - if (conf->authentication) { + if (rpl_conf_option_security(conf)) { return false; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h index b80e0e9f2a5..4b594325950 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h @@ -26,7 +26,7 @@ void rpl_policy_force_tunnel_set(bool enable); bool rpl_policy_join_instance(rpl_domain_t *domain, uint8_t instance_id, const uint8_t *dodagid); bool rpl_policy_join_dodag(rpl_domain_t *domain, uint8_t g_mop_prf, uint8_t instance_id, const uint8_t *dodagid); -bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_t *conf, bool *leaf_only); +bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_int_t *conf, bool *leaf_only); bool rpl_policy_request_dao_acks(const rpl_domain_t *domain, uint8_t mop); uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h index 0adeaacbf91..d43dea4a208 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h @@ -81,7 +81,7 @@ struct rpl_dodag { uint32_t timestamp; /* How long since we heard a DIO */ uint8_t id[16]; /* Root identifier */ uint8_t g_mop_prf; /* Grounded, Mode, Preference */ - rpl_dodag_conf_t config; /* Configuration from DIO */ + rpl_dodag_conf_int_t config; /* Configuration from DIO */ uint8_t info_version; /* Version for g_mop_prf and config */ bool root: 1; /* We are the root of this DODAG */ bool was_root: 1; /* If we have ever been a root in this DODAG */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c index 283dff2b9c1..c4347fc76d9 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c @@ -729,7 +729,7 @@ void rpl_delete_dodag_root(rpl_dodag_t *dodag) /* Convert RPL configuration to generic trickle parameters. Returns true if * the value in the generic object has changed. */ -static bool rpl_dodag_conf_convert_trickle_parameters(trickle_params_t *params_out, const rpl_dodag_conf_t *conf) +static bool rpl_dodag_conf_convert_trickle_parameters(trickle_params_t *params_out, const rpl_dodag_conf_int_t *conf) { /* Convert trickle parameters into 100ms ticks */ uint32_t Imin_ms = conf->dio_interval_min < 32 ? (1ul << conf->dio_interval_min) : 0xfffffffful; @@ -756,7 +756,7 @@ uint8_t rpl_dodag_mop(const rpl_dodag_t *dodag) return dodag->g_mop_prf & RPL_MODE_MASK; } -bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_t *conf, const uint8_t *src, bool *become_leaf) +bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_int_t *conf, const uint8_t *src, bool *become_leaf) { /* If already have config, don't update unless it's coming from preferred parent */ if (dodag->have_config) { @@ -863,7 +863,7 @@ bool rpl_dodag_is_current(const rpl_dodag_t *dodag) return dodag->instance->current_dodag_version && dodag->instance->current_dodag_version->dodag == dodag; } -const rpl_dodag_conf_t *rpl_dodag_get_config(const rpl_dodag_t *dodag) +const rpl_dodag_conf_int_t *rpl_dodag_get_config(const rpl_dodag_t *dodag) { return dodag->have_config ? &dodag->config : NULL; } @@ -1677,7 +1677,7 @@ void rpl_instance_dio_trigger(rpl_instance_t *instance, protocol_interface_info_ } // Always send config in unicasts (as required), never in multicasts (optional) - rpl_dodag_conf_t *conf; + rpl_dodag_conf_int_t *conf; if (addr) { conf = &dodag->config; //Unicast diff --git a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h index 3a3cb183c24..b15e65f4389 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.h @@ -108,7 +108,7 @@ uint8_t rpl_dodag_get_version_number_as_root(const rpl_dodag_t *dodag); void rpl_dodag_set_version_number_as_root(rpl_dodag_t *dodag, uint8_t number); void rpl_dodag_set_leaf(rpl_dodag_t *dodag, bool leaf); bool rpl_dodag_am_leaf(const rpl_dodag_t *dodag); -const rpl_dodag_conf_t *rpl_dodag_get_config(const rpl_dodag_t *dodag); +const rpl_dodag_conf_int_t *rpl_dodag_get_config(const rpl_dodag_t *dodag); void rpl_dodag_inconsistency(rpl_dodag_t *dodag); void rpl_dodag_increment_dtsn(rpl_dodag_t *dodag); rpl_cmp_t rpl_dodag_pref_compare(const rpl_dodag_t *a, const rpl_dodag_t *b); @@ -138,7 +138,7 @@ rpl_neighbour_t *rpl_lookup_neighbour_by_ll_address(const rpl_instance_t *instan rpl_neighbour_t *rpl_lookup_last_candidate_from_list(const rpl_instance_t *instance); rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *instance, const uint8_t *ll_addr, int8_t if_id, uint8_t g_mop_prf, uint8_t dtsn); void rpl_delete_neighbour(rpl_instance_t *instance, rpl_neighbour_t *neighbour); -bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_t *conf, const uint8_t *src, bool *become_leaf); +bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_int_t *conf, const uint8_t *src, bool *become_leaf); const uint8_t *rpl_neighbour_ll_address(const rpl_neighbour_t *neighbour); const uint8_t *rpl_neighbour_global_address(const rpl_neighbour_t *neighbour); void rpl_neighbour_update_global_address(rpl_neighbour_t *neighbour, const uint8_t *addr); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/Security/CMakeLists.txt index b945694ffa0..63aaf0653a5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c index 4f1d3a725bb..d4a7c476e8b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c @@ -411,7 +411,7 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) tr_info("EAP-TLS start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, SEC_PROT_RETRYING_PROTOCOL_TIMEOUT); // KMP-CREATE.confirm prot->create_conf(prot, SEC_RESULT_OK); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/radius_eap_tls_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/radius_eap_tls_sec_prot.c index 09944249d93..1591df9cac7 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/radius_eap_tls_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/radius_eap_tls_sec_prot.c @@ -436,7 +436,7 @@ static void radius_eap_tls_sec_prot_state_machine(sec_prot_t *prot) tr_info("EAP-TLS: start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, SEC_PROT_RETRYING_PROTOCOL_TIMEOUT); // KMP-CREATE.confirm prot->create_conf(prot, SEC_RESULT_OK); @@ -482,7 +482,7 @@ static void radius_eap_tls_sec_prot_state_machine(sec_prot_t *prot) sec_prot_timer_trickle_stop(&data->common); // Set timeout to wait for RADIUS client to continue - data->common.ticks = RADIUS_EAP_TLS_CLIENT_TIMEOUT; + sec_prot_timeout_set(&data->common, RADIUS_EAP_TLS_CLIENT_TIMEOUT); // Send to radius client data->radius_client_send(data->radius_client_prot, (void *) &data->recv_eapol_pdu, length); @@ -547,7 +547,7 @@ static void radius_eap_tls_sec_prot_state_machine(sec_prot_t *prot) sec_prot_timer_trickle_stop(&data->common); // Set timeout to wait for RADIUS client to continue - data->common.ticks = RADIUS_EAP_TLS_CLIENT_TIMEOUT; + sec_prot_timeout_set(&data->common, RADIUS_EAP_TLS_CLIENT_TIMEOUT); // Send to radius client data->radius_client_send(data->radius_client_prot, (void *) &data->recv_eapol_pdu, length); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c index aa296c39d1e..a80a3ea2587 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c @@ -406,7 +406,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) } // Set retry timeout based on network size - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); // Store sequence ID supp_eap_tls_sec_prot_seq_id_update(prot); @@ -451,7 +451,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) supp_eap_tls_sec_prot_seq_id_update(prot); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_REQUEST); - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); // Initialize TLS protocol if (supp_eap_tls_sec_prot_init_tls(prot) < 0) { @@ -485,7 +485,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) // Store sequence ID if (supp_eap_tls_sec_prot_seq_id_update(prot)) { // When receiving a new sequence number, adds more time for re-send if no response - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); } // All fragments received for a message diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c index 8138fe8ed4f..cae58691271 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c @@ -120,7 +120,7 @@ static int8_t auth_fwh_sec_prot_init(sec_prot_t *prot) sec_prot_init(&data->common); sec_prot_state_set(prot, &data->common, FWH_STATE_INIT); - data->common.ticks = 15 * 10; // 15 seconds + sec_prot_timeout_set(&data->common, 15 * 10); // 15 seconds uint8_t eui64[8] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08}; sec_prot_lib_nonce_init(data->nonce, eui64, 1000); @@ -348,7 +348,7 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) tr_info("4WH: start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, SEC_PROT_RETRYING_PROTOCOL_TIMEOUT); uint8_t *pmk = sec_prot_keys_pmk_get(prot->sec_keys); if (!pmk) { // If PMK is not set fails diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c index 84e91e61ca3..1f98e8c92f7 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c @@ -139,7 +139,7 @@ static int8_t supp_fwh_sec_prot_init(sec_prot_t *prot) sec_prot_init(&data->common); sec_prot_state_set(prot, &data->common, FWH_STATE_INIT); - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); data->msg3_received = false; data->msg3_retry_wait = false; data->recv_replay_cnt = 0; @@ -314,7 +314,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) } // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); tr_info("4WH: start"); @@ -337,7 +337,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) if (sec_prot_result_ok_check(&data->common)) { // Send 4WH message 2 supp_fwh_sec_prot_message_send(prot, FWH_MESSAGE_2); - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); sec_prot_state_set(prot, &data->common, FWH_STATE_MESSAGE_3); } else { // Ready to be deleted @@ -365,7 +365,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) // Send 4WH message 2 supp_fwh_sec_prot_message_send(prot, FWH_MESSAGE_2); - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); return; } else if (data->recv_msg != FWH_MESSAGE_3) { return; @@ -392,7 +392,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) // Sends 4WH Message 4 supp_fwh_sec_prot_message_send(prot, FWH_MESSAGE_4); - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); sec_prot_state_set(prot, &data->common, FWH_STATE_FINISH); break; @@ -412,7 +412,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) sec_prot_keys_ptk_write(prot->sec_keys, data->new_ptk, prot->sec_cfg->timer_cfg.ptk_lifetime); sec_prot_keys_ptk_eui_64_write(prot->sec_keys, data->remote_eui64); - data->common.ticks = 60 * 10; // 60 seconds + sec_prot_timeout_set(&data->common, 60 * 10); // 60 seconds // KMP-FINISHED.indication prot->finished_ind(prot, sec_prot_result_get(&data->common), prot->sec_keys); sec_prot_state_set(prot, &data->common, FWH_STATE_MESSAGE_3_RETRY_WAIT); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c index b01d60c824e..416a0797b1f 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c @@ -295,7 +295,7 @@ static void auth_gkh_sec_prot_state_machine(sec_prot_t *prot) tr_info("GKH start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, SEC_PROT_RETRYING_PROTOCOL_TIMEOUT); // KMP-CREATE.confirm prot->create_conf(prot, SEC_RESULT_OK); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c index a836e5870bd..cffe5f704e1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c @@ -247,7 +247,7 @@ static void supp_gkh_sec_prot_state_machine(sec_prot_t *prot) } // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); supp_gkh_sec_prot_security_replay_counter_update(prot); diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/key_sec_prot/key_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/key_sec_prot/key_sec_prot.c index 540ed35c71a..817f3c43e99 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/key_sec_prot/key_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/key_sec_prot/key_sec_prot.c @@ -370,7 +370,7 @@ static void supp_key_sec_prot_state_machine(sec_prot_t *prot) // KMP-FINISHED.indication, prot->finished_ind(prot, sec_prot_result_get(&data->common), 0); sec_prot_state_set(prot, &data->common, KEY_STATE_FINISHED); - data->common.ticks = KEY_SEC_FINISHED_TIMEOUT; + sec_prot_timeout_set(&data->common, KEY_SEC_FINISHED_TIMEOUT); break; case KEY_STATE_FINISHED: @@ -416,7 +416,7 @@ static void auth_key_sec_prot_state_machine(sec_prot_t *prot) // KMP-FINISHED.indication, prot->finished_ind(prot, sec_prot_result_get(&data->common), 0); sec_prot_state_set(prot, &data->common, KEY_STATE_FINISHED); - data->common.ticks = KEY_SEC_FINISHED_TIMEOUT; + sec_prot_timeout_set(&data->common, KEY_SEC_FINISHED_TIMEOUT); break; case KEY_STATE_FINISHED: { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/radius_sec_prot/radius_client_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/radius_sec_prot/radius_client_sec_prot.c index 21dc0bf7e0b..c646b24cd2e 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/radius_sec_prot/radius_client_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/radius_sec_prot/radius_client_sec_prot.c @@ -786,19 +786,31 @@ static int8_t radius_client_sec_prot_eui_64_hash_generate(uint8_t *eui_64, uint8 mbedtls_sha256_init(&ctx); +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_starts(&ctx, 0) != 0) { +#else if (mbedtls_sha256_starts_ret(&ctx, 0) != 0) { +#endif ret_val = -1; goto error; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_update(&ctx, hashed_string, 24) != 0) { +#else if (mbedtls_sha256_update_ret(&ctx, hashed_string, 24) != 0) { +#endif ret_val = -1; goto error; } uint8_t output[32]; +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_finish(&ctx, output) != 0) { +#else if (mbedtls_sha256_finish_ret(&ctx, output) != 0) { +#endif ret_val = -1; goto error; } @@ -872,19 +884,35 @@ static int8_t radius_client_sec_prot_response_authenticator_calc(sec_prot_t *pro mbedtls_md5_init(&ctx); +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_starts(&ctx) != 0) { +#else if (mbedtls_md5_starts_ret(&ctx) != 0) { +#endif goto end; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_update(&ctx, msg_ptr, msg_len) != 0) { +#else if (mbedtls_md5_update_ret(&ctx, msg_ptr, msg_len) != 0) { +#endif goto end; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_update(&ctx, key, key_len) != 0) { +#else if (mbedtls_md5_update_ret(&ctx, key, key_len) != 0) { +#endif goto end; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_finish(&ctx, auth_ptr) != 0) { +#else if (mbedtls_md5_finish_ret(&ctx, auth_ptr) != 0) { +#endif goto end; } @@ -940,35 +968,59 @@ static int8_t radius_client_sec_prot_ms_mppe_recv_key_pmk_decrypt(sec_prot_t *pr while (cipher_text_len >= MS_MPPE_RECV_KEY_BLOCK_LEN) { mbedtls_md5_init(&ctx); +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_starts(&ctx) != 0) { +#else if (mbedtls_md5_starts_ret(&ctx) != 0) { +#endif md5_failed = true; break; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_update(&ctx, key, key_len) != 0) { +#else if (mbedtls_md5_update_ret(&ctx, key, key_len) != 0) { +#endif md5_failed = true; break; } if (first_interm_b_value) { // b(1) = MD5(secret + request-authenticator + salt) +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_update(&ctx, request_authenticator, MS_MPPE_RECV_KEY_BLOCK_LEN) != 0) { +#else if (mbedtls_md5_update_ret(&ctx, request_authenticator, MS_MPPE_RECV_KEY_BLOCK_LEN) != 0) { +#endif md5_failed = true; break; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_update(&ctx, salt_ptr, MS_MPPE_RECV_KEY_SALT_LEN) != 0) { +#else if (mbedtls_md5_update_ret(&ctx, salt_ptr, MS_MPPE_RECV_KEY_SALT_LEN) != 0) { +#endif md5_failed = true; break; } } else { // b(i) = MD5(secret + cipher_text(i - 1)) +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_update(&ctx, cipher_text_ptr - MS_MPPE_RECV_KEY_BLOCK_LEN, MS_MPPE_RECV_KEY_BLOCK_LEN) != 0) { +#else if (mbedtls_md5_update_ret(&ctx, cipher_text_ptr - MS_MPPE_RECV_KEY_BLOCK_LEN, MS_MPPE_RECV_KEY_BLOCK_LEN) != 0) { +#endif md5_failed = true; break; } } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_md5_finish(&ctx, interm_b_val) != 0) { +#else if (mbedtls_md5_finish_ret(&ctx, interm_b_val) != 0) { +#endif md5_failed = true; break; } @@ -1037,7 +1089,7 @@ static void radius_client_sec_prot_state_machine(sec_prot_t *prot) tr_info("Radius: start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, SEC_PROT_RETRYING_PROTOCOL_TIMEOUT); sec_prot_state_set(prot, &data->common, RADIUS_STATE_CREATE_RESP); @@ -1096,7 +1148,7 @@ static void radius_client_sec_prot_state_machine(sec_prot_t *prot) sec_prot_timer_trickle_stop(&data->common); // Set timeout to wait for EAP-TLS to continue - data->common.ticks = prot->sec_cfg->prot_cfg.sec_prot_retry_timeout; + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); // Send to radius EAP-TLS if (data->radius_eap_tls_send && data->radius_eap_tls_prot && data->recv_eap_msg && data->recv_eap_msg_len > 0) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.c index 02748f08fcd..ebe5f6ab056 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.c @@ -507,7 +507,7 @@ uint32_t sec_prot_keys_gtk_lifetime_get(sec_prot_gtk_keys_t *gtks, uint8_t index return gtks->gtk[index].lifetime; } -uint32_t sec_prot_keys_gtk_lifetime_decrement(sec_prot_gtk_keys_t *gtks, uint8_t index, uint64_t current_time, uint16_t seconds, bool gtk_update_enable) +uint32_t sec_prot_keys_gtk_lifetime_decrement(sec_prot_gtk_keys_t *gtks, uint8_t index, uint64_t current_time, uint32_t seconds, bool gtk_update_enable) { if (gtks->gtk[index].lifetime > seconds) { gtks->gtk[index].lifetime -= seconds; @@ -527,6 +527,7 @@ uint32_t sec_prot_keys_gtk_lifetime_decrement(sec_prot_gtk_keys_t *gtks, uint8_t // If timestamps differ for more than 5 minutes marks field as updated (and stores to NVM) if (diff > 300 && gtk_update_enable) { gtks->updated = true; + sec_prot_keys_gtk_expirytime_set(gtks, index, expirytime); } return gtks->gtk[index].lifetime; @@ -716,7 +717,7 @@ int8_t sec_prot_keys_gtk_valid_check(uint8_t *gtk) return 0; } -gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t *gtkhash) +gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t *gtkhash, bool del_gtk_on_mismatch) { uint8_t *gtk_hash_ptr = gtkhash; @@ -729,11 +730,15 @@ gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t uint32_t lifetime = sec_prot_keys_gtk_lifetime_get(gtks, i); if (lifetime > GTK_EXPIRE_MISMATCH_TIME) { tr_info("GTK mismatch %i expired time, lifetime: %"PRIu32"", i, lifetime); - if (mismatch < GTK_LIFETIME_MISMATCH) { + // Only indicate mismatch in case fresh hash is received + if (mismatch < GTK_LIFETIME_MISMATCH && del_gtk_on_mismatch) { mismatch = GTK_LIFETIME_MISMATCH; } } - sec_prot_keys_gtk_clear(gtks, i); + // Only delete in case fresh hash is received + if (del_gtk_on_mismatch) { + sec_prot_keys_gtk_clear(gtks, i); + } } } else { // Check is hash matches to existing key @@ -759,7 +764,10 @@ gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t if (mismatch < GTK_HASH_MISMATCH) { mismatch = GTK_HASH_MISMATCH; } - sec_prot_keys_gtk_clear(gtks, i); + // Only delete in case fresh hash is received + if (del_gtk_on_mismatch) { + sec_prot_keys_gtk_clear(gtks, i); + } } } } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.h b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.h index 6215bdc759f..242618bd363 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_keys.h @@ -62,6 +62,10 @@ #define SEC_MAXIMUM_LIFETIME (60 * 60 * 24 * 30 * 24) // Maximum life time for PMK, PTK, GTKs etc. is two years +// System time changed +#define SYSTEM_TIME_NOT_CHANGED 0 +#define SYSTEM_TIME_CHANGED 1 + typedef struct { uint8_t key[GTK_LEN]; /**< Group Transient Key (128 bits) */ uint64_t expirytime; /**< GTK expiry time on storage */ @@ -108,7 +112,8 @@ typedef struct { typedef struct { uint8_t gtk[GTK_LEN]; /**< GTK of the frame counter */ uint32_t frame_counter; /**< Current frame counter */ - uint32_t stored_frame_counter; /**< Stored Frame counter */ + uint32_t stored_frame_counter; /**< Stored frame counter */ + uint32_t max_frame_counter_chg; /**< Maximum frame counter change */ bool set : 1; /**< Value has been set */ } frame_counter_t; @@ -144,6 +149,7 @@ typedef struct { uint16_t new_pan_id; /**< new PAN ID indicated by bootstrap */ uint16_t key_pan_id; /**< PAN ID for keys */ uint16_t pan_version; /**< PAN version for keys */ + uint8_t system_time_changed; /**< System time changed */ bool updated : 1; /**< Network info has been updated */ } sec_prot_keys_nw_info_t; @@ -630,7 +636,7 @@ uint32_t sec_prot_keys_gtk_lifetime_get(sec_prot_gtk_keys_t *gtks, uint8_t index * \return new GTK lifetime * */ -uint32_t sec_prot_keys_gtk_lifetime_decrement(sec_prot_gtk_keys_t *gtks, uint8_t index, uint64_t current_time, uint16_t seconds, bool gtk_update_enable); +uint32_t sec_prot_keys_gtk_lifetime_decrement(sec_prot_gtk_keys_t *gtks, uint8_t index, uint64_t current_time, uint32_t seconds, bool gtk_update_enable); /** * sec_prot_keys_gtk_exptime_from_lifetime_get converts GTK lifetime to expiry time. @@ -806,11 +812,12 @@ int8_t sec_prot_keys_gtk_valid_check(uint8_t *gtk); * * \param gtks GTK keys * \param gtk_hash GTK hash + * \param del_gtk_on_mismatch Delete GTK in case of mismatch * * \return GTK mismatch type or no mismatch * */ -gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t *gtkhash); +gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t *gtkhash, bool del_gtk_on_mismatch); /** * sec_prot_keys_gtk_hash_empty checks if GTK hash field is empty diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c index 7789020660c..09495a817cf 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c @@ -174,9 +174,9 @@ bool sec_prot_result_ok_check(sec_prot_common_t *data) return false; } -void sec_prot_default_timeout_set(sec_prot_common_t *data) +void sec_prot_timeout_set(sec_prot_common_t *data, uint16_t ticks) { - data->ticks = SEC_TOTAL_TIMEOUT; + data->ticks = ticks; } void sec_prot_lib_nonce_generate(uint8_t *nonce) @@ -514,19 +514,31 @@ int8_t sec_prot_lib_gtkhash_generate(uint8_t *gtk, uint8_t *gtk_hash) mbedtls_sha256_init(&ctx); +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_starts(&ctx, 0) != 0) { +#else if (mbedtls_sha256_starts_ret(&ctx, 0) != 0) { +#endif ret_val = -1; goto error; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_update(&ctx, gtk, 16) != 0) { +#else if (mbedtls_sha256_update_ret(&ctx, gtk, 16) != 0) { +#endif ret_val = -1; goto error; } uint8_t output[32]; +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_sha256_finish(&ctx, output) != 0) { +#else if (mbedtls_sha256_finish_ret(&ctx, output) != 0) { +#endif ret_val = -1; goto error; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h index 83a01879c2e..cc04b141a70 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h @@ -26,7 +26,6 @@ */ #define EUI64_LEN 8 -#define SEC_TOTAL_TIMEOUT 30 * 60 * 10 // 30 minutes #define SEC_FINISHED_TIMEOUT 5 * 10 // 5 seconds #define FWH_NONCE_LENGTH 32 @@ -299,11 +298,12 @@ bool sec_prot_result_timeout_check(sec_prot_common_t *data); bool sec_prot_result_ok_check(sec_prot_common_t *data); /** - * sec_prot_default_timeout_set sets default timeout for protocol + * sec_prot_timeout_set sets timeout for protocol * * \param data common data + * \param ticks ticks * */ -void sec_prot_default_timeout_set(sec_prot_common_t *data); +void sec_prot_timeout_set(sec_prot_common_t *data, uint16_t ticks); #endif /* SEC_PROT_LIB_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c index 545dbbcb87f..a7cb9b163f1 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c @@ -320,7 +320,7 @@ static void client_tls_sec_prot_state_machine(sec_prot_t *prot) sec_prot_state_set(prot, &data->common, TLS_STATE_CREATE_REQ); prot->timer_start(prot); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); break; // Wait KMP-CREATE.request @@ -355,6 +355,8 @@ static void client_tls_sec_prot_state_machine(sec_prot_t *prot) data->calculating = false; } + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); + if (data->tls_send.data) { prot->send(prot, data->tls_send.data, data->tls_send.handled_len); eap_tls_sec_prot_lib_message_init(&data->tls_send); @@ -415,7 +417,7 @@ static void server_tls_sec_prot_state_machine(sec_prot_t *prot) sec_prot_state_set(prot, &data->common, TLS_STATE_CLIENT_HELLO); prot->timer_start(prot); // Set default timeout for the total maximum length of the negotiation - sec_prot_default_timeout_set(&data->common); + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); break; // Wait EAP request, Identity (starts handshake on supplicant) @@ -474,6 +476,8 @@ static void server_tls_sec_prot_state_machine(sec_prot_t *prot) data->calculating = false; } + sec_prot_timeout_set(&data->common, prot->sec_cfg->prot_cfg.sec_prot_retry_timeout); + if (data->tls_send.data) { prot->send(prot, data->tls_send.data, data->tls_send.handled_len); eap_tls_sec_prot_lib_message_init(&data->tls_send); @@ -595,7 +599,7 @@ static void tls_sec_prot_tls_export_keys(void *handle, const uint8_t *master_sec const uint8_t *print_data = eap_tls_key_material; uint16_t print_data_len = 128; while (true) { - tr_debug("EAP-TLS key material %s\n", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); + tr_debug("EAP-TLS key material %s", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); if (print_data_len > 32) { print_data_len -= 32; print_data += 32; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index 36f50a8b098..fa3df55593b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -18,12 +18,8 @@ #include "nsconfig.h" #ifdef HAVE_WS -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/version.h" #if defined(MBEDTLS_SSL_TLS_C) && defined(MBEDTLS_X509_CRT_PARSE_C) && defined(MBEDTLS_SSL_EXPORT_KEYS) /* EXPORT_KEYS not supported by mbedtls baremetal yet */ #define WS_MBEDTLS_SECURITY_ENABLED #endif @@ -49,7 +45,6 @@ #include "mbedtls/platform.h" #include "mbedtls/ssl_cookie.h" #include "mbedtls/entropy.h" -#include "mbedtls/entropy_poll.h" #include "mbedtls/ctr_drbg.h" #include "mbedtls/ssl_ciphersuites.h" #include "mbedtls/debug.h" @@ -77,7 +72,9 @@ struct tls_security_s { mbedtls_pk_context pkey; /**< Private key for own certificate */ void *handle; /**< Handle provided in callbacks (defined by library user) */ bool ext_cert_valid : 1; /**< Extended certificate validation enabled */ +#if (MBEDTLS_VERSION_MAJOR < 3) tls_sec_prot_lib_crt_verify_cb *crt_verify; /**< Verify function for client/server certificate */ +#endif tls_sec_prot_lib_send *send; /**< Send callback */ tls_sec_prot_lib_receive *receive; /**< Receive callback */ tls_sec_prot_lib_export_keys *export_keys; /**< Export keys callback */ @@ -90,12 +87,22 @@ static int tls_sec_prot_lib_ssl_get_timer(void *ctx); static int tls_sec_lib_entropy_poll(void *data, unsigned char *output, size_t len, size_t *olen); static int tls_sec_prot_lib_ssl_send(void *ctx, const unsigned char *buf, size_t len); static int tls_sec_prot_lib_ssl_recv(void *ctx, unsigned char *buf, size_t len); -static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char *ms, +#if (MBEDTLS_VERSION_MAJOR >= 3) +static void tls_sec_prot_lib_ssl_export_keys(void *p_expkey, mbedtls_ssl_key_export_type type, + const unsigned char *secret, + size_t secret_len, + const unsigned char client_random[32], + const unsigned char server_random[32], + mbedtls_tls_prf_types tls_prf_type); +#else +static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char *secret, const unsigned char *kb, size_t maclen, size_t keylen, size_t ivlen, const unsigned char client_random[32], const unsigned char server_random[32], mbedtls_tls_prf_types tls_prf_type); +#endif +#if (MBEDTLS_VERSION_MAJOR < 3) static int tls_sec_prot_lib_x509_crt_verify(void *ctx, mbedtls_x509_crt *crt, int certificate_depth, uint32_t *flags); static int8_t tls_sec_prot_lib_subject_alternative_name_validate(mbedtls_x509_crt *crt); static int8_t tls_sec_prot_lib_extended_key_usage_validate(mbedtls_x509_crt *crt); @@ -105,6 +112,7 @@ static int tls_sec_prot_lib_x509_crt_idevid_ldevid_verify(tls_security_t *sec, m #ifdef HAVE_PAE_SUPP static int tls_sec_prot_lib_x509_crt_server_verify(tls_security_t *sec, mbedtls_x509_crt *crt, uint32_t *flags); #endif +#endif #ifdef TLS_SEC_PROT_LIB_TLS_DEBUG static void tls_sec_prot_lib_debug(void *ctx, int level, const char *file, int line, const char *string); #endif @@ -234,7 +242,11 @@ static int tls_sec_prot_lib_configure_certificates(tls_security_t *sec, const se return -1; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (mbedtls_pk_parse_key(&sec->pkey, key, key_len, NULL, 0, mbedtls_ctr_drbg_random, &sec->ctr_drbg) < 0) { +#else if (mbedtls_pk_parse_key(&sec->pkey, key, key_len, NULL, 0) < 0) { +#endif tr_error("Private key parse error"); return -1; } @@ -310,6 +322,7 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } +#if (MBEDTLS_VERSION_MAJOR < 3) #ifdef HAVE_PAE_SUPP if (is_server_is_not_set) { sec->crt_verify = tls_sec_prot_lib_x509_crt_server_verify; @@ -320,7 +333,7 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p sec->crt_verify = tls_sec_prot_lib_x509_crt_idevid_ldevid_verify; } #endif - +#endif if ((mbedtls_ssl_config_defaults(&sec->conf, is_server_is_set ? MBEDTLS_SSL_IS_SERVER : MBEDTLS_SSL_IS_CLIENT, @@ -384,7 +397,11 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p #endif // Export keys callback +#if (MBEDTLS_VERSION_MAJOR >= 3) + mbedtls_ssl_set_export_keys_cb(&sec->ssl, tls_sec_prot_lib_ssl_export_keys, sec); +#else mbedtls_ssl_conf_export_keys_ext_cb(&sec->conf, tls_sec_prot_lib_ssl_export_keys, sec); +#endif #if !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) mbedtls_ssl_conf_min_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); @@ -395,7 +412,9 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p #endif /* !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) */ // Set certificate verify callback +#if (MBEDTLS_VERSION_MAJOR < 3) mbedtls_ssl_set_verify(&sec->ssl, tls_sec_prot_lib_x509_crt_verify, sec); +#endif /* Currently assuming we are running fast enough HW that ECC calculations are not blocking any normal operation. * @@ -432,7 +451,11 @@ int8_t tls_sec_prot_lib_process(tls_security_t *sec) return TLS_SEC_PROT_LIB_ERROR; } +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (sec->ssl.private_state == MBEDTLS_SSL_HANDSHAKE_OVER) { +#else if (sec->ssl.state == MBEDTLS_SSL_HANDSHAKE_OVER) { +#endif return TLS_SEC_PROT_LIB_HANDSHAKE_OVER; } } @@ -469,16 +492,31 @@ static int tls_sec_prot_lib_ssl_recv(void *ctx, unsigned char *buf, size_t len) return ret; } -static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char *ms, +#if (MBEDTLS_VERSION_MAJOR >= 3) +static void tls_sec_prot_lib_ssl_export_keys(void *p_expkey, mbedtls_ssl_key_export_type type, + const unsigned char *secret, + size_t secret_len, + const unsigned char client_random[32], + const unsigned char server_random[32], + mbedtls_tls_prf_types tls_prf_type) +#else +static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char *secret, const unsigned char *kb, size_t maclen, size_t keylen, size_t ivlen, const unsigned char client_random[32], const unsigned char server_random[32], mbedtls_tls_prf_types tls_prf_type) +#endif { +#if (MBEDTLS_VERSION_MAJOR >= 3) + if (type != MBEDTLS_SSL_KEY_EXPORT_TLS12_MASTER_SECRET || secret_len < 48) { + return; + } +#else (void) kb; (void) maclen; (void) keylen; (void) ivlen; +#endif tls_security_t *sec = (tls_security_t *)p_expkey; @@ -487,18 +525,24 @@ static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char memcpy(random, client_random, 32); memcpy(&random[32], server_random, 32); - int ret = mbedtls_ssl_tls_prf(tls_prf_type, ms, 48, "client EAP encryption", + int ret = mbedtls_ssl_tls_prf(tls_prf_type, secret, 48, "client EAP encryption", random, 64, eap_tls_key_material, 128); if (ret != 0) { tr_error("key material PRF error"); +#if (MBEDTLS_VERSION_MAJOR < 3) return 0; +#endif } - sec->export_keys(sec->handle, ms, eap_tls_key_material); + sec->export_keys(sec->handle, secret, eap_tls_key_material); + +#if (MBEDTLS_VERSION_MAJOR < 3) return 0; +#endif } +#if (MBEDTLS_VERSION_MAJOR < 3) static int tls_sec_prot_lib_x509_crt_verify(void *ctx, mbedtls_x509_crt *crt, int certificate_depth, uint32_t *flags) { tls_security_t *sec = (tls_security_t *) ctx; @@ -605,6 +649,7 @@ static int tls_sec_prot_lib_x509_crt_server_verify(tls_security_t *sec, mbedtls_ return 0; } #endif +#endif static int tls_sec_lib_entropy_poll(void *ctx, unsigned char *output, size_t len, size_t *olen) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/CMakeLists.txt index b77b3bc7840..846fc8cb055 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/channel_list.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/channel_list.c index a25ffe12b41..9af436a7cae 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/channel_list.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/channel_list.c @@ -35,7 +35,7 @@ static bool channel_list_bit_test32(uint32_t word, int_fast8_t bit_number) { bool bitSet; - if (word & ((uint32_t) 1 << bit_number)) { + if (word & (1U << bit_number)) { bitSet = true; } else { bitSet = false; @@ -92,9 +92,9 @@ void channel_list_set_channel(uint32_t *list, int channel, bool active) return; } if (active) { - list[channel / 32] |= (1 << channel % 32); + list[channel / 32] |= (1U << channel % 32); } else { - list[channel / 32] &= ~(1 << channel % 32); + list[channel / 32] &= ~(1U << channel % 32); } return; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c index 090520570bf..061337395c5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c @@ -292,7 +292,7 @@ static int32_t fhss_channel_index_from_mask(const uint32_t *channel_mask, int32_ int32_t active_channels = 0; // Set channel maks outside excluded channels for (int32_t i = 0; i < number_of_channels; i++) { - if (channel_mask[0 + (i / 32)] & (1 << (i % 32))) { + if (channel_mask[i / 32] & (1U << (i % 32))) { if (channel_index == active_channels) { return i; } diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/hmac/hmac_md.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/hmac/hmac_md.c index 0ef22158e11..affc569b3e5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/hmac/hmac_md.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/hmac/hmac_md.c @@ -29,12 +29,12 @@ int8_t hmac_md_calc(const alg_hmac_md_e md, const uint8_t *key, uint16_t key_len { #ifdef EXTRA_DEBUG_INFO // Extensive debug for now, to be disabled later - tr_debug("hmac_md key %s\n", trace_array(key, key_len)); + tr_debug("hmac_md key %s", trace_array(key, key_len)); const uint8_t *print_data = data; uint16_t print_data_len = data_len; while (true) { - tr_debug("hmac_md data %s\n", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); + tr_debug("hmac_md data %s", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); if (print_data_len > 32) { print_data_len -= 32; print_data += 32; @@ -81,7 +81,7 @@ int8_t hmac_md_calc(const alg_hmac_md_e md, const uint8_t *key, uint16_t key_len memcpy(result, result_value, result_len); #ifdef EXTRA_DEBUG_INFO - tr_debug("hmac_md result %s\n", trace_array(result_value, 20)); + tr_debug("hmac_md result %s", trace_array(result_value, 20)); #endif return 0; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nd_proxy/nd_proxy.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nd_proxy/nd_proxy.c index 6d75180313e..5a9dd6f7486 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nd_proxy/nd_proxy.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nd_proxy/nd_proxy.c @@ -349,7 +349,7 @@ int nd_proxy_downstream_interface_register(int8_t interface_id, nd_proxy_req_cb ns_list_foreach(nd_proxy_upstream_list_s, e, &upstream_interface_list) { if (proxy_cache_interface_enable_proxy(e->id, interface_id) == 0) { - tr_debug("Proxy bridge enabled for interface %i to %i\n", e->id, interface_id); + tr_debug("Proxy bridge enabled for interface %i to %i", e->id, interface_id); } } @@ -391,7 +391,7 @@ int nd_proxy_upstream_interface_register(int8_t interface_id, nd_proxy_req_cb *r ns_list_foreach(nd_proxy_downstream_list_s, e, &downstream_interface_list) { if (proxy_cache_interface_enable_proxy(interface_id, e->id) == 0) { - tr_debug("Proxy bridge enabled for interface %i to %i \n", interface_id, e->id); + tr_debug("Proxy bridge enabled for interface %i to %i", interface_id, e->id); } } return 0; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nist_aes_kw/nist_aes_kw.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nist_aes_kw/nist_aes_kw.c index 98f6a698128..282d9e46ba9 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nist_aes_kw/nist_aes_kw.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/nist_aes_kw/nist_aes_kw.c @@ -21,11 +21,7 @@ #include "ns_list.h" #include "ns_trace.h" -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "mbedtls/version.h" #if defined(MBEDTLS_NIST_KW_C) && defined(HAVE_WS) && (defined(HAVE_PAE_SUPP) || defined(HAVE_PAE_AUTH)) #include "mbedtls/nist_kw.h" @@ -48,7 +44,7 @@ int8_t nist_aes_key_wrap(uint8_t is_wrap, const uint8_t *key, int16_t key_bits, const uint8_t *print_data = key; uint16_t print_data_len = key_bits / 8; while (true) { - tr_debug("nist_aes_key_wrap key %s\n", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); + tr_debug("nist_aes_key_wrap key %s", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); if (print_data_len > 32) { print_data_len -= 32; print_data += 32; @@ -60,7 +56,7 @@ int8_t nist_aes_key_wrap(uint8_t is_wrap, const uint8_t *key, int16_t key_bits, print_data = input; print_data_len = input_len; while (true) { - tr_debug("nist_aes_key_wrap in %s\n", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); + tr_debug("nist_aes_key_wrap in %s", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); if (print_data_len > 32) { print_data_len -= 32; print_data += 32; @@ -95,7 +91,7 @@ int8_t nist_aes_key_wrap(uint8_t is_wrap, const uint8_t *key, int16_t key_bits, print_data = output; print_data_len = *output_len; while (true) { - tr_debug("nist_aes_key_wrap out %s\n", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); + tr_debug("nist_aes_key_wrap out %s", trace_array(print_data, print_data_len > 32 ? 32 : print_data_len)); if (print_data_len > 32) { print_data_len -= 32; print_data += 32; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.c index 9e8bf761b3a..e0aabe979e4 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.c @@ -22,6 +22,9 @@ static ns_time_api_system_time_callback *system_time_read_callback = NULL; static ns_time_api_system_time_write_callback *system_time_write_callback = NULL; +static ns_time_api_time_configuration_notify_callback *system_time_configuration_notify_callback = NULL; + +static bool system_time_acquired = false; void ns_time_api_system_time_callback_set(ns_time_api_system_time_callback callback_rd) { @@ -33,10 +36,16 @@ void ns_time_api_system_time_write_callback_set(ns_time_api_system_time_write_ca system_time_write_callback = callback_wr; } +void ns_time_api_time_configuration_notify_callback_set(ns_time_api_time_configuration_notify_callback callback_wr) +{ + system_time_configuration_notify_callback = callback_wr; +} + int ns_time_system_time_write(uint64_t time_write) { if (system_time_write_callback) { system_time_write_callback(time_write); + system_time_acquired = true; return 0; } @@ -53,3 +62,23 @@ int ns_time_system_time_read(uint64_t *time_read) return -1; } + +int ns_time_system_timezone_info_notify(timezone_info_t *info_ptr) +{ + if (system_time_configuration_notify_callback && info_ptr) { + system_time_configuration_notify_callback(info_ptr); + return 0; + } + + return -1; +} + +void ns_time_system_time_acquired_set(void) +{ + system_time_acquired = true; +} + +bool ns_time_system_time_acquired_get(void) +{ + return system_time_acquired; +} diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.h b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.h index 27299ce0bbd..34256af055c 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/utils/ns_time.h @@ -22,6 +22,7 @@ * \file ns_time.h * \brief Nanostack internal time handling API. */ +#include "ns_time_api.h" /** * Write new time as a platform time @@ -51,6 +52,33 @@ int ns_time_system_time_write(uint64_t time_write); */ int ns_time_system_time_read(uint64_t *time_read); +/** + * Notify Time zone and daylight saving time information + * + * \param info_ptr time zone information pointer. + * + * \return 0 in success. + * \return <0 in case of errors. + * + */ +int ns_time_system_timezone_info_notify(timezone_info_t *info_ptr); +/** + * Set system time acquired + * + * Sets system time acquired (e.g. has been acquired from network) + * + */ +void ns_time_system_time_acquired_set(void); + +/** + * Get system time acquired + * + * Checks whether system time has been acquired (e.g. has been written) + * + * \return TRUE system time has been acquired, FALSE system time has not been acquired + * + */ +bool ns_time_system_time_acquired_get(void); #endif /* _NS_TIME_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/configs/CMakeLists.txt index 98525e80b73..232128a026d 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/configs/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_full.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_full.h new file mode 100644 index 00000000000..798f3c88a06 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_full.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cfg_ws_border_router.h" + +#define HAVE_PAE_SUPP diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h new file mode 100644 index 00000000000..aec86edcd3c --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_host.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define HAVE_WS +#define HAVE_WS_HOST +#define HAVE_WS_VERSION_1_1 +#define HAVE_MPL +#define HAVE_6LOWPAN_ND +#define HAVE_IPV6_ND +#define HAVE_6LOWPAN_ROUTER diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h index a8a07c57004..5e36562036b 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/base/cfg_ws_router.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Pelion and affiliates. + * Copyright (c) 2019-2021, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,12 +15,8 @@ * limitations under the License. */ -#define HAVE_6LOWPAN_ROUTER -#define HAVE_WS_ROUTER +#include "cfg_ws_host.h" + #define HAVE_RPL -#define HAVE_IPV6_ND -#define HAVE_6LOWPAN_ND -#define HAVE_MPL -#define HAVE_WS -#define HAVE_PAE_SUPP +#define HAVE_WS_ROUTER #define HAVE_EAPOL_RELAY diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h index d17b1378500..49ccb5ee99e 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_generic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, 2016-2019, Pelion and affiliates. + * Copyright (c) 2014, 2016-2021, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,7 +20,7 @@ #include "base/cfg_lowpan_border_router.h" #include "base/cfg_local_socket.h" #include "base/cfg_rf_tunnel.h" -#include "base/cfg_ws_border_router.h" +#include "base/cfg_ws_full.h" #define FEA_TRACE_SUPPORT #define EXTRA_CONSISTENCY_CHECKS @@ -32,4 +32,5 @@ #define TCP_TEST #define THREAD_THCI_SUPPORT #define HAVE_WS +#define HAVE_WS_VERSION_1_1 #define MLE_TEST diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_full.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_full.h new file mode 100644 index 00000000000..798f3c88a06 --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_full.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cfg_ws_border_router.h" + +#define HAVE_PAE_SUPP diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h new file mode 100644 index 00000000000..debfeb2c87c --- /dev/null +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_host.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021, Pelion and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "base/cfg_ws_host.h" + +#define FEA_TRACE_SUPPORT +#define EXTRA_CONSISTENCY_CHECKS +#define HAVE_PAE_SUPP + diff --git a/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h index a4cf9525016..da740e5c69d 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/configs/cfg_ws_router.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Pelion and affiliates. + * Copyright (c) 2019-2021, Pelion and affiliates. * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,4 +20,5 @@ #define FEA_TRACE_SUPPORT #define EXTRA_CONSISTENCY_CHECKS +#define HAVE_PAE_SUPP diff --git a/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/CMakeLists.txt index 9bc0e259ff2..6ef7fbb31cf 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/protocol_ipv6.c b/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/protocol_ipv6.c index 6041ac623a4..982405b0341 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/protocol_ipv6.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/ipv6_stack/protocol_ipv6.c @@ -323,16 +323,16 @@ static void ipv6_nd_bootstrap(protocol_interface_info_entry_t *cur) break; case IPV6_ROUTER_SOLICATION: - tr_debug("Waiting for ICMPv6 Router Advertisement"); if (ipv6_nd_rs(cur)) { + tr_debug("Waiting for ICMPv6 Router Advertisement"); if (cur->ipv6_configure->routerSolicationRetryCounter != ROUTER_SOL_MAX_COUNTER) { cur->ipv6_configure->routerSolicationRetryCounter++; } - cur->ipv6_configure->ND_TIMER = (cur->ipv6_configure->routerSolicationRetryCounter * 25); - - } else { - cur->ipv6_configure->ND_TIMER = 1; } + if (cur->ipv6_configure->routerSolicationRetryCounter == 0) { + cur->ipv6_configure->routerSolicationRetryCounter++; + } + cur->ipv6_configure->ND_TIMER = (cur->ipv6_configure->routerSolicationRetryCounter * 25); break; case IPV6_GP_GEN: diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/CMakeLists.txt index c012616ddc6..f922d6e437a 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.c b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.c index fb6b909c7c6..0eda579b324 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.c @@ -137,7 +137,7 @@ uint8_t *net_vendor_option_current_time_read(uint8_t *ptr, uint16_t length, int3 } option_len = common_read_16_bit(ptr + 2); - ptr += 4; + ptr += 2 * sizeof(uint16_t); if (option_len < 3 * sizeof(uint32_t)) { // Corrupted as not enough room for fields @@ -147,11 +147,70 @@ uint8_t *net_vendor_option_current_time_read(uint8_t *ptr, uint16_t length, int3 if (era) { *era = (int32_t)common_read_32_bit(ptr); } + if (offset) { *offset = common_read_32_bit(ptr + sizeof(uint32_t)); } + if (fraction) { - *fraction = common_read_32_bit(ptr + 2 * sizeof(uint32_t)); + *fraction = common_read_32_bit(ptr + sizeof(uint32_t) + sizeof(uint32_t)); + } + + return ptr; +} + +uint16_t net_vendor_option_time_configuration_length(void) +{ + return 4 + 1 * sizeof(uint64_t) + 2 * sizeof(int16_t) + 1 * sizeof(uint16_t); +} + +uint8_t *net_vendor_option_time_configuration_write(uint8_t *ptr, uint64_t timestamp, int16_t timezone, int16_t deviation, uint16_t status) +{ + + ptr = common_write_16_bit(ARM_DHCP_VENDOR_DATA_TIME_CONFIGURATION, ptr); + ptr = common_write_16_bit(1 * sizeof(uint64_t) + 2 * sizeof(int16_t) + 1 * sizeof(uint16_t), ptr); + ptr = common_write_16_bit(status, ptr); + ptr = common_write_64_bit(timestamp, ptr); + ptr = common_write_16_bit((uint16_t)deviation, ptr); + ptr = common_write_16_bit((uint16_t)timezone, ptr); + return ptr; +} + +uint8_t *net_vendor_option_time_configuration_read(uint8_t *ptr, uint16_t length, uint64_t *timestamp, int16_t *timezone, int16_t *deviation, uint16_t *status) +{ + uint16_t option_len; + + if (length < net_vendor_option_time_configuration_length()) { + // Corrupted as there is no room for all fields + return 0; + } + + if (common_read_16_bit(ptr) != ARM_DHCP_VENDOR_DATA_TIME_CONFIGURATION) { + return 0; + } + + option_len = common_read_16_bit(ptr + sizeof(uint16_t)); + ptr += 2 * sizeof(uint16_t); + + if (option_len < 1 * sizeof(uint64_t) + 2 * sizeof(int16_t) + 1 * sizeof(uint16_t)) { + // Corrupted as not enough room for fields + return 0; + } + + if (status) { + *status = (uint16_t)common_read_16_bit(ptr); + } + + if (timestamp) { + *timestamp = common_read_64_bit(ptr + sizeof(uint16_t)); + } + + if (deviation) { + *deviation = (int16_t)common_read_16_bit(ptr + sizeof(uint16_t) + sizeof(uint64_t)); + } + + if (timezone) { + *timezone = (int16_t)common_read_16_bit(ptr + sizeof(uint16_t) + sizeof(uint64_t) + sizeof(uint16_t)); } return ptr; diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.h b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.h index a9974e88625..1fc33d0d444 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.h +++ b/connectivity/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6_vendordata.h @@ -66,6 +66,17 @@ * */ #define ARM_DHCP_VENDOR_DATA_NETWORK_TIME 298 +/* ARM Defined vendor data option to distribute Time configuration + * + * uint16_t status Bit field for status + * bit 1 Daylight saving time status 0 = false 1 = true + * Additional bits reserved for future and are ignored on receive + * uint64_t timestamp Time stamp of the Daylight saving time change + * int16_t deviation Change that is applied when time stamp is reached + * int16_t timezone Time zone information in minutes compared to UTC time + */ +#define ARM_DHCP_VENDOR_DATA_TIME_CONFIGURATION 299 + /* DHCPv6 vendor options to distribute ARM vendor data*/ uint16_t net_dns_option_vendor_option_data_dns_query_length(char *domain); @@ -78,5 +89,8 @@ uint16_t net_vendor_option_current_time_length(void); uint8_t *net_vendor_option_current_time_write(uint8_t *ptr, int32_t era, uint32_t offset, uint32_t fraction); uint8_t *net_vendor_option_current_time_read(uint8_t *ptr, uint16_t length, int32_t *era, uint32_t *offset, uint32_t *fraction); +uint16_t net_vendor_option_time_configuration_length(void); +uint8_t *net_vendor_option_time_configuration_write(uint8_t *ptr, uint64_t timestamp, int16_t timezone, int16_t deviation, uint16_t status); +uint8_t *net_vendor_option_time_configuration_read(uint8_t *ptr, uint16_t length, uint64_t *timestamp, int16_t *timezone, int16_t *deviation, uint16_t *status); #endif /* LIBDHCPV6_VENDOR_DATA_H_ */ diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libNET/CMakeLists.txt b/connectivity/nanostack/sal-stack-nanostack/source/libNET/CMakeLists.txt index 2ad2d7edd75..8d2a977d728 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libNET/CMakeLists.txt +++ b/connectivity/nanostack/sal-stack-nanostack/source/libNET/CMakeLists.txt @@ -1,4 +1,4 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021, Pelion and affiliates. # SPDX-License-Identifier: Apache-2.0 target_include_directories(mbed-nanostack-sal_stack diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/net_load_balance.c b/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/net_load_balance.c index 7dbbe1ae298..34fb9bf32d8 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/net_load_balance.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/net_load_balance.c @@ -248,7 +248,7 @@ void net_load_balance_internal_state_activate(protocol_interface_info_entry_t *i if (state && interface_ptr->rpl_domain) { struct rpl_instance *instance = rpl_control_lookup_instance(interface_ptr->rpl_domain, 1, NULL); if (instance) { - const rpl_dodag_conf_t *dodag_config = rpl_control_get_dodag_config(instance); + const rpl_dodag_conf_int_t *dodag_config = rpl_control_get_dodag_config(instance); if (dodag_config) { //dio max Period caluclate in seconds uint32_t Imax_ms = (dodag_config->dio_interval_min + dodag_config->dio_interval_doublings) < 32 ? diff --git a/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c b/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c index dd3883c6efb..eecd38f772a 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c @@ -67,7 +67,7 @@ #include "6LoWPAN/Thread/thread_routing.h" #include "6LoWPAN/Thread/thread_bootstrap.h" #include "6LoWPAN/Thread/thread_management_internal.h" -#include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_common.h" #ifdef HAVE_WS #include "6LoWPAN/ws/ws_pae_controller.h" #endif @@ -168,7 +168,7 @@ int8_t arm_net_nwk_scan(int8_t interface_id, channel_list_s *scan_list, void (*p if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { ret_val = -1; } else if (arm_channel_list_validation(scan_list)) { - tr_debug("Given channel mask is empty!\n"); + tr_debug("Given channel mask is empty!"); ret_val = -2; } else { nwk_scan_params_t *scan_params = &cur->mac_parameters->nwk_scan_params; @@ -768,7 +768,7 @@ static int arm_net_channel_bit_mask_to_number(const uint32_t *channel_mask) for (j = 0; j < 8; j++) { for (i = 0; i < 32; i++) { - if (channel_mask[j] & ((uint32_t)1 << i)) { + if (channel_mask[j] & (1U << i)) { break; } } @@ -804,7 +804,7 @@ int8_t arm_nwk_interface_network_driver_set(int8_t interface_id, const channel_l protocol_interface_info_entry_t *cur = 0; if (arm_channel_list_validation(nwk_channel_list)) { - tr_debug("Given channel mask is empty!\n"); + tr_debug("Given channel mask is empty!"); return -5; } @@ -981,15 +981,21 @@ int8_t arm_nwk_link_layer_security_mode(int8_t interface_id, net_6lowpan_link_la int8_t arm_network_certificate_chain_set(const arm_certificate_chain_entry_s *chain_info) { + int8_t ret = -2; + #if !defined(PANA) && !defined(HAVE_WS) (void)chain_info; #endif #ifdef HAVE_WS - ws_pae_controller_certificate_chain_set(chain_info); + ret = ws_pae_controller_certificate_chain_set(chain_info); +#endif + +#ifdef PANA + ret = pana_interface_certificate_chain_set(chain_info); #endif - return pana_interface_certificate_chain_set(chain_info); + return ret; } int8_t arm_network_trusted_certificate_add(const arm_certificate_entry_s *cert) @@ -1207,7 +1213,7 @@ int8_t arm_nwk_interface_configure_6lowpan_bootstrap_set(int8_t interface_id, ne if (net_6lowpan_mode_extension == NET_6LOWPAN_THREAD) { ret_val = thread_node_bootstrap_init(interface_id, bootstrap_mode); } else if (net_6lowpan_mode_extension == NET_6LOWPAN_WS) { - ret_val = ws_bootstrap_init(interface_id, bootstrap_mode); + ret_val = ws_common_init(interface_id, bootstrap_mode); } else { ret_val = arm_6lowpan_bootstarp_bootstrap_set(interface_id, bootstrap_mode, net_6lowpan_mode_extension); } @@ -1226,7 +1232,7 @@ int8_t arm_nwk_set_channel_list(int8_t interface_id, const channel_list_s *nwk_c } if (arm_channel_list_validation(nwk_channel_list)) { - tr_debug("Given channel mask is empty!\n"); + tr_debug("Given channel mask is empty!"); return -2; } diff --git a/connectivity/nanostack/sal-stack-nanostack/sources.mk b/connectivity/nanostack/sal-stack-nanostack/sources.mk index 7c5af85febc..417d2d63f4d 100644 --- a/connectivity/nanostack/sal-stack-nanostack/sources.mk +++ b/connectivity/nanostack/sal-stack-nanostack/sources.mk @@ -23,6 +23,10 @@ SRCS += \ source/6LoWPAN/ws/ws_mpx_header.c \ source/6LoWPAN/ws/ws_neighbor_class.c \ source/6LoWPAN/ws/ws_bootstrap.c \ + source/6LoWPAN/ws/ws_bootstrap_6lbr.c \ + source/6LoWPAN/ws/ws_bootstrap_6lr.c \ + source/6LoWPAN/ws/ws_bootstrap_6ln.c \ + source/6LoWPAN/ws/ws_bootstrap_ffn.c \ source/6LoWPAN/ws/ws_common.c \ source/6LoWPAN/ws/ws_management_api.c \ source/6LoWPAN/ws/ws_bbr_api.c \ @@ -43,6 +47,7 @@ SRCS += \ source/6LoWPAN/ws/ws_eapol_pdu.c \ source/6LoWPAN/ws/ws_stats.c \ source/6LoWPAN/ws/ws_cfg_settings.c \ + source/6LoWPAN/ws/ws_phy.c \ source/BorderRouter/border_router.c \ source/Common_Protocols/icmpv6.c \ source/Common_Protocols/icmpv6_prefix.c \ @@ -83,6 +88,7 @@ SRCS += \ source/MAC/IEEE802_15_4/sw_mac.c \ source/MAC/IEEE802_15_4/mac_fhss_callbacks.c \ source/MAC/IEEE802_15_4/mac_cca_threshold.c \ + source/MAC/IEEE802_15_4/mac_mode_switch.c \ source/MAC/ethernet/ethernet_mac_api.c \ source/MAC/serial/serial_mac_api.c \ source/MAC/virtual_rf/virtual_rf_client.c \ diff --git a/connectivity/netsocket/CMakeLists.txt b/connectivity/netsocket/CMakeLists.txt index 9760c60316d..d9748a11465 100644 --- a/connectivity/netsocket/CMakeLists.txt +++ b/connectivity/netsocket/CMakeLists.txt @@ -69,6 +69,7 @@ endif() target_link_libraries(mbed-netsocket INTERFACE + mbed-wifi mbed-cellular mbed-nanostack-libservice ) diff --git a/connectivity/netsocket/include/netsocket/DTLSSocketWrapper.h b/connectivity/netsocket/include/netsocket/DTLSSocketWrapper.h index 5f7ff00e0a4..17e2a6349a7 100644 --- a/connectivity/netsocket/include/netsocket/DTLSSocketWrapper.h +++ b/connectivity/netsocket/include/netsocket/DTLSSocketWrapper.h @@ -40,6 +40,14 @@ class DTLSSocketWrapper : public TLSSocketWrapper { * @param control Transport control mode. See @ref control_transport. */ DTLSSocketWrapper(Socket *transport, const char *hostname = NULL, control_transport control = TRANSPORT_CONNECT_AND_CLOSE); + + /** Destroy a socket wrapper. + * + * Closes socket wrapper if the socket wrapper is still opened. + */ + ~DTLSSocketWrapper(); + + nsapi_error_t close() override; private: static void timing_set_delay(void *ctx, uint32_t int_ms, uint32_t fin_ms); static int timing_get_delay(void *ctx); diff --git a/connectivity/netsocket/source/DTLSSocketWrapper.cpp b/connectivity/netsocket/source/DTLSSocketWrapper.cpp index 2f8666def02..ca7544b0cb2 100644 --- a/connectivity/netsocket/source/DTLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/DTLSSocketWrapper.cpp @@ -36,6 +36,11 @@ DTLSSocketWrapper::DTLSSocketWrapper(Socket *transport, const char *hostname, co #endif /* !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) */ } +DTLSSocketWrapper::~DTLSSocketWrapper() +{ + close(); +} + void DTLSSocketWrapper::timing_set_delay(void *ctx, uint32_t int_ms, uint32_t fin_ms) { DTLSSocketWrapper *context = static_cast(ctx); @@ -74,6 +79,16 @@ int DTLSSocketWrapper::timing_get_delay(void *ctx) } } +nsapi_error_t DTLSSocketWrapper::close() +{ + if (_timer_event_id != 0) { + mbed::mbed_event_queue()->cancel(_timer_event_id); + _timer_event_id = 0; + } + + return TLSSocketWrapper::close(); +} + void DTLSSocketWrapper::timer_event(void) { _timer_expired = true; diff --git a/connectivity/netsocket/tests/TESTS/netsocket/dns/main.cpp b/connectivity/netsocket/tests/TESTS/netsocket/dns/main.cpp index 01e35d453f1..d9723f44cb6 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/dns/main.cpp +++ b/connectivity/netsocket/tests/TESTS/netsocket/dns/main.cpp @@ -168,6 +168,7 @@ static void net_bringup() MBED_ASSERT(MBED_CONF_APP_DNS_TEST_HOSTS_NUM >= MBED_CONF_NSAPI_DNS_CACHE_SIZE && MBED_CONF_APP_DNS_TEST_HOSTS_NUM >= MBED_CONF_APP_DNS_SIMULT_QUERIES + 1); net = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(net, "No NetworkInterface configured"); nsapi_error_t err = net->connect(); TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, err); SocketAddress address; diff --git a/connectivity/netsocket/tests/TESTS/netsocket/tcp/main.cpp b/connectivity/netsocket/tests/TESTS/netsocket/tcp/main.cpp index f2be5b880c4..0dde5a99d3f 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/tcp/main.cpp +++ b/connectivity/netsocket/tests/TESTS/netsocket/tcp/main.cpp @@ -75,6 +75,7 @@ nsapi_version_t get_ip_version() static void _ifup() { NetworkInterface *net = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(net, "No NetworkInterface configured"); nsapi_error_t err = net->connect(); TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, err); SocketAddress address; diff --git a/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp b/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp index f6489a3d736..aa256a7128e 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp +++ b/connectivity/netsocket/tests/TESTS/netsocket/tls/main.cpp @@ -71,6 +71,7 @@ void drop_bad_packets(TLSSocket &sock, int orig_timeout) static void _ifup() { NetworkInterface *net = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(net, "No NetworkInterface configured"); nsapi_error_t err = net->connect(); TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, err); SocketAddress address; diff --git a/connectivity/netsocket/tests/TESTS/netsocket/udp/main.cpp b/connectivity/netsocket/tests/TESTS/netsocket/udp/main.cpp index b3bfa899fc5..4b88b607b2a 100644 --- a/connectivity/netsocket/tests/TESTS/netsocket/udp/main.cpp +++ b/connectivity/netsocket/tests/TESTS/netsocket/udp/main.cpp @@ -62,6 +62,7 @@ void drop_bad_packets(UDPSocket &sock, int orig_timeout) static void _ifup() { NetworkInterface *net = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(net, "No NetworkInterface configured"); nsapi_error_t err = net->connect(); TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, err); SocketAddress address; diff --git a/connectivity/netsocket/tests/TESTS/network/interface/networkinterface_status.cpp b/connectivity/netsocket/tests/TESTS/network/interface/networkinterface_status.cpp index 8ed56986668..ce95d08d6c7 100644 --- a/connectivity/netsocket/tests/TESTS/network/interface/networkinterface_status.cpp +++ b/connectivity/netsocket/tests/TESTS/network/interface/networkinterface_status.cpp @@ -75,6 +75,7 @@ void NETWORKINTERFACE_STATUS() current_status = NSAPI_STATUS_ERROR_UNSUPPORTED; net = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(net, "No NetworkInterface configured"); net->attach(status_cb); net->set_blocking(true); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect.cpp index aec259f130b..fbd6f59c219 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect.cpp @@ -30,6 +30,10 @@ using namespace utest::v1; void wifi_connect(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } char ssid[SSID_MAX_LEN + 1] = MBED_CONF_APP_WIFI_UNSECURE_SSID; diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp index de24fa53130..898233da018 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_connect_disconnect_repeat(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } nsapi_error_t error; error = wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security()); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_nocredentials.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_nocredentials.cpp index 73e8c015fca..bae1a6ed9e9 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_nocredentials.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_nocredentials.cpp @@ -26,6 +26,10 @@ using namespace utest::v1; void wifi_connect_nocredentials(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } nsapi_error_t error_connect, error_disconnect; error_connect = wifi->connect(); error_disconnect = wifi->disconnect(); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel.cpp index a7fb57c4c6c..6be5b7d0db9 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_connect_params_channel(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("set_channel() not supported"); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp index 40b2bc9a0de..fc27f34dd78 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_connect_params_channel_fail(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("set_channel() not supported"); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_null.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_null.cpp index 0c2350dfcec..8fbe4be3ea1 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_null.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_null.cpp @@ -27,6 +27,10 @@ void wifi_connect_params_null(void) { nsapi_error_t error; WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } error = wifi->connect(NULL, NULL); wifi->disconnect(); TEST_ASSERT_EQUAL(NSAPI_ERROR_PARAMETER, error); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp index 2b3f1e9ec88..3264d90c5cd 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_connect_params_valid_secure(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } if (wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security()) == NSAPI_ERROR_OK) { if (wifi->disconnect() == NSAPI_ERROR_OK) { diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure.cpp index ee3059f21c2..82f8e51261e 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_connect_secure(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } // Driver shall cache the credentials char ssid[] = MBED_CONF_APP_WIFI_SECURE_SSID; diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure_fail.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure_fail.cpp index 72da4c03404..44d2793ad6b 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure_fail.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_connect_secure_fail.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_connect_secure_fail(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, "aaaaaaaa", get_security())); nsapi_error_t error; diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_get_rssi.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_get_rssi.cpp index 3cf5ab193f9..d6400a6b261 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_get_rssi.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_get_rssi.cpp @@ -28,6 +28,10 @@ using namespace utest::v1; void wifi_get_rssi(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, get_security())); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan.cpp index cfa86355b6e..1ae8e139a2b 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan.cpp @@ -27,6 +27,10 @@ using namespace utest::v1; void wifi_scan(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } WiFiAccessPoint ap[MBED_CONF_APP_MAX_SCAN_SIZE]; diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan_null.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan_null.cpp index 46751484c59..fc862e20cd1 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan_null.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_scan_null.cpp @@ -26,5 +26,9 @@ using namespace utest::v1; void wifi_scan_null(void) { WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } TEST_ASSERT(wifi->scan(NULL, 0) >= 1); } diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_channel.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_channel.cpp index 09eaa23d7f4..cddd90a4bfc 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_channel.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_channel.cpp @@ -30,6 +30,10 @@ void wifi_set_channel(void) bool is_5Ghz = false; WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); + if (wifi == NULL) { + return; + } if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) { TEST_IGNORE_MESSAGE("set_channel() not supported"); diff --git a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_credential.cpp b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_credential.cpp index b21e8f9443f..f7aae234b59 100644 --- a/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_credential.cpp +++ b/connectivity/netsocket/tests/TESTS/network/wifi/wifi_set_credential.cpp @@ -26,6 +26,10 @@ using namespace utest::v1; void wifi_set_credential(void) { WiFiInterface *iface = get_interface(); + TEST_ASSERT(iface); + if (iface == NULL) { + return; + } nsapi_error_t error; error = iface->set_credentials(NULL, NULL, NSAPI_SECURITY_NONE); diff --git a/connectivity/nfc/CMakeLists.txt b/connectivity/nfc/CMakeLists.txt index b8098066ae2..a1c48ac0453 100644 --- a/connectivity/nfc/CMakeLists.txt +++ b/connectivity/nfc/CMakeLists.txt @@ -3,6 +3,12 @@ add_subdirectory(libraries) +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + if(BUILD_GREENTEA_TESTS) + add_subdirectory(tests/TESTS) + endif() +endif() + target_include_directories(mbed-nfc INTERFACE . diff --git a/connectivity/nfc/tests/TESTS/CMakeLists.txt b/connectivity/nfc/tests/TESTS/CMakeLists.txt new file mode 100644 index 00000000000..c146e3a6753 --- /dev/null +++ b/connectivity/nfc/tests/TESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(nfc/eeprom) diff --git a/connectivity/nfc/tests/TESTS/nfc/eeprom/CMakeLists.txt b/connectivity/nfc/tests/TESTS/nfc/eeprom/CMakeLists.txt index f57d64918bb..0acf6fa0ed0 100644 --- a/connectivity/nfc/tests/TESTS/nfc/eeprom/CMakeLists.txt +++ b/connectivity/nfc/tests/TESTS/nfc/eeprom/CMakeLists.txt @@ -1,20 +1,19 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -cmake_minimum_required(VERSION 3.19.0 FATAL_ERROR) +include(mbed_greentea) -set(MBED_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../../../../../.. CACHE INTERNAL "") -set(TEST_TARGET mbed-connectivity-nfc-eeprom) - -include(${MBED_PATH}/tools/cmake/mbed_greentea.cmake) - -project(${TEST_TARGET}) +if(NOT "MBED_CONF_NFCEEPROM=1" IN_LIST MBED_CONFIG_DEFINITIONS) + set(TEST_SKIPPED "NFC EEPROM required") +endif() mbed_greentea_add_test( TEST_NAME - ${TEST_TARGET} + mbed-connectivity-nfc-eeprom TEST_SOURCES main.cpp TEST_REQUIRED_LIBS mbed-nfc + TEST_SKIPPED + ${TEST_SKIPPED} ) diff --git a/drivers/include/drivers/CAN.h b/drivers/include/drivers/CAN.h index be404f8955d..b1fa704a506 100644 --- a/drivers/include/drivers/CAN.h +++ b/drivers/include/drivers/CAN.h @@ -205,7 +205,7 @@ class CAN */ void attach(Callback func, IrqType type = IrqType::RxIrq); - static void _irq_handler(uint32_t id, CanIrqType type); + static void _irq_handler(uintptr_t context, CanIrqType type); #if !defined(DOXYGEN_ONLY) protected: diff --git a/drivers/include/drivers/FlashIAP.h b/drivers/include/drivers/FlashIAP.h index 43196e7648d..5e7d9d80987 100644 --- a/drivers/include/drivers/FlashIAP.h +++ b/drivers/include/drivers/FlashIAP.h @@ -26,7 +26,7 @@ #if DEVICE_FLASH || defined(DOXYGEN_ONLY) -#include "flash_api.h" +#include "hal/flash_api.h" #include "platform/SingletonPtr.h" #include "platform/PlatformMutex.h" #include "platform/NonCopyable.h" diff --git a/drivers/include/drivers/InterruptIn.h b/drivers/include/drivers/InterruptIn.h index a5ac24eb041..1b3a9eaddf0 100644 --- a/drivers/include/drivers/InterruptIn.h +++ b/drivers/include/drivers/InterruptIn.h @@ -99,12 +99,14 @@ class InterruptIn : private NonCopyable { /** Attach a function to call when a rising edge occurs on the input + * Interrupts are enabled for the pin * * @param func A pointer to a void function, or 0 to set as none */ void rise(Callback func); /** Attach a function to call when a falling edge occurs on the input + * Interrupts are enabled for the pin * * @param func A pointer to a void function, or 0 to set as none */ @@ -127,7 +129,7 @@ class InterruptIn : private NonCopyable { */ void disable_irq(); - static void _irq_handler(uint32_t id, gpio_irq_event event); + static void _irq_handler(uintptr_t context, gpio_irq_event event); #if !defined(DOXYGEN_ONLY) protected: gpio_t gpio; diff --git a/drivers/include/drivers/SerialBase.h b/drivers/include/drivers/SerialBase.h index 9288c271e15..7e1f6308112 100644 --- a/drivers/include/drivers/SerialBase.h +++ b/drivers/include/drivers/SerialBase.h @@ -173,7 +173,7 @@ class SerialBase : private NonCopyable { void set_flow_control(Flow type, const serial_fc_pinmap_t &static_pinmap); #endif - static void _irq_handler(uint32_t id, SerialIrq irq_type); + static void _irq_handler(uintptr_t context, SerialIrq irq_type); #if DEVICE_SERIAL_ASYNCH diff --git a/drivers/include/drivers/TickerDataClock.h b/drivers/include/drivers/TickerDataClock.h index 5c894442f49..448c29670ac 100644 --- a/drivers/include/drivers/TickerDataClock.h +++ b/drivers/include/drivers/TickerDataClock.h @@ -93,7 +93,7 @@ class TickerDataClock { * @param timestamp The event's timestamp * @param id The event object */ - void insert_event(ticker_event_t *obj, time_point timestamp, uint32_t id) + void insert_event(ticker_event_t *obj, time_point timestamp, uintptr_t id) { ticker_insert_event_us(_ticker, obj, timestamp.time_since_epoch().count(), id); } diff --git a/drivers/include/drivers/TimerEvent.h b/drivers/include/drivers/TimerEvent.h index 52befcf1bdd..c59ee5d699b 100644 --- a/drivers/include/drivers/TimerEvent.h +++ b/drivers/include/drivers/TimerEvent.h @@ -43,7 +43,7 @@ class TimerEvent : private NonCopyable { * * @param id Timer Event ID */ - static void irq(uint32_t id); + static void irq(uintptr_t id); /** Destruction removes it... */ diff --git a/drivers/source/CAN.cpp b/drivers/source/CAN.cpp index 2767c0743c7..f8aa18e00c1 100644 --- a/drivers/source/CAN.cpp +++ b/drivers/source/CAN.cpp @@ -26,28 +26,28 @@ CAN::CAN(PinName rd, PinName td) : _can(), _irq() { // No lock needed in constructor can_init(&_can, rd, td); - can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this); + can_irq_init(&_can, (&CAN::_irq_handler), reinterpret_cast(this)); } CAN::CAN(PinName rd, PinName td, int hz) : _can(), _irq() { // No lock needed in constructor can_init_freq(&_can, rd, td, hz); - can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this); + can_irq_init(&_can, (&CAN::_irq_handler), reinterpret_cast(this)); } CAN::CAN(const can_pinmap_t &pinmap) : _can(), _irq() { // No lock needed in constructor can_init_direct(&_can, &pinmap); - can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this); + can_irq_init(&_can, (&CAN::_irq_handler), reinterpret_cast(this)); } CAN::CAN(const can_pinmap_t &pinmap, int hz) : _can(), _irq() { // No lock needed in constructor can_init_freq_direct(&_can, &pinmap, hz); - can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this); + can_irq_init(&_can, (&CAN::_irq_handler), reinterpret_cast(this)); } CAN::~CAN() @@ -153,9 +153,9 @@ void CAN::attach(Callback func, IrqType type) unlock(); } -void CAN::_irq_handler(uint32_t id, CanIrqType type) +void CAN::_irq_handler(uintptr_t context, CanIrqType type) { - CAN *handler = (CAN *)id; + CAN *handler = reinterpret_cast(context); if (handler->_irq[type]) { handler->_irq[type].call(); } diff --git a/drivers/source/InterruptIn.cpp b/drivers/source/InterruptIn.cpp index 113213a289f..2d61ed48feb 100644 --- a/drivers/source/InterruptIn.cpp +++ b/drivers/source/InterruptIn.cpp @@ -47,7 +47,7 @@ InterruptIn::InterruptIn(PinName pin, PinMode mode) : void InterruptIn::irq_init(PinName pin) { - gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this); + gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), reinterpret_cast(this)); } InterruptIn::~InterruptIn() @@ -95,9 +95,9 @@ void InterruptIn::fall(Callback func) core_util_critical_section_exit(); } -void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) +void InterruptIn::_irq_handler(uintptr_t context, gpio_irq_event event) { - InterruptIn *handler = (InterruptIn *)id; + InterruptIn *handler = reinterpret_cast(context); switch (event) { case IRQ_RISE: if (handler->_rise) { diff --git a/drivers/source/SerialBase.cpp b/drivers/source/SerialBase.cpp index 40bf7d0b618..1ebc9a056c0 100644 --- a/drivers/source/SerialBase.cpp +++ b/drivers/source/SerialBase.cpp @@ -114,9 +114,9 @@ void SerialBase::attach(Callback func, IrqType type) unlock(); } -void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) +void SerialBase::_irq_handler(uintptr_t context, SerialIrq irq_type) { - SerialBase *handler = (SerialBase *)id; + SerialBase *handler = reinterpret_cast(context); if (handler->_irq[irq_type]) { handler->_irq[irq_type](); } @@ -144,7 +144,7 @@ void SerialBase::_init() } #endif serial_baud(&_serial, _baud); - serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this); + serial_irq_handler(&_serial, SerialBase::_irq_handler, reinterpret_cast(this)); } void SerialBase::_init_direct() @@ -156,7 +156,7 @@ void SerialBase::_init_direct() } #endif serial_baud(&_serial, _baud); - serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this); + serial_irq_handler(&_serial, SerialBase::_irq_handler, reinterpret_cast(this)); } void SerialBase::_deinit() diff --git a/drivers/source/TimerEvent.cpp b/drivers/source/TimerEvent.cpp index 69e10b14c1d..68a033eb9c3 100644 --- a/drivers/source/TimerEvent.cpp +++ b/drivers/source/TimerEvent.cpp @@ -28,7 +28,7 @@ TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) _ticker_data.set_handler(irq); } -void TimerEvent::irq(uint32_t id) +void TimerEvent::irq(uintptr_t id) { TimerEvent *timer_event = reinterpret_cast(id); timer_event->handler(); @@ -42,7 +42,7 @@ TimerEvent::~TimerEvent() // insert in to linked list void TimerEvent::insert(timestamp_t timestamp) { - ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this); + ticker_insert_event(_ticker_data, &event, timestamp, reinterpret_cast(this)); } void TimerEvent::insert(microseconds rel_time) @@ -52,12 +52,12 @@ void TimerEvent::insert(microseconds rel_time) void TimerEvent::insert_absolute(us_timestamp_t timestamp) { - ticker_insert_event_us(_ticker_data, &event, timestamp, (uint32_t)this); + ticker_insert_event_us(_ticker_data, &event, timestamp, reinterpret_cast(this)); } void TimerEvent::insert_absolute(TickerDataClock::time_point timestamp) { - _ticker_data.insert_event(&event, timestamp, (uint32_t)this); + _ticker_data.insert_event(&event, timestamp, reinterpret_cast(this)); } void TimerEvent::remove() diff --git a/drivers/tests/UNITTESTS/AnalogOut/CMakeLists.txt b/drivers/tests/UNITTESTS/AnalogOut/CMakeLists.txt new file mode 100644 index 00000000000..eb1f41414ff --- /dev/null +++ b/drivers/tests/UNITTESTS/AnalogOut/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME analogout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_ANALOGOUT +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/AnalogOut.cpp + test_analogout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/AnalogOut/test_analogout.cpp b/drivers/tests/UNITTESTS/AnalogOut/test_analogout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/AnalogOut/test_analogout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/BufferedSerial/CMakeLists.txt b/drivers/tests/UNITTESTS/BufferedSerial/CMakeLists.txt new file mode 100644 index 00000000000..ca030bb1ef0 --- /dev/null +++ b/drivers/tests/UNITTESTS/BufferedSerial/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME bufferedserial-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL + DEVICE_INTERRUPTIN + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/BufferedSerial.cpp + test_bufferedserial.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-platform + mbed-stubs-drivers +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/BufferedSerial/test_bufferedserial.cpp b/drivers/tests/UNITTESTS/BufferedSerial/test_bufferedserial.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/BufferedSerial/test_bufferedserial.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/BusIn/CMakeLists.txt b/drivers/tests/UNITTESTS/BusIn/CMakeLists.txt new file mode 100644 index 00000000000..9a39e2e0b99 --- /dev/null +++ b/drivers/tests/UNITTESTS/BusIn/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME busin-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/BusIn.cpp + test_busin.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-drivers + mbed-headers-hal + mbed-stubs-platform + mbed-stubs-drivers + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/BusIn/test_busin.cpp b/drivers/tests/UNITTESTS/BusIn/test_busin.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/BusIn/test_busin.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/BusInOut/CMakeLists.txt b/drivers/tests/UNITTESTS/BusInOut/CMakeLists.txt new file mode 100644 index 00000000000..c15b071e1c4 --- /dev/null +++ b/drivers/tests/UNITTESTS/BusInOut/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME businout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/BusInOut.cpp + test_businout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-platform + mbed-stubs-hal + mbed-stubs-drivers +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/BusInOut/test_businout.cpp b/drivers/tests/UNITTESTS/BusInOut/test_businout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/BusInOut/test_businout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/BusOut/CMakeLists.txt b/drivers/tests/UNITTESTS/BusOut/CMakeLists.txt new file mode 100644 index 00000000000..d9eef386bbf --- /dev/null +++ b/drivers/tests/UNITTESTS/BusOut/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME busout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/BusOut.cpp + test_busout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/BusOut/test_busout.cpp b/drivers/tests/UNITTESTS/BusOut/test_busout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/BusOut/test_busout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/CAN/CMakeLists.txt b/drivers/tests/UNITTESTS/CAN/CMakeLists.txt new file mode 100644 index 00000000000..d4268ef4d6d --- /dev/null +++ b/drivers/tests/UNITTESTS/CAN/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME can-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_CAN +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/CAN.cpp + test_can.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/CAN/test_can.cpp b/drivers/tests/UNITTESTS/CAN/test_can.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/CAN/test_can.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/CMakeLists.txt b/drivers/tests/UNITTESTS/CMakeLists.txt index 2e4ce437c1d..b42f9339cac 100644 --- a/drivers/tests/UNITTESTS/CMakeLists.txt +++ b/drivers/tests/UNITTESTS/CMakeLists.txt @@ -2,5 +2,33 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory(doubles) add_subdirectory(AnalogIn) +add_subdirectory(AnalogOut) +add_subdirectory(BufferedSerial) +add_subdirectory(BusIn) +add_subdirectory(BusInOut) +add_subdirectory(BusOut) +add_subdirectory(CAN) +add_subdirectory(DigitalIn) +add_subdirectory(DigitalInOut) +add_subdirectory(DigitalOut) +add_subdirectory(FlashIAP) +add_subdirectory(I2C) +add_subdirectory(I2CSlave) +add_subdirectory(InterruptIn) +add_subdirectory(MbedCRC) +add_subdirectory(OSPI) +add_subdirectory(PortIn) +add_subdirectory(PortInOut) +add_subdirectory(PortOut) add_subdirectory(PwmOut) +add_subdirectory(QSPI) +add_subdirectory(ResetReason) +add_subdirectory(SPI) +add_subdirectory(SPISlave) +add_subdirectory(SerialBase) +add_subdirectory(SerialWireOutput) +add_subdirectory(Ticker) +add_subdirectory(Timeout) +add_subdirectory(TimerEvent) +add_subdirectory(UnbufferedSerial) add_subdirectory(Watchdog) diff --git a/drivers/tests/UNITTESTS/DigitalIn/CMakeLists.txt b/drivers/tests/UNITTESTS/DigitalIn/CMakeLists.txt new file mode 100644 index 00000000000..6d3bd002370 --- /dev/null +++ b/drivers/tests/UNITTESTS/DigitalIn/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME digitalin-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/DigitalIn.cpp + test_digitalin.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/DigitalIn/test_digitalin.cpp b/drivers/tests/UNITTESTS/DigitalIn/test_digitalin.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/DigitalIn/test_digitalin.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/DigitalInOut/CMakeLists.txt b/drivers/tests/UNITTESTS/DigitalInOut/CMakeLists.txt new file mode 100644 index 00000000000..9d11fb4f256 --- /dev/null +++ b/drivers/tests/UNITTESTS/DigitalInOut/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME digitalinout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/DigitalInOut.cpp + test_digitalinout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/DigitalInOut/test_digitalinout.cpp b/drivers/tests/UNITTESTS/DigitalInOut/test_digitalinout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/DigitalInOut/test_digitalinout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/DigitalOut/CMakeLists.txt b/drivers/tests/UNITTESTS/DigitalOut/CMakeLists.txt new file mode 100644 index 00000000000..2319f4a0041 --- /dev/null +++ b/drivers/tests/UNITTESTS/DigitalOut/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME digitalout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/DigitalOut.cpp + test_digitalout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/DigitalOut/test_digitalout.cpp b/drivers/tests/UNITTESTS/DigitalOut/test_digitalout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/DigitalOut/test_digitalout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/FlashIAP/CMakeLists.txt b/drivers/tests/UNITTESTS/FlashIAP/CMakeLists.txt new file mode 100644 index 00000000000..95e715fabb0 --- /dev/null +++ b/drivers/tests/UNITTESTS/FlashIAP/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME flashiap-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_FLASH +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/FlashIAP.cpp + test_flashiap.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-hal + mbed-headers-drivers + mbed-headers-platform + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/FlashIAP/test_flashiap.cpp b/drivers/tests/UNITTESTS/FlashIAP/test_flashiap.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/FlashIAP/test_flashiap.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/I2C/CMakeLists.txt b/drivers/tests/UNITTESTS/I2C/CMakeLists.txt new file mode 100644 index 00000000000..e46e0157e91 --- /dev/null +++ b/drivers/tests/UNITTESTS/I2C/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME i2c-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_I2C + DEVICE_I2C_ASYNCH +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/I2C.cpp + test_i2c.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-platform + mbed-stubs-hal + mbed-stubs-drivers +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/I2C/test_i2c.cpp b/drivers/tests/UNITTESTS/I2C/test_i2c.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/I2C/test_i2c.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/I2CSlave/CMakeLists.txt b/drivers/tests/UNITTESTS/I2CSlave/CMakeLists.txt new file mode 100644 index 00000000000..a78563b284f --- /dev/null +++ b/drivers/tests/UNITTESTS/I2CSlave/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME i2cslave-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_I2C + DEVICE_I2CSLAVE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/I2CSlave.cpp + test_i2cslave.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/I2CSlave/test_i2cslave.cpp b/drivers/tests/UNITTESTS/I2CSlave/test_i2cslave.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/I2CSlave/test_i2cslave.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/InterruptIn/CMakeLists.txt b/drivers/tests/UNITTESTS/InterruptIn/CMakeLists.txt new file mode 100644 index 00000000000..bd5f5c7760a --- /dev/null +++ b/drivers/tests/UNITTESTS/InterruptIn/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME interruptin-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_INTERRUPTIN +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/InterruptIn.cpp + test_interruptin.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-hal + mbed-headers-platform + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/InterruptIn/test_interruptin.cpp b/drivers/tests/UNITTESTS/InterruptIn/test_interruptin.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/InterruptIn/test_interruptin.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/MbedCRC/CMakeLists.txt b/drivers/tests/UNITTESTS/MbedCRC/CMakeLists.txt new file mode 100644 index 00000000000..9fd70021877 --- /dev/null +++ b/drivers/tests/UNITTESTS/MbedCRC/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME mbedcrc-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_CRC + MBED_CRC_TABLE_SIZE=0 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/MbedCRC.cpp + test_mbedcrc.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/MbedCRC/test_mbedcrc.cpp b/drivers/tests/UNITTESTS/MbedCRC/test_mbedcrc.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/MbedCRC/test_mbedcrc.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/OSPI/CMakeLists.txt b/drivers/tests/UNITTESTS/OSPI/CMakeLists.txt new file mode 100644 index 00000000000..e8383ca97db --- /dev/null +++ b/drivers/tests/UNITTESTS/OSPI/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME ospi-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_OSPI +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/OSPI.cpp + test_ospi.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-hal + mbed-headers-platform + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/OSPI/test_ospi.cpp b/drivers/tests/UNITTESTS/OSPI/test_ospi.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/OSPI/test_ospi.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/PortIn/CMakeLists.txt b/drivers/tests/UNITTESTS/PortIn/CMakeLists.txt new file mode 100644 index 00000000000..ee3554112bf --- /dev/null +++ b/drivers/tests/UNITTESTS/PortIn/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME portin-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_PORTIN +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/PortIn.cpp + test_portin.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/PortIn/test_portin.cpp b/drivers/tests/UNITTESTS/PortIn/test_portin.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/PortIn/test_portin.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/PortInOut/CMakeLists.txt b/drivers/tests/UNITTESTS/PortInOut/CMakeLists.txt new file mode 100644 index 00000000000..947815b83fc --- /dev/null +++ b/drivers/tests/UNITTESTS/PortInOut/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME portinout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_PORTIN + DEVICE_PORTINOUT + DEVICE_PORTOUT +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/PortInOut.cpp + test_portinout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/PortInOut/test_portinout.cpp b/drivers/tests/UNITTESTS/PortInOut/test_portinout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/PortInOut/test_portinout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/PortOut/CMakeLists.txt b/drivers/tests/UNITTESTS/PortOut/CMakeLists.txt new file mode 100644 index 00000000000..e4a29ad789a --- /dev/null +++ b/drivers/tests/UNITTESTS/PortOut/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME portout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_PORTOUT +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/PortOut.cpp + test_portout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/PortOut/test_portout.cpp b/drivers/tests/UNITTESTS/PortOut/test_portout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/PortOut/test_portout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/QSPI/CMakeLists.txt b/drivers/tests/UNITTESTS/QSPI/CMakeLists.txt new file mode 100644 index 00000000000..53aea5f8490 --- /dev/null +++ b/drivers/tests/UNITTESTS/QSPI/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME qspi-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_QSPI +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/QSPI.cpp + test_qspi.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/QSPI/test_qspi.cpp b/drivers/tests/UNITTESTS/QSPI/test_qspi.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/QSPI/test_qspi.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/ResetReason/CMakeLists.txt b/drivers/tests/UNITTESTS/ResetReason/CMakeLists.txt new file mode 100644 index 00000000000..d319af606d1 --- /dev/null +++ b/drivers/tests/UNITTESTS/ResetReason/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME resetreason-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_RESETREASON +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/ResetReason.cpp + test_resetreason.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-drivers +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/ResetReason/test_resetreason.cpp b/drivers/tests/UNITTESTS/ResetReason/test_resetreason.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/ResetReason/test_resetreason.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/SPI/CMakeLists.txt b/drivers/tests/UNITTESTS/SPI/CMakeLists.txt new file mode 100644 index 00000000000..7544a73b0e5 --- /dev/null +++ b/drivers/tests/UNITTESTS/SPI/CMakeLists.txt @@ -0,0 +1,33 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME spi-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SPI + DEVICE_SPI_COUNT + DEVICE_SPI_ASYNCH + TRANSACTION_QUEUE_SIZE_SPI +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/SPI.cpp + test_spi.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-platform + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/SPI/test_spi.cpp b/drivers/tests/UNITTESTS/SPI/test_spi.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/SPI/test_spi.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/SPISlave/CMakeLists.txt b/drivers/tests/UNITTESTS/SPISlave/CMakeLists.txt new file mode 100644 index 00000000000..d5781cdf80b --- /dev/null +++ b/drivers/tests/UNITTESTS/SPISlave/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME spislave-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SPI_SLAVE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/SPISlave.cpp + test_spislave.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/SPISlave/test_spislave.cpp b/drivers/tests/UNITTESTS/SPISlave/test_spislave.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/SPISlave/test_spislave.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/SerialBase/CMakeLists.txt b/drivers/tests/UNITTESTS/SerialBase/CMakeLists.txt new file mode 100644 index 00000000000..2f75764236e --- /dev/null +++ b/drivers/tests/UNITTESTS/SerialBase/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME serialbase-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL + DEVICE_SERIAL_FC + DEVICE_SERIAL_ASYNCH +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/SerialBase.cpp + test_serialbase.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/SerialBase/test_serialbase.cpp b/drivers/tests/UNITTESTS/SerialBase/test_serialbase.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/SerialBase/test_serialbase.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/SerialWireOutput/CMakeLists.txt b/drivers/tests/UNITTESTS/SerialWireOutput/CMakeLists.txt new file mode 100644 index 00000000000..4e738669aae --- /dev/null +++ b/drivers/tests/UNITTESTS/SerialWireOutput/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME serialwireoutput-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_ITM +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/SerialWireOutput.cpp + test_serialwireoutput.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/SerialWireOutput/test_serialwireoutput.cpp b/drivers/tests/UNITTESTS/SerialWireOutput/test_serialwireoutput.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/SerialWireOutput/test_serialwireoutput.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/Ticker/CMakeLists.txt b/drivers/tests/UNITTESTS/Ticker/CMakeLists.txt new file mode 100644 index 00000000000..2984fc76347 --- /dev/null +++ b/drivers/tests/UNITTESTS/Ticker/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME ticker-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_LPTICKER +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/Ticker.cpp + test_ticker.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform + mbed-stubs-drivers +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/Ticker/test_ticker.cpp b/drivers/tests/UNITTESTS/Ticker/test_ticker.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/Ticker/test_ticker.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/Timeout/CMakeLists.txt b/drivers/tests/UNITTESTS/Timeout/CMakeLists.txt new file mode 100644 index 00000000000..b9db63b629d --- /dev/null +++ b/drivers/tests/UNITTESTS/Timeout/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME timeout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/Timeout.cpp + ${mbed-os_SOURCE_DIR}/drivers/source/Ticker.cpp + test_timeout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-drivers + mbed-headers-platform + mbed-headers-hal + mbed-stubs-drivers + mbed-stubs-platform + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/Timeout/test_timeout.cpp b/drivers/tests/UNITTESTS/Timeout/test_timeout.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/Timeout/test_timeout.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/Timer/CMakeLists.txt b/drivers/tests/UNITTESTS/Timer/CMakeLists.txt new file mode 100644 index 00000000000..c0ac369d90d --- /dev/null +++ b/drivers/tests/UNITTESTS/Timer/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME analogin-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_ANALOGIN + MBED_CONF_TARGET_DEFAULT_ADC_VREF=3.3f +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/AnalogIn.cpp + test_analogin.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/Timer/test_timer.cpp b/drivers/tests/UNITTESTS/Timer/test_timer.cpp new file mode 100644 index 00000000000..813f3c485ed --- /dev/null +++ b/drivers/tests/UNITTESTS/Timer/test_timer.cpp @@ -0,0 +1,30 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() { + return 0; +} diff --git a/drivers/tests/UNITTESTS/TimerEvent/CMakeLists.txt b/drivers/tests/UNITTESTS/TimerEvent/CMakeLists.txt new file mode 100644 index 00000000000..f6b6ecb0274 --- /dev/null +++ b/drivers/tests/UNITTESTS/TimerEvent/CMakeLists.txt @@ -0,0 +1,28 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME timerevent-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/TimerEvent.cpp + test_timerevent.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/TimerEvent/test_timerevent.cpp b/drivers/tests/UNITTESTS/TimerEvent/test_timerevent.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/TimerEvent/test_timerevent.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/UnbufferedSerial/CMakeLists.txt b/drivers/tests/UNITTESTS/UnbufferedSerial/CMakeLists.txt new file mode 100644 index 00000000000..7defd055f7b --- /dev/null +++ b/drivers/tests/UNITTESTS/UnbufferedSerial/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(GoogleTest) + +set(TEST_NAME unbufferedserial-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL + DEVICE_SERIAL_FC + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/UnbufferedSerial.cpp + test_unbufferedserial.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-drivers + mbed-stubs-platform +) + +gtest_discover_tests(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/UnbufferedSerial/test_unbufferedserial.cpp b/drivers/tests/UNITTESTS/UnbufferedSerial/test_unbufferedserial.cpp new file mode 100644 index 00000000000..d089b5a4c12 --- /dev/null +++ b/drivers/tests/UNITTESTS/UnbufferedSerial/test_unbufferedserial.cpp @@ -0,0 +1,31 @@ +/* Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* This empty test file is present in order to generate coverage data for the + * corresponding source file. This file allows an executable CMake target to be + * created, which builds the corresponding source file and produces a .gcno + * file to be used by a coverage tool. + * + * Replace this main function with Google Test tests, as described in the + * Mbed OS documentation: + * + * https://os.mbed.com/docs/mbed-os/latest/debug-test/unit-testing.html + * + */ +int main() +{ + return 0; +} diff --git a/drivers/tests/UNITTESTS/doubles/CMakeLists.txt b/drivers/tests/UNITTESTS/doubles/CMakeLists.txt index 042d02c8b3a..e75b5192039 100644 --- a/drivers/tests/UNITTESTS/doubles/CMakeLists.txt +++ b/drivers/tests/UNITTESTS/doubles/CMakeLists.txt @@ -5,7 +5,6 @@ add_library(mbed-headers-drivers INTERFACE) target_include_directories(mbed-headers-drivers INTERFACE - . ${mbed-os_SOURCE_DIR}/drivers ${mbed-os_SOURCE_DIR}/drivers/include ${mbed-os_SOURCE_DIR}/drivers/include/drivers @@ -13,15 +12,25 @@ target_include_directories(mbed-headers-drivers add_library(mbed-stubs-drivers) +target_include_directories(mbed-stubs-drivers + PUBLIC + . +) + target_sources(mbed-stubs-drivers PRIVATE BufferedSerial_stub.cpp SerialBase_stub.cpp + InterruptIn_stub.cpp + DigitalIn_stub.cpp + DigitalInOut_stub.cpp + TimerEvent_stub.cpp ) target_compile_definitions(mbed-stubs-drivers PRIVATE DEVICE_SERIAL=1 + DEVICE_SERIAL_FC=1 DEVICE_INTERRUPTIN=1 MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 ) diff --git a/drivers/tests/UNITTESTS/doubles/DigitalInOut_stub.cpp b/drivers/tests/UNITTESTS/doubles/DigitalInOut_stub.cpp new file mode 100644 index 00000000000..ef8cb891871 --- /dev/null +++ b/drivers/tests/UNITTESTS/doubles/DigitalInOut_stub.cpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drivers/DigitalInOut.h" + +namespace mbed { + +void DigitalInOut::output() +{ +} + +void DigitalInOut::input() +{ +} + +void DigitalInOut::mode(PinMode pull) +{ +} + +} // namespace mbed diff --git a/drivers/tests/UNITTESTS/doubles/DigitalIn_stub.cpp b/drivers/tests/UNITTESTS/doubles/DigitalIn_stub.cpp new file mode 100644 index 00000000000..8e60d045dc8 --- /dev/null +++ b/drivers/tests/UNITTESTS/doubles/DigitalIn_stub.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drivers/DigitalIn.h" + +namespace mbed { + +void DigitalIn::mode(PinMode pull) +{ +} + +} // namespace mbed diff --git a/drivers/tests/UNITTESTS/doubles/InterruptIn_stub.cpp b/drivers/tests/UNITTESTS/doubles/InterruptIn_stub.cpp new file mode 100644 index 00000000000..5e18f8076cc --- /dev/null +++ b/drivers/tests/UNITTESTS/doubles/InterruptIn_stub.cpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2021, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drivers/InterruptIn.h" + +namespace mbed { + + +InterruptIn::InterruptIn(PinName pin) : gpio(), gpio_irq(), _rise(), _fall() +{ +} + +InterruptIn::~InterruptIn() +{ +} + +int InterruptIn::read() +{ + return 0; +} + +void InterruptIn::rise(Callback func) +{ +} + +void InterruptIn::fall(Callback func) +{ +} + +} // namespace mbed diff --git a/drivers/tests/UNITTESTS/doubles/SerialBase_stub.cpp b/drivers/tests/UNITTESTS/doubles/SerialBase_stub.cpp index 67c31d96396..ac1d34643dc 100644 --- a/drivers/tests/UNITTESTS/doubles/SerialBase_stub.cpp +++ b/drivers/tests/UNITTESTS/doubles/SerialBase_stub.cpp @@ -24,6 +24,14 @@ SerialBase::SerialBase(PinName tx, PinName rx, int baud) : { } +SerialBase::SerialBase(const serial_pinmap_t &static_pinmap, int baud) : + _baud(baud), + _tx_pin(static_pinmap.tx_pin), + _rx_pin(static_pinmap.rx_pin), + _static_pinmap(&static_pinmap) +{ +} + SerialBase::~SerialBase() { @@ -52,7 +60,7 @@ void SerialBase::attach(Callback func, IrqType type) { } -void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) +void SerialBase::_irq_handler(uintptr_t context, SerialIrq irq_type) { } @@ -66,6 +74,14 @@ int SerialBase::_base_putc(int c) return 0; } +void SerialBase::enable_input(bool enable) +{ +} + +void SerialBase::enable_output(bool enable) +{ +} + void SerialBase::send_break() { } @@ -78,4 +94,10 @@ void SerialBase:: unlock() { } +#if DEVICE_SERIAL_FC +void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) +{ +} +#endif // DEVICE_SERIAL_FC + } diff --git a/drivers/tests/UNITTESTS/doubles/TimerEvent_stub.cpp b/drivers/tests/UNITTESTS/doubles/TimerEvent_stub.cpp new file mode 100644 index 00000000000..dfe6a3ac691 --- /dev/null +++ b/drivers/tests/UNITTESTS/doubles/TimerEvent_stub.cpp @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2021, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "drivers/TimerEvent.h" + +using namespace std::chrono; + +namespace mbed { + +TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) +{ +} + +TimerEvent::~TimerEvent() +{ +} + +void TimerEvent::insert_absolute(TickerDataClock::time_point timestamp) +{ +} + +void TimerEvent::remove() +{ +} + +} // namespace mbed diff --git a/hal/include/hal/can_api.h b/hal/include/hal/can_api.h index 9774d12b386..61d96441d75 100644 --- a/hal/include/hal/can_api.h +++ b/hal/include/hal/can_api.h @@ -63,7 +63,7 @@ typedef struct { int td_function; } can_pinmap_t; -typedef void (*can_irq_handler)(uint32_t id, CanIrqType type); +typedef void (*can_irq_handler)(uintptr_t context, CanIrqType type); typedef struct can_s can_t; @@ -74,7 +74,7 @@ void can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int h void can_free(can_t *obj); int can_frequency(can_t *obj, int hz); -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id); +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context); void can_irq_free(can_t *obj); void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable); diff --git a/hal/include/hal/gpio_irq_api.h b/hal/include/hal/gpio_irq_api.h index e08b049c55c..cb9a40d5c2a 100644 --- a/hal/include/hal/gpio_irq_api.h +++ b/hal/include/hal/gpio_irq_api.h @@ -41,7 +41,7 @@ typedef enum { */ typedef struct gpio_irq_s gpio_irq_t; -typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); +typedef void (*gpio_irq_handler)(uintptr_t context, gpio_irq_event event); /** * \defgroup hal_gpioirq GPIO IRQ HAL functions @@ -75,10 +75,10 @@ typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) + * @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id); +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context); /** Release the GPIO IRQ PIN * diff --git a/hal/include/hal/ospi_api.h b/hal/include/hal/ospi_api.h index fd9f6513213..ff4c7e1916f 100644 --- a/hal/include/hal/ospi_api.h +++ b/hal/include/hal/ospi_api.h @@ -23,6 +23,7 @@ #include "device.h" #include "pinmap.h" #include +#include #if DEVICE_OSPI diff --git a/hal/include/hal/qspi_api.h b/hal/include/hal/qspi_api.h index f753de2c38b..5bc582772b3 100644 --- a/hal/include/hal/qspi_api.h +++ b/hal/include/hal/qspi_api.h @@ -22,6 +22,7 @@ #include "device.h" #include "pinmap.h" +#include #include #if DEVICE_QSPI diff --git a/hal/include/hal/serial_api.h b/hal/include/hal/serial_api.h index 78a1ee8aa40..b57251f7f69 100644 --- a/hal/include/hal/serial_api.h +++ b/hal/include/hal/serial_api.h @@ -84,7 +84,7 @@ typedef enum { FlowControlRTSCTS } FlowControl; -typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event); +typedef void (*uart_irq_handler)(uintptr_t context, SerialIrq event); #if DEVICE_SERIAL_ASYNCH /** Asynch serial HAL structure @@ -256,9 +256,9 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * * @param obj The serial object * @param handler The interrupt handler which will be invoked when the interrupt fires - * @param id The SerialBase object + * @param context The SerialBase object */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id); +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context); /** Configure serial interrupt. This function is used for word-approach * diff --git a/hal/include/hal/ticker_api.h b/hal/include/hal/ticker_api.h index ade060fb9cb..cb748d8b78b 100644 --- a/hal/include/hal/ticker_api.h +++ b/hal/include/hal/ticker_api.h @@ -42,11 +42,11 @@ typedef uint64_t us_timestamp_t; */ typedef struct ticker_event_s { us_timestamp_t timestamp; /**< Event's timestamp */ - uint32_t id; /**< TimerEvent object */ + uintptr_t id; /**< TimerEvent object */ struct ticker_event_s *next; /**< Next event in the queue */ } ticker_event_t; -typedef void (*ticker_event_handler)(uint32_t id); +typedef void (*ticker_event_handler)(uintptr_t id); /** Information about the ticker implementation */ @@ -193,7 +193,7 @@ void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj) * @param timestamp The event's timestamp * @param id The event object */ -void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id); +void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uintptr_t id); /** Insert an event to the queue * @@ -208,7 +208,7 @@ void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, * @param timestamp The event's timestamp * @param id The event object */ -void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id); +void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uintptr_t id); /** Read the current (relative) ticker's timestamp * diff --git a/hal/source/mbed_ticker_api.c b/hal/source/mbed_ticker_api.c index 999e464fccd..fba65375170 100644 --- a/hal/source/mbed_ticker_api.c +++ b/hal/source/mbed_ticker_api.c @@ -366,7 +366,7 @@ static timestamp_t compute_tick_round_up(const ticker_data_t *const ticker, us_t } //NOTE: Must be called from critical section! -static void insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id) +static void insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uintptr_t id) { ticker_event_queue_t *queue = ticker->queue; @@ -521,7 +521,7 @@ void ticker_irq_handler(const ticker_data_t *const ticker) } -void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) +void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uintptr_t id) { core_util_critical_section_enter(); @@ -537,7 +537,7 @@ void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, core_util_critical_section_exit(); } -void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id) +void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uintptr_t id) { core_util_critical_section_enter(); diff --git a/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp b/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp index 08d99814b8c..5848493f8bc 100644 --- a/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp +++ b/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/gpio_irq/main.cpp @@ -40,7 +40,7 @@ using namespace utest::v1; MbedTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins()); static volatile uint32_t call_counter; -void test_gpio_irq_handler(uint32_t id, gpio_irq_event event) +void test_gpio_irq_handler(uintptr_t context, gpio_irq_event event) { call_counter++; } @@ -63,8 +63,8 @@ void fpga_gpio_irq_test(PinName pin) gpio_init_in(&gpio, pin); gpio_irq_t gpio_irq; - uint32_t id = 123; - TEST_ASSERT_EQUAL(0, gpio_irq_init(&gpio_irq, pin, test_gpio_irq_handler, id)); + uintptr_t context = 123; + TEST_ASSERT_EQUAL(0, gpio_irq_init(&gpio_irq, pin, test_gpio_irq_handler, context)); gpio_irq_set(&gpio_irq, IRQ_RISE, true); gpio_irq_enable(&gpio_irq); diff --git a/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp b/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp index 3719f035447..6afd6836bf3 100644 --- a/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp +++ b/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp @@ -59,9 +59,9 @@ typedef struct { uint32_t tx_cnt; } serial_test_data_t; -static void test_irq_handler(uint32_t id, SerialIrq event) +static void test_irq_handler(uintptr_t context, SerialIrq event) { - serial_test_data_t *td = (serial_test_data_t *)id; + serial_test_data_t *td = (serial_test_data_t *)context; int c = 0x01; // arbitrary, non-zero value if (event == RxIrq) { c = serial_getc(td->ser); @@ -243,7 +243,7 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i TEST_ASSERT_EQUAL(tester_buff, rx_buff[i]); } - serial_irq_handler(&serial, test_irq_handler, (uint32_t) &td); + serial_irq_handler(&serial, test_irq_handler, reinterpret_cast(&td)); // DUT TX (IRQ) / FPGA RX tx_val = rand() % ((1 << test_buff_bits) - PUTC_REPS); diff --git a/hal/tests/TESTS/pin_names/arduino_uno/main.cpp b/hal/tests/TESTS/pin_names/arduino_uno/main.cpp index c9be5e9759d..8022d507bc9 100644 --- a/hal/tests/TESTS/pin_names/arduino_uno/main.cpp +++ b/hal/tests/TESTS/pin_names/arduino_uno/main.cpp @@ -155,7 +155,9 @@ void UART_test() // 3. check if Arduino_uno pins are not using the same UART instance as console int console_uart = pinmap_peripheral(CONSOLE_TX, serial_tx_pinmap()); - TEST_ASSERT_NOT_EQUAL(console_uart, pinmap_peripheral(TX_pin, serial_tx_pinmap())); + if (console_uart != 0) { + TEST_ASSERT_NOT_EQUAL(console_uart, pinmap_peripheral(TX_pin, serial_tx_pinmap())); + } // 4. check if UART pins can be initialized BufferedSerial TEST(TX_pin, RX_pin); diff --git a/hal/tests/UNITTESTS/doubles/CMakeLists.txt b/hal/tests/UNITTESTS/doubles/CMakeLists.txt index dd0f3faf079..dfd0c393ad1 100644 --- a/hal/tests/UNITTESTS/doubles/CMakeLists.txt +++ b/hal/tests/UNITTESTS/doubles/CMakeLists.txt @@ -18,6 +18,26 @@ target_compile_definitions(mbed-stubs-hal DEVICE_WATCHDOG MBED_WDOG_ASSERT=1 DEVICE_ANALOGIN + DEVICE_ANALOGOUT + DEVICE_FLASH + DEVICE_I2C + DEVICE_I2C_ASYNCH + DEVICE_I2CSLAVE + DEVICE_CAN + DEVICE_INTERRUPTIN + DEVICE_CRC + DEVICE_OSPI + DEVICE_PORTIN + DEVICE_PORTOUT + DEVICE_QSPI + DEVICE_SPI + DEVICE_SPI_COUNT + DEVICE_SPI_ASYNCH + DEVICE_SERIAL + DEVICE_SERIAL_ASYNCH + DEVICE_SERIAL_FC + DEVICE_ITM + DEVICE_LPTICKER ) target_sources(mbed-stubs-hal @@ -26,6 +46,20 @@ target_sources(mbed-stubs-hal us_ticker_stub.cpp watchdog_api_stub.c analogin_api_stub.c + analogout_api_stub.c + gpio_api_stub.c + flash_api_stub.c + i2c_api_stub.c + can_api_stub.c + gpio_irq_api_stub.c + ospi_api_stub.c + port_api_stub.c + qspi_api_stub.c + spi_api_stub.c + serial_api_stub.c + itm_api_stub.c + ticker_api_stub.c + lp_ticker_api_stub.c ) target_link_libraries(mbed-stubs-hal diff --git a/hal/tests/UNITTESTS/doubles/PeripheralNames.h b/hal/tests/UNITTESTS/doubles/PeripheralNames.h index 3ca0e7b53ed..4103d767915 100644 --- a/hal/tests/UNITTESTS/doubles/PeripheralNames.h +++ b/hal/tests/UNITTESTS/doubles/PeripheralNames.h @@ -18,4 +18,8 @@ #ifndef MBED_PERIPHERALNAMES_H #define MBED_PERIPHERALNAMES_H +typedef enum { + SPI_1, +} SPIName; + #endif diff --git a/hal/tests/UNITTESTS/doubles/analogout_api_stub.c b/hal/tests/UNITTESTS/doubles/analogout_api_stub.c new file mode 100644 index 00000000000..8e34161186e --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/analogout_api_stub.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/analogout_api.h" +#include + +#if DEVICE_ANALOGOUT + +void analogout_init_direct(dac_t *obj, const PinMap *pinmap) +{ +} + +void analogout_init(dac_t *obj, PinName pin) +{ +} + +void analogout_free(dac_t *obj) +{ +} + +void analogout_write(dac_t *obj, float value) +{ +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ +} + +float analogout_read(dac_t *obj) +{ + return 0; +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + return 0; +} + +const PinMap *analogout_pinmap(void) +{ + return NULL; +} + +#endif // DEVICE_ANALOGOUT diff --git a/hal/tests/UNITTESTS/doubles/can_api_stub.c b/hal/tests/UNITTESTS/doubles/can_api_stub.c new file mode 100644 index 00000000000..8363b90c03a --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/can_api_stub.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/can_api.h" + +#if DEVICE_CAN + +void can_init(can_t *obj, PinName rd, PinName td) +{ +} + +void can_init_direct(can_t *obj, const can_pinmap_t *pinmap) +{ +} + +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) +{ +} + +void can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz) +{ +} + +void can_free(can_t *obj) +{ +} + +int can_frequency(can_t *obj, int hz) +{ + return 0; +} + +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t id) +{ +} + +void can_irq_free(can_t *obj) +{ +} + +void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) +{ +} + +int can_write(can_t *obj, CAN_Message msg, int cc) +{ + return 0; +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) +{ + return 0; +} + +int can_mode(can_t *obj, CanMode mode) +{ + return 0; +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ + return 0; +} + +void can_reset(can_t *obj) +{ +} + +unsigned char can_rderror(can_t *obj) +{ + return 0; +} + +unsigned char can_tderror(can_t *obj) +{ + return 0; +} + +void can_monitor(can_t *obj, int silent) +{ +} + +#endif // DEVICE_CAN diff --git a/hal/tests/UNITTESTS/doubles/device.h b/hal/tests/UNITTESTS/doubles/device.h index c052aa04bde..feb49358596 100644 --- a/hal/tests/UNITTESTS/doubles/device.h +++ b/hal/tests/UNITTESTS/doubles/device.h @@ -21,4 +21,8 @@ #include "objects.h" #include "PinNames.h" +#if DEVICE_CRC +#define HAL_CRC_IS_SUPPORTED(polynomial, width) false +#endif // DEVICE_CRC + #endif diff --git a/hal/tests/UNITTESTS/doubles/flash_api_stub.c b/hal/tests/UNITTESTS/doubles/flash_api_stub.c new file mode 100644 index 00000000000..c320cbc1893 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/flash_api_stub.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/flash_api.h" + +#if DEVICE_FLASH + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + return 0; +} + +int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + return 0; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + return 0; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + return 0; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return 0; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return 0; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return 0; +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + return 0; +} + +#endif // DEVICE_FLASH diff --git a/hal/tests/UNITTESTS/doubles/gpio_api_stub.c b/hal/tests/UNITTESTS/doubles/gpio_api_stub.c new file mode 100644 index 00000000000..8ac8f7d69bb --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/gpio_api_stub.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/gpio_api.h" + +#if DEVICE_INTERRUPTIN + +int gpio_is_connected(const gpio_t *obj) +{ + return 0; +} + +void gpio_free(gpio_t *obj) +{ +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ +} + +void gpio_write(gpio_t *obj, int value) +{ +} + +int gpio_read(gpio_t *obj) +{ + return 0; +} + +void gpio_init_in(gpio_t *gpio, PinName pin) +{ +} + +void gpio_init_in_ex(gpio_t *gpio, PinName pin, PinMode mode) +{ +} + +void gpio_init_out(gpio_t *gpio, PinName pin) +{ +} + +void gpio_init_out_ex(gpio_t *gpio, PinName pin, int value) +{ +} + +void gpio_init_inout(gpio_t *gpio, PinName pin, PinDirection direction, PinMode mode, int value) +{ +} + +#endif // DEVICE_INTERRUPTIN diff --git a/hal/tests/UNITTESTS/doubles/gpio_irq_api_stub.c b/hal/tests/UNITTESTS/doubles/gpio_irq_api_stub.c new file mode 100644 index 00000000000..ee15d4cd136 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/gpio_irq_api_stub.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/gpio_irq_api.h" + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) +{ + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ +} diff --git a/hal/tests/UNITTESTS/doubles/i2c_api_stub.c b/hal/tests/UNITTESTS/doubles/i2c_api_stub.c new file mode 100644 index 00000000000..b1ab77a4211 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/i2c_api_stub.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/i2c_api.h" + +#if DEVICE_I2C + +void i2c_init_direct(i2c_t *obj, const i2c_pinmap_t *pinmap) +{ +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ +} + +void i2c_frequency(i2c_t *obj, int hz) +{ +} + +int i2c_start(i2c_t *obj) +{ + return 0; +} + +int i2c_stop(i2c_t *obj) +{ + return 0; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + return 0; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + return 0; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + return 0; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + return 0; +} + +#if DEVICE_I2CSLAVE + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ +} + +int i2c_slave_receive(i2c_t *obj) +{ + return 0; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + return 0; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + return 0; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ +} + +#endif // DEVICE_I2CSLAVE + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + return 0; +} + +uint8_t i2c_active(i2c_t *obj) +{ + return 0; +} + +void i2c_abort_asynch(i2c_t *obj) +{ +} + +#endif // DEVICE_I2C_ASYNCH + +#endif // DEVICE_I2C diff --git a/hal/tests/UNITTESTS/doubles/itm_api_stub.c b/hal/tests/UNITTESTS/doubles/itm_api_stub.c new file mode 100644 index 00000000000..9ea9677d639 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/itm_api_stub.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/itm_api.h" + +#if DEVICE_ITM + +void mbed_itm_init(void) +{ +} + +void mbed_itm_send_block(uint32_t port, const void *data, size_t len) +{ +} + +#endif // DEVICE_ITM diff --git a/hal/tests/UNITTESTS/doubles/lp_ticker_api_stub.c b/hal/tests/UNITTESTS/doubles/lp_ticker_api_stub.c new file mode 100644 index 00000000000..46a337f6ca9 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/lp_ticker_api_stub.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2022 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "hal/lp_ticker_api.h" + +#include + +#if DEVICE_LPTICKER + +const ticker_data_t *get_lp_ticker_data(void) +{ + return NULL; +} + +#endif // DEVICE_LPTICKER diff --git a/hal/tests/UNITTESTS/doubles/objects.h b/hal/tests/UNITTESTS/doubles/objects.h index 23a634db262..da05cdabb7c 100644 --- a/hal/tests/UNITTESTS/doubles/objects.h +++ b/hal/tests/UNITTESTS/doubles/objects.h @@ -70,6 +70,10 @@ struct can_s { int unused; }; +struct ospi_s { + int unused; +}; + #include "gpio_object.h" #ifdef __cplusplus diff --git a/hal/tests/UNITTESTS/doubles/ospi_api_stub.c b/hal/tests/UNITTESTS/doubles/ospi_api_stub.c new file mode 100644 index 00000000000..46ae654971b --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/ospi_api_stub.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/ospi_api.h" + +#if DEVICE_OSPI + +ospi_status_t ospi_command_transfer(ospi_t *obj, const ospi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size) +{ + return OSPI_STATUS_OK; +} + +ospi_status_t ospi_frequency(ospi_t *obj, int hz) +{ + return OSPI_STATUS_OK; +} + +ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName io4, PinName io5, PinName io6, PinName io7, + PinName sclk, PinName ssel, PinName dqs, uint32_t hz, uint8_t mode) +{ + return OSPI_STATUS_OK; +} + +ospi_status_t ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, uint32_t hz, uint8_t mode) +{ + return OSPI_STATUS_OK; +} + +ospi_status_t ospi_read(ospi_t *obj, const ospi_command_t *command, void *data, size_t *length) +{ + return OSPI_STATUS_OK; +} + +ospi_status_t ospi_write(ospi_t *obj, const ospi_command_t *command, const void *data, size_t *length) +{ + return OSPI_STATUS_OK; +} + +#endif // DEVICE_OSPI diff --git a/hal/tests/UNITTESTS/doubles/port_api_stub.c b/hal/tests/UNITTESTS/doubles/port_api_stub.c new file mode 100644 index 00000000000..b424af5b3c4 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/port_api_stub.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/port_api.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT + +PinName port_pin(PortName port, int pin_n) +{ + return NC; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ +} + +void port_mode(port_t *obj, PinMode mode) +{ +} + +void port_dir(port_t *obj, PinDirection dir) +{ +} + +void port_write(port_t *obj, int value) +{ +} + +int port_read(port_t *obj) +{ + return 0; +} + +#endif // DEVICE_PORTIN || DEVICE_PORTOUT diff --git a/hal/tests/UNITTESTS/doubles/qspi_api_stub.c b/hal/tests/UNITTESTS/doubles/qspi_api_stub.c new file mode 100644 index 00000000000..5d141b5d9e7 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/qspi_api_stub.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/qspi_api.h" + +#if DEVICE_QSPI + +qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode) +{ + return QSPI_STATUS_OK; +} + +qspi_status_t qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, uint32_t hz, uint8_t mode) +{ + return QSPI_STATUS_OK; +} + +qspi_status_t qspi_free(qspi_t *obj) +{ + return QSPI_STATUS_OK; +} + +qspi_status_t qspi_frequency(qspi_t *obj, int hz) +{ + return QSPI_STATUS_OK; +} + +qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length) +{ + return QSPI_STATUS_OK; +} + +qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size) +{ + return QSPI_STATUS_OK; +} + +qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length) +{ + return QSPI_STATUS_OK; +} + +const PinMap *qspi_master_sclk_pinmap(void) +{ + return NULL; +} + +const PinMap *qspi_master_ssel_pinmap(void) +{ + return NULL; +} + +const PinMap *qspi_master_data0_pinmap(void) +{ + return NULL; +} + +const PinMap *qspi_master_data1_pinmap(void) +{ + return NULL; +} + +const PinMap *qspi_master_data2_pinmap(void) +{ + return NULL; +} + +const PinMap *qspi_master_data3_pinmap(void) +{ + return NULL; +} + +#endif // DEVICE_QSPI diff --git a/hal/tests/UNITTESTS/doubles/serial_api_stub.c b/hal/tests/UNITTESTS/doubles/serial_api_stub.c new file mode 100644 index 00000000000..7c8b06859f1 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/serial_api_stub.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/serial_api.h" + +#if DEVICE_SERIAL + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ +} + +void serial_init_direct(serial_t *obj, const serial_pinmap_t *pinmap) +{ +} + +void serial_free(serial_t *obj) +{ +} + +void serial_baud(serial_t *obj, int baudrate) +{ +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) +{ +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ +} + +int serial_getc(serial_t *obj) +{ + return 0; +} + +void serial_putc(serial_t *obj, int c) +{ +} + +int serial_readable(serial_t *obj) +{ + return 0; +} + +int serial_writable(serial_t *obj) +{ + return 0; +} + +void serial_clear(serial_t *obj) +{ +} + +void serial_break_set(serial_t *obj) +{ +} + +void serial_break_clear(serial_t *obj) +{ +} + +void serial_pinout_tx(PinName tx) +{ +} + +#if DEVICE_SERIAL_FC +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ +} + +void serial_set_flow_control_direct(serial_t *obj, FlowControl type, const serial_fc_pinmap_t *pinmap) +{ +} +#endif // DEVICE_SERIAL_FC + +const PinMap *serial_tx_pinmap(void) +{ + return NULL; +} + +const PinMap *serial_rx_pinmap(void) +{ + return NULL; +} + +#if DEVICE_SERIAL_FC +const PinMap *serial_cts_pinmap(void) +{ + return NULL; +} + +const PinMap *serial_rts_pinmap(void) +{ + return NULL; +} +#endif // DEVICE_SERIAL_FC + +#if DEVICE_SERIAL_ASYNCH +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + return 0; +} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ +} + +uint8_t serial_tx_active(serial_t *obj) +{ + return 0; +} + +uint8_t serial_rx_active(serial_t *obj) +{ + return 0; +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + return 0; +} + +void serial_tx_abort_asynch(serial_t *obj) +{ +} + +void serial_rx_abort_asynch(serial_t *obj) +{ +} +#endif // DEVICE_SERIAL_ASYNCH + +#endif // DEVICE_SERIAL diff --git a/hal/tests/UNITTESTS/doubles/spi_api_stub.c b/hal/tests/UNITTESTS/doubles/spi_api_stub.c new file mode 100644 index 00000000000..53c16371f59 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/spi_api_stub.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2021 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "hal/spi_api.h" + +#if DEVICE_SPI + +#ifdef DEVICE_SPI_COUNT +SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName mclk) +{ + return (SPIName)NC; + +} +#endif // DEVICE_SPI_COUNT + +void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap) +{ +} + +void spi_init_direct(spi_t *obj, const spi_pinmap_t *pinmap) +{ +} + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ +} + +void spi_free(spi_t *obj) +{ +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ +} + +void spi_frequency(spi_t *obj, int hz) +{ +} + +int spi_master_write(spi_t *obj, int value) +{ + return 0; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + return 0; +} + +int spi_slave_receive(spi_t *obj) +{ + return 0; +} + +int spi_slave_read(spi_t *obj) +{ + return 0; +} + +void spi_slave_write(spi_t *obj, int value) +{ +} + +int spi_busy(spi_t *obj) +{ + return 0; +} + +uint8_t spi_get_module(spi_t *obj) +{ + return 0; +} + +const PinMap *spi_master_mosi_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_master_miso_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_master_clk_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_master_cs_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_slave_mosi_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_slave_miso_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_slave_clk_pinmap(void) +{ + return NULL; +} + +const PinMap *spi_slave_cs_pinmap(void) +{ + return NULL; +} + +#if DEVICE_SPI_ASYNCH +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ +} + +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + return 0; +} + +uint8_t spi_active(spi_t *obj) +{ + return 0; +} +void spi_abort_asynch(spi_t *obj) +{ +} +#endif // DEVICE_SPI_ASYNCH + +#endif // DEVICE_SPI diff --git a/hal/tests/UNITTESTS/doubles/ticker_api_stub.c b/hal/tests/UNITTESTS/doubles/ticker_api_stub.c new file mode 100644 index 00000000000..193e9df1bc3 --- /dev/null +++ b/hal/tests/UNITTESTS/doubles/ticker_api_stub.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2022 Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "hal/ticker_api.h" + +void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler) +{ +} + +void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj) +{ +} + +void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uintptr_t id) +{ +} + +void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uintptr_t id) +{ +} + +us_timestamp_t ticker_read_us(const ticker_data_t *const ticker) +{ + return 0; +} diff --git a/platform/cxxsupport/mstd_span b/platform/cxxsupport/mstd_span index 184f14ee32a..ef0873dd275 100644 --- a/platform/cxxsupport/mstd_span +++ b/platform/cxxsupport/mstd_span @@ -139,7 +139,9 @@ class span { public: using element_type = ElementType; using value_type = typename mstd::remove_cv_t; - using index_type = size_t; + using size_type = size_t; + // Typedef because IAR does not allow [[deprecated]] with using + [[deprecated("Use size_type instead.")]] typedef size_t index_type; using difference_type = ptrdiff_t; using pointer = element_type *; using const_pointer = const element_type *; @@ -148,7 +150,7 @@ public: using iterator = pointer; using reverse_iterator = std::reverse_iterator; - static constexpr index_type extent = Extent; + static constexpr size_type extent = Extent; // Constructors, copy and assignment template>(*)[], ElementType(*)[]>::value, int> = 0> - constexpr span(It ptr, index_type count) : + constexpr span(It ptr, size_type count) : _storage(ptr, count) { MBED_ASSERT(extent == dynamic_extent || extent == count); @@ -251,32 +253,32 @@ public: return {data() + Offset, Count != dynamic_extent ? Count : size() - Offset}; } - constexpr span first(index_type count) const + constexpr span first(size_type count) const { MBED_ASSERT(count <= size()); return {data(), count}; } - constexpr span last(index_type count) const + constexpr span last(size_type count) const { MBED_ASSERT(count <= size()); return {data() + (size() - count), count}; } constexpr span - subspan(index_type offset, index_type count = dynamic_extent) const + subspan(size_type offset, size_type count = dynamic_extent) const { MBED_ASSERT(offset <= size() && (count == dynamic_extent || count <= size() - offset)); return {data() + offset, count == dynamic_extent ? size() - offset : count }; } // Observers - constexpr index_type size() const noexcept + constexpr size_type size() const noexcept { return _storage._size; } - constexpr index_type size_bytes() const noexcept + constexpr size_type size_bytes() const noexcept { return size() * sizeof(element_type); } @@ -287,7 +289,7 @@ public: } // Element access - constexpr reference operator[](index_type idx) const + constexpr reference operator[](size_type idx) const { MBED_ASSERT(idx < size()); return *(data() + idx); @@ -336,7 +338,7 @@ private: }; template -constexpr span::index_type span::extent; +constexpr span::size_type span::extent; #if __cplusplus >= 201703L || __cpp_deduction_guides >= 201703L // Deduction guides diff --git a/platform/include/platform/mbed_assert.h b/platform/include/platform/mbed_assert.h index c5ec5702b8f..34ee1587d0e 100644 --- a/platform/include/platform/mbed_assert.h +++ b/platform/include/platform/mbed_assert.h @@ -66,7 +66,7 @@ MBED_NORETURN void mbed_assert_internal(const char *expr, const char *file, int #define MBED_ASSERT(expr) \ do { \ if (!(expr)) { \ - mbed_assert_internal(#expr, __FILE__, __LINE__); \ + mbed_assert_internal(#expr, MBED_FILENAME, __LINE__); \ } \ } while (0) #endif diff --git a/platform/include/platform/mbed_toolchain.h b/platform/include/platform/mbed_toolchain.h index 2fa91d69e26..f9c016ab8ec 100644 --- a/platform/include/platform/mbed_toolchain.h +++ b/platform/include/platform/mbed_toolchain.h @@ -33,6 +33,11 @@ #endif #endif +/* Fix strrchr() not declared for IAR, used in MBED_FILENAME */ +#if defined(__ICCARM__) +#include +#endif + // Warning for unsupported compilers #if !defined(__GNUC__) /* GCC */ \ && !defined(__clang__) /* LLVM/Clang */ \ diff --git a/platform/include/platform/mbed_version.h b/platform/include/platform/mbed_version.h index 7ee9e28c043..acb21d3675c 100644 --- a/platform/include/platform/mbed_version.h +++ b/platform/include/platform/mbed_version.h @@ -45,7 +45,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_PATCH_VERSION 0 +#define MBED_PATCH_VERSION 1 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch)) diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index 6b03c00075f..fce62ea2554 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -114,6 +114,17 @@ "value": null }, + "deepsleep-stats-enabled": { + "macro_name": "MBED_SLEEP_TRACING_ENABLED", + "help": "Set to 1 to enable deepsleep lock stats", + "value": null + }, + + "deepsleep-stats-verbose": { + "help": "Stats are logged at each step (need deepsleep-stats-enable)", + "value": true + }, + "cthunk_count_max": { "help": "The maximum CThunk objects used at the same time. This must be greater than 0 and less 256", "value": 8 @@ -156,6 +167,9 @@ } }, "target_overrides": { + "STM": { + "deepsleep-stats-verbose": false + }, "EFM32": { "stdio-baud-rate": 115200 }, diff --git a/platform/source/mbed_power_mgmt.c b/platform/source/mbed_power_mgmt.c index 9d7724aea3f..8da2c347d8e 100644 --- a/platform/source/mbed_power_mgmt.c +++ b/platform/source/mbed_power_mgmt.c @@ -28,6 +28,9 @@ #include "platform/mbed_wait_api.h" #include +#ifdef MBED_SLEEP_TRACING_ENABLED +#include +#endif #if DEVICE_SLEEP @@ -138,19 +141,27 @@ static sleep_statistic_t *sleep_tracker_add(const char *const filename) static void sleep_tracker_print_stats(void) { - mbed_error_printf("Sleep locks held:\r\n"); - for (int i = 0; i < STATISTIC_COUNT; ++i) { - if (sleep_stats[i].count == 0) { - continue; - } - - if (sleep_stats[i].identifier[0] == '\0') { - return; + if (sleep_manager_can_deep_sleep()) { + mbed_error_printf("deepsleep unlocked"); +#ifdef MBED_DEBUG + mbed_error_printf(" but disabled with MBED_DEBUG"); +#endif + } else { + mbed_error_printf("deepsleep locked by:"); + for (int i = 0; i < STATISTIC_COUNT; ++i) { + if (sleep_stats[i].count == 0) { + continue; + } + + if (sleep_stats[i].identifier[0] == '\0') { + return; + } + + mbed_error_printf(" [%s x %u]", sleep_stats[i].identifier, + sleep_stats[i].count); } - - mbed_error_printf("[id: %s, count: %u]\r\n", sleep_stats[i].identifier, - sleep_stats[i].count); } + mbed_error_printf("\r\n"); } void sleep_tracker_lock(const char *const filename, int line) @@ -164,7 +175,9 @@ void sleep_tracker_lock(const char *const filename, int line) core_util_atomic_incr_u8(&stat->count, 1); +#if MBED_CONF_PLATFORM_DEEPSLEEP_STATS_VERBOSE mbed_error_printf("LOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock); +#endif } void sleep_tracker_unlock(const char *const filename, int line) @@ -179,7 +192,9 @@ void sleep_tracker_unlock(const char *const filename, int line) core_util_atomic_decr_u8(&stat->count, 1); +#if MBED_CONF_PLATFORM_DEEPSLEEP_STATS_VERBOSE mbed_error_printf("UNLOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock); +#endif } #endif // MBED_SLEEP_TRACING_ENABLED diff --git a/platform/source/minimal-printf/mbed_printf_implementation.c b/platform/source/minimal-printf/mbed_printf_implementation.c index ba3e2538fd1..b01a5ee5b20 100644 --- a/platform/source/minimal-printf/mbed_printf_implementation.c +++ b/platform/source/minimal-printf/mbed_printf_implementation.c @@ -267,20 +267,51 @@ static void mbed_minimal_formatted_string_double(char *buffer, size_t length, in { /* get integer part */ MBED_SIGNED_STORAGE integer = value; + /* fractional part represented as the int that will be formatted after the dot, e.g. 95 for 1.95 */ + MBED_SIGNED_STORAGE decimal = 0; if (dec_precision == PRECISION_DEFAULT) { dec_precision = MBED_CONF_PLATFORM_MINIMAL_PRINTF_SET_FLOATING_POINT_MAX_DECIMALS; } if (dec_precision != 0) { + /* get decimal part */ + MBED_SIGNED_STORAGE precision = 1; + for (int index = 0; index < dec_precision; index++) { + precision *= 10; + } + + /* Multiply the frac part so we get an int value with the required accuracy. + E.g. For 0.1234 and dec_precision=3 you'd get 123.4 */ + double decimal_double = (value - integer) * precision; + if (value < 0) { + /* The part after the dot does not have a sign, so negate the value before rounding */ + decimal = -decimal_double + 0.5; + if (decimal >= precision) { + /* Rounding carries over to value's integer part (e.g. -1.95 with dec_precision=1 -> -2.0) */ + integer--; + decimal = 0; + } + } else { + /* Round the value */ + decimal = decimal_double + 0.5; + if (decimal >= precision) { + /* Rounding carries over to value's integer part (e.g. 1.95 with dec_precision=1 -> 2.0) */ + integer++; + decimal = 0; + } + } + width_size -= dec_precision + 1; // decimal precision plus '.' if (width_size < 0) { width_size = 0; } } else { value = (value - integer) * 1.0; - if (!((value > -0.5) && (value < 0.5))) { + if (value > 0.5) { integer++; + } else if (value < -0.5) { + integer--; } } @@ -294,30 +325,6 @@ static void mbed_minimal_formatted_string_double(char *buffer, size_t length, in if (dec_precision != 0) { /* write decimal point */ mbed_minimal_putchar(buffer, length, result, '.', stream); - - /* get decimal part */ - double precision = 1.0; - - for (size_t index = 0; index < dec_precision; index++) { - precision *= 10; - } - - value = (value - integer) * precision; - - /* convert to positive number */ - if (value < 0.0) { - value *= -1.0; - } - - MBED_UNSIGNED_STORAGE decimal = value; - - /* round up or down */ - value -= decimal; - - if (!((value > -0.5) && (value < 0.5))) { - decimal++; - } - /* write decimal part */ mbed_minimal_formatted_string_integer(buffer, length, result, decimal, INT_UNSIGNED, dec_precision, true, stream); } diff --git a/platform/tests/UNITTESTS/CMakeLists.txt b/platform/tests/UNITTESTS/CMakeLists.txt index 88b941022a0..e7038fa4c4e 100644 --- a/platform/tests/UNITTESTS/CMakeLists.txt +++ b/platform/tests/UNITTESTS/CMakeLists.txt @@ -4,3 +4,4 @@ add_subdirectory(doubles) add_subdirectory(ATCmdParser) add_subdirectory(CircularBuffer) +add_subdirectory(minimal-printf) diff --git a/platform/tests/UNITTESTS/doubles/CMakeLists.txt b/platform/tests/UNITTESTS/doubles/CMakeLists.txt index 827466bc22d..65dccbd53cc 100644 --- a/platform/tests/UNITTESTS/doubles/CMakeLists.txt +++ b/platform/tests/UNITTESTS/doubles/CMakeLists.txt @@ -32,6 +32,9 @@ target_sources(mbed-stubs-platform nvic_wrapper_stub.c randLIB_stub.c randLIB_stub.cpp + mbed_thread_stub.cpp + mbed_power_mgmt_stub.cpp + CriticalSectionLock_stub.cpp ) target_include_directories(mbed-stubs-platform PUBLIC diff --git a/platform/tests/UNITTESTS/doubles/CriticalSectionLock_stub.cpp b/platform/tests/UNITTESTS/doubles/CriticalSectionLock_stub.cpp new file mode 100644 index 00000000000..0bce0120bdf --- /dev/null +++ b/platform/tests/UNITTESTS/doubles/CriticalSectionLock_stub.cpp @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "platform/CriticalSectionLock.h" + +namespace mbed { + +CriticalSectionLock::CriticalSectionLock() +{ +} + +CriticalSectionLock::~CriticalSectionLock() +{ +} +} // namespace mbed diff --git a/platform/tests/UNITTESTS/doubles/mbed_assert_stub.cpp b/platform/tests/UNITTESTS/doubles/mbed_assert_stub.cpp index baea5f221cd..4b046d7f41c 100644 --- a/platform/tests/UNITTESTS/doubles/mbed_assert_stub.cpp +++ b/platform/tests/UNITTESTS/doubles/mbed_assert_stub.cpp @@ -26,7 +26,11 @@ extern "C" void mbed_assert_internal(const char *expr, const char *file, int lin { fprintf(stderr, "mbed assertation failed: %s, file: %s, line %d \n", expr, file, line); if (mbed_assert_throw_errors) { +#ifdef __EXCEPTIONS throw 1; +#else + FAIL(); +#endif } /* Ensure we fail the unit test if the Mbed assertion fails. Without this, diff --git a/platform/tests/UNITTESTS/doubles/mbed_power_mgmt_stub.cpp b/platform/tests/UNITTESTS/doubles/mbed_power_mgmt_stub.cpp new file mode 100644 index 00000000000..715f1e058a9 --- /dev/null +++ b/platform/tests/UNITTESTS/doubles/mbed_power_mgmt_stub.cpp @@ -0,0 +1,26 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "platform/mbed_power_mgmt.h" + +void sleep_manager_lock_deep_sleep(void) +{ +} + +void sleep_manager_unlock_deep_sleep(void) +{ +} diff --git a/platform/tests/UNITTESTS/doubles/mbed_thread_stub.cpp b/platform/tests/UNITTESTS/doubles/mbed_thread_stub.cpp new file mode 100644 index 00000000000..90cc796ecb3 --- /dev/null +++ b/platform/tests/UNITTESTS/doubles/mbed_thread_stub.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2021, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "platform/mbed_thread.h" + +extern "C" { + + void thread_sleep_for(uint32_t millisec) + { + } + +} diff --git a/platform/tests/UNITTESTS/minimal-printf/CMakeLists.txt b/platform/tests/UNITTESTS/minimal-printf/CMakeLists.txt new file mode 100644 index 00000000000..08a95696117 --- /dev/null +++ b/platform/tests/UNITTESTS/minimal-printf/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME minimal-printf-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/platform/source/minimal-printf/mbed_printf_implementation.c + test_minimal-printf-implementation.cpp +) + +target_include_directories(mbed-headers-platform + INTERFACE + ${mbed-os_SOURCE_DIR}/platform/source/minimal-printf +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "platform") diff --git a/platform/tests/UNITTESTS/minimal-printf/test_minimal-printf-implementation.cpp b/platform/tests/UNITTESTS/minimal-printf/test_minimal-printf-implementation.cpp new file mode 100644 index 00000000000..78e39de4b00 --- /dev/null +++ b/platform/tests/UNITTESTS/minimal-printf/test_minimal-printf-implementation.cpp @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include "gtest/gtest.h" + +/* "mbed_printf_implementation.h" does not declare it as extern "C", so pull it in manually */ +extern "C" int mbed_minimal_formatted_string(char *buffer, size_t length, const char *format, va_list arguments, FILE *stream); + +namespace +{ + std::string format(const char *fmt, ...) + { + va_list arguments; + va_start(arguments, fmt); + + constexpr int buf_size = 128; + char buffer[buf_size]; + int n = mbed_minimal_formatted_string(buffer, buf_size, fmt, arguments, nullptr); + va_end(arguments); + + if (n >= buf_size) { + return "overflow"; + } + + return std::string(buffer); + } +} + +TEST(minimal_printf, floats) +{ + /* std::nextafter is used for the values below to make sure the numbers are + floating point representations of at least the value we want to test. + This hopefully mitigates false failures due to different floating point + implementations */ + + /* Positive numbers */ + float value = std::nextafter(1.5f, 0.0f); /* Something like 1.499999, i.e just below 1.5 */ + EXPECT_EQ("1", format("%.0f", value)); + EXPECT_EQ("1.5", format("%.1f", value)); + EXPECT_EQ("1.50", format("%.2f", value)); + EXPECT_EQ("1.500", format("%.3f", value)); + EXPECT_EQ("1.5000", format("%.4f", value)); + EXPECT_EQ("1.50000", format("%.5f", value)); + EXPECT_EQ("1.500000", format("%.6f", value)); + + value = std::nextafter(1.5f, 2.0f); /* Something like 1.500001, i.e just above 1.5 */ + EXPECT_EQ("2", format("%.0f", value)); + EXPECT_EQ("1.5", format("%.1f", value)); + EXPECT_EQ("1.50", format("%.2f", value)); + EXPECT_EQ("1.500", format("%.3f", value)); + EXPECT_EQ("1.5000", format("%.4f", value)); + EXPECT_EQ("1.50000", format("%.5f", value)); + EXPECT_EQ("1.500000", format("%.6f", value)); + + value = std::nextafter(2.0f, 0.0f); /* Something like 1.999999, i.e just below 2.0 */ + EXPECT_EQ("2", format("%.0f", value)); + EXPECT_EQ("2.0", format("%.1f", value)); + EXPECT_EQ("2.00", format("%.2f", value)); + EXPECT_EQ("2.000", format("%.3f", value)); + EXPECT_EQ("2.0000", format("%.4f", value)); + EXPECT_EQ("2.00000", format("%.5f", value)); + EXPECT_EQ("2.000000", format("%.6f", value)); + + /* Negative numbers */ + value = std::nextafter(-1.5f, 0.0f); /* Something like -1.499999, i.e just above -1.5 */ + EXPECT_EQ("-1", format("%.0f", value)); + EXPECT_EQ("-1.5", format("%.1f", value)); + EXPECT_EQ("-1.50", format("%.2f", value)); + EXPECT_EQ("-1.500", format("%.3f", value)); + EXPECT_EQ("-1.5000", format("%.4f", value)); + EXPECT_EQ("-1.50000", format("%.5f", value)); + EXPECT_EQ("-1.500000", format("%.6f", value)); + + value = std::nextafter(-1.5f, -2.0f); /* Something like -1.500001, i.e just below -1.5 */ + EXPECT_EQ("-2", format("%.0f", value)); + EXPECT_EQ("-1.5", format("%.1f", value)); + EXPECT_EQ("-1.50", format("%.2f", value)); + EXPECT_EQ("-1.500", format("%.3f", value)); + EXPECT_EQ("-1.5000", format("%.4f", value)); + EXPECT_EQ("-1.50000", format("%.5f", value)); + EXPECT_EQ("-1.500000", format("%.6f", value)); + + value = std::nextafter(-2.0f, 0.0f); /* Something like -1.999999, i.e just above -2.0 */ + EXPECT_EQ("-2", format("%.0f", value)); + EXPECT_EQ("-2.0", format("%.1f", value)); + EXPECT_EQ("-2.00", format("%.2f", value)); + EXPECT_EQ("-2.000", format("%.3f", value)); + EXPECT_EQ("-2.0000", format("%.4f", value)); + EXPECT_EQ("-2.00000", format("%.5f", value)); + EXPECT_EQ("-2.000000", format("%.6f", value)); + + // And some near zero stuff + EXPECT_EQ("-0", format("%.0f", std::nextafter(0.0f, -1.0f))); + EXPECT_EQ("0", format("%.0f", 0.0)); + EXPECT_EQ("0", format("%.0f", std::nextafter(0.0f, 1.0f))); +} + +TEST(minimal_printf, padding) +{ + // Right aligned integers + EXPECT_EQ("12", format("%1d", 12)); + EXPECT_EQ("12", format("%2d", 12)); + EXPECT_EQ(" 12", format("%3d", 12)); + EXPECT_EQ(" 12", format("%4d", 12)); + + EXPECT_EQ("-12", format("%1d", -12)); + EXPECT_EQ("-12", format("%3d", -12)); + EXPECT_EQ(" -12", format("%4d", -12)); + EXPECT_EQ(" -12", format("%5d", -12)); + + EXPECT_EQ("0012", format("%04d", 12)); + EXPECT_EQ("-012", format("%04d", -12)); + + // Right aligned floats + EXPECT_EQ("12.3", format("%1.1f", 12.345f)); + EXPECT_EQ("12.3", format("%4.1f", 12.345)); + EXPECT_EQ(" 12.3", format("%5.1f", 12.345)); + EXPECT_EQ(" 12.3", format("%6.1f", 12.345)); + + EXPECT_EQ("-12.3", format("%1.1f", -12.345f)); + EXPECT_EQ("-12.3", format("%4.1f", -12.345)); + EXPECT_EQ(" -12.3", format("%6.1f", -12.345)); + EXPECT_EQ(" -12.3", format("%7.1f", -12.345)); + + EXPECT_EQ("012.3", format("%05.1f", 12.345)); + EXPECT_EQ("-012.3", format("%06.1f", -12.345)); +} + diff --git a/requirements.txt b/requirements.txt index e08dccc3fdb..ba57f92e968 100644 --- a/requirements.txt +++ b/requirements.txt @@ -14,14 +14,14 @@ mbed-ls>=1.5.1,<2.0 mbed-host-tests>=1.4.4,<2.0 mbed-greentea>=0.2.24,<2.0 beautifulsoup4>=4,<=4.6.3 -pyelftools>=0.24,<=0.25 +pyelftools>=0.27,<=0.28 pycryptodome>=3.9.3,<4 pyusb>=1.0.0,<2.0.0 hidapi>=0.7.99,<0.8.0;platform_system!="Linux" cmsis-pack-manager>=0.2.3,<0.3.0 pywin32>=301;platform_system=='Windows' wmi==1.4.9;platform_system=='Windows' -psutil==5.6.6 +psutil==5.6.7 cryptography>=3.2,<4 Click>=7.0,<8 cbor>=1.0.0 diff --git a/script.py b/script.py new file mode 100644 index 00000000000..e2b2bb44362 --- /dev/null +++ b/script.py @@ -0,0 +1,22 @@ +import os + +path = os.getcwd() +source = os.path.join(path, "drivers/source") +source_dirs = os.listdir(source) +test_dir = os.path.join(path, "drivers/tests/UNITTESTS") + +cmake_file = os.path.join(test_dir, "AnalogIn/CMakeLists.txt") +test_file = os.path.join(test_dir, "AnalogIn/test_analogin.cpp") + +for filename in source_dirs: + try: + # Create target Directory + dirName = os.path.join(test_dir, os.path.splitext(filename)[0]) + os.mkdir(dirName) + os.popen(f"cp {cmake_file} {dirName}/CMakeLists.txt") + os.popen(f"cp {test_file} {dirName}/test_{os.path.splitext(filename)[0].lower()}.cpp") + #print("Directory " , dirName , " Created ") + #print(f"cp {test_file} {dirName}/test_{os.path.splitext(filename)[0].lower()}.cpp") + except FileExistsError: + print("Directory " , dirName , " already exists") + diff --git a/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h index 3ebd0e504cf..2903ecad32f 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_QSPIF/include/QSPIF/QSPIFBlockDevice.h @@ -315,7 +315,7 @@ class QSPIFBlockDevice : public mbed::BlockDevice { /* SFDP Detection and Parsing Functions */ /****************************************/ // Parse and Detect required Basic Parameters from Table - int _sfdp_parse_basic_param_table(mbed::Callback sfdp_reader, + int _sfdp_parse_basic_param_table(mbed::Callback sfdp_reader, mbed::sfdp_hdr_info &sfdp_info); // Detect the soft reset protocol and reset - returns error if soft reset is not supported diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c index 7fa3bc16376..70c7ba6f81b 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/gpio_irq_api.c @@ -24,7 +24,7 @@ #define CMSDK_GPIO_1 CMSDK_GPIO1 #define PININT_IRQ 0 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; static inline void handle_interrupt_in(uint32_t channel) @@ -35,31 +35,31 @@ static inline void handle_interrupt_in(uint32_t channel) // * There is no user handler // * It is a level interrupt, not an edge interrupt if (ch_bit < 16) { - if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0)) { + if (((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_contexts[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0)) { return; } if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); + irq_handler(channel_contexts[channel], IRQ_RISE); CMSDK_GPIO_0->INTPOLSET = ch_bit; } if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_contexts[channel], IRQ_FALL); } CMSDK_GPIO_0->INTCLEAR = ch_bit; } if (ch_bit >= 16) { - if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0)) { + if (((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_contexts[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0)) { return; } if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); + irq_handler(channel_contexts[channel], IRQ_RISE); CMSDK_GPIO_1->INTPOLSET = ch_bit; } if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_contexts[channel], IRQ_FALL); } CMSDK_GPIO_1->INTCLEAR = ch_bit; } @@ -195,7 +195,7 @@ void gpio1_irq15(void) } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -206,8 +206,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 int found_free_channel = 0; int i = 0; for (i = 0; i < CHANNEL_NUM; i++) { - if (channel_ids[i] == 0) { - channel_ids[i] = id; + if (channel_contexts[i] == 0) { + channel_contexts[i] = context; obj->ch = i; found_free_channel = 1; break; diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c index 296b383816c..a8140cfd0a6 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c @@ -54,7 +54,7 @@ int stdio_uart_inited = 0; serial_t stdio_uart; struct serial_global_data_s { - uint32_t serial_irq_id; + uintptr_t serial_irq_context; gpio_t sw_rts, sw_cts; uint8_t count, rx_irq_set_flow, rx_irq_set_api; }; @@ -165,7 +165,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; + uart_data[obj->index].serial_irq_context = 0; } // serial_baud @@ -241,9 +241,9 @@ static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeD } } - if (uart_data[index].serial_irq_id != 0) { + if (uart_data[index].serial_irq_context != 0) { if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) { - irq_handler(uart_data[index].serial_irq_id, irq_type); + irq_handler(uart_data[index].serial_irq_context, irq_type); } } @@ -273,10 +273,10 @@ void uart3_irq() uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef *)CMSDK_UART4); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; + uart_data[obj->index].serial_irq_context = context; } static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c index 4c1d47d5068..74c636ce424 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c @@ -24,7 +24,7 @@ struct gpio_irq_handler_t { gpio_irq_handler handler; gpio_irq_event event; - uint32_t id; + uintptr_t context; }; /* Handlers registered */ @@ -69,7 +69,7 @@ static void handler(struct arm_gpio_dev_t* dev, uint32_t gpio_number, exp_pin_number = exp_pin_base + pin_number; - gpio_irq[exp_pin_number].handler(gpio_irq[exp_pin_number].id, + gpio_irq[exp_pin_number].handler(gpio_irq[exp_pin_number].context, gpio_irq[exp_pin_number].event); } @@ -102,7 +102,7 @@ void PORT3_ALL_IRQHandler(void) #endif /* ARM_GPIO3 */ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, - uint32_t id) + uintptr_t context) { struct arm_gpio_dev_t *gpio_dev; @@ -146,7 +146,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, /* Save the handler and id into the global structure */ gpio_irq[pin].handler = handler; - gpio_irq[pin].id = id; + gpio_irq[pin].context = context; return 0; } else { diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c index 466e70599c2..032032e83b0 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c @@ -36,7 +36,7 @@ struct uart_irq_t { uart_irq_handler handler; - uint32_t id; + uintptr_t context; }; static const PinMap PinMap_UART_TX[] = { @@ -144,7 +144,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { - uart_irq[obj->index].id = 0; + uart_irq[obj->index].context = 0; uart_irq[obj->index].handler = 0; } @@ -178,14 +178,14 @@ void UART0_IRQHandler() if(uart_irq[UART_0].handler) { switch(irq) { case ARM_UART_IRQ_RX: - uart_irq[UART_0].handler(uart_irq[UART_0].id, RxIrq); + uart_irq[UART_0].handler(uart_irq[UART_0].context, RxIrq); break; case ARM_UART_IRQ_TX: - uart_irq[UART_0].handler(uart_irq[UART_0].id, TxIrq); + uart_irq[UART_0].handler(uart_irq[UART_0].context, TxIrq); break; case ARM_UART_IRQ_COMBINED: - uart_irq[UART_0].handler(uart_irq[UART_0].id, RxIrq); - uart_irq[UART_0].handler(uart_irq[UART_0].id, TxIrq); + uart_irq[UART_0].handler(uart_irq[UART_0].context, RxIrq); + uart_irq[UART_0].handler(uart_irq[UART_0].context, TxIrq); break; case ARM_UART_IRQ_NONE: default: @@ -203,14 +203,14 @@ void UART1_IRQHandler() if(uart_irq[UART_1].handler) { switch(irq) { case ARM_UART_IRQ_RX: - uart_irq[UART_1].handler(uart_irq[UART_1].id, RxIrq); + uart_irq[UART_1].handler(uart_irq[UART_1].context, RxIrq); break; case ARM_UART_IRQ_TX: - uart_irq[UART_1].handler(uart_irq[UART_1].id, TxIrq); + uart_irq[UART_1].handler(uart_irq[UART_1].context, TxIrq); break; case ARM_UART_IRQ_COMBINED: - uart_irq[UART_1].handler(uart_irq[UART_1].id, RxIrq); - uart_irq[UART_1].handler(uart_irq[UART_1].id, TxIrq); + uart_irq[UART_1].handler(uart_irq[UART_1].context, RxIrq); + uart_irq[UART_1].handler(uart_irq[UART_1].context, TxIrq); break; case ARM_UART_IRQ_NONE: default: @@ -228,14 +228,14 @@ void UART2_IRQHandler() if(uart_irq[UART_2].handler) { switch(irq) { case ARM_UART_IRQ_RX: - uart_irq[UART_2].handler(uart_irq[UART_2].id, RxIrq); + uart_irq[UART_2].handler(uart_irq[UART_2].context, RxIrq); break; case ARM_UART_IRQ_TX: - uart_irq[UART_2].handler(uart_irq[UART_2].id, TxIrq); + uart_irq[UART_2].handler(uart_irq[UART_2].context, TxIrq); break; case ARM_UART_IRQ_COMBINED: - uart_irq[UART_2].handler(uart_irq[UART_2].id, RxIrq); - uart_irq[UART_2].handler(uart_irq[UART_2].id, TxIrq); + uart_irq[UART_2].handler(uart_irq[UART_2].context, RxIrq); + uart_irq[UART_2].handler(uart_irq[UART_2].context, TxIrq); break; case ARM_UART_IRQ_NONE: default: @@ -253,14 +253,14 @@ void UART3_IRQHandler() if(uart_irq[UART_3].handler) { switch(irq) { case ARM_UART_IRQ_RX: - uart_irq[UART_3].handler(uart_irq[UART_3].id, RxIrq); + uart_irq[UART_3].handler(uart_irq[UART_3].context, RxIrq); break; case ARM_UART_IRQ_TX: - uart_irq[UART_3].handler(uart_irq[UART_3].id, TxIrq); + uart_irq[UART_3].handler(uart_irq[UART_3].context, TxIrq); break; case ARM_UART_IRQ_COMBINED: - uart_irq[UART_3].handler(uart_irq[UART_3].id, RxIrq); - uart_irq[UART_3].handler(uart_irq[UART_3].id, TxIrq); + uart_irq[UART_3].handler(uart_irq[UART_3].context, RxIrq); + uart_irq[UART_3].handler(uart_irq[UART_3].context, TxIrq); break; case ARM_UART_IRQ_NONE: default: @@ -278,14 +278,14 @@ void UART4_IRQHandler() if(uart_irq[UART_4].handler) { switch(irq) { case ARM_UART_IRQ_RX: - uart_irq[UART_4].handler(uart_irq[UART_4].id, RxIrq); + uart_irq[UART_4].handler(uart_irq[UART_4].context, RxIrq); break; case ARM_UART_IRQ_TX: - uart_irq[UART_4].handler(uart_irq[UART_4].id, TxIrq); + uart_irq[UART_4].handler(uart_irq[UART_4].context, TxIrq); break; case ARM_UART_IRQ_COMBINED: - uart_irq[UART_4].handler(uart_irq[UART_4].id, RxIrq); - uart_irq[UART_4].handler(uart_irq[UART_4].id, TxIrq); + uart_irq[UART_4].handler(uart_irq[UART_4].context, RxIrq); + uart_irq[UART_4].handler(uart_irq[UART_4].context, TxIrq); break; case ARM_UART_IRQ_NONE: default: @@ -295,10 +295,10 @@ void UART4_IRQHandler() } #endif /* ARM_UART4 */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { uart_irq[obj->index].handler = handler; - uart_irq[obj->index].id = id; + uart_irq[obj->index].context = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c index 7a54736a2e2..11fcd5d4b37 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/gpio_irq_api.c @@ -24,7 +24,7 @@ #define CMSDK_GPIO_1 CMSDK_GPIO1 #define PININT_IRQ 0 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; static inline void handle_interrupt_in(uint32_t channel) { @@ -34,27 +34,27 @@ static inline void handle_interrupt_in(uint32_t channel) { // * There is no user handler // * It is a level interrupt, not an edge interrupt if (ch_bit <16){ - if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; + if ( ((CMSDK_GPIO_0->INTSTATUS) == 0) || (channel_contexts[channel] == 0) || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) return; if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); + irq_handler(channel_contexts[channel], IRQ_RISE); CMSDK_GPIO_0->INTPOLSET = ch_bit; } if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_contexts[channel], IRQ_FALL); } CMSDK_GPIO_0->INTCLEAR = ch_bit; } if (ch_bit>=16) { - if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_ids[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; + if ( ((CMSDK_GPIO_1->INTSTATUS) == 0) || (channel_contexts[channel] == 0) || ((CMSDK_GPIO_1->INTTYPESET) == 0) ) return; if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); + irq_handler(channel_contexts[channel], IRQ_RISE); CMSDK_GPIO_1->INTPOLSET = ch_bit; } if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_contexts[channel], IRQ_FALL); } CMSDK_GPIO_1->INTCLEAR = ch_bit; } @@ -94,7 +94,7 @@ void gpio1_irq14(void) {handle_interrupt_in(30);} void gpio1_irq15(void) {handle_interrupt_in(31);} -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) {return -1;} else { @@ -103,8 +103,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 int found_free_channel = 0; int i = 0; for (i=0; ich = i; found_free_channel = 1; break; diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c index 6cf18c98c5b..5712f730110 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c @@ -54,7 +54,7 @@ int stdio_uart_inited = 0; serial_t stdio_uart; struct serial_global_data_s { - uint32_t serial_irq_id; + uintptr_t serial_irq_context; gpio_t sw_rts, sw_cts; uint8_t count, rx_irq_set_flow, rx_irq_set_api; }; @@ -168,7 +168,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; + uart_data[obj->index].serial_irq_context = 0; } // serial_baud @@ -235,11 +235,11 @@ static inline void uart_irq(uint32_t intstatus, uint32_t index, CMSDK_UART_TypeD } } - if (uart_data[index].serial_irq_id != 0) + if (uart_data[index].serial_irq_context != 0) { if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) { - irq_handler(uart_data[index].serial_irq_id, irq_type); + irq_handler(uart_data[index].serial_irq_context, irq_type); } } @@ -260,9 +260,9 @@ void uart1_irq() {uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef* void uart2_irq() {uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART3);} void uart3_irq() {uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART4);} -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; + uart_data[obj->index].serial_irq_context = context; } static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { diff --git a/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/gpio_irq_api.c b/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/gpio_irq_api.c index 69c638a996c..e853aea91e3 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/gpio_irq_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/gpio_irq_api.c @@ -29,7 +29,7 @@ #include "mbed_error.h" int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, - uint32_t id) + uintptr_t context) { /* Due to a HW limitation, GPIO in Musca-B1 is Secure only, in NS domain, * GPIO platform service is used. The current implementation of GPIO diff --git a/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/serial_api.c b/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/serial_api.c index d01b6e57994..ac92d4cf23f 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/serial_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MUSCA_B1/serial_api.c @@ -130,10 +130,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, uart_word_len, uart_parity, uart_stop_bits); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { uart_irq[obj->uart_index].handler = handler; - uart_irq[obj->uart_index].id = id; + uart_irq[obj->uart_index].id = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/gpio_irq_api.c b/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/gpio_irq_api.c index 9d98f8defff..d07d1425749 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/gpio_irq_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/gpio_irq_api.c @@ -29,7 +29,7 @@ #include "mbed_error.h" int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, - uint32_t id) + uintptr_t context) { /* Due to a HW limitation, GPIO in Musca-S1 is Secure only, in NS domain, * GPIO platform service is used. The current implementation of GPIO diff --git a/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/serial_api.c b/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/serial_api.c index d6a85011aad..b49059d7da9 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/serial_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MUSCA_S1/serial_api.c @@ -131,10 +131,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, uart_word_len, uart_parity, uart_stop_bits); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { uart_irq[obj->uart_index].handler = handler; - uart_irq[obj->uart_index].id = id; + uart_irq[obj->uart_index].id = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c index a42d181c057..2c6f87d2463 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/gpio_irq_api.c @@ -36,7 +36,7 @@ uint32_t ap3_gpio_enable_interrupts(uint32_t ui32Pin, am_hal_gpio_intdir_e eIntD */ typedef struct gpio_irq_s gpio_irq_t; -typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event); +typedef void (*gpio_irq_handler)(uintptr_t context, gpio_irq_event event); extern void am_gpio_isr(void); static ap3_gpio_irq_control_t gpio_irq_control[AP3_GPIO_MAX_PADS]; @@ -62,10 +62,10 @@ static ap3_gpio_irq_control_t gpio_irq_control[AP3_GPIO_MAX_PADS]; * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ -* @param id The object ID (id != 0, 0 is reserved) +* @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { //grab the correct irq control object ap3_gpio_irq_control_t *control = &gpio_irq_control[pin]; @@ -73,7 +73,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 //Register locally control->pad = pin; control->handler = handler; - control->id = id; + control->id = context; control->events = IRQ_NONE; //Attach to object diff --git a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c index 83d23f34834..9e8d30e4a61 100644 --- a/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c +++ b/targets/TARGET_Ambiq_Micro/TARGET_Apollo3/device/serial_api.c @@ -221,10 +221,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b MBED_ASSERT(am_hal_uart_configure_fifo(obj->serial.uart_control->handle, &(obj->serial.uart_control->cfg), false) == AM_HAL_STATUS_SUCCESS); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - obj->serial.uart_control->serial_irq_id = id; + obj->serial.uart_control->serial_irq_id = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c index 242e6fabdd7..ed8981b29c8 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c @@ -49,7 +49,7 @@ #define MAX_GPIO_PORTS ADI_GPIO_NUM_PORTS typedef struct { - unsigned int id; + uintptr_t context; gpio_irq_event event; uint8_t int_enable; } gpio_chan_info_t; @@ -59,7 +59,7 @@ typedef struct { *******************************************************************************/ extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; extern uint8_t gpio_initialized; -static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; +static gpio_chan_info_t channel_contexts[MAX_GPIO_PORTS][MAX_GPIO_LINES]; static gpio_irq_handler irq_handler = NULL; @@ -75,7 +75,7 @@ static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg) if (pin & 0x01) { // call the user ISR. The argument Event is the port number of the GPIO line. if (irq_handler != NULL) - irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event); + irq_handler(channel_contexts[Event][index].context, channel_contexts[Event][index].event); } index++; pin >>= 1; @@ -178,16 +178,16 @@ static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_T * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) + * @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { uint32_t port = pin >> GPIO_PORT_SHIFT; uint32_t pin_num = pin & 0xFF; - // check for valid pin and ID - if ((pin == NC) || (id == 0)) { + // check for valid pin and context + if ((pin == NC) || (context == 0)) { return -1; } @@ -208,11 +208,11 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // set the port pin as input adi_gpio_InputEnable(port, 1 << pin_num, true); - // save the ID for future reference - channel_ids[port][pin_num].id = (uint32_t)id; - channel_ids[port][pin_num].event = IRQ_NONE; - channel_ids[port][pin_num].int_enable = 0; - obj->id = id; + // save the context for future reference + channel_contexts[port][pin_num].context = context; + channel_contexts[port][pin_num].event = IRQ_NONE; + channel_contexts[port][pin_num].int_enable = 0; + obj->id = context; obj->pinname = pin; return 0; @@ -231,9 +231,9 @@ void gpio_irq_free(gpio_irq_t *obj) gpio_irq_disable(obj); // clear the status table - channel_ids[port][pin_num].id = (uint32_t)0; - channel_ids[port][pin_num].event = IRQ_NONE; - channel_ids[port][pin_num].int_enable = 0; + channel_contexts[port][pin_num].context = (uintptr_t)0; + channel_contexts[port][pin_num].event = IRQ_NONE; + channel_contexts[port][pin_num].int_enable = 0; } /** Enable/disable pin IRQ event @@ -264,7 +264,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) // set the polarity register adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg); - channel_ids[port][pin_num].event = event; + channel_contexts[port][pin_num].event = event; // enable interrupt for this pin if enable flag is set if (enable) { @@ -284,22 +284,22 @@ void gpio_irq_enable(gpio_irq_t *obj) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (channel_ids[port][pin_num].event == IRQ_NONE) { + if (channel_contexts[port][pin_num].event == IRQ_NONE) { return; } // Group all RISE interrupts in INTA and FALL interrupts in INTB - if (channel_ids[port][pin_num].event == IRQ_RISE) { + if (channel_contexts[port][pin_num].event == IRQ_RISE) { // set the callback routine adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj); enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn); - } else if (channel_ids[port][pin_num].event == IRQ_FALL) { + } else if (channel_contexts[port][pin_num].event == IRQ_FALL) { // set the callback routine adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj); enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn); } - channel_ids[port][pin_num].int_enable = 1; + channel_contexts[port][pin_num].int_enable = 1; } /** Disable GPIO IRQ @@ -312,19 +312,19 @@ void gpio_irq_disable(gpio_irq_t *obj) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (channel_ids[port][pin_num].event == IRQ_NONE) { + if (channel_contexts[port][pin_num].event == IRQ_NONE) { return; } // Group all RISE interrupts in INTA and FALL interrupts in INTB - if (channel_ids[port][pin_num].event == IRQ_RISE) { + if (channel_contexts[port][pin_num].event == IRQ_RISE) { disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); } - else if (channel_ids[port][pin_num].event == IRQ_FALL) { + else if (channel_contexts[port][pin_num].event == IRQ_FALL) { disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); } - channel_ids[port][pin_num].int_enable = 0; + channel_contexts[port][pin_num].int_enable = 0; } #endif // #if DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c index cd0d2b2bf76..dc054cc0b18 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c @@ -57,7 +57,7 @@ static ADI_UART_HANDLE hDevice; static uint32_t UartDeviceMem[(ADI_UART_MEMORY_SIZE + 3)/4]; -static uint32_t serial_irq_ids[2] = {0}; +static uintptr_t serial_irq_contexts[2] = {0}; static uart_irq_handler irq_handler = NULL; int stdio_uart_inited = 0; serial_t stdio_uart; @@ -69,9 +69,9 @@ static void uart_callback(void *pCBParam, uint32_t Event, void *pArg) MBED_ASSERT(irq_handler); if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED) - irq_handler(serial_irq_ids[0], TxIrq); + irq_handler(serial_irq_contexts[0], TxIrq); else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED) - irq_handler(serial_irq_ids[0], RxIrq); + irq_handler(serial_irq_contexts[0], RxIrq); } @@ -284,13 +284,13 @@ void serial_break_clear(serial_t *obj) adi_uart_ForceTxBreak(hDevice, false); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { MBED_ASSERT(obj); irq_handler = handler; - serial_irq_ids[0] = id; + serial_irq_contexts[0] = context; } const PinMap *serial_tx_pinmap() diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c index 9fea1bb7134..385ba879cbf 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c @@ -48,7 +48,7 @@ #define MAX_GPIO_PORTS ADI_GPIO_NUM_PORTS typedef struct { - unsigned int id; + uintptr_t context; gpio_irq_event event; uint8_t int_enable; } gpio_chan_info_t; @@ -58,7 +58,7 @@ typedef struct { *******************************************************************************/ extern uint32_t gpioMemory[(ADI_GPIO_MEMORY_SIZE + 3)/4]; extern uint8_t gpio_initialized; -static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; +static gpio_chan_info_t channel_contexts[MAX_GPIO_PORTS][MAX_GPIO_LINES]; static gpio_irq_handler irq_handler = NULL; @@ -74,7 +74,7 @@ static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg) if (pin & 0x01) { // call the user ISR. The argument Event is the port number of the GPIO line. if (irq_handler != NULL) - irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event); + irq_handler(channel_contexts[Event][index].context, channel_contexts[Event][index].event); } index++; pin >>= 1; @@ -177,16 +177,16 @@ static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_T * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) + * @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { uint32_t port = pin >> GPIO_PORT_SHIFT; uint32_t pin_num = pin & 0xFF; - // check for valid pin and ID - if ((pin == NC) || (id == 0)) { + // check for valid pin and context + if ((pin == NC) || (context == 0)) { return -1; } @@ -207,11 +207,11 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // set the port pin as input adi_gpio_InputEnable(port, 1 << pin_num, true); - // save the ID for future reference - channel_ids[port][pin_num].id = id; - channel_ids[port][pin_num].event = IRQ_NONE; - channel_ids[port][pin_num].int_enable = 0; - obj->id = id; + // save the context for future reference + channel_contexts[port][pin_num].context = context; + channel_contexts[port][pin_num].event = IRQ_NONE; + channel_contexts[port][pin_num].int_enable = 0; + obj->id = context; obj->pinname = pin; return 0; @@ -230,9 +230,9 @@ void gpio_irq_free(gpio_irq_t *obj) gpio_irq_disable(obj); // clear the status table - channel_ids[port][pin_num].id = 0; - channel_ids[port][pin_num].event = IRQ_NONE; - channel_ids[port][pin_num].int_enable = 0; + channel_contexts[port][pin_num].context = 0; + channel_contexts[port][pin_num].event = IRQ_NONE; + channel_contexts[port][pin_num].int_enable = 0; } /** Enable/disable pin IRQ event @@ -263,7 +263,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) // set the polarity register adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg); - channel_ids[port][pin_num].event = event; + channel_contexts[port][pin_num].event = event; // enable interrupt for this pin if enable flag is set if (enable) { @@ -283,22 +283,22 @@ void gpio_irq_enable(gpio_irq_t *obj) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (channel_ids[port][pin_num].event == IRQ_NONE) { + if (channel_contexts[port][pin_num].event == IRQ_NONE) { return; } // Group all RISE interrupts in INTA and FALL interrupts in INTB - if (channel_ids[port][pin_num].event == IRQ_RISE) { + if (channel_contexts[port][pin_num].event == IRQ_RISE) { // set the callback routine adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj); enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn); - } else if (channel_ids[port][pin_num].event == IRQ_FALL) { + } else if (channel_contexts[port][pin_num].event == IRQ_FALL) { // set the callback routine adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj); enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn); } - channel_ids[port][pin_num].int_enable = 1; + channel_contexts[port][pin_num].int_enable = 1; } /** Disable GPIO IRQ @@ -311,19 +311,19 @@ void gpio_irq_disable(gpio_irq_t *obj) uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; uint32_t pin_num = obj->pinname & 0xFF; - if (channel_ids[port][pin_num].event == IRQ_NONE) { + if (channel_contexts[port][pin_num].event == IRQ_NONE) { return; } // Group all RISE interrupts in INTA and FALL interrupts in INTB - if (channel_ids[port][pin_num].event == IRQ_RISE) { + if (channel_contexts[port][pin_num].event == IRQ_RISE) { disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); } - else if (channel_ids[port][pin_num].event == IRQ_FALL) { + else if (channel_contexts[port][pin_num].event == IRQ_FALL) { disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); } - channel_ids[port][pin_num].int_enable = 0; + channel_contexts[port][pin_num].int_enable = 0; } #endif // #if DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c index ef48996dc9a..1953124bdc9 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c @@ -57,7 +57,7 @@ static ADI_UART_HANDLE hDevice[ADI_UART_NUM_DEVICES]; static uint32_t UartDeviceMem[ADI_UART_NUM_DEVICES][(ADI_UART_MEMORY_SIZE + 3)/4]; -static uint32_t serial_irq_ids[ADI_UART_NUM_DEVICES] = {0}; +static uintptr_t serial_irq_contexts[ADI_UART_NUM_DEVICES] = {0}; static uart_irq_handler irq_handler = NULL; int stdio_uart_inited = 0; serial_t stdio_uart; @@ -69,9 +69,9 @@ static void uart_callback(void *pCBParam, uint32_t Event, void *pArg) MBED_ASSERT(irq_handler); serial_t *obj = pCBParam; if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED) - irq_handler(serial_irq_ids[obj->index], TxIrq); + irq_handler(serial_irq_contexts[obj->index], TxIrq); else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED) - irq_handler(serial_irq_ids[obj->index], RxIrq); + irq_handler(serial_irq_contexts[obj->index], RxIrq); } @@ -239,13 +239,13 @@ void serial_break_clear(serial_t *obj) adi_uart_ForceTxBreak(hDevice[obj->index], false); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { MBED_ASSERT(obj); irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } const PinMap *serial_tx_pinmap() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt index 212174df64a..59d2b3304eb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt @@ -46,14 +46,16 @@ target_sources(mbed-cm0p-secure psoc6cm0p/COMPONENT_CM0P_SECURE/psoc6_03_cm0p_secure.c ) -add_library(mbed-cm0p-sleep INTERFACE) -target_sources(mbed-cm0p-sleep - INTERFACE - psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c - psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c - psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c - psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_04_cm0p_sleep.c -) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + add_library(mbed-cm0p-sleep INTERFACE) + target_sources(mbed-cm0p-sleep + INTERFACE + psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c + psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c + psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c + psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_04_cm0p_sleep.c + ) +endif() add_library(mbed-udb-sdio-p12 INTERFACE) target_include_directories(mbed-udb-sdio-p12 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/CMakeLists.txt index 287eec26007..6c0e9f529a5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT064B0S2_4343W/CMakeLists.txt @@ -67,11 +67,17 @@ target_link_libraries(mbed-cy8ckit064b0s2-4343w mbed-cy8ckit064b0s2-4343w-bsp-design-modus mbed-cm0p-secure mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-4343w - mbed-cy8ckit-064b0s2-4343w-whd ) +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8ckit064b0s2-4343w + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-4343w + mbed-cy8ckit-064b0s2-4343w-whd + ) +endif() + target_compile_definitions(mbed-cy8ckit064b0s2-4343w INTERFACE "CYB0644ABZI_S2D44" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/CMakeLists.txt index 6cb68eed848..519eb9f153c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/CMakeLists.txt @@ -63,13 +63,25 @@ target_link_libraries(mbed-cy8ckit-062s2-43012 mbed-cat1a mbed-cy8ckit-062s2-43012-cm4 mbed-cy8ckit-062s2-43012-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-43012 - mbed-cy8ckit-062s2-43012-whd ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8ckit-062s2-43012 + INTERFACE + mbed-cm0p-sleep + ) +endif() + +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8ckit-062s2-43012 + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-43012 + mbed-cy8ckit-062s2-43012-whd + ) +endif() + target_compile_definitions(mbed-cy8ckit-062s2-43012 INTERFACE "CY8C624ABZI_D44" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/CMakeLists.txt index 06fb29f1e4c..3eeb7c969bf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/CMakeLists.txt @@ -63,10 +63,16 @@ target_link_libraries(mbed-cy8ckit-062-ble mbed-cat1a mbed-cy8ckit-062-ble-cm4 mbed-cy8ckit-062-ble-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8ckit-062-ble + INTERFACE + mbed-cm0p-sleep + ) +endif() + target_compile_definitions(mbed-cy8ckit-062-ble INTERFACE "CY8C6347BZI_BLD53" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/CMakeLists.txt index 2d66224f692..178d3fa9c1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/CMakeLists.txt @@ -63,14 +63,26 @@ target_link_libraries(mbed-cy8ckit-062-wifi-bt mbed-cat1a mbed-cy8ckit-062-wifi-bt-cm4 mbed-cy8ckit-062-wifi-bt-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-4343w - mbed-cy8ckit-062-wifi-bt-whd mbed-udb-sdio-p12 ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8ckit-062-wifi-bt + INTERFACE + mbed-cm0p-sleep + ) +endif() + +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8ckit-062-wifi-bt + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-4343w + mbed-cy8ckit-062-wifi-bt-whd + ) +endif() + target_compile_definitions(mbed-cy8ckit-062-wifi-bt INTERFACE "CY8C6247BZI_D54" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/CMakeLists.txt index 5edf88d0c31..cb88e65846e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/CMakeLists.txt @@ -64,14 +64,26 @@ target_link_libraries(mbed-cy8cproto-062s3-4343w mbed-cat1a mbed-cy8cproto-062s3-4343w-cm4 mbed-cy8cproto-062s3-4343w-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-4343w - mbed-cy8cproto-062s3-4343w-whd mbed-cy-external-wifi-fw ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8cproto-062s3-4343w + INTERFACE + mbed-cm0p-sleep + ) +endif() + +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8cproto-062s3-4343w + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-4343w + mbed-cy8cproto-062s3-4343w-whd + ) +endif() + target_compile_definitions(mbed-cy8cproto-062s3-4343w INTERFACE "CY8C6245LQI_S3D72" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/CMakeLists.txt index 5490d9d0136..2c70a0af9c9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/CMakeLists.txt @@ -64,13 +64,25 @@ target_link_libraries(mbed-cy8cproto-062-4343w mbed-cat1a mbed-cy8cproto-062-4343w-cm4 mbed-cy8cproto-062-4343w-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-4343w - mbed-cy8cproto-062-4343w-whd ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8cproto-062-4343w + INTERFACE + mbed-cm0p-sleep + ) +endif() + +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cy8cproto-062-4343w + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-4343w + mbed-cy8cproto-062-4343w-whd + ) +endif() + target_compile_definitions(mbed-cy8cproto-062-4343w INTERFACE "CY8C624ABZI_D44" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/CMakeLists.txt index 0c4784db758..9c3afacb056 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYTFM_064B0S2_4343W/CMakeLists.txt @@ -58,11 +58,17 @@ target_link_libraries(mbed-cytfm-064b0s2-4343w mbed-cytfm-064b0s2-4343w-cm4 mbed-cytfm-064b0s2-4343w-bsp-design-modus mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-4343w - mbed-cytfm-064b0s2-4343w-whd ) +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cytfm-064b0s2-4343w + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-4343w + mbed-cytfm-064b0s2-4343w-whd + ) +endif() + target_compile_definitions(mbed-cytfm-064b0s2-4343w INTERFACE "CYB0644ABZI_S2D44" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/CMakeLists.txt index dc3a1e4f460..5d6d718d851 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/CMakeLists.txt @@ -65,14 +65,26 @@ target_link_libraries(mbed-cyw9p62s1-43012evb-01 mbed-cat1a mbed-cyw9p62s1-43012evb-01-cm4 mbed-cyw9p62s1-43012evb-01-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-43012 - mbed-cyw9p62s1-43012evb-01-whd mbed-udb-sdio-p12 ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cyw9p62s1-43012evb-01 + INTERFACE + mbed-cm0p-sleep + ) +endif() + +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cyw9p62s1-43012evb-01 + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-43012 + mbed-cyw9p62s1-43012evb-01-whd + ) +endif() + target_compile_definitions(mbed-cyw9p62s1-43012evb-01 INTERFACE "CY8C6247FDI_D52" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/CMakeLists.txt index 72531c1c0f1..ef6e56e39d2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/CMakeLists.txt @@ -64,14 +64,26 @@ target_link_libraries(mbed-cyw9p62s1-43438evb-01 mbed-cat1a mbed-cyw9p62s1-43438evb-01-cm4 mbed-cyw9p62s1-43438evb-01-bsp-design-modus - mbed-cm0p-sleep mbed-psoc6 - mbed-cy-psoc6-whd - mbed-cy-psoc6-whd-43438 - mbed-cyw9p62s1-43438evb-01-whd mbed-udb-sdio-p2 ) +if("CM0P_SLEEP" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cyw9p62s1-43438evb-01 + INTERFACE + mbed-cm0p-sleep + ) +endif() + +if("WHD" IN_LIST MBED_TARGET_LABELS) + target_link_libraries(mbed-cyw9p62s1-43438evb-01 + INTERFACE + mbed-cy-psoc6-whd + mbed-cy-psoc6-whd-43438 + mbed-cyw9p62s1-43438evb-01-whd + ) +endif() + target_compile_definitions(mbed-cyw9p62s1-43438evb-01 INTERFACE "CY8C6247BZI_D54" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c index 1d81de5a0c8..aacd42fc85d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_gpio_irq_api.c @@ -46,11 +46,11 @@ void cy_gpio_irq_handler_impl(void *handler_arg, cyhal_gpio_irq_event_t event) } } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { obj->pin = pin; obj->handler = (void *)handler; - obj->id = id; + obj->id = context; obj->mask = CYHAL_GPIO_IRQ_NONE; if (pin != NC) { gpio_irq_enable(obj); // InterruptIn expects IRQ to be initially enabled diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c index dee7cf2b252..ff41de8c0da 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_pwmout_api.c @@ -28,6 +28,8 @@ extern "C" { static const int CY_US_PER_SECOND = 1000000; static const int CY_US_PER_MS = 1000; +static float _percent = 0.0f; + void pwmout_init(pwmout_t *obj, PinName pin) { if (CY_RSLT_SUCCESS != cyhal_pwm_init(&(obj->hal_pwm), pin, NULL)) { @@ -35,6 +37,7 @@ void pwmout_init(pwmout_t *obj, PinName pin) } obj->period_us = 100; obj->width_us = 0; + _percent = 0.0f; } void pwmout_free(pwmout_t *obj) @@ -46,6 +49,7 @@ void pwmout_write(pwmout_t *obj, float percent) { MBED_ASSERT(percent >= 0.0f && percent <= 1.0f); pwmout_pulsewidth_us(obj, (int)(percent * obj->period_us)); + _percent = percent; } float pwmout_read(pwmout_t *obj) @@ -66,6 +70,9 @@ void pwmout_period_ms(pwmout_t *obj, int ms) void pwmout_period_us(pwmout_t *obj, int us) { obj->period_us = (uint32_t)us; + if (_percent != 0.0f) { + obj->width_us = (int)(_percent * obj->period_us); + } if (CY_RSLT_SUCCESS != cyhal_pwm_set_period(&(obj->hal_pwm), obj->period_us, obj->width_us)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_set_period"); } @@ -91,6 +98,7 @@ void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) void pwmout_pulsewidth_us(pwmout_t *obj, int us) { + _percent = 0.0f; obj->width_us = (uint32_t)us; if (CY_RSLT_SUCCESS != cyhal_pwm_set_period(&(obj->hal_pwm), obj->period_us, obj->width_us)) { MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_PWM, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_pwm_set_period"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c index 26086aa7bf2..65d02ea293d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c @@ -137,10 +137,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b } } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *ser = cy_serial_get_struct(obj); - ser->handler_arg = id; + ser->handler_arg = context; // The struct uses a different type because objects.h cannot include serial_api.h without creating a cycle ser->handler = (void *)handler; } diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c index 17022afcfa3..f5be345d07c 100644 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c @@ -23,7 +23,7 @@ #define CHANNEL_NUM 64 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; #define IRQ_DISABLED (0) @@ -44,7 +44,7 @@ static void handle_interrupt_in(PORT_Type *port, int ch_base) { location += 1 << (4 - i); } - uint32_t id = channel_ids[ch_base + location]; + uint32_t id = channel_contexts[ch_base + location]; if (id == 0) { continue; } @@ -75,7 +75,7 @@ static void handle_interrupt_in(PORT_Type *port, int ch_base) { void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);} void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);} -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) return -1; irq_handler = handler; @@ -102,13 +102,13 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 NVIC_EnableIRQ(irq_n); obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; + channel_contexts[obj->ch] = context; return 0; } void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c index 7da437b5197..cdb0e70270e 100644 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/serial_api.c @@ -52,7 +52,7 @@ * INITIALIZATION ******************************************************************************/ -static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; static uart_irq_handler irq_handler; int stdio_uart_inited = 0; @@ -124,7 +124,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } // serial_baud @@ -202,12 +202,12 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * INTERRUPTS HANDLING ******************************************************************************/ static inline void uart_irq(uint8_t status, uint32_t index) { - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (status & UARTLP_S1_TDRE_MASK) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (status & UARTLP_S1_RDRF_MASK) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -221,9 +221,9 @@ void uart1_irq() {uart_irq(UART1->S1, 1);} void uart2_irq() {uart_irq(UART2->S1, 2);} #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c index ebffa752923..f56d640b3b4 100644 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/gpio_irq_api.c @@ -23,7 +23,7 @@ #define CHANNEL_NUM 96 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; #define IRQ_DISABLED (0) @@ -44,7 +44,7 @@ static void handle_interrupt_in(PORT_Type *port, int ch_base) { location += 1 << (4 - i); } - uint32_t id = channel_ids[ch_base + location]; + uint32_t id = channel_contexts[ch_base + location]; if (id == 0) { continue; } @@ -91,7 +91,7 @@ void gpio_irqCD(void) { } } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) return -1; @@ -123,13 +123,13 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 NVIC_EnableIRQ(irq_n); obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; + channel_contexts[obj->ch] = context; return 0; } void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/serial_api.c b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/serial_api.c index f38c3c8424a..29f73a425a5 100644 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/serial_api.c @@ -52,7 +52,7 @@ * INITIALIZATION ******************************************************************************/ -static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; static uart_irq_handler irq_handler; int stdio_uart_inited = 0; @@ -124,7 +124,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } // serial_baud @@ -202,12 +202,12 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * INTERRUPTS HANDLING ******************************************************************************/ static inline void uart_irq(uint8_t status, uint32_t index) { - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (status & UARTLP_S1_TDRE_MASK) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (status & UARTLP_S1_RDRF_MASK) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -221,9 +221,9 @@ void uart1_irq() {uart_irq(UART1->S1, 1);} void uart2_irq() {uart_irq(UART2->S1, 2);} #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c index 44f776d2e1b..ac9b250b659 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c @@ -33,7 +33,7 @@ #include "dma_reqs.h" #include "fsl_clock_config.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_UART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static UART_Type *const uart_addrs[] = UART_BASE_PTRS; @@ -93,7 +93,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { UART_Deinit(uart_addrs[obj->serial.index]); - serial_irq_ids[obj->serial.index] = 0; + serial_irq_contexts[obj->serial.index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -141,12 +141,12 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint (void)base->D; } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_TxDataRegEmptyInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (receive_full && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_RxDataRegFullInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -180,10 +180,10 @@ void uart4_irq() uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->serial.index] = id; + serial_irq_contexts[obj->serial.index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c index 7e54d19c021..884d7897ac7 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c @@ -31,7 +31,7 @@ #include "PeripheralPins.h" #include "fsl_clock_config.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; @@ -101,7 +101,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { LPUART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -152,12 +152,12 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (LPUART_GetEnabledInterrupts(uart_addrs[index]) & kLPUART_TxDataRegEmptyInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (receive_full && (LPUART_GetEnabledInterrupts(uart_addrs[index]) & kLPUART_RxDataRegFullInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -191,10 +191,10 @@ void uart4_irq() uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c index 340400927e5..2ee0263d408 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c @@ -31,7 +31,7 @@ #include "PeripheralPins.h" #include "fsl_clock_config.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; @@ -84,7 +84,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { LPUART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -135,12 +135,12 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (LPUART_GetEnabledInterrupts(uart_addrs[index]) & kLPUART_TxDataRegEmptyInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (receive_full && (LPUART_GetEnabledInterrupts(uart_addrs[index]) & kLPUART_RxDataRegFullInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -156,10 +156,10 @@ void uart1_irq() uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c index 675e101e007..3807a0ead1c 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c @@ -31,7 +31,7 @@ #include "PeripheralPins.h" #include "fsl_clock_config.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_LPUART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; @@ -80,7 +80,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { LPUART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -131,12 +131,12 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (LPUART_GetEnabledInterrupts(uart_addrs[index]) & kLPUART_TxDataRegEmptyInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (receive_full && (LPUART_GetEnabledInterrupts(uart_addrs[index]) & kLPUART_RxDataRegFullInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -146,10 +146,10 @@ void uart0_irq() uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 0); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/serial_api.c index 25e8b8bd255..b564c268979 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/serial_api.c @@ -31,7 +31,7 @@ #include "PeripheralPins.h" #include "fsl_clock_config.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_UART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static UART_Type *const uart_addrs[] = UART_BASE_PTRS; @@ -79,7 +79,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { UART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -127,12 +127,12 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint (void)base->D; } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_TxDataRegEmptyInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (receive_full && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_RxDataRegFullInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -154,10 +154,10 @@ void uart2_irq() uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/serial_api.c index 0b16d007069..d21dc81c533 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/serial_api.c @@ -33,7 +33,7 @@ #include "dma_reqs.h" #include "fsl_clock_config.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_UART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static UART_Type *const uart_addrs[] = UART_BASE_PTRS; @@ -106,7 +106,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { UART_Deinit(uart_addrs[obj->serial.index]); - serial_irq_ids[obj->serial.index] = 0; + serial_irq_contexts[obj->serial.index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -152,13 +152,13 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint (void)base->D; } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_TxDataRegEmptyInterruptEnable)) { - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); } if (receive_full && (UART_GetEnabledInterrupts(uart_addrs[index]) & kUART_RxDataRegFullInterruptEnable)) { - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } } @@ -199,10 +199,10 @@ void uart5_irq() uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 5); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->serial.index] = id; + serial_irq_contexts[obj->serial.index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/gpio_irq_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/gpio_irq_api.c index ce51b07d2f4..18a75d04dad 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/gpio_irq_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/gpio_irq_api.c @@ -28,7 +28,7 @@ #define CHANNEL_NUM 160 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; /* Array of PORT peripheral base address. */ static PORT_Type *const port_addrs[] = PORT_BASE_PTRS; @@ -51,8 +51,8 @@ static void handle_interrupt_in(PortName port, int ch_base) for (i = 0; i < 32; i++) { if (interrupt_flags & (1 << i)) { - uint32_t id = channel_ids[ch_base + i]; - if (id == 0) { + uintptr_t context = channel_contexts[ch_base + i]; + if (context == 0) { continue; } @@ -74,7 +74,7 @@ static void handle_interrupt_in(PortName port, int ch_base) break; } if (event != IRQ_NONE) { - irq_handler(id, event); + irq_handler(context, event); } } } @@ -106,7 +106,7 @@ void gpio_irqE(void) handle_interrupt_in(PortE, 128); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -148,14 +148,14 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 NVIC_EnableIRQ(port_irqs[obj->port]); obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; + channel_contexts[obj->ch] = context; return 0; } void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c index db92b9db4da..afdc8722cd3 100644 --- a/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/can_api.c @@ -38,7 +38,7 @@ /* CAN1 interrupt vector number */ #define CAN1_IRQ_BASE_NUM 63 -static uint32_t can_irq_ids[2] = {0}; +static uintptr_t can_irq_contexts[2] = {0}; static can_irq_handler irq_callback; /** CAN interrupt handle . @@ -66,13 +66,13 @@ static void dev_can_irq_handle(uint32_t periph, int id) /* CAN transmit complete interrupt handle */ if (flag0 || flag1 || flag2) { - irq_callback(can_irq_ids[id], IRQ_TX); + irq_callback(can_irq_contexts[id], IRQ_TX); } /* CAN receive complete interrupt handle */ if (CAN_INTEN_RFNEIE0 == (CAN_INTEN(periph) & CAN_INTEN_RFNEIE0)) { if (0 != can_receive_message_length_get(periph, CAN_FIFO0)) { - irq_callback(can_irq_ids[id], IRQ_RX); + irq_callback(can_irq_contexts[id], IRQ_RX); } } @@ -81,18 +81,18 @@ static void dev_can_irq_handle(uint32_t periph, int id) /* passive error interrupt handle */ if (CAN_INTEN_PERRIE == (CAN_INTEN(periph) & CAN_INTEN_PERRIE)) { if (SET == can_flag_get(periph, CAN_FLAG_PERR)) { - irq_callback(can_irq_ids[id], IRQ_PASSIVE); + irq_callback(can_irq_contexts[id], IRQ_PASSIVE); } } /* bus-off interrupt handle */ if (CAN_INTEN_BOIE == (CAN_INTEN(periph) & CAN_INTEN_BOIE)) { if (SET == can_flag_get(periph, CAN_FLAG_BOERR)) { - irq_callback(can_irq_ids[id], IRQ_BUS); + irq_callback(can_irq_contexts[id], IRQ_BUS); } } - irq_callback(can_irq_ids[id], IRQ_ERROR); + irq_callback(can_irq_contexts[id], IRQ_ERROR); } } @@ -330,10 +330,10 @@ int can_frequency(can_t *obj, int hz) * @param handler the interrupt callback. * @param id the CANx index. */ -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_callback = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } /** disable the interrupt. @@ -351,7 +351,7 @@ void can_irq_free(can_t *obj) CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); } - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; } /** Set the interrupt handle. diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c index c48633977e5..7fe969035f2 100644 --- a/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/gpio_irq_api.c @@ -29,7 +29,7 @@ extern uint32_t gpio_clock_enable(uint32_t port_idx); static gpio_irq_handler irq_handler; typedef struct { - uint32_t exti_idx; + uintptr_t exti_contextx; uint32_t exti_gpiox; /* base address of gpio */ uint32_t exti_pinx; /* pin number */ } gpio_exti_info_struct; @@ -54,9 +54,9 @@ static void exti_handle_interrupt(uint32_t irq_index) exti_interrupt_flag_clear((exti_line_enum)pin); /* check which edge has generated the irq */ if ((GPIO_ISTAT(gpio) & pin) == 0) { - irq_handler(gpio_exti->exti_idx, IRQ_FALL); + irq_handler(gpio_exti->exti_contextx, IRQ_FALL); } else { - irq_handler(gpio_exti->exti_idx, IRQ_RISE); + irq_handler(gpio_exti->exti_contextx, IRQ_RISE); } } @@ -148,10 +148,10 @@ static void gpio_irq_exti15(void) * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) + * @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { uint32_t vector = 0; gpio_exti_info_struct *gpio_exti; @@ -243,7 +243,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; gpio_exti = &exti_info_array[obj->irq_index]; - gpio_exti->exti_idx = id; + gpio_exti->exti_contextx = context; gpio_exti->exti_gpiox = gpio_add; gpio_exti->exti_pinx = pin_index; @@ -267,7 +267,7 @@ void gpio_irq_free(gpio_irq_t *obj) /* Disable EXTI interrupt */ gpio_irq_disable(obj); /* Reset struct of exti information */ - gpio_exti->exti_idx = 0; + gpio_exti->exti_contextx = 0; gpio_exti->exti_gpiox = 0; gpio_exti->exti_pinx = 0; } diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c index 50347de3ff0..bc60e8e8459 100644 --- a/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c +++ b/targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c @@ -28,7 +28,7 @@ #define USART_NUM (5) -static uint32_t serial_irq_ids[USART_NUM] = {0}; +static uintptr_t serial_irq_contexts[USART_NUM] = {0}; static rcu_periph_enum usart_clk[USART_NUM] = {RCU_USART0, RCU_USART1, RCU_USART2, RCU_UART3, RCU_UART4}; static IRQn_Type usart_irq_n[USART_NUM] = {USART0_IRQn, USART1_IRQn, USART2_IRQn, UART3_IRQn, UART4_IRQn}; @@ -159,7 +159,7 @@ void serial_free(serial_t *obj) usart_deinit(p_obj->uart); rcu_periph_clock_disable(rcu_periph); - serial_irq_ids[p_obj->index] = 0; + serial_irq_contexts[p_obj->index] = 0; /* reset the GPIO state */ pin_function(p_obj->pin_tx, MODE_IN_FLOATING); @@ -266,12 +266,12 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * @param handler The interrupt handler which will be invoked when the interrupt fires * @param id The SerialBase object */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *p_obj = GET_SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[p_obj->index] = id; + serial_irq_contexts[p_obj->index] = context; } /** This function handles USART interrupt handler @@ -281,15 +281,15 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) */ static void usart_irq(int usart_index, uint32_t usart_periph) { - if (serial_irq_ids[usart_index] != 0) { + if (serial_irq_contexts[usart_index] != 0) { if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_TC) != RESET) { usart_interrupt_flag_clear(usart_periph, USART_FLAG_TC); - irq_handler(serial_irq_ids[usart_index], TxIrq); + irq_handler(serial_irq_contexts[usart_index], TxIrq); } if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_RBNE) != RESET) { usart_interrupt_flag_clear(usart_periph, USART_FLAG_RBNE); - irq_handler(serial_irq_ids[usart_index], RxIrq); + irq_handler(serial_irq_contexts[usart_index], RxIrq); } if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_ORERR) != RESET) { diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/can_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/can_api.c index 15c67b17260..79614ff053f 100644 --- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/can_api.c +++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/can_api.c @@ -38,7 +38,7 @@ /* CAN1 interrupt vector number */ #define CAN1_IRQ_BASE_NUM 63 -static uint32_t can_irq_ids[2] = {0}; +static uintptr_t can_irq_contexts[2] = {0}; static can_irq_handler irq_callback; /** CAN interrupt handle . @@ -66,13 +66,13 @@ static void dev_can_irq_handle(uint32_t periph, int id) /* CAN transmit complete interrupt handle */ if (flag0 || flag1 || flag2) { - irq_callback(can_irq_ids[id], IRQ_TX); + irq_callback(can_irq_contexts[id], IRQ_TX); } /* CAN receive complete interrupt handle */ if (CAN_INTEN_RFNEIE0 == (CAN_INTEN(periph) & CAN_INTEN_RFNEIE0)) { if (0 != can_receive_message_length_get(periph, CAN_FIFO0)) { - irq_callback(can_irq_ids[id], IRQ_RX); + irq_callback(can_irq_contexts[id], IRQ_RX); } } @@ -81,18 +81,18 @@ static void dev_can_irq_handle(uint32_t periph, int id) /* passive error interrupt handle */ if (CAN_INTEN_PERRIE == (CAN_INTEN(periph) & CAN_INTEN_PERRIE)) { if (SET == can_flag_get(periph, CAN_FLAG_PERR)) { - irq_callback(can_irq_ids[id], IRQ_PASSIVE); + irq_callback(can_irq_contexts[id], IRQ_PASSIVE); } } /* bus-off interrupt handle */ if (CAN_INTEN_BOIE == (CAN_INTEN(periph) & CAN_INTEN_BOIE)) { if (SET == can_flag_get(periph, CAN_FLAG_BOERR)) { - irq_callback(can_irq_ids[id], IRQ_BUS); + irq_callback(can_irq_contexts[id], IRQ_BUS); } } - irq_callback(can_irq_ids[id], IRQ_ERROR); + irq_callback(can_irq_contexts[id], IRQ_ERROR); } } @@ -331,10 +331,10 @@ int can_frequency(can_t *obj, int hz) * @param handler the interrupt callback. * @param id the CANx index. */ -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_callback = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } /** disable the interrupt. @@ -352,7 +352,7 @@ void can_irq_free(can_t *obj) CAN_INTEN_PERRIE | CAN_INTEN_BOIE | CAN_INTEN_ERRIE); } - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; } /** Set the interrupt handle. diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/gpio_irq_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/gpio_irq_api.c index a248f1e7851..a964cbe4e6a 100644 --- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/gpio_irq_api.c +++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/gpio_irq_api.c @@ -29,7 +29,7 @@ extern uint32_t gpio_clock_enable(uint32_t port_idx); static gpio_irq_handler irq_handler; typedef struct { - uint32_t exti_idx; + uintptr_t exti_contextx; uint32_t exti_gpiox; /* base address of gpio */ uint32_t exti_pinx; /* pin number */ } gpio_exti_info_struct; @@ -54,9 +54,9 @@ static void exti_handle_interrupt(uint32_t irq_index) exti_interrupt_flag_clear((exti_line_enum)pin); /* check which edge has generated the irq */ if ((GPIO_ISTAT(gpio) & pin) == 0) { - irq_handler(gpio_exti->exti_idx, IRQ_FALL); + irq_handler(gpio_exti->exti_contextx, IRQ_FALL); } else { - irq_handler(gpio_exti->exti_idx, IRQ_RISE); + irq_handler(gpio_exti->exti_contextx, IRQ_RISE); } } } @@ -147,10 +147,10 @@ static void gpio_irq_exti15(void) * @param obj The GPIO object to initialize * @param pin The GPIO pin name * @param handler The handler to be attached to GPIO IRQ - * @param id The object ID (id != 0, 0 is reserved) + * @param context The context to be passed back to the handler (context != 0, 0 is reserved) * @return -1 if pin is NC, 0 otherwise */ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { uint32_t vector = 0; gpio_exti_info_struct *gpio_exti; @@ -245,7 +245,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; gpio_exti = &exti_info_array[obj->irq_index]; - gpio_exti->exti_idx = id; + gpio_exti->exti_contextx = context; gpio_exti->exti_gpiox = gpio_add; gpio_exti->exti_pinx = pin_index; @@ -269,7 +269,7 @@ void gpio_irq_free(gpio_irq_t *obj) /* disable EXTI interrupt */ gpio_irq_disable(obj); /* reset struct of EXTI information */ - gpio_exti->exti_idx = 0; + gpio_exti->exti_contextx = 0; gpio_exti->exti_gpiox = 0; gpio_exti->exti_pinx = 0; } diff --git a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/serial_api.c b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/serial_api.c index 5fd4ee48355..10e5c514b99 100644 --- a/targets/TARGET_GigaDevice/TARGET_GD32F4XX/serial_api.c +++ b/targets/TARGET_GigaDevice/TARGET_GD32F4XX/serial_api.c @@ -28,7 +28,7 @@ #define USART_NUM (8) -static uint32_t serial_irq_ids[USART_NUM] = {0}; +static uintptr_t serial_irq_contexts[USART_NUM] = {0}; static rcu_periph_enum usart_clk[USART_NUM] = {RCU_USART0, RCU_USART1, RCU_USART2, RCU_UART3, RCU_UART4, RCU_USART5, RCU_UART6, RCU_UART7 }; @@ -172,7 +172,7 @@ void serial_free(serial_t *obj) usart_deinit(p_obj->uart); rcu_periph_clock_disable(rcu_periph); - serial_irq_ids[p_obj->index] = 0; + serial_irq_contexts[p_obj->index] = 0; /* reset the GPIO state */ pin_function(p_obj->pin_tx, PullNone); @@ -279,12 +279,12 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b * @param handler The interrupt handler which will be invoked when the interrupt fires * @param id The SerialBase object */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *p_obj = GET_SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[p_obj->index] = id; + serial_irq_contexts[p_obj->index] = context; } /** This function handles USART interrupt handler @@ -294,15 +294,15 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) */ static void usart_irq(int usart_index, uint32_t usart_periph) { - if (serial_irq_ids[usart_index] != 0) { + if (serial_irq_contexts[usart_index] != 0) { if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_TC) != RESET) { usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_TC); - irq_handler(serial_irq_ids[usart_index], TxIrq); + irq_handler(serial_irq_contexts[usart_index], TxIrq); } if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_RBNE) != RESET) { usart_interrupt_flag_clear(usart_periph, USART_INT_FLAG_RBNE); - irq_handler(serial_irq_ids[usart_index], RxIrq); + irq_handler(serial_irq_contexts[usart_index], RxIrq); } if (usart_interrupt_flag_get(usart_periph, USART_INT_FLAG_ERR_ORERR) != RESET) { diff --git a/targets/TARGET_Maxim/CMakeLists.txt b/targets/TARGET_Maxim/CMakeLists.txt index 3b4402d8539..bdbb751ca23 100644 --- a/targets/TARGET_Maxim/CMakeLists.txt +++ b/targets/TARGET_Maxim/CMakeLists.txt @@ -5,6 +5,7 @@ add_subdirectory(TARGET_MAX32620C EXCLUDE_FROM_ALL) add_subdirectory(TARGET_MAX32625 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_MAX32630 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_MAX32660 EXCLUDE_FROM_ALL) add_library(mbed-maxim INTERFACE) diff --git a/targets/TARGET_Maxim/TARGET_MAX32620C/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32620C/gpio_irq_api.c index 3157cbeca1d..e699927167c 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32620C/gpio_irq_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32620C/gpio_irq_api.c @@ -78,7 +78,7 @@ void gpio_irq_4(void) { handle_irq(4); } void gpio_irq_5(void) { handle_irq(5); } void gpio_irq_6(void) { handle_irq(6); } -int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uintptr_t context) { if (name == NC) { return -1; @@ -93,7 +93,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3 obj->port = port; obj->pin = pin; - obj->id = id; + obj->id = context; objs[port][pin] = obj; /* register handlers */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32620C/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32620C/serial_api.c index b51826815bf..c5103418a8f 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32620C/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32620C/serial_api.c @@ -203,10 +203,10 @@ void uart2_handler(void) { uart_handler(objs[2]); } void uart3_handler(void) { uart_handler(objs[3]); } //****************************************************************************** -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - obj->id = id; + obj->id = context; } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/startup_MAX32625.S b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/startup_MAX32625.S index da2c479093d..40eb5867297 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/startup_MAX32625.S +++ b/targets/TARGET_Maxim/TARGET_MAX32625/device/TOOLCHAIN_ARM_STD/startup_MAX32625.S @@ -138,47 +138,47 @@ __SPIN NMI_Handler PROC EXPORT NMI_Handler [WEAK] - B NMI_Handler + B . ENDP HardFault_Handler PROC EXPORT HardFault_Handler [WEAK] - B HardFault_Handler + B . ENDP MemManage_Handler PROC EXPORT MemManage_Handler [WEAK] - B MemManage_Handler + B . ENDP BusFault_Handler PROC EXPORT BusFault_Handler [WEAK] - B BusFault_Handler + B . ENDP UsageFault_Handler PROC EXPORT UsageFault_Handler [WEAK] - B UsageFault_Handler + B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] - B SVC_Handler + B . ENDP DebugMon_Handler PROC EXPORT DebugMon_Handler [WEAK] - B DebugMon_Handler + B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] - B PendSV_Handler + B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] - B SysTick_Handler + B . ENDP Default_Handler PROC diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/gpio_irq_api.c index ead582a1bb8..d8b579e0edd 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/gpio_irq_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/gpio_irq_api.c @@ -76,7 +76,7 @@ void gpio_irq_2(void) { handle_irq(2); } void gpio_irq_3(void) { handle_irq(3); } void gpio_irq_4(void) { handle_irq(4); } -int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uintptr_t context) { if (name == NC) { return -1; @@ -91,7 +91,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3 obj->port = port; obj->pin = pin; - obj->id = id; + obj->id = context; objs[port][pin] = obj; /* register handlers */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c index 7fc1cc09001..02e4a9fc6f6 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c @@ -206,10 +206,10 @@ void uart1_handler(void) { uart_handler(objs[1]); } void uart2_handler(void) { uart_handler(objs[2]); } //****************************************************************************** -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - obj->id = id; + obj->id = context; } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S index a3f202abdca..09da9063a9a 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S +++ b/targets/TARGET_Maxim/TARGET_MAX32630/device/TOOLCHAIN_ARM_STD/startup_MAX3263x.S @@ -138,47 +138,47 @@ __SPIN NMI_Handler PROC EXPORT NMI_Handler [WEAK] - B NMI_Handler + B . ENDP HardFault_Handler PROC EXPORT HardFault_Handler [WEAK] - B HardFault_Handler + B . ENDP MemManage_Handler PROC EXPORT MemManage_Handler [WEAK] - B MemManage_Handler + B . ENDP BusFault_Handler PROC EXPORT BusFault_Handler [WEAK] - B BusFault_Handler + B . ENDP UsageFault_Handler PROC EXPORT UsageFault_Handler [WEAK] - B UsageFault_Handler + B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] - B SVC_Handler + B . ENDP DebugMon_Handler PROC EXPORT DebugMon_Handler [WEAK] - B DebugMon_Handler + B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] - B PendSV_Handler + B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] - B SysTick_Handler + B . ENDP Default_Handler PROC diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c index 8a9e7bb4221..20037621389 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c @@ -80,7 +80,7 @@ void gpio_irq_6(void) { handle_irq(6); } void gpio_irq_7(void) { handle_irq(7); } void gpio_irq_8(void) { handle_irq(8); } -int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uintptr_t context) { if (name == NC) { return -1; @@ -95,7 +95,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3 obj->port = port; obj->pin = pin; - obj->id = id; + obj->id = context; objs[port][pin] = obj; /* register handlers */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c index aa0a86f76ba..3485f6a73b4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c @@ -127,10 +127,10 @@ time_t rtc_read(void) //****************************************************************************** void lp_ticker_init(void) { + init_rtc(); RTC_DisableINT(MXC_F_RTC_INTEN_COMP0); NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler); NVIC_EnableIRQ(RTC0_IRQn); - init_rtc(); } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c index b9bbc9ed78f..0ea0da50279 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c @@ -202,10 +202,10 @@ void uart2_handler(void) { uart_handler(objs[2]); } void uart3_handler(void) { uart_handler(objs[3]); } //****************************************************************************** -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - obj->id = id; + obj->id = context; } //****************************************************************************** diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/CMakeLists.txt b/targets/TARGET_Maxim/TARGET_MAX32660/CMakeLists.txt new file mode 100644 index 00000000000..cf5339074a4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/CMakeLists.txt @@ -0,0 +1,120 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TARGET_MAX32660EVSYS EXCLUDE_FROM_ALL) + +if(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MAX32660.sct) + set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_max32660.S) +elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/max32660.ld) + set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_max32660.S) +endif() + +add_library(mbed-max32660 INTERFACE) +mbed_set_linker_script(mbed-max32660 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +set(MXM_PARTNUMBER MAX32660) +set(MXM_SOURCE_DIR ./Libraries/PeriphDrivers/Source) +set(MXM_PERIPH_DRIVER_DIR ./Libraries/PeriphDrivers) +set(MXM_CMSIS_DIR ./Libraries/CMSIS/Device/Maxim) + +target_include_directories(mbed-max32660 + INTERFACE + . + device + + ${MXM_PERIPH_DRIVER_DIR}/Include/${MXM_PARTNUMBER} + ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Include + + ${MXM_SOURCE_DIR}/DMA + ${MXM_SOURCE_DIR}/LP + ${MXM_SOURCE_DIR}/FLC + ${MXM_SOURCE_DIR}/GPIO + ${MXM_SOURCE_DIR}/I2C + ${MXM_SOURCE_DIR}/ICC + ${MXM_SOURCE_DIR}/RTC + ${MXM_SOURCE_DIR}/SPI + ${MXM_SOURCE_DIR}/SPIMSS + ${MXM_SOURCE_DIR}/TMR + ${MXM_SOURCE_DIR}/UART + ${MXM_SOURCE_DIR}/WDT +) + +target_sources(mbed-max32660 + INTERFACE + PeripheralPins.c + gpio_api.c + gpio_irq_api.c + i2c_api.c + pinmap.c + port_api.c + rtc_api.c + serial_api.c + sleep.c + spi_api.c + us_ticker.c + lp_ticker.c + flash_api.c + watchdog_api.c + + ${MXM_CMSIS_DIR}/${MXM_PARTNUMBER}/Source/system_max32660.c + + ${MXM_SOURCE_DIR}/SYS/mxc_assert.c + ${MXM_SOURCE_DIR}/SYS/mxc_delay.c + ${MXM_SOURCE_DIR}/SYS/mxc_lock.c + ${MXM_SOURCE_DIR}/SYS/pins_me11.c + ${MXM_SOURCE_DIR}/SYS/sys_me11.c + + ${MXM_SOURCE_DIR}/DMA/dma_me11.c + ${MXM_SOURCE_DIR}/DMA/dma_reva.c + + ${MXM_SOURCE_DIR}/LP/lp_me11.c + + ${MXM_SOURCE_DIR}/FLC/flc_common.c + ${MXM_SOURCE_DIR}/FLC/flc_me11.c + ${MXM_SOURCE_DIR}/FLC/flc_reva.c + + ${MXM_SOURCE_DIR}/GPIO/gpio_common.c + ${MXM_SOURCE_DIR}/GPIO/gpio_me11.c + ${MXM_SOURCE_DIR}/GPIO/gpio_reva.c + + ${MXM_SOURCE_DIR}/I2C/i2c_me11.c + ${MXM_SOURCE_DIR}/I2C/i2c_reva.c + + ${MXM_SOURCE_DIR}/SPIMSS/spimss_me11.c + ${MXM_SOURCE_DIR}/SPIMSS/spimss_reva.c + ${MXM_SOURCE_DIR}/SPIMSS/i2s_me11.c + ${MXM_SOURCE_DIR}/SPIMSS/i2s_reva.c + + ${MXM_SOURCE_DIR}/ICC/icc_common.c + ${MXM_SOURCE_DIR}/ICC/icc_me11.c + ${MXM_SOURCE_DIR}/ICC/icc_reva.c + + ${MXM_SOURCE_DIR}/RTC/rtc_me11.c + ${MXM_SOURCE_DIR}/RTC/rtc_reva.c + + ${MXM_SOURCE_DIR}/SPI/spi_me11.c + ${MXM_SOURCE_DIR}/SPI/spi_reva.c + + ${MXM_SOURCE_DIR}/TMR/tmr_common.c + ${MXM_SOURCE_DIR}/TMR/tmr_me11.c + ${MXM_SOURCE_DIR}/TMR/tmr_reva.c + + ${MXM_SOURCE_DIR}/UART/uart_common.c + ${MXM_SOURCE_DIR}/UART/uart_me11.c + ${MXM_SOURCE_DIR}/UART/uart_reva.c + + ${MXM_SOURCE_DIR}/WDT/wdt_common.c + ${MXM_SOURCE_DIR}/WDT/wdt_me11.c + ${MXM_SOURCE_DIR}/WDT/wdt_reva.c + + ${STARTUP_FILE} +) + +target_link_libraries(mbed-max32660 + INTERFACE + mbed-maxim +) + + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h new file mode 100644 index 00000000000..cf370a9d4d4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h @@ -0,0 +1,390 @@ +/** + * @file dma_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _DMA_REGS_H_ +#define _DMA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dma + * @defgroup dma_registers DMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @details DMA Controller Fully programmable, chaining capable DMA channels. + */ + +/** + * @ingroup dma_registers + * Structure type to access the DMA Channel Registers. + */ +typedef struct { + __IO uint32_t cfg; /**< \b 0x100: DMA CFG Register */ + __IO uint32_t stat; /**< \b 0x104: DMA STAT Register */ + __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ + __IO uint32_t src_rld; /**< \b 0x114: DMA SRC_RLD Register */ + __IO uint32_t dst_rld; /**< \b 0x118: DMA DST_RLD Register */ + __IO uint32_t cnt_rld; /**< \b 0x11C: DMA CNT_RLD Register */ +} mxc_dma_ch_regs_t; + +/** + * @ingroup dma_registers + * Structure type to access the DMA Registers. + */ +typedef struct { + __IO uint32_t int_en; /**< \b 0x000: DMA INT_EN Register */ + __I uint32_t int_fl; /**< \b 0x004: DMA INT_FL Register */ + __I uint32_t rsv_0x8_0xff[62]; + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ +} mxc_dma_regs_t; + +/* Register offsets for module DMA */ +/** + * @ingroup dma_registers + * @defgroup DMA_Register_Offsets Register Offsets + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @{ + */ + #define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ + #define MXC_R_DMA_STAT ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ + #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ + #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ + #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ + #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ + #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ + #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ + #define MXC_R_DMA_INT_EN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ + #define MXC_R_DMA_INT_FL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ + #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +/**@} end of group dma_registers */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INT_EN DMA_INT_EN + * @brief DMA Control Register. + * @{ + */ + #define MXC_F_DMA_INT_EN_CHIEN_POS 0 /**< INT_EN_CHIEN Position */ + #define MXC_F_DMA_INT_EN_CHIEN ((uint32_t)(0xFUL << MXC_F_DMA_INT_EN_CHIEN_POS)) /**< INT_EN_CHIEN Mask */ + #define MXC_V_DMA_INT_EN_CHIEN_DIS ((uint32_t)0x0UL) /**< INT_EN_CHIEN_DIS Value */ + #define MXC_S_DMA_INT_EN_CHIEN_DIS (MXC_V_DMA_INT_EN_CHIEN_DIS << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_DIS Setting */ + #define MXC_V_DMA_INT_EN_CHIEN_EN ((uint32_t)0x1UL) /**< INT_EN_CHIEN_EN Value */ + #define MXC_S_DMA_INT_EN_CHIEN_EN (MXC_V_DMA_INT_EN_CHIEN_EN << MXC_F_DMA_INT_EN_CHIEN_POS) /**< INT_EN_CHIEN_EN Setting */ + +/**@} end of group DMA_INT_EN_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INT_FL DMA_INT_FL + * @brief DMA Interrupt Register. + * @{ + */ + #define MXC_F_DMA_INT_FL_IPEND_POS 0 /**< INT_FL_IPEND Position */ + #define MXC_F_DMA_INT_FL_IPEND ((uint32_t)(0xFUL << MXC_F_DMA_INT_FL_IPEND_POS)) /**< INT_FL_IPEND Mask */ + #define MXC_V_DMA_INT_FL_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IPEND_INACTIVE Value */ + #define MXC_S_DMA_INT_FL_IPEND_INACTIVE (MXC_V_DMA_INT_FL_IPEND_INACTIVE << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_INACTIVE Setting */ + #define MXC_V_DMA_INT_FL_IPEND_PENDING ((uint32_t)0x1UL) /**< INT_FL_IPEND_PENDING Value */ + #define MXC_S_DMA_INT_FL_IPEND_PENDING (MXC_V_DMA_INT_FL_IPEND_PENDING << MXC_F_DMA_INT_FL_IPEND_POS) /**< INT_FL_IPEND_PENDING Setting */ + +/**@} end of group DMA_INT_FL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CFG DMA_CFG + * @brief DMA Channel Configuration Register. + * @{ + */ + #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ + #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ + + #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ + #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ + + #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ + #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ + #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ + #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ + #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ + #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ + #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ + #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ + #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ + #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ + + #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ + #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ + #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ + #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ + + #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ + #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ + + #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ + #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ + #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ + + #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ + #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ + #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ + #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ + + #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ + #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ + #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ + #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ + #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ + #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ + #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ + #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ + + #define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */ + #define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */ + + #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ + #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ + #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ + #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ + #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ + #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ + #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ + #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ + + #define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ + #define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ + + #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ + #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ + + #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ + #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ + + #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ + #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ + +/**@} end of group DMA_CFG_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_STAT DMA_STAT + * @brief DMA Channel Status Register. + * @{ + */ + #define MXC_F_DMA_STAT_CH_ST_POS 0 /**< STAT_CH_ST Position */ + #define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS)) /**< STAT_CH_ST Mask */ + + #define MXC_F_DMA_STAT_IPEND_POS 1 /**< STAT_IPEND Position */ + #define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS)) /**< STAT_IPEND Mask */ + + #define MXC_F_DMA_STAT_CTZ_ST_POS 2 /**< STAT_CTZ_ST Position */ + #define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS)) /**< STAT_CTZ_ST Mask */ + + #define MXC_F_DMA_STAT_RLD_ST_POS 3 /**< STAT_RLD_ST Position */ + #define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS)) /**< STAT_RLD_ST Mask */ + + #define MXC_F_DMA_STAT_BUS_ERR_POS 4 /**< STAT_BUS_ERR Position */ + #define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS)) /**< STAT_BUS_ERR Mask */ + + #define MXC_F_DMA_STAT_TO_ST_POS 6 /**< STAT_TO_ST Position */ + #define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS)) /**< STAT_TO_ST Mask */ + +/**@} end of group DMA_STAT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC DMA_SRC + * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or + * 4, depending on the data width of each AHB cycle. For peripheral transfers, some + * or all of the actual address bits are fixed. If SRCINC=0, this register remains + * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the + * register is reloaded with the contents of DMA_SRC_RLD. + * @{ + */ + #define MXC_F_DMA_SRC_SRC_POS 0 /**< SRC_SRC Position */ + #define MXC_F_DMA_SRC_SRC ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_SRC_POS)) /**< SRC_SRC Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST DMA_DST + * @brief Destination Device Address. For peripheral transfers, some or all of the actual + * address bits are fixed. If DSTINC=1, this register is incremented on every AHB + * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the + * data width of each AHB cycle. In the case where a count-to-zero condition occurs + * while RLDEN=1, the register is reloaded with DMA_DST_RLD. + * @{ + */ + #define MXC_F_DMA_DST_DST_POS 0 /**< DST_DST Position */ + #define MXC_F_DMA_DST_DST ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_DST_POS)) /**< DST_DST Mask */ + +/**@} end of group DMA_DST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT DMA_CNT + * @brief DMA Counter. The user loads this register with the number of bytes to transfer. + * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will + * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter + * reaches 0, a count-to-zero condition is triggered. + * @{ + */ + #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ + #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC_RLD DMA_SRC_RLD + * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC + * upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ + #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ + +/**@} end of group DMA_SRC_RLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST_RLD DMA_DST_RLD + * @brief Destination Address Reload Value. The value of this register is loaded into + * DMA0_DST upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ + #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ + +/**@} end of group DMA_DST_RLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT_RLD DMA_CNT_RLD + * @brief DMA Channel Count Reload Register. + * @{ + */ + #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ + #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ + + #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ + #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ + +/**@} end of group DMA_CNT_RLD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _DMA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h new file mode 100644 index 00000000000..6ece5a1ccfd --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h @@ -0,0 +1,124 @@ +/** + * @file fcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _FCR_REGS_H_ +#define _FCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup fcr + * @defgroup fcr_registers FCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @details Function Control. + */ + +/** + * @ingroup fcr_registers + * Structure type to access the FCR Registers. + */ +typedef struct { + __IO uint32_t reg0; /**< \b 0x00: FCR REG0 Register */ +} mxc_fcr_regs_t; + +/* Register offsets for module FCR */ +/** + * @ingroup fcr_registers + * @defgroup FCR_Register_Offsets Register Offsets + * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. + * @{ + */ + #define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ +/**@} end of group fcr_registers */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_REG0 FCR_REG0 + * @brief Register 0. + * @{ + */ + #define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS 20 /**< REG0_I2C0_SDA_FILTER_EN Position */ + #define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS)) /**< REG0_I2C0_SDA_FILTER_EN Mask */ + + #define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS 21 /**< REG0_I2C0_SCL_FILTER_EN Position */ + #define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS)) /**< REG0_I2C0_SCL_FILTER_EN Mask */ + + #define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS 22 /**< REG0_I2C1_SDA_FILTER_EN Position */ + #define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS)) /**< REG0_I2C1_SDA_FILTER_EN Mask */ + + #define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS 23 /**< REG0_I2C1_SCL_FILTER_EN Position */ + #define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS)) /**< REG0_I2C1_SCL_FILTER_EN Mask */ + +/**@} end of group FCR_REG0_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FCR_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h new file mode 100644 index 00000000000..f1f2d701dc8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h @@ -0,0 +1,228 @@ +/** + * @file flc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _FLC_REGS_H_ +#define _FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers FLC_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ + __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ + __I uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ + __I uint32_t rsv_0x28_0x2f[2]; + __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ + __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ +} mxc_flc_regs_t; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ + #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ + #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ + #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ + #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ + #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ + #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ADDR FLC_ADDR + * @brief Flash Write Address. + * @{ + */ + #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ + #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CLKDIV FLC_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ + #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ + #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CTRL FLC_CTRL + * @brief Flash Control Register. + * @{ + */ + #define MXC_F_FLC_CTRL_WRITE_POS 0 /**< CTRL_WRITE Position */ + #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WRITE_POS)) /**< CTRL_WRITE Mask */ + + #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1 /**< CTRL_MASS_ERASE Position */ + #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_MASS_ERASE_POS)) /**< CTRL_MASS_ERASE Mask */ + + #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2 /**< CTRL_PAGE_ERASE Position */ + #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS)) /**< CTRL_PAGE_ERASE Mask */ + + #define MXC_F_FLC_CTRL_WIDTH_POS 4 /**< CTRL_WIDTH Position */ + #define MXC_F_FLC_CTRL_WIDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WIDTH_POS)) /**< CTRL_WIDTH Mask */ + + #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ + #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ + #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ + #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ + #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ + #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ + #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ + #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ + + #define MXC_F_FLC_CTRL_BUSY_POS 24 /**< CTRL_BUSY Position */ + #define MXC_F_FLC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + + #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ + #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ + + #define MXC_F_FLC_CTRL_UNLOCK_CODE_POS 28 /**< CTRL_UNLOCK_CODE Position */ + #define MXC_F_FLC_CTRL_UNLOCK_CODE ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_CODE_POS)) /**< CTRL_UNLOCK_CODE Mask */ + #define MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_CODE_UNLOCKED Value */ + #define MXC_S_FLC_CTRL_UNLOCK_CODE_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_UNLOCKED Setting */ + #define MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_CODE_LOCKED Value */ + #define MXC_S_FLC_CTRL_UNLOCK_CODE_LOCKED (MXC_V_FLC_CTRL_UNLOCK_CODE_LOCKED << MXC_F_FLC_CTRL_UNLOCK_CODE_POS) /**< CTRL_UNLOCK_CODE_LOCKED Setting */ + +/**@} end of group FLC_CTRL_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_INTR FLC_INTR + * @brief Flash Interrupt Register. + * @{ + */ + #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ + #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ + + #define MXC_F_FLC_INTR_ACCESS_FAIL_POS 1 /**< INTR_ACCESS_FAIL Position */ + #define MXC_F_FLC_INTR_ACCESS_FAIL ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_POS)) /**< INTR_ACCESS_FAIL Mask */ + + #define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ + #define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ + + #define MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS 9 /**< INTR_ACCESS_FAIL_IE Position */ + #define MXC_F_FLC_INTR_ACCESS_FAIL_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_ACCESS_FAIL_IE_POS)) /**< INTR_ACCESS_FAIL_IE Mask */ + +/**@} end of group FLC_INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_DATA FLC_DATA + * @brief Flash Write Data. + * @{ + */ + #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ + #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ACTRL FLC_ACTRL + * @brief Access Control Register. Writing the ACTRL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = + * 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of + * any word will disable access to system and user information block. Readback of + * this register is always zero. + * @{ + */ + #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ + #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ + +/**@} end of group FLC_ACTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h new file mode 100644 index 00000000000..c85118ff3bf --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h @@ -0,0 +1,436 @@ +/** + * @file gcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GCR_REGS_H_ +#define _GCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gcr + * @defgroup gcr_registers GCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @details Global Control Registers. + */ + +/** + * @ingroup gcr_registers + * Structure type to access the GCR Registers. + */ +typedef struct { + __IO uint32_t scon; /**< \b 0x00: GCR SCON Register */ + __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ + __IO uint32_t clk_ctrl; /**< \b 0x08: GCR CLK_CTRL Register */ + __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ + __I uint32_t rsv_0x10_0x23[5]; + __IO uint32_t pclk_dis0; /**< \b 0x24: GCR PCLK_DIS0 Register */ + __IO uint32_t mem_ctrl; /**< \b 0x28: GCR MEM_CTRL Register */ + __IO uint32_t mem_zctrl; /**< \b 0x2C: GCR MEM_ZCTRL Register */ + __I uint32_t rsv_0x30_0x3f[4]; + __IO uint32_t sys_stat; /**< \b 0x40: GCR SYS_STAT Register */ + __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ + __IO uint32_t pclk_dis1; /**< \b 0x48: GCR PCLK_DIS1 Register */ + __IO uint32_t evten; /**< \b 0x4C: GCR EVTEN Register */ + __I uint32_t rev; /**< \b 0x50: GCR REV Register */ + __IO uint32_t sys_ie; /**< \b 0x54: GCR SYS_IE Register */ +} mxc_gcr_regs_t; + +/* Register offsets for module GCR */ +/** + * @ingroup gcr_registers + * @defgroup GCR_Register_Offsets Register Offsets + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @{ + */ + #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ + #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ + #define MXC_R_GCR_CLK_CTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ + #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ + #define MXC_R_GCR_PCLK_DIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ + #define MXC_R_GCR_MEM_CTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ + #define MXC_R_GCR_MEM_ZCTRL ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ + #define MXC_R_GCR_SYS_STAT ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ + #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ + #define MXC_R_GCR_PCLK_DIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ + #define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ + #define MXC_R_GCR_REV ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ + #define MXC_R_GCR_SYS_IE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +/**@} end of group gcr_registers */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SCON GCR_SCON + * @brief System Control. + * @{ + */ + #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ + #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ + + #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ + #define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ + + #define MXC_F_GCR_SCON_ICC0_FLUSH_POS 6 /**< SCON_ICC0_FLUSH Position */ + #define MXC_F_GCR_SCON_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_ICC0_FLUSH_POS)) /**< SCON_ICC0_FLUSH Mask */ + + #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ + #define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ + +/**@} end of group GCR_SCON_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RST0 GCR_RST0 + * @brief Reset. + * @{ + */ + #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ + #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ + + #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ + #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ + + #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ + #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ + + #define MXC_F_GCR_RST0_TIMER0_POS 5 /**< RST0_TIMER0 Position */ + #define MXC_F_GCR_RST0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS)) /**< RST0_TIMER0 Mask */ + + #define MXC_F_GCR_RST0_TIMER1_POS 6 /**< RST0_TIMER1 Position */ + #define MXC_F_GCR_RST0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS)) /**< RST0_TIMER1 Mask */ + + #define MXC_F_GCR_RST0_TIMER2_POS 7 /**< RST0_TIMER2 Position */ + #define MXC_F_GCR_RST0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS)) /**< RST0_TIMER2 Mask */ + + #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ + #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ + + #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ + #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ + + #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ + #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ + + #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ + #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ + + #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ + #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ + + #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ + #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ + + #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ + #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ + + #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ + #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ + + #define MXC_F_GCR_RST0_SYSTEM_POS 31 /**< RST0_SYSTEM Position */ + #define MXC_F_GCR_RST0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS)) /**< RST0_SYSTEM Mask */ + +/**@} end of group GCR_RST0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_CLK_CTRL GCR_CLK_CTRL + * @brief Clock Control. + * @{ + */ + #define MXC_F_GCR_CLK_CTRL_PSC_POS 6 /**< CLK_CTRL_PSC Position */ + #define MXC_F_GCR_CLK_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_PSC_POS)) /**< CLK_CTRL_PSC Mask */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CLK_CTRL_PSC_DIV1 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV1 (MXC_V_GCR_CLK_CTRL_PSC_DIV1 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV1 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CLK_CTRL_PSC_DIV2 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV2 (MXC_V_GCR_CLK_CTRL_PSC_DIV2 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV2 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CLK_CTRL_PSC_DIV4 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV4 (MXC_V_GCR_CLK_CTRL_PSC_DIV4 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV4 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CLK_CTRL_PSC_DIV8 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV8 (MXC_V_GCR_CLK_CTRL_PSC_DIV8 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV8 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CLK_CTRL_PSC_DIV16 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV16 (MXC_V_GCR_CLK_CTRL_PSC_DIV16 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV16 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CLK_CTRL_PSC_DIV32 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV32 (MXC_V_GCR_CLK_CTRL_PSC_DIV32 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV32 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CLK_CTRL_PSC_DIV64 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV64 (MXC_V_GCR_CLK_CTRL_PSC_DIV64 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV64 Setting */ + #define MXC_V_GCR_CLK_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CLK_CTRL_PSC_DIV128 Value */ + #define MXC_S_GCR_CLK_CTRL_PSC_DIV128 (MXC_V_GCR_CLK_CTRL_PSC_DIV128 << MXC_F_GCR_CLK_CTRL_PSC_POS) /**< CLK_CTRL_PSC_DIV128 Setting */ + + #define MXC_F_GCR_CLK_CTRL_CLKSEL_POS 9 /**< CLK_CTRL_CLKSEL Position */ + #define MXC_F_GCR_CLK_CTRL_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLK_CTRL_CLKSEL_POS)) /**< CLK_CTRL_CLKSEL Mask */ + #define MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLK_CTRL_CLKSEL_HIRC Value */ + #define MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC (MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HIRC Setting */ + #define MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLK_CTRL_CLKSEL_NANORING Value */ + #define MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING (MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_NANORING Setting */ + #define MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLK_CTRL_CLKSEL_HFXIN Value */ + #define MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN (MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN << MXC_F_GCR_CLK_CTRL_CLKSEL_POS) /**< CLK_CTRL_CLKSEL_HFXIN Setting */ + + #define MXC_F_GCR_CLK_CTRL_CLKRDY_POS 13 /**< CLK_CTRL_CLKRDY Position */ + #define MXC_F_GCR_CLK_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_CLKRDY_POS)) /**< CLK_CTRL_CLKRDY Mask */ + + #define MXC_F_GCR_CLK_CTRL_X32K_EN_POS 17 /**< CLK_CTRL_X32K_EN Position */ + #define MXC_F_GCR_CLK_CTRL_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_EN_POS)) /**< CLK_CTRL_X32K_EN Mask */ + + #define MXC_F_GCR_CLK_CTRL_HIRC_EN_POS 18 /**< CLK_CTRL_HIRC_EN Position */ + #define MXC_F_GCR_CLK_CTRL_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_EN_POS)) /**< CLK_CTRL_HIRC_EN Mask */ + + #define MXC_F_GCR_CLK_CTRL_X32K_RDY_POS 25 /**< CLK_CTRL_X32K_RDY Position */ + #define MXC_F_GCR_CLK_CTRL_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_X32K_RDY_POS)) /**< CLK_CTRL_X32K_RDY Mask */ + + #define MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS 26 /**< CLK_CTRL_HIRC_RDY Position */ + #define MXC_F_GCR_CLK_CTRL_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_HIRC_RDY_POS)) /**< CLK_CTRL_HIRC_RDY Mask */ + + #define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS 29 /**< CLK_CTRL_LIRC8K_RDY Position */ + #define MXC_F_GCR_CLK_CTRL_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLK_CTRL_LIRC8K_RDY_POS)) /**< CLK_CTRL_LIRC8K_RDY Mask */ + +/**@} end of group GCR_CLK_CTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PM GCR_PM + * @brief Power Management. + * @{ + */ + #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ + #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ + #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ + #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ + #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ + #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ + #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ + #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ + + #define MXC_F_GCR_PM_GPIOWK_EN_POS 4 /**< PM_GPIOWK_EN Position */ + #define MXC_F_GCR_PM_GPIOWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWK_EN_POS)) /**< PM_GPIOWK_EN Mask */ + + #define MXC_F_GCR_PM_RTCWK_EN_POS 5 /**< PM_RTCWK_EN Position */ + #define MXC_F_GCR_PM_RTCWK_EN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWK_EN_POS)) /**< PM_RTCWK_EN Mask */ + + #define MXC_F_GCR_PM_HFIOPD_POS 15 /**< PM_HFIOPD Position */ + #define MXC_F_GCR_PM_HFIOPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HFIOPD_POS)) /**< PM_HFIOPD Mask */ + +/**@} end of group GCR_PM_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLK_DIS0 GCR_PCLK_DIS0 + * @brief Peripheral Clock Disable. + * @{ + */ + #define MXC_F_GCR_PCLK_DIS0_GPIO0D_POS 0 /**< PCLK_DIS0_GPIO0D Position */ + #define MXC_F_GCR_PCLK_DIS0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_GPIO0D_POS)) /**< PCLK_DIS0_GPIO0D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_DMAD_POS 5 /**< PCLK_DIS0_DMAD Position */ + #define MXC_F_GCR_PCLK_DIS0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_DMAD_POS)) /**< PCLK_DIS0_DMAD Mask */ + + #define MXC_F_GCR_PCLK_DIS0_SPI0D_POS 6 /**< PCLK_DIS0_SPI0D Position */ + #define MXC_F_GCR_PCLK_DIS0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI0D_POS)) /**< PCLK_DIS0_SPI0D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_SPI1D_POS 7 /**< PCLK_DIS0_SPI1D Position */ + #define MXC_F_GCR_PCLK_DIS0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_SPI1D_POS)) /**< PCLK_DIS0_SPI1D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_UART0D_POS 9 /**< PCLK_DIS0_UART0D Position */ + #define MXC_F_GCR_PCLK_DIS0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART0D_POS)) /**< PCLK_DIS0_UART0D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_UART1D_POS 10 /**< PCLK_DIS0_UART1D Position */ + #define MXC_F_GCR_PCLK_DIS0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_UART1D_POS)) /**< PCLK_DIS0_UART1D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_I2C0D_POS 13 /**< PCLK_DIS0_I2C0D Position */ + #define MXC_F_GCR_PCLK_DIS0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C0D_POS)) /**< PCLK_DIS0_I2C0D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_TIMER0D_POS 15 /**< PCLK_DIS0_TIMER0D Position */ + #define MXC_F_GCR_PCLK_DIS0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER0D_POS)) /**< PCLK_DIS0_TIMER0D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_TIMER1D_POS 16 /**< PCLK_DIS0_TIMER1D Position */ + #define MXC_F_GCR_PCLK_DIS0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER1D_POS)) /**< PCLK_DIS0_TIMER1D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_TIMER2D_POS 17 /**< PCLK_DIS0_TIMER2D Position */ + #define MXC_F_GCR_PCLK_DIS0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_TIMER2D_POS)) /**< PCLK_DIS0_TIMER2D Mask */ + + #define MXC_F_GCR_PCLK_DIS0_I2C1D_POS 28 /**< PCLK_DIS0_I2C1D Position */ + #define MXC_F_GCR_PCLK_DIS0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS0_I2C1D_POS)) /**< PCLK_DIS0_I2C1D Mask */ + +/**@} end of group GCR_PCLK_DIS0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEM_CTRL GCR_MEM_CTRL + * @brief Memory Clock Control Register. + * @{ + */ + #define MXC_F_GCR_MEM_CTRL_FWS_POS 0 /**< MEM_CTRL_FWS Position */ + #define MXC_F_GCR_MEM_CTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEM_CTRL_FWS_POS)) /**< MEM_CTRL_FWS Mask */ + + #define MXC_F_GCR_MEM_CTRL_RAM0_LS_POS 8 /**< MEM_CTRL_RAM0_LS Position */ + #define MXC_F_GCR_MEM_CTRL_RAM0_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM0_LS_POS)) /**< MEM_CTRL_RAM0_LS Mask */ + + #define MXC_F_GCR_MEM_CTRL_RAM1_LS_POS 9 /**< MEM_CTRL_RAM1_LS Position */ + #define MXC_F_GCR_MEM_CTRL_RAM1_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM1_LS_POS)) /**< MEM_CTRL_RAM1_LS Mask */ + + #define MXC_F_GCR_MEM_CTRL_RAM2_LS_POS 10 /**< MEM_CTRL_RAM2_LS Position */ + #define MXC_F_GCR_MEM_CTRL_RAM2_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM2_LS_POS)) /**< MEM_CTRL_RAM2_LS Mask */ + + #define MXC_F_GCR_MEM_CTRL_RAM3_LS_POS 11 /**< MEM_CTRL_RAM3_LS Position */ + #define MXC_F_GCR_MEM_CTRL_RAM3_LS ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_RAM3_LS_POS)) /**< MEM_CTRL_RAM3_LS Mask */ + + #define MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS 12 /**< MEM_CTRL_ICACHE_RET Position */ + #define MXC_F_GCR_MEM_CTRL_ICACHE_RET ((uint32_t)(0x1UL << MXC_F_GCR_MEM_CTRL_ICACHE_RET_POS)) /**< MEM_CTRL_ICACHE_RET Mask */ + +/**@} end of group GCR_MEM_CTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEM_ZCTRL GCR_MEM_ZCTRL + * @brief Memory Zeroize Control. + * @{ + */ + #define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS 0 /**< MEM_ZCTRL_SRAM_ZERO Position */ + #define MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_SRAM_ZERO_POS)) /**< MEM_ZCTRL_SRAM_ZERO Mask */ + + #define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS 1 /**< MEM_ZCTRL_ICACHE_ZERO Position */ + #define MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO ((uint32_t)(0x1UL << MXC_F_GCR_MEM_ZCTRL_ICACHE_ZERO_POS)) /**< MEM_ZCTRL_ICACHE_ZERO Mask */ + +/**@} end of group GCR_MEM_ZCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYS_STAT GCR_SYS_STAT + * @brief System Status Register. + * @{ + */ + #define MXC_F_GCR_SYS_STAT_ICECLOCK_POS 0 /**< SYS_STAT_ICECLOCK Position */ + #define MXC_F_GCR_SYS_STAT_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYS_STAT_ICECLOCK_POS)) /**< SYS_STAT_ICECLOCK Mask */ + +/**@} end of group GCR_SYS_STAT_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RST1 GCR_RST1 + * @brief Reset 1. + * @{ + */ + #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ + #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ + +/**@} end of group GCR_RST1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLK_DIS1 GCR_PCLK_DIS1 + * @brief Peripheral Clock Disable. + * @{ + */ + #define MXC_F_GCR_PCLK_DIS1_FLCD_POS 3 /**< PCLK_DIS1_FLCD Position */ + #define MXC_F_GCR_PCLK_DIS1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_FLCD_POS)) /**< PCLK_DIS1_FLCD Mask */ + + #define MXC_F_GCR_PCLK_DIS1_ICCD_POS 11 /**< PCLK_DIS1_ICCD Position */ + #define MXC_F_GCR_PCLK_DIS1_ICCD ((uint32_t)(0x1UL << MXC_F_GCR_PCLK_DIS1_ICCD_POS)) /**< PCLK_DIS1_ICCD Mask */ + +/**@} end of group GCR_PCLK_DIS1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_EVTEN GCR_EVTEN + * @brief Event Enable Register. + * @{ + */ + #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ + #define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ + + #define MXC_F_GCR_EVTEN_RX_EVT_POS 1 /**< EVTEN_RX_EVT Position */ + #define MXC_F_GCR_EVTEN_RX_EVT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RX_EVT_POS)) /**< EVTEN_RX_EVT Mask */ + +/**@} end of group GCR_EVTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_REV GCR_REV + * @brief Revision Register. + * @{ + */ + #define MXC_F_GCR_REV_REVISION_POS 0 /**< REV_REVISION Position */ + #define MXC_F_GCR_REV_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REV_REVISION_POS)) /**< REV_REVISION Mask */ + +/**@} end of group GCR_REV_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYS_IE GCR_SYS_IE + * @brief System Status Interrupt Enable + * @{ + */ + #define MXC_F_GCR_SYS_IE_ICEULIE_POS 0 /**< SYS_IE_ICEULIE Position */ + #define MXC_F_GCR_SYS_IE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYS_IE_ICEULIE_POS)) /**< SYS_IE_ICEULIE Mask */ + +/**@} end of group GCR_SYS_IE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GCR_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h new file mode 100644 index 00000000000..93db2513f4f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h @@ -0,0 +1,677 @@ +/** + * @file gpio_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GPIO_REGS_H_ +#define _GPIO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers GPIO_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @details Individual I/O for each GPIO + */ + +/** + * @ingroup gpio_registers + * Structure type to access the GPIO Registers. + */ +typedef struct { + __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ + __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ + __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ + __IO uint32_t out_en; /**< \b 0x0C: GPIO OUT_EN Register */ + __IO uint32_t out_en_set; /**< \b 0x10: GPIO OUT_EN_SET Register */ + __IO uint32_t out_en_clr; /**< \b 0x14: GPIO OUT_EN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO IN Register */ + __IO uint32_t int_mod; /**< \b 0x28: GPIO INT_MOD Register */ + __IO uint32_t int_pol; /**< \b 0x2C: GPIO INT_POL Register */ + __IO uint32_t in_en; /**< \b 0x30: GPIO IN_EN Register */ + __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ + __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ + __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ + __IO uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ + __I uint32_t rsv_0x44; + __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ + __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ + __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ + __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ + __I uint32_t rsv_0x58; + __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ + __IO uint32_t pad_cfg1; /**< \b 0x60: GPIO PAD_CFG1 Register */ + __IO uint32_t pad_cfg2; /**< \b 0x64: GPIO PAD_CFG2 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ + __I uint32_t rsv_0x80_0xa7[10]; + __IO uint32_t is; /**< \b 0xA8: GPIO IS Register */ + __IO uint32_t sr; /**< \b 0xAC: GPIO SR Register */ + __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ + __I uint32_t rsv_0xbc; + __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ +} mxc_gpio_regs_t; + +/* Register offsets for module GPIO */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ + #define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ + #define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ + #define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ + #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ + #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ + #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ + #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ + #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ + #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ + #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ + #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ + #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ + #define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ + #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ + #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ + #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ + #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ + #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ + #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ + #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ + #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ + #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ + #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ + #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ + #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ + #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ + #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ + #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ + #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ + #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ + #define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ + #define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ + #define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ + #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ + #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ + #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ +/**@} end of group gpio_registers */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0 GPIO_EN0 + * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * GPIO pin on the associated port. + * @{ + */ + #define MXC_F_GPIO_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_EN Position */ + #define MXC_F_GPIO_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ + #define MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ + #define MXC_S_GPIO_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ + #define MXC_V_GPIO_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ + #define MXC_S_GPIO_EN0_GPIO_EN_GPIO (MXC_V_GPIO_EN0_GPIO_EN_GPIO << MXC_F_GPIO_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ + +/**@} end of group GPIO_EN0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_SET GPIO_EN0_SET + * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * register sets the bits in the same positions in GPIO_EN to 1, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ + #define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ + +/**@} end of group GPIO_EN0_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR + * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ + #define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ + +/**@} end of group GPIO_EN0_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN GPIO_OUT_EN + * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one + * GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ + #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ + #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ + #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ + #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ + #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ + +/**@} end of group GPIO_OUT_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET + * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits + * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ + #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ + +/**@} end of group GPIO_OUT_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR + * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more + * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ + #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ + +/**@} end of group GPIO_OUT_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT GPIO_OUT + * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the + * associated port. This register can be written either directly, or by using the + * GPIO_OUT_SET and GPIO_OUT_CLR registers. + * @{ + */ + #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ + #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ + #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ + #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ + #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ + #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ + +/**@} end of group GPIO_OUT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits + * in the same positions in GPIO_OUT to 1, without affecting other bits in that + * register. + * @{ + */ + #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ + #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ + #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ + #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ + #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ + #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ + +/**@} end of group GPIO_OUT_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_OUT to 0, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ + #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ + +/**@} end of group GPIO_OUT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN GPIO_IN + * @brief GPIO Input Register. Read-only register to read from the logic states of the + * GPIO pins on this port. + * @{ + */ + #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ + #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ + +/**@} end of group GPIO_IN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_MOD GPIO_INT_MOD + * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt + * mode setting for the associated GPIO pin on this port. + * @{ + */ + #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ + #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ + #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ + #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ + #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ + #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ + +/**@} end of group GPIO_INT_MOD_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_POL GPIO_INT_POL + * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the + * interrupt polarity setting for one GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ + #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ + #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ + #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ + #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ + #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ + +/**@} end of group GPIO_INT_POL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN_EN GPIO_IN_EN + * @brief GPIO Port Input Enable. + * @{ + */ + #define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */ + #define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */ + #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */ + #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */ + #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */ + #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */ + +/**@} end of group GPIO_IN_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN GPIO_INT_EN + * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO + * interrupt enable for the associated pin on the GPIO port. + * @{ + */ + #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ + #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ + #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ + #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ + #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ + #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ + +/**@} end of group GPIO_INT_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET + * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets + * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ + #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ + #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ + #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ + #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ + #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ + +/**@} end of group GPIO_INT_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR + * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ + #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ + #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ + #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ + #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ + #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ + +/**@} end of group GPIO_INT_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_STAT GPIO_INT_STAT + * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending + * interrupt status for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ + #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ + #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ + #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ + #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ + #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ + +/**@} end of group GPIO_INT_STAT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_CLR GPIO_INT_CLR + * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ + #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ + +/**@} end of group GPIO_INT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN + * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup + * enable for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ + #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ + #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ + #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ + #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ + #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ + +/**@} end of group GPIO_WAKE_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET + * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the + * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ + #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ + +/**@} end of group GPIO_WAKE_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR + * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears + * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ + #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ + +/**@} end of group GPIO_WAKE_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE + * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual + * edge mode for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ + #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ + #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ + #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ + #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ + #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ + +/**@} end of group GPIO_INT_DUAL_EDGE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1 + * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ + #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ + +/**@} end of group GPIO_PAD_CFG1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2 + * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ + #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ + +/**@} end of group GPIO_PAD_CFG2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1 GPIO_EN1 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ + #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ + #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ + #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ + #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ + #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ + +/**@} end of group GPIO_EN1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ + #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ + +/**@} end of group GPIO_EN1_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ + #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ + +/**@} end of group GPIO_EN1_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2 GPIO_EN2 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ + #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ + #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ + #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ + #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ + #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ + +/**@} end of group GPIO_EN2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ + #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ + +/**@} end of group GPIO_EN2_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN2 to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ + #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_EN2_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS0 GPIO_DS0 + * @brief GPIO Drive Strength Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ + #define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ + #define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ + #define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ + #define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ + #define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ + +/**@} end of group GPIO_DS0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS1 GPIO_DS1 + * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ + #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + +/**@} end of group GPIO_DS1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PS GPIO_PS + * @brief GPIO Pull Select Mode. + * @{ + */ + #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ + #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ + +/**@} end of group GPIO_PS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_VSSEL GPIO_VSSEL + * @brief GPIO Voltage Select. + * @{ + */ + #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ + #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ + +/**@} end of group GPIO_VSSEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h new file mode 100644 index 00000000000..e47b5550995 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h @@ -0,0 +1,586 @@ +/** + * @file i2c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _I2C_REGS_H_ +#define _I2C_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2c + * @defgroup i2c_registers I2C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @details Inter-Integrated Circuit. + */ + +/** + * @ingroup i2c_registers + * Structure type to access the I2C Registers. + */ +typedef struct { + __IO uint32_t ctrl0; /**< \b 0x00: I2C CTRL0 Register */ + __IO uint32_t status; /**< \b 0x04: I2C STATUS Register */ + __IO uint32_t intfl0; /**< \b 0x08: I2C INTFL0 Register */ + __IO uint32_t inten0; /**< \b 0x0C: I2C INTEN0 Register */ + __IO uint32_t intfl1; /**< \b 0x10: I2C INTFL1 Register */ + __IO uint32_t inten1; /**< \b 0x14: I2C INTEN1 Register */ + __IO uint32_t fifolen; /**< \b 0x18: I2C FIFOLEN Register */ + __IO uint32_t rxctrl0; /**< \b 0x1C: I2C RXCTRL0 Register */ + __IO uint32_t rxctrl1; /**< \b 0x20: I2C RXCTRL1 Register */ + __IO uint32_t txctrl0; /**< \b 0x24: I2C TXCTRL0 Register */ + __IO uint32_t txctrl1; /**< \b 0x28: I2C TXCTRL1 Register */ + __IO uint32_t fifo; /**< \b 0x2C: I2C FIFO Register */ + __IO uint32_t mstr_mode; /**< \b 0x30: I2C MSTR_MODE Register */ + __IO uint32_t clklo; /**< \b 0x34: I2C CLKLO Register */ + __IO uint32_t clkhi; /**< \b 0x38: I2C CLKHI Register */ + __IO uint32_t hs_clk; /**< \b 0x3C: I2C HS_CLK Register */ + __IO uint32_t timeout; /**< \b 0x40: I2C TIMEOUT Register */ + __IO uint32_t sladdr; /**< \b 0x44: I2C SLADDR Register */ + __IO uint32_t dma; /**< \b 0x48: I2C DMA Register */ +} mxc_i2c_regs_t; + +/* Register offsets for module I2C */ +/** + * @ingroup i2c_registers + * @defgroup I2C_Register_Offsets Register Offsets + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @{ + */ + #define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ + #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ + #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ + #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ + #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ + #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ + #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ + #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ + #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ + #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ + #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ + #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ + #define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ + #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ + #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ + #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ + #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ + #define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ + #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +/**@} end of group i2c_registers */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CTRL0 I2C_CTRL0 + * @brief Control Register0. + * @{ + */ + #define MXC_F_I2C_CTRL0_I2CEN_POS 0 /**< CTRL0_I2CEN Position */ + #define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) /**< CTRL0_I2CEN Mask */ + + #define MXC_F_I2C_CTRL0_MST_POS 1 /**< CTRL0_MST Position */ + #define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) /**< CTRL0_MST Mask */ + + #define MXC_F_I2C_CTRL0_GCEN_POS 2 /**< CTRL0_GCEN Position */ + #define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) /**< CTRL0_GCEN Mask */ + + #define MXC_F_I2C_CTRL0_IRXM_POS 3 /**< CTRL0_IRXM Position */ + #define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) /**< CTRL0_IRXM Mask */ + + #define MXC_F_I2C_CTRL0_ACK_POS 4 /**< CTRL0_ACK Position */ + #define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) /**< CTRL0_ACK Mask */ + + #define MXC_F_I2C_CTRL0_SCLO_POS 6 /**< CTRL0_SCLO Position */ + #define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) /**< CTRL0_SCLO Mask */ + + #define MXC_F_I2C_CTRL0_SDAO_POS 7 /**< CTRL0_SDAO Position */ + #define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) /**< CTRL0_SDAO Mask */ + + #define MXC_F_I2C_CTRL0_SCL_POS 8 /**< CTRL0_SCL Position */ + #define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) /**< CTRL0_SCL Mask */ + + #define MXC_F_I2C_CTRL0_SDA_POS 9 /**< CTRL0_SDA Position */ + #define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) /**< CTRL0_SDA Mask */ + + #define MXC_F_I2C_CTRL0_SWOE_POS 10 /**< CTRL0_SWOE Position */ + #define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) /**< CTRL0_SWOE Mask */ + + #define MXC_F_I2C_CTRL0_READ_POS 11 /**< CTRL0_READ Position */ + #define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) /**< CTRL0_READ Mask */ + + #define MXC_F_I2C_CTRL0_SCL_STRD_POS 12 /**< CTRL0_SCL_STRD Position */ + #define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) /**< CTRL0_SCL_STRD Mask */ + + #define MXC_F_I2C_CTRL0_SCL_PPM_POS 13 /**< CTRL0_SCL_PPM Position */ + #define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) /**< CTRL0_SCL_PPM Mask */ + + #define MXC_F_I2C_CTRL0_HSMODE_POS 15 /**< CTRL0_HSMODE Position */ + #define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) /**< CTRL0_HSMODE Mask */ + +/**@} end of group I2C_CTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_STATUS I2C_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ + #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + + #define MXC_F_I2C_STATUS_RXE_POS 1 /**< STATUS_RXE Position */ + #define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) /**< STATUS_RXE Mask */ + + #define MXC_F_I2C_STATUS_RXF_POS 2 /**< STATUS_RXF Position */ + #define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) /**< STATUS_RXF Mask */ + + #define MXC_F_I2C_STATUS_TXE_POS 3 /**< STATUS_TXE Position */ + #define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) /**< STATUS_TXE Mask */ + + #define MXC_F_I2C_STATUS_TXF_POS 4 /**< STATUS_TXF Position */ + #define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) /**< STATUS_TXF Mask */ + + #define MXC_F_I2C_STATUS_CKMD_POS 5 /**< STATUS_CKMD Position */ + #define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) /**< STATUS_CKMD Mask */ + + #define MXC_F_I2C_STATUS_STAT_POS 8 /**< STATUS_STAT Position */ + #define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) /**< STATUS_STAT Mask */ + #define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) /**< STATUS_STAT_IDLE Value */ + #define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_IDLE Setting */ + #define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STAT_MTX_ADDR Value */ + #define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STAT_MRX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STAT_MTX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MTX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STAT_MRX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_MRX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STAT_SRX_ADDR Value */ + #define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STAT_STX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STAT_SRX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_SRX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STAT_STX_EX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_STX_EX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) /**< STATUS_STAT_TX Value */ + #define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX Setting */ + #define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STAT_RX_ACK Value */ + #define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX_ACK Setting */ + #define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) /**< STATUS_STAT_RX Value */ + #define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_RX Setting */ + #define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STAT_TX_ACK Value */ + #define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_TX_ACK Setting */ + #define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) /**< STATUS_STAT_NACK Value */ + #define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_NACK Setting */ + #define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) /**< STATUS_STAT_BY_ST Value */ + #define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) /**< STATUS_STAT_BY_ST Setting */ + +/**@} end of group I2C_STATUS_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTFL0 I2C_INTFL0 + * @brief Interrupt Status Register. + * @{ + */ + #define MXC_F_I2C_INTFL0_DONEI_POS 0 /**< INTFL0_DONEI Position */ + #define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) /**< INTFL0_DONEI Mask */ + + #define MXC_F_I2C_INTFL0_IRXMI_POS 1 /**< INTFL0_IRXMI Position */ + #define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) /**< INTFL0_IRXMI Mask */ + + #define MXC_F_I2C_INTFL0_GCI_POS 2 /**< INTFL0_GCI Position */ + #define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) /**< INTFL0_GCI Mask */ + + #define MXC_F_I2C_INTFL0_AMI_POS 3 /**< INTFL0_AMI Position */ + #define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) /**< INTFL0_AMI Mask */ + + #define MXC_F_I2C_INTFL0_RXTHI_POS 4 /**< INTFL0_RXTHI Position */ + #define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) /**< INTFL0_RXTHI Mask */ + + #define MXC_F_I2C_INTFL0_TXTHI_POS 5 /**< INTFL0_TXTHI Position */ + #define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) /**< INTFL0_TXTHI Mask */ + + #define MXC_F_I2C_INTFL0_STOPI_POS 6 /**< INTFL0_STOPI Position */ + #define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) /**< INTFL0_STOPI Mask */ + + #define MXC_F_I2C_INTFL0_ADRACKI_POS 7 /**< INTFL0_ADRACKI Position */ + #define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) /**< INTFL0_ADRACKI Mask */ + + #define MXC_F_I2C_INTFL0_ARBERI_POS 8 /**< INTFL0_ARBERI Position */ + #define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) /**< INTFL0_ARBERI Mask */ + + #define MXC_F_I2C_INTFL0_TOERI_POS 9 /**< INTFL0_TOERI Position */ + #define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) /**< INTFL0_TOERI Mask */ + + #define MXC_F_I2C_INTFL0_ADRERI_POS 10 /**< INTFL0_ADRERI Position */ + #define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) /**< INTFL0_ADRERI Mask */ + + #define MXC_F_I2C_INTFL0_DATERI_POS 11 /**< INTFL0_DATERI Position */ + #define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) /**< INTFL0_DATERI Mask */ + + #define MXC_F_I2C_INTFL0_DNRERI_POS 12 /**< INTFL0_DNRERI Position */ + #define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) /**< INTFL0_DNRERI Mask */ + + #define MXC_F_I2C_INTFL0_STRTERI_POS 13 /**< INTFL0_STRTERI Position */ + #define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) /**< INTFL0_STRTERI Mask */ + + #define MXC_F_I2C_INTFL0_STOPERI_POS 14 /**< INTFL0_STOPERI Position */ + #define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) /**< INTFL0_STOPERI Mask */ + + #define MXC_F_I2C_INTFL0_TXLOI_POS 15 /**< INTFL0_TXLOI Position */ + #define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) /**< INTFL0_TXLOI Mask */ + +/**@} end of group I2C_INTFL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTEN0 I2C_INTEN0 + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_I2C_INTEN0_DONEIE_POS 0 /**< INTEN0_DONEIE Position */ + #define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) /**< INTEN0_DONEIE Mask */ + + #define MXC_F_I2C_INTEN0_IRXMIE_POS 1 /**< INTEN0_IRXMIE Position */ + #define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) /**< INTEN0_IRXMIE Mask */ + + #define MXC_F_I2C_INTEN0_GCIE_POS 2 /**< INTEN0_GCIE Position */ + #define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) /**< INTEN0_GCIE Mask */ + + #define MXC_F_I2C_INTEN0_AMIE_POS 3 /**< INTEN0_AMIE Position */ + #define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) /**< INTEN0_AMIE Mask */ + + #define MXC_F_I2C_INTEN0_RXTHIE_POS 4 /**< INTEN0_RXTHIE Position */ + #define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) /**< INTEN0_RXTHIE Mask */ + + #define MXC_F_I2C_INTEN0_TXTHIE_POS 5 /**< INTEN0_TXTHIE Position */ + #define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) /**< INTEN0_TXTHIE Mask */ + + #define MXC_F_I2C_INTEN0_STOPIE_POS 6 /**< INTEN0_STOPIE Position */ + #define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) /**< INTEN0_STOPIE Mask */ + + #define MXC_F_I2C_INTEN0_ADRACKIE_POS 7 /**< INTEN0_ADRACKIE Position */ + #define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) /**< INTEN0_ADRACKIE Mask */ + + #define MXC_F_I2C_INTEN0_ARBERIE_POS 8 /**< INTEN0_ARBERIE Position */ + #define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) /**< INTEN0_ARBERIE Mask */ + + #define MXC_F_I2C_INTEN0_TOERIE_POS 9 /**< INTEN0_TOERIE Position */ + #define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) /**< INTEN0_TOERIE Mask */ + + #define MXC_F_I2C_INTEN0_ADRERIE_POS 10 /**< INTEN0_ADRERIE Position */ + #define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) /**< INTEN0_ADRERIE Mask */ + + #define MXC_F_I2C_INTEN0_DATERIE_POS 11 /**< INTEN0_DATERIE Position */ + #define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) /**< INTEN0_DATERIE Mask */ + + #define MXC_F_I2C_INTEN0_DNRERIE_POS 12 /**< INTEN0_DNRERIE Position */ + #define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) /**< INTEN0_DNRERIE Mask */ + + #define MXC_F_I2C_INTEN0_STRTERIE_POS 13 /**< INTEN0_STRTERIE Position */ + #define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) /**< INTEN0_STRTERIE Mask */ + + #define MXC_F_I2C_INTEN0_STOPERIE_POS 14 /**< INTEN0_STOPERIE Position */ + #define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) /**< INTEN0_STOPERIE Mask */ + + #define MXC_F_I2C_INTEN0_TXLOIE_POS 15 /**< INTEN0_TXLOIE Position */ + #define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) /**< INTEN0_TXLOIE Mask */ + +/**@} end of group I2C_INTEN0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTFL1 I2C_INTFL1 + * @brief Interrupt Status Register 1. + * @{ + */ + #define MXC_F_I2C_INTFL1_RXOFI_POS 0 /**< INTFL1_RXOFI Position */ + #define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) /**< INTFL1_RXOFI Mask */ + + #define MXC_F_I2C_INTFL1_TXUFI_POS 1 /**< INTFL1_TXUFI Position */ + #define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) /**< INTFL1_TXUFI Mask */ + +/**@} end of group I2C_INTFL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTEN1 I2C_INTEN1 + * @brief Interrupt Staus Register 1. + * @{ + */ + #define MXC_F_I2C_INTEN1_RXOFIE_POS 0 /**< INTEN1_RXOFIE Position */ + #define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) /**< INTEN1_RXOFIE Mask */ + + #define MXC_F_I2C_INTEN1_TXUFIE_POS 1 /**< INTEN1_TXUFIE Position */ + #define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) /**< INTEN1_TXUFIE Mask */ + +/**@} end of group I2C_INTEN1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFOLEN I2C_FIFOLEN + * @brief FIFO Configuration Register. + * @{ + */ + #define MXC_F_I2C_FIFOLEN_RXLEN_POS 0 /**< FIFOLEN_RXLEN Position */ + #define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) /**< FIFOLEN_RXLEN Mask */ + + #define MXC_F_I2C_FIFOLEN_TXLEN_POS 8 /**< FIFOLEN_TXLEN Position */ + #define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) /**< FIFOLEN_TXLEN Mask */ + +/**@} end of group I2C_FIFOLEN_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RXCTRL0 I2C_RXCTRL0 + * @brief Receive Control Register 0. + * @{ + */ + #define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ + #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ + + #define MXC_F_I2C_RXCTRL0_RXFSH_POS 7 /**< RXCTRL0_RXFSH Position */ + #define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) /**< RXCTRL0_RXFSH Mask */ + + #define MXC_F_I2C_RXCTRL0_RXTH_POS 8 /**< RXCTRL0_RXTH Position */ + #define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) /**< RXCTRL0_RXTH Mask */ + +/**@} end of group I2C_RXCTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RXCTRL1 I2C_RXCTRL1 + * @brief Receive Control Register 1. + * @{ + */ + #define MXC_F_I2C_RXCTRL1_RXCNT_POS 0 /**< RXCTRL1_RXCNT Position */ + #define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) /**< RXCTRL1_RXCNT Mask */ + + #define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 /**< RXCTRL1_RXFIFO Position */ + #define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) /**< RXCTRL1_RXFIFO Mask */ + +/**@} end of group I2C_RXCTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TXCTRL0 I2C_TXCTRL0 + * @brief Transmit Control Register 0. + * @{ + */ + #define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 /**< TXCTRL0_TXPRELD Position */ + #define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) /**< TXCTRL0_TXPRELD Mask */ + + #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ + #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ + + #define MXC_F_I2C_TXCTRL0_TXFSH_POS 7 /**< TXCTRL0_TXFSH Position */ + #define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) /**< TXCTRL0_TXFSH Mask */ + + #define MXC_F_I2C_TXCTRL0_TXTH_POS 8 /**< TXCTRL0_TXTH Position */ + #define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) /**< TXCTRL0_TXTH Mask */ + +/**@} end of group I2C_TXCTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TXCTRL1 I2C_TXCTRL1 + * @brief Transmit Control Register 1. + * @{ + */ + #define MXC_F_I2C_TXCTRL1_TXRDY_POS 0 /**< TXCTRL1_TXRDY Position */ + #define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) /**< TXCTRL1_TXRDY Mask */ + + #define MXC_F_I2C_TXCTRL1_TXLAST_POS 1 /**< TXCTRL1_TXLAST Position */ + #define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) /**< TXCTRL1_TXLAST Mask */ + + #define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 /**< TXCTRL1_FLSH_GCADDR_DIS Position */ + #define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) /**< TXCTRL1_FLSH_GCADDR_DIS Mask */ + + #define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 /**< TXCTRL1_FLSH_SLADDR_DIS Position */ + #define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) /**< TXCTRL1_FLSH_SLADDR_DIS Mask */ + + #define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 /**< TXCTRL1_FLSH_NACK_DIS Position */ + #define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) /**< TXCTRL1_FLSH_NACK_DIS Mask */ + + #define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 /**< TXCTRL1_TXFIFO Position */ + #define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) /**< TXCTRL1_TXFIFO Mask */ + +/**@} end of group I2C_TXCTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO I2C_FIFO + * @brief Data Register. + * @{ + */ + #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ + #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group I2C_FIFO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_MSTR_MODE I2C_MSTR_MODE + * @brief Master Control Register. + * @{ + */ + #define MXC_F_I2C_MSTR_MODE_START_POS 0 /**< MSTR_MODE_START Position */ + #define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) /**< MSTR_MODE_START Mask */ + + #define MXC_F_I2C_MSTR_MODE_RESTART_POS 1 /**< MSTR_MODE_RESTART Position */ + #define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) /**< MSTR_MODE_RESTART Mask */ + + #define MXC_F_I2C_MSTR_MODE_STOP_POS 2 /**< MSTR_MODE_STOP Position */ + #define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) /**< MSTR_MODE_STOP Mask */ + + #define MXC_F_I2C_MSTR_MODE_SEA_POS 7 /**< MSTR_MODE_SEA Position */ + #define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) /**< MSTR_MODE_SEA Mask */ + +/**@} end of group I2C_MSTR_MODE_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLKLO I2C_CLKLO + * @brief Clock Low Register. + * @{ + */ + #define MXC_F_I2C_CLKLO_SCL_LO_POS 0 /**< CLKLO_SCL_LO Position */ + #define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) /**< CLKLO_SCL_LO Mask */ + +/**@} end of group I2C_CLKLO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLKHI I2C_CLKHI + * @brief Clock high Register. + * @{ + */ + #define MXC_F_I2C_CLKHI_SCL_HI_POS 0 /**< CLKHI_SCL_HI Position */ + #define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) /**< CLKHI_SCL_HI Mask */ + +/**@} end of group I2C_CLKHI_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_HS_CLK I2C_HS_CLK + * @brief HS-Mode Clock Control Register + * @{ + */ + #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ + #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ + + #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ + #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ + +/**@} end of group I2C_HS_CLK_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TIMEOUT I2C_TIMEOUT + * @brief Timeout Register + * @{ + */ + #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ + #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ + +/**@} end of group I2C_TIMEOUT_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_SLADDR I2C_SLADDR + * @brief Slave Address Register. + * @{ + */ + #define MXC_F_I2C_SLADDR_SLA_POS 0 /**< SLADDR_SLA Position */ + #define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) /**< SLADDR_SLA Mask */ + + #define MXC_F_I2C_SLADDR_EA_POS 15 /**< SLADDR_EA Position */ + #define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) /**< SLADDR_EA Mask */ + +/**@} end of group I2C_SLADDR_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_DMA I2C_DMA + * @brief DMA Register. + * @{ + */ + #define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */ + #define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ + + #define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */ + #define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ + +/**@} end of group I2C_DMA_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _I2C_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h new file mode 100644 index 00000000000..4a929955678 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h @@ -0,0 +1,157 @@ +/** + * @file icc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _ICC_REGS_H_ +#define _ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers ICC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_registers + * Structure type to access the ICC Registers. + */ +typedef struct { + __I uint32_t cache_id; /**< \b 0x0000: ICC CACHE_ID Register */ + __I uint32_t mem_size; /**< \b 0x0004: ICC MEM_SIZE Register */ + __I uint32_t rsv_0x8_0xff[62]; + __IO uint32_t cache_ctrl; /**< \b 0x0100: ICC CACHE_CTRL Register */ + __I uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ +} mxc_icc_regs_t; + +/* Register offsets for module ICC */ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @{ + */ + #define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ + #define MXC_R_ICC_MEM_SIZE ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ + #define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ + #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +/**@} end of group icc_registers */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CACHE_ID ICC_CACHE_ID + * @brief Cache ID Register. + * @{ + */ + #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ + #define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ + + #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ + #define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ + + #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ + #define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ + +/**@} end of group ICC_CACHE_ID_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_MEM_SIZE ICC_MEM_SIZE + * @brief Memory Configuration Register. + * @{ + */ + #define MXC_F_ICC_MEM_SIZE_CCHSZ_POS 0 /**< MEM_SIZE_CCHSZ Position */ + #define MXC_F_ICC_MEM_SIZE_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_CCHSZ_POS)) /**< MEM_SIZE_CCHSZ Mask */ + + #define MXC_F_ICC_MEM_SIZE_MEMSZ_POS 16 /**< MEM_SIZE_MEMSZ Position */ + #define MXC_F_ICC_MEM_SIZE_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEM_SIZE_MEMSZ_POS)) /**< MEM_SIZE_MEMSZ Mask */ + +/**@} end of group ICC_MEM_SIZE_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL + * @brief Cache Control and Status Register. + * @{ + */ + #define MXC_F_ICC_CACHE_CTRL_ENABLE_POS 0 /**< CACHE_CTRL_ENABLE Position */ + #define MXC_F_ICC_CACHE_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_ENABLE_POS)) /**< CACHE_CTRL_ENABLE Mask */ + + #define MXC_F_ICC_CACHE_CTRL_READY_POS 16 /**< CACHE_CTRL_READY Position */ + #define MXC_F_ICC_CACHE_CTRL_READY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_READY_POS)) /**< CACHE_CTRL_READY Mask */ + +/**@} end of group ICC_CACHE_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h new file mode 100644 index 00000000000..14431a40b38 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/max32660.h @@ -0,0 +1,408 @@ +/** + * @file max32660.h + * @brief Device-specific perhiperal header file + */ + +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + ******************************************************************************/ + +#ifndef _MAX32660_REGS_H_ +#define _MAX32660_REGS_H_ + +#ifndef TARGET_NUM +#define TARGET_NUM 32660 +#endif + +#include + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +#if !defined (__GNUC__) +#define CMSIS_VECTAB_VIRTUAL +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" +#endif /* !__GNUC__ */ + +/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ +#if defined ( __GNUC__ ) /* GCC */ +#define __weak __attribute__((weak)) + +#elif defined ( __CC_ARM) /* Keil */ + +#define inline __inline +#pragma anon_unions + +#endif + +typedef enum { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Device-specific interrupt sources (external to ARM core) */ + /* table entry number */ + /* |||| */ + /* |||| table offset address */ + /* vvvv vvvvvv */ + + PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ + WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ + RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */ + RTC_IRQn, /* 0x13 0x004C 19: RTC */ + RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */ + TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ + TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ + TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ + RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */ + RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */ + RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */ + RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */ + RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */ + I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ + UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ + UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ + SPI0_IRQn, /* 0x20 0x0080 32: SPI17Y */ + SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */ + RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */ + RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */ + RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */ + RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */ + RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */ + FLC_IRQn, /* 0x27 0x009C 39: FLC */ + GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ + RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */ + RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */ + RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */ + DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ + DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ + DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ + DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ + RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */ + RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */ + RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */ + RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */ + I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ + RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */ + RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */ + RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */ + RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */ + RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */ + RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */ + RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */ + RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */ + RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */ + RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */ + RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */ + RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */ + RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */ + RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */ + RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */ + RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */ + RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */ + GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_max32660.h" /*!< System Header */ + + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +#define MXC_FLASH_MEM_BASE 0x00000000UL +#define MXC_FLASH_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_MEM_SIZE 0x00040000UL +#define MXC_INFO_MEM_BASE 0x00040000UL +#define MXC_INFO_MEM_SIZE 0x00001000UL +#define MXC_SRAM_MEM_BASE 0x20000000UL +#define MXC_SRAM_MEM_SIZE 0x00018000UL + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* + Base addresses and configuration settings for all MAX32660 peripheral modules. +*/ + +/******************************************************************************/ +/* Global control */ +#define MXC_BASE_GCR ((uint32_t)0x40000000UL) +#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR) + +/******************************************************************************/ +/* Non-battery backed SI Registers */ +#define MXC_BASE_SIR ((uint32_t)0x40000400UL) +#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR) + +/******************************************************************************/ +/* Watchdog */ +#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0) + +/******************************************************************************/ +/* Real Time Clock */ +#define MXC_BASE_RTC ((uint32_t)0x40006000UL) +#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC) + +/******************************************************************************/ +/* Power Sequencer */ +#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ) + + +/******************************************************************************/ +/* GPIO */ +#define MXC_CFG_GPIO_INSTANCES (1) +#define MXC_CFG_GPIO_PINS_PORT (14) + +#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) +#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0) + +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1) + +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) + +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) + +/******************************************************************************/ +/* Timer */ +#define MXC_CFG_TMR_INSTANCES (3) + +#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0) +#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1) +#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2) + +#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : 0) + +#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : 0) + +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : 0) + +#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : -1) + +/******************************************************************************/ +/* SPIMSS */ + +#define MXC_SPIMSS_INSTANCES (1) +#define MXC_SPIMSS_FIFO_DEPTH (8) + +#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL) +#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS) + +#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1) +#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0) + +/******************************************************************************/ +/* I2C */ +#define MXC_I2C_INSTANCES (2) +#define MXC_I2C_FIFO_DEPTH (8) + +#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) +#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0) +#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) +#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1) + +#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \ + (i) == 1 ? I2C1_IRQn : 0) + +#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \ + (i) == 1 ? MXC_BASE_I2C1 : 0) + +#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \ + (i) == 1 ? MXC_I2C1 : 0) + +#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \ + (p) == MXC_I2C1 ? 1 : -1) + +/******************************************************************************/ +/* DMA */ +#define MXC_DMA_CHANNELS (4) +#define MXC_DMA_INSTANCES (1) + +#define MXC_BASE_DMA ((uint32_t)0x40028000UL) +#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA) + +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA ? 0 : -1) + +/******************************************************************************/ +/* FLC */ +#define MXC_FLC_INSTANCES (1) + +#define MXC_BASE_FLC ((uint32_t)0x40029000UL) +#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC) + +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) + +/******************************************************************************/ +/* Instruction Cache */ +#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) +#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC) + +/******************************************************************************/ +/* UART / Serial Port Interface */ + +#define MXC_UART_INSTANCES (2) +#define MXC_UART_FIFO_DEPTH (8) + +#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) +#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0) +#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) +#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1) + +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : 0) + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : 0) + +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ + (i) == 1 ? MXC_UART1 : 0) + +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ + (p) == MXC_UART1 ? 1 : -1) + +/******************************************************************************/ +/* SPI */ +#include "spi_regs.h" + +#define MXC_SPI_INSTANCES (1) +#define MXC_SPI_SS_INSTANCES (1) +#define MXC_SPI_FIFO_DEPTH (32) + +#define MXC_BASE_SPI ((uint32_t)0x40046000UL) +#define MXC_SPI0 ((mxc_spi_regs_t*)MXC_BASE_SPI) + +#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI0 ? 0 : -1) + +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) + +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : 0) + +/******************************************************************************/ +/* Bit Shifting */ + +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) + +/******************************************************************************/ +/* Bit Banding */ + +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) + +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask)) + +/******************************************************************************/ +/* SCB CPACR */ + +/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ + +#endif /* _MAX32660_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h new file mode 100644 index 00000000000..3fa8f797f52 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h @@ -0,0 +1,207 @@ +/** + * @file pwrseq_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _PWRSEQ_REGS_H_ +#define _PWRSEQ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup pwrseq + * @defgroup pwrseq_registers PWRSEQ_Registers + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @details Power Sequencer / Low Power Control Register. + */ + +/** + * @ingroup pwrseq_registers + * Structure type to access the PWRSEQ Registers. + */ +typedef struct { + __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ + __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ + __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ + __I uint32_t rsv_0xc_0x3f[13]; + __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ +} mxc_pwrseq_regs_t; + +/* Register offsets for module PWRSEQ */ +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_Register_Offsets Register Offsets + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @{ + */ + #define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ + #define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ + #define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ + #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +/**@} end of group pwrseq_registers */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL + * @brief Low Power Control Register. + * @{ + */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ + #define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */ + #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ + #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */ + + #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */ + +/**@} end of group PWRSEQ_LP_CTRL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL + * @brief Low Power Mode Wakeup Flags for GPIO0 + * @{ + */ + #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ + #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */ + +/**@} end of group PWRSEQ_LP_WAKEFL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN + * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup + * functionality for GPIO0. + * @{ + */ + #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ + #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */ + +/**@} end of group PWRSEQ_LPWK_EN_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD + * @brief Low Power Memory Shutdown Control. + * @{ + */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */ + +/**@} end of group PWRSEQ_LPMEMSD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _PWRSEQ_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h new file mode 100644 index 00000000000..f6fb132dccf --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/rtc_regs.h @@ -0,0 +1,253 @@ +/** + * @file rtc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _RTC_REGS_H_ +#define _RTC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC_Registers + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @details Real Time Clock and Alarm. + */ + +/** + * @ingroup rtc_registers + * Structure type to access the RTC Registers. + */ +typedef struct { + __IO uint32_t sec; /**< \b 0x00: RTC SEC Register */ + __IO uint32_t ssec; /**< \b 0x04: RTC SSEC Register */ + __IO uint32_t ras; /**< \b 0x08: RTC RAS Register */ + __IO uint32_t rssa; /**< \b 0x0C: RTC RSSA Register */ + __IO uint32_t ctrl; /**< \b 0x10: RTC CTRL Register */ + __IO uint32_t trim; /**< \b 0x14: RTC TRIM Register */ + __IO uint32_t oscctrl; /**< \b 0x18: RTC OSCCTRL Register */ +} mxc_rtc_regs_t; + +/* Register offsets for module RTC */ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @{ + */ + #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ + #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ + #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ + #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ + #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ + #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ + #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +/**@} end of group rtc_registers */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSEC RTC_SSEC + * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented + * when this register rolls over from 0xFF to 0x00. + * @{ + */ + #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ + #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ + +/**@} end of group RTC_SSEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_RAS RTC_RAS + * @brief Time-of-day Alarm. + * @{ + */ + #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ + #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ + +/**@} end of group RTC_RAS_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_RSSA RTC_RSSA + * @brief RTC sub-second alarm. This register contains the reload value for the sub- + * second alarm. + * @{ + */ + #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ + #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ + +/**@} end of group RTC_RSSA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL RTC_CTRL + * @brief RTC Control Register. + * @{ + */ + #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ + #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ + + #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ + #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ + + #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ + #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ + + #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ + #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + + #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ + #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + + #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ + #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ + + #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ + #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ + + #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ + #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ + + #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ + #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ + + #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ + #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ + #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ + #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ + #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ + #define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ + #define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ + + #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ + #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ + #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ + #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ + + #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ + #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ + +/**@} end of group RTC_CTRL_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM RTC_TRIM + * @brief RTC Trim Register. + * @{ + */ + #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ + #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ + + #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ + #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ + +/**@} end of group RTC_TRIM_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_OSCCTRL RTC_OSCCTRL + * @brief RTC Oscillator Control Register. + * @{ + */ + #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ + #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ + #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ + + #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ + #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ + #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ + #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ + + #define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ + #define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ + +/**@} end of group RTC_OSCCTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTC_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h new file mode 100644 index 00000000000..2eb73735908 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/sir_regs.h @@ -0,0 +1,135 @@ +/** + * @file sir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SIR_REGS_H_ +#define _SIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sir + * @defgroup sir_registers SIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @details System Initialization Registers. + */ + +/** + * @ingroup sir_registers + * Structure type to access the SIR Registers. + */ +typedef struct { + __I uint32_t status; /**< \b 0x00: SIR STATUS Register */ + __I uint32_t addr; /**< \b 0x04: SIR ADDR Register */ +} mxc_sir_regs_t; + +/* Register offsets for module SIR */ +/** + * @ingroup sir_registers + * @defgroup SIR_Register_Offsets Register Offsets + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @{ + */ + #define MXC_R_SIR_STATUS ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ + #define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +/**@} end of group sir_registers */ + +/** + * @ingroup sir_registers + * @defgroup SIR_STATUS SIR_STATUS + * @brief System Initialization Status Register. + * @{ + */ + #define MXC_F_SIR_STATUS_CFG_VALID_POS 0 /**< STATUS_CFG_VALID Position */ + #define MXC_F_SIR_STATUS_CFG_VALID ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_VALID_POS)) /**< STATUS_CFG_VALID Mask */ + + #define MXC_F_SIR_STATUS_CFG_ERR_POS 1 /**< STATUS_CFG_ERR Position */ + #define MXC_F_SIR_STATUS_CFG_ERR ((uint32_t)(0x1UL << MXC_F_SIR_STATUS_CFG_ERR_POS)) /**< STATUS_CFG_ERR Mask */ + +/**@} end of group SIR_STATUS_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_ADDR SIR_ADDR + * @brief Read-only field set by the SIB block if a CRC error occurs during the read of + * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals + * 1). + * @{ + */ + #define MXC_F_SIR_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ + #define MXC_F_SIR_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group SIR_ADDR_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SIR_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h new file mode 100644 index 00000000000..e45ef62e6ea --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h @@ -0,0 +1,442 @@ +/** + * @file spi_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPI_REGS_H_ +#define _SPI_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spi + * @defgroup spi_registers SPI_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @details SPI peripheral. + */ + +/** + * @ingroup spi_registers + * Structure type to access the SPI Registers. + */ +typedef struct { + __IO uint32_t data; /**< \b 0x00: SPI DATA Register */ + __IO uint32_t ctrl0; /**< \b 0x04: SPI CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x08: SPI CTRL1 Register */ + __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ + __IO uint32_t ss_time; /**< \b 0x10: SPI SS_TIME Register */ + __IO uint32_t clk_cfg; /**< \b 0x14: SPI CLK_CFG Register */ + __I uint32_t rsv_0x18; + __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ + __IO uint32_t int_fl; /**< \b 0x20: SPI INT_FL Register */ + __IO uint32_t int_en; /**< \b 0x24: SPI INT_EN Register */ + __IO uint32_t wake_fl; /**< \b 0x28: SPI WAKE_FL Register */ + __IO uint32_t wake_en; /**< \b 0x2C: SPI WAKE_EN Register */ + __I uint32_t stat; /**< \b 0x30: SPI STAT Register */ +} mxc_spi_regs_t; + +/* Register offsets for module SPI */ +/** + * @ingroup spi_registers + * @defgroup SPI_Register_Offsets Register Offsets + * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. + * @{ + */ + #define MXC_R_SPI_DATA ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ + #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ + #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ + #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ + #define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ + #define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ + #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ + #define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ + #define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ + #define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ + #define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ + #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +/**@} end of group spi_registers */ + +/** + * @ingroup spi_registers + * @defgroup SPI_DATA SPI_DATA + * @brief Register for reading and writing the FIFO. + * @{ + */ +/**@} end of group SPI_DATA_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL0 SPI_CTRL0 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI_CTRL0_SPI_EN_POS 0 /**< CTRL0_SPI_EN Position */ + #define MXC_F_SPI_CTRL0_SPI_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SPI_EN_POS)) /**< CTRL0_SPI_EN Mask */ + + #define MXC_F_SPI_CTRL0_MM_EN_POS 1 /**< CTRL0_MM_EN Position */ + #define MXC_F_SPI_CTRL0_MM_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MM_EN_POS)) /**< CTRL0_MM_EN Mask */ + + #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ + #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ + + #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ + #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ + + #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ + #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ + + #define MXC_F_SPI_CTRL0_SS_SEL_POS 16 /**< CTRL0_SS_SEL Position */ + #define MXC_F_SPI_CTRL0_SS_SEL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_SEL_POS)) /**< CTRL0_SS_SEL Mask */ + #define MXC_V_SPI_CTRL0_SS_SEL_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SEL_SS0 Value */ + #define MXC_S_SPI_CTRL0_SS_SEL_SS0 (MXC_V_SPI_CTRL0_SS_SEL_SS0 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS0 Setting */ + #define MXC_V_SPI_CTRL0_SS_SEL_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SEL_SS1 Value */ + #define MXC_S_SPI_CTRL0_SS_SEL_SS1 (MXC_V_SPI_CTRL0_SS_SEL_SS1 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS1 Setting */ + #define MXC_V_SPI_CTRL0_SS_SEL_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SEL_SS2 Value */ + #define MXC_S_SPI_CTRL0_SS_SEL_SS2 (MXC_V_SPI_CTRL0_SS_SEL_SS2 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS2 Setting */ + #define MXC_V_SPI_CTRL0_SS_SEL_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SEL_SS3 Value */ + #define MXC_S_SPI_CTRL0_SS_SEL_SS3 (MXC_V_SPI_CTRL0_SS_SEL_SS3 << MXC_F_SPI_CTRL0_SS_SEL_POS) /**< CTRL0_SS_SEL_SS3 Setting */ + +/**@} end of group SPI_CTRL0_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL1 SPI_CTRL1 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ + #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ + + #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ + #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ + +/**@} end of group SPI_CTRL1_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL2 SPI_CTRL2 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI_CTRL2_CLK_PHA_POS 0 /**< CTRL2_CLK_PHA Position */ + #define MXC_F_SPI_CTRL2_CLK_PHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_PHA_POS)) /**< CTRL2_CLK_PHA Mask */ + + #define MXC_F_SPI_CTRL2_CLK_POL_POS 1 /**< CTRL2_CLK_POL Position */ + #define MXC_F_SPI_CTRL2_CLK_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLK_POL_POS)) /**< CTRL2_CLK_POL Mask */ + + #define MXC_F_SPI_CTRL2_NUM_BITS_POS 8 /**< CTRL2_NUM_BITS Position */ + #define MXC_F_SPI_CTRL2_NUM_BITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUM_BITS_POS)) /**< CTRL2_NUM_BITS Mask */ + #define MXC_V_SPI_CTRL2_NUM_BITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUM_BITS_0 Value */ + #define MXC_S_SPI_CTRL2_NUM_BITS_0 (MXC_V_SPI_CTRL2_NUM_BITS_0 << MXC_F_SPI_CTRL2_NUM_BITS_POS) /**< CTRL2_NUM_BITS_0 Setting */ + + #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ + #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ + #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ + #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ + #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ + #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ + #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ + #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ + + #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ + #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ + + #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ + #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ + +/**@} end of group SPI_CTRL2_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_SS_TIME SPI_SS_TIME + * @brief Register for controlling SPI peripheral/Slave Select Timing. + * @{ + */ + #define MXC_F_SPI_SS_TIME_SSACT1_POS 0 /**< SS_TIME_SSACT1 Position */ + #define MXC_F_SPI_SS_TIME_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT1_POS)) /**< SS_TIME_SSACT1 Mask */ + #define MXC_V_SPI_SS_TIME_SSACT1_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT1_256 Value */ + #define MXC_S_SPI_SS_TIME_SSACT1_256 (MXC_V_SPI_SS_TIME_SSACT1_256 << MXC_F_SPI_SS_TIME_SSACT1_POS) /**< SS_TIME_SSACT1_256 Setting */ + + #define MXC_F_SPI_SS_TIME_SSACT2_POS 8 /**< SS_TIME_SSACT2 Position */ + #define MXC_F_SPI_SS_TIME_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSACT2_POS)) /**< SS_TIME_SSACT2 Mask */ + #define MXC_V_SPI_SS_TIME_SSACT2_256 ((uint32_t)0x0UL) /**< SS_TIME_SSACT2_256 Value */ + #define MXC_S_SPI_SS_TIME_SSACT2_256 (MXC_V_SPI_SS_TIME_SSACT2_256 << MXC_F_SPI_SS_TIME_SSACT2_POS) /**< SS_TIME_SSACT2_256 Setting */ + + #define MXC_F_SPI_SS_TIME_SSINACT_POS 16 /**< SS_TIME_SSINACT Position */ + #define MXC_F_SPI_SS_TIME_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_SSINACT_POS)) /**< SS_TIME_SSINACT Mask */ + #define MXC_V_SPI_SS_TIME_SSINACT_256 ((uint32_t)0x0UL) /**< SS_TIME_SSINACT_256 Value */ + #define MXC_S_SPI_SS_TIME_SSINACT_256 (MXC_V_SPI_SS_TIME_SSINACT_256 << MXC_F_SPI_SS_TIME_SSINACT_POS) /**< SS_TIME_SSINACT_256 Setting */ + +/**@} end of group SPI_SS_TIME_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CLK_CFG SPI_CLK_CFG + * @brief Register for controlling SPI clock rate. + * @{ + */ + #define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ + #define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ + #define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ + #define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ + + #define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ + #define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ + #define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ + #define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ + + #define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ + #define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ + +/**@} end of group SPI_CLK_CFG_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_DMA SPI_DMA + * @brief Register for controlling DMA. + * @{ + */ + #define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ + #define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ + + #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ + #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ + + #define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ + #define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ + + #define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + + #define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ + #define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ + + #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ + #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ + + #define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ + #define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ + + #define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + +/**@} end of group SPI_DMA_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INT_FL SPI_INT_FL + * @brief Register for reading and clearing interrupt flags. All bits are write 1 to + * clear. + * @{ + */ + #define MXC_F_SPI_INT_FL_TX_LEVEL_POS 0 /**< INT_FL_TX_LEVEL Position */ + #define MXC_F_SPI_INT_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_LEVEL_POS)) /**< INT_FL_TX_LEVEL Mask */ + + #define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ + #define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ + + #define MXC_F_SPI_INT_FL_RX_LEVEL_POS 2 /**< INT_FL_RX_LEVEL Position */ + #define MXC_F_SPI_INT_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_LEVEL_POS)) /**< INT_FL_RX_LEVEL Mask */ + + #define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ + #define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ + + #define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ + #define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ + + #define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ + #define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ + + #define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ + #define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ + + #define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ + #define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ + + #define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ + #define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ + + #define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ + #define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ + + #define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ + #define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ + + #define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ + #define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ + +/**@} end of group SPI_INT_FL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INT_EN SPI_INT_EN + * @brief Register for enabling interrupts. + * @{ + */ + #define MXC_F_SPI_INT_EN_TX_LEVEL_POS 0 /**< INT_EN_TX_LEVEL Position */ + #define MXC_F_SPI_INT_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_LEVEL_POS)) /**< INT_EN_TX_LEVEL Mask */ + + #define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ + #define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ + + #define MXC_F_SPI_INT_EN_RX_LEVEL_POS 2 /**< INT_EN_RX_LEVEL Position */ + #define MXC_F_SPI_INT_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_LEVEL_POS)) /**< INT_EN_RX_LEVEL Mask */ + + #define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ + #define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ + + #define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ + #define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ + + #define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ + #define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ + + #define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ + #define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ + + #define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ + #define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ + + #define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ + #define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ + + #define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ + #define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ + + #define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ + #define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ + + #define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ + #define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ + + #define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ + #define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ + +/**@} end of group SPI_INT_EN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WAKE_FL SPI_WAKE_FL + * @brief Register for wake up flags. All bits in this register are write 1 to clear. + * @{ + */ + #define MXC_F_SPI_WAKE_FL_TX_LEVEL_POS 0 /**< WAKE_FL_TX_LEVEL Position */ + #define MXC_F_SPI_WAKE_FL_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_LEVEL_POS)) /**< WAKE_FL_TX_LEVEL Mask */ + + #define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ + #define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ + + #define MXC_F_SPI_WAKE_FL_RX_LEVEL_POS 2 /**< WAKE_FL_RX_LEVEL Position */ + #define MXC_F_SPI_WAKE_FL_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_LEVEL_POS)) /**< WAKE_FL_RX_LEVEL Mask */ + + #define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ + #define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ + +/**@} end of group SPI_WAKE_FL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WAKE_EN SPI_WAKE_EN + * @brief Register for wake up enable. + * @{ + */ + #define MXC_F_SPI_WAKE_EN_TX_LEVEL_POS 0 /**< WAKE_EN_TX_LEVEL Position */ + #define MXC_F_SPI_WAKE_EN_TX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_LEVEL_POS)) /**< WAKE_EN_TX_LEVEL Mask */ + + #define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ + #define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ + + #define MXC_F_SPI_WAKE_EN_RX_LEVEL_POS 2 /**< WAKE_EN_RX_LEVEL Position */ + #define MXC_F_SPI_WAKE_EN_RX_LEVEL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_LEVEL_POS)) /**< WAKE_EN_RX_LEVEL Mask */ + + #define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ + #define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ + +/**@} end of group SPI_WAKE_EN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_STAT SPI_STAT + * @brief SPI Status register. + * @{ + */ + #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ + #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ + +/**@} end of group SPI_STAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPI_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h new file mode 100644 index 00000000000..c2cb890c5ed --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h @@ -0,0 +1,346 @@ +/** + * @file spimss_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPIMSS_REGS_H_ +#define _SPIMSS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spimss + * @defgroup spimss_registers SPIMSS_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + * @details Serial Peripheral Interface. + */ + +/** + * @ingroup spimss_registers + * Structure type to access the SPIMSS Registers. + */ +typedef struct { + __IO uint16_t data; /**< \b 0x00: SPIMSS DATA Register */ + __I uint16_t rsv_0x2; + __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ + __IO uint32_t int_fl; /**< \b 0x08: SPIMSS INT_FL Register */ + __IO uint32_t mode; /**< \b 0x0C: SPIMSS MODE Register */ + __I uint32_t rsv_0x10; + __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ + __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ + __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ +} mxc_spimss_regs_t; + +/* Register offsets for module SPIMSS */ +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_Register_Offsets Register Offsets + * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. + * @{ + */ + #define MXC_R_SPIMSS_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ + #define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: 0x0004 */ + #define MXC_R_SPIMSS_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: 0x0008 */ + #define MXC_R_SPIMSS_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: 0x000C */ + #define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: 0x0014 */ + #define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: 0x0018 */ + #define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: 0x001C */ +/**@} end of group spimss_registers */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DATA SPIMSS_DATA + * @brief SPI 16-bit Data Access + * @{ + */ + #define MXC_F_SPIMSS_DATA_DATA_POS 0 /**< DATA_DATA Position */ + #define MXC_F_SPIMSS_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group SPIMSS_DATA_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_CTRL SPIMSS_CTRL + * @brief SPI Control Register. + * @{ + */ + #define MXC_F_SPIMSS_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ + #define MXC_F_SPIMSS_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ + + #define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ + #define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ + + #define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ + #define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ + + #define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ + #define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ + + #define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ + #define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ + + #define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ + #define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ + + #define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */ + #define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */ + + #define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ + #define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ + +/**@} end of group SPIMSS_CTRL_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_INT_FL SPIMSS_INT_FL + * @brief SPI Interrupt Flag Register. + * @{ + */ + #define MXC_F_SPIMSS_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */ + #define MXC_F_SPIMSS_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */ + + #define MXC_F_SPIMSS_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */ + #define MXC_F_SPIMSS_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */ + + #define MXC_F_SPIMSS_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */ + #define MXC_F_SPIMSS_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */ + + #define MXC_F_SPIMSS_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */ + #define MXC_F_SPIMSS_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */ + + #define MXC_F_SPIMSS_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */ + #define MXC_F_SPIMSS_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */ + + #define MXC_F_SPIMSS_INT_FL_COL_POS 5 /**< INT_FL_COL Position */ + #define MXC_F_SPIMSS_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_COL_POS)) /**< INT_FL_COL Mask */ + + #define MXC_F_SPIMSS_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */ + #define MXC_F_SPIMSS_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */ + + #define MXC_F_SPIMSS_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */ + #define MXC_F_SPIMSS_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */ + +/**@} end of group SPIMSS_INT_FL_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_MODE SPIMSS_MODE + * @brief SPI Mode Register. + * @{ + */ + #define MXC_F_SPIMSS_MODE_SSV_POS 0 /**< MODE_SSV Position */ + #define MXC_F_SPIMSS_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SSV_POS)) /**< MODE_SSV Mask */ + + #define MXC_F_SPIMSS_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */ + #define MXC_F_SPIMSS_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */ + + #define MXC_F_SPIMSS_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */ + #define MXC_F_SPIMSS_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */ + #define MXC_V_SPIMSS_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */ + #define MXC_S_SPIMSS_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */ + + #define MXC_F_SPIMSS_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */ + #define MXC_F_SPIMSS_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */ + +/**@} end of group SPIMSS_MODE_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_BRG SPIMSS_BRG + * @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for + * the SPI Baud Rate Generator. The reload value must be greater than or equal to + * 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by + * 4). + * @{ + */ + #define MXC_F_SPIMSS_BRG_DIV_POS 0 /**< BRG_DIV Position */ + #define MXC_F_SPIMSS_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_DIV_POS)) /**< BRG_DIV Mask */ + +/**@} end of group SPIMSS_BRG_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DMA SPIMSS_DMA + * @brief SPI DMA Register. + * @{ + */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */ + + #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + +/**@} end of group SPIMSS_DMA_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL + * @brief I2S Control Register. + * @{ + */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ + +/**@} end of group SPIMSS_I2S_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPIMSS_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h new file mode 100644 index 00000000000..b2688facdaf --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h @@ -0,0 +1,91 @@ +/** + * @file system_max32660.h + * @brief System-specific header file + */ + + +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + ******************************************************************************/ + +#ifndef _SYSTEM_MAX32660_H_ +#define _SYSTEM_MAX32660_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#ifndef HFX_FREQ +#define HFX_FREQ 32768 +#endif + +#ifndef NANORING_FREQ +#define NANORING_FREQ 8000 +#endif + +#ifndef HIRC96_FREQ +#define HIRC96_FREQ 96000000 +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +#ifndef PeripheralClock +#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */ +#endif + +/* + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/* + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MAX32660_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h new file mode 100644 index 00000000000..d9062f849cd --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h @@ -0,0 +1,239 @@ +/** + * @file tmr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _TMR_REGS_H_ +#define _TMR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup tmr + * @defgroup tmr_registers TMR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @details Low-Power Configurable Timer + */ + +/** + * @ingroup tmr_registers + * Structure type to access the TMR Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ + __IO uint32_t intr; /**< \b 0x0C: TMR INTR Register */ + __IO uint32_t cn; /**< \b 0x10: TMR CN Register */ +} mxc_tmr_regs_t; + +/* Register offsets for module TMR */ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @{ + */ + #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ + #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ + #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ + #define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ + #define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +/**@} end of group tmr_registers */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CNT TMR_CNT + * @brief Timer Counter Register. + * @{ + */ + #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ + #define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group TMR_CNT_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CMP TMR_CMP + * @brief Timer Compare Register. + * @{ + */ + #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ + #define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ + +/**@} end of group TMR_CMP_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_PWM TMR_PWM + * @brief Timer PWM Register. + * @{ + */ + #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ + #define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ + +/**@} end of group TMR_PWM_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTR TMR_INTR + * @brief Timer Interrupt Status Register. + * @{ + */ + #define MXC_F_TMR_INTR_IRQ_POS 0 /**< INTR_IRQ Position */ + #define MXC_F_TMR_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_POS)) /**< INTR_IRQ Mask */ + +/**@} end of group TMR_INTR_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CN TMR_CN + * @brief Timer Control Register. + * @{ + */ + #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ + #define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ + #define MXC_V_TMR_CN_TMODE_ONE_SHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONE_SHOT Value */ + #define MXC_S_TMR_CN_TMODE_ONE_SHOT (MXC_V_TMR_CN_TMODE_ONE_SHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONE_SHOT Setting */ + #define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ + #define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ + #define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ + #define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ + #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ + #define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ + #define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ + #define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ + #define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ + #define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ + #define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ + #define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ + #define MXC_V_TMR_CN_TMODE_CAPCOMP ((uint32_t)0x7UL) /**< CN_TMODE_CAPCOMP Value */ + #define MXC_S_TMR_CN_TMODE_CAPCOMP (MXC_V_TMR_CN_TMODE_CAPCOMP << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPCOMP Setting */ + #define MXC_V_TMR_CN_TMODE_DUAL_EDGE ((uint32_t)0x8UL) /**< CN_TMODE_DUAL_EDGE Value */ + #define MXC_S_TMR_CN_TMODE_DUAL_EDGE (MXC_V_TMR_CN_TMODE_DUAL_EDGE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_DUAL_EDGE Setting */ + #define MXC_V_TMR_CN_TMODE_IGATED ((uint32_t)0xCUL) /**< CN_TMODE_IGATED Value */ + #define MXC_S_TMR_CN_TMODE_IGATED (MXC_V_TMR_CN_TMODE_IGATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_IGATED Setting */ + + #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ + #define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ + #define MXC_V_TMR_CN_PRES_DIV_BY_1 ((uint32_t)0x0UL) /**< CN_PRES_DIV_BY_1 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_1 (MXC_V_TMR_CN_PRES_DIV_BY_1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_2 ((uint32_t)0x1UL) /**< CN_PRES_DIV_BY_2 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_2 (MXC_V_TMR_CN_PRES_DIV_BY_2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_4 ((uint32_t)0x2UL) /**< CN_PRES_DIV_BY_4 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_4 (MXC_V_TMR_CN_PRES_DIV_BY_4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_8 ((uint32_t)0x3UL) /**< CN_PRES_DIV_BY_8 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_8 (MXC_V_TMR_CN_PRES_DIV_BY_8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_16 ((uint32_t)0x4UL) /**< CN_PRES_DIV_BY_16 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_16 (MXC_V_TMR_CN_PRES_DIV_BY_16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_16 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_32 ((uint32_t)0x5UL) /**< CN_PRES_DIV_BY_32 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_32 (MXC_V_TMR_CN_PRES_DIV_BY_32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_32 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_64 ((uint32_t)0x6UL) /**< CN_PRES_DIV_BY_64 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_64 (MXC_V_TMR_CN_PRES_DIV_BY_64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_64 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_128 ((uint32_t)0x7UL) /**< CN_PRES_DIV_BY_128 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_128 (MXC_V_TMR_CN_PRES_DIV_BY_128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_128 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_256 ((uint32_t)0x8UL) /**< CN_PRES_DIV_BY_256 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_256 (MXC_V_TMR_CN_PRES_DIV_BY_256 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_256 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_512 ((uint32_t)0x9UL) /**< CN_PRES_DIV_BY_512 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_512 (MXC_V_TMR_CN_PRES_DIV_BY_512 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_512 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_1024 ((uint32_t)0xAUL) /**< CN_PRES_DIV_BY_1024 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_1024 (MXC_V_TMR_CN_PRES_DIV_BY_1024 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_1024 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_2048 ((uint32_t)0xBUL) /**< CN_PRES_DIV_BY_2048 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_2048 (MXC_V_TMR_CN_PRES_DIV_BY_2048 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_2048 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_4096 ((uint32_t)0xCUL) /**< CN_PRES_DIV_BY_4096 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_4096 (MXC_V_TMR_CN_PRES_DIV_BY_4096 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_4096 Setting */ + #define MXC_V_TMR_CN_PRES_DIV_BY_8192 ((uint32_t)0xDUL) /**< CN_PRES_DIV_BY_8192 Value */ + #define MXC_S_TMR_CN_PRES_DIV_BY_8192 (MXC_V_TMR_CN_PRES_DIV_BY_8192 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV_BY_8192 Setting */ + + #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ + #define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ + + #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ + #define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ + + #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ + #define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ + + #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ + #define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ + + #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ + #define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ + + #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ + #define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ + + #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ + #define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ + +/**@} end of group TMR_CN_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h new file mode 100644 index 00000000000..6340801d687 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h @@ -0,0 +1,402 @@ +/** + * @file uart_regs.h + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _UART_REGS_H_ +#define _UART_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup uart + * @defgroup uart_registers UART_Registers + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @details UART + */ + +/** + * @ingroup uart_registers + * Structure type to access the UART Registers. + */ +typedef struct { + __IO uint32_t ctrl0; /**< \b 0x00: UART CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x04: UART CTRL1 Register */ + __I uint32_t stat; /**< \b 0x08: UART STAT Register */ + __IO uint32_t int_en; /**< \b 0x0C: UART INT_EN Register */ + __IO uint32_t int_fl; /**< \b 0x10: UART INT_FL Register */ + __IO uint32_t baud0; /**< \b 0x14: UART BAUD0 Register */ + __IO uint32_t baud1; /**< \b 0x18: UART BAUD1 Register */ + __IO uint32_t fifo; /**< \b 0x1C: UART FIFO Register */ + __IO uint32_t dma; /**< \b 0x20: UART DMA Register */ + __IO uint32_t txfifo; /**< \b 0x24: UART TXFIFO Register */ +} mxc_uart_regs_t; + +/* Register offsets for module UART */ +/** + * @ingroup uart_registers + * @defgroup UART_Register_Offsets Register Offsets + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @{ + */ + #define MXC_R_UART_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ + #define MXC_R_UART_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ + #define MXC_R_UART_STAT ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ + #define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ + #define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ + #define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ + #define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ + #define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ + #define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ + #define MXC_R_UART_TXFIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: 0x0024 */ +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL0 UART_CTRL0 + * @brief Control Register. + * @{ + */ + #define MXC_F_UART_CTRL0_ENABLE_POS 0 /**< CTRL0_ENABLE Position */ + #define MXC_F_UART_CTRL0_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_ENABLE_POS)) /**< CTRL0_ENABLE Mask */ + + #define MXC_F_UART_CTRL0_PARITY_EN_POS 1 /**< CTRL0_PARITY_EN Position */ + #define MXC_F_UART_CTRL0_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_EN_POS)) /**< CTRL0_PARITY_EN Mask */ + + #define MXC_F_UART_CTRL0_PARITY_MODE_POS 2 /**< CTRL0_PARITY_MODE Position */ + #define MXC_F_UART_CTRL0_PARITY_MODE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_PARITY_MODE_POS)) /**< CTRL0_PARITY_MODE Mask */ + #define MXC_V_UART_CTRL0_PARITY_MODE_EVEN ((uint32_t)0x0UL) /**< CTRL0_PARITY_MODE_EVEN Value */ + #define MXC_S_UART_CTRL0_PARITY_MODE_EVEN (MXC_V_UART_CTRL0_PARITY_MODE_EVEN << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_EVEN Setting */ + #define MXC_V_UART_CTRL0_PARITY_MODE_ODD ((uint32_t)0x1UL) /**< CTRL0_PARITY_MODE_ODD Value */ + #define MXC_S_UART_CTRL0_PARITY_MODE_ODD (MXC_V_UART_CTRL0_PARITY_MODE_ODD << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_ODD Setting */ + #define MXC_V_UART_CTRL0_PARITY_MODE_MARK ((uint32_t)0x2UL) /**< CTRL0_PARITY_MODE_MARK Value */ + #define MXC_S_UART_CTRL0_PARITY_MODE_MARK (MXC_V_UART_CTRL0_PARITY_MODE_MARK << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_MARK Setting */ + #define MXC_V_UART_CTRL0_PARITY_MODE_SPACE ((uint32_t)0x3UL) /**< CTRL0_PARITY_MODE_SPACE Value */ + #define MXC_S_UART_CTRL0_PARITY_MODE_SPACE (MXC_V_UART_CTRL0_PARITY_MODE_SPACE << MXC_F_UART_CTRL0_PARITY_MODE_POS) /**< CTRL0_PARITY_MODE_SPACE Setting */ + + #define MXC_F_UART_CTRL0_PARITY_LVL_POS 4 /**< CTRL0_PARITY_LVL Position */ + #define MXC_F_UART_CTRL0_PARITY_LVL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_PARITY_LVL_POS)) /**< CTRL0_PARITY_LVL Mask */ + + #define MXC_F_UART_CTRL0_TXFLUSH_POS 5 /**< CTRL0_TXFLUSH Position */ + #define MXC_F_UART_CTRL0_TXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_TXFLUSH_POS)) /**< CTRL0_TXFLUSH Mask */ + + #define MXC_F_UART_CTRL0_RXFLUSH_POS 6 /**< CTRL0_RXFLUSH Position */ + #define MXC_F_UART_CTRL0_RXFLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_RXFLUSH_POS)) /**< CTRL0_RXFLUSH Mask */ + + #define MXC_F_UART_CTRL0_BITACC_POS 7 /**< CTRL0_BITACC Position */ + #define MXC_F_UART_CTRL0_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BITACC_POS)) /**< CTRL0_BITACC Mask */ + + #define MXC_F_UART_CTRL0_SIZE_POS 8 /**< CTRL0_SIZE Position */ + #define MXC_F_UART_CTRL0_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL0_SIZE_POS)) /**< CTRL0_SIZE Mask */ + #define MXC_V_UART_CTRL0_SIZE_5 ((uint32_t)0x0UL) /**< CTRL0_SIZE_5 Value */ + #define MXC_S_UART_CTRL0_SIZE_5 (MXC_V_UART_CTRL0_SIZE_5 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_5 Setting */ + #define MXC_V_UART_CTRL0_SIZE_6 ((uint32_t)0x1UL) /**< CTRL0_SIZE_6 Value */ + #define MXC_S_UART_CTRL0_SIZE_6 (MXC_V_UART_CTRL0_SIZE_6 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_6 Setting */ + #define MXC_V_UART_CTRL0_SIZE_7 ((uint32_t)0x2UL) /**< CTRL0_SIZE_7 Value */ + #define MXC_S_UART_CTRL0_SIZE_7 (MXC_V_UART_CTRL0_SIZE_7 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_7 Setting */ + #define MXC_V_UART_CTRL0_SIZE_8 ((uint32_t)0x3UL) /**< CTRL0_SIZE_8 Value */ + #define MXC_S_UART_CTRL0_SIZE_8 (MXC_V_UART_CTRL0_SIZE_8 << MXC_F_UART_CTRL0_SIZE_POS) /**< CTRL0_SIZE_8 Setting */ + + #define MXC_F_UART_CTRL0_STOP_POS 10 /**< CTRL0_STOP Position */ + #define MXC_F_UART_CTRL0_STOP ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_STOP_POS)) /**< CTRL0_STOP Mask */ + + #define MXC_F_UART_CTRL0_FLOW_POS 11 /**< CTRL0_FLOW Position */ + #define MXC_F_UART_CTRL0_FLOW ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOW_POS)) /**< CTRL0_FLOW Mask */ + + #define MXC_F_UART_CTRL0_FLOWPOL_POS 12 /**< CTRL0_FLOWPOL Position */ + #define MXC_F_UART_CTRL0_FLOWPOL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_FLOWPOL_POS)) /**< CTRL0_FLOWPOL Mask */ + + #define MXC_F_UART_CTRL0_NULLMOD_POS 13 /**< CTRL0_NULLMOD Position */ + #define MXC_F_UART_CTRL0_NULLMOD ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_NULLMOD_POS)) /**< CTRL0_NULLMOD Mask */ + + #define MXC_F_UART_CTRL0_BREAK_POS 14 /**< CTRL0_BREAK Position */ + #define MXC_F_UART_CTRL0_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_BREAK_POS)) /**< CTRL0_BREAK Mask */ + + #define MXC_F_UART_CTRL0_CLK_SEL_POS 15 /**< CTRL0_CLK_SEL Position */ + #define MXC_F_UART_CTRL0_CLK_SEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL0_CLK_SEL_POS)) /**< CTRL0_CLK_SEL Mask */ + + #define MXC_F_UART_CTRL0_TO_CNT_POS 16 /**< CTRL0_TO_CNT Position */ + #define MXC_F_UART_CTRL0_TO_CNT ((uint32_t)(0xFFUL << MXC_F_UART_CTRL0_TO_CNT_POS)) /**< CTRL0_TO_CNT Mask */ + +/**@} end of group UART_CTRL0_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL1 UART_CTRL1 + * @brief Threshold Control register. + * @{ + */ + #define MXC_F_UART_CTRL1_RX_FIFO_LVL_POS 0 /**< CTRL1_RX_FIFO_LVL Position */ + #define MXC_F_UART_CTRL1_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS)) /**< CTRL1_RX_FIFO_LVL Mask */ + + #define MXC_F_UART_CTRL1_TX_FIFO_LVL_POS 8 /**< CTRL1_TX_FIFO_LVL Position */ + #define MXC_F_UART_CTRL1_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS)) /**< CTRL1_TX_FIFO_LVL Mask */ + + #define MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS 16 /**< CTRL1_RTS_FIFO_LVL Position */ + #define MXC_F_UART_CTRL1_RTS_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_UART_CTRL1_RTS_FIFO_LVL_POS)) /**< CTRL1_RTS_FIFO_LVL Mask */ + +/**@} end of group UART_CTRL1_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_STAT UART_STAT + * @brief Status Register. + * @{ + */ + #define MXC_F_UART_STAT_TX_BUSY_POS 0 /**< STAT_TX_BUSY Position */ + #define MXC_F_UART_STAT_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_BUSY_POS)) /**< STAT_TX_BUSY Mask */ + + #define MXC_F_UART_STAT_RX_BUSY_POS 1 /**< STAT_RX_BUSY Position */ + #define MXC_F_UART_STAT_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_BUSY_POS)) /**< STAT_RX_BUSY Mask */ + + #define MXC_F_UART_STAT_PARITY_POS 2 /**< STAT_PARITY Position */ + #define MXC_F_UART_STAT_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STAT_PARITY_POS)) /**< STAT_PARITY Mask */ + + #define MXC_F_UART_STAT_BREAK_POS 3 /**< STAT_BREAK Position */ + #define MXC_F_UART_STAT_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STAT_BREAK_POS)) /**< STAT_BREAK Mask */ + + #define MXC_F_UART_STAT_RX_EMPTY_POS 4 /**< STAT_RX_EMPTY Position */ + #define MXC_F_UART_STAT_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_EMPTY_POS)) /**< STAT_RX_EMPTY Mask */ + + #define MXC_F_UART_STAT_RX_FULL_POS 5 /**< STAT_RX_FULL Position */ + #define MXC_F_UART_STAT_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_FULL_POS)) /**< STAT_RX_FULL Mask */ + + #define MXC_F_UART_STAT_TX_EMPTY_POS 6 /**< STAT_TX_EMPTY Position */ + #define MXC_F_UART_STAT_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_EMPTY_POS)) /**< STAT_TX_EMPTY Mask */ + + #define MXC_F_UART_STAT_TX_FULL_POS 7 /**< STAT_TX_FULL Position */ + #define MXC_F_UART_STAT_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STAT_TX_FULL_POS)) /**< STAT_TX_FULL Mask */ + + #define MXC_F_UART_STAT_RX_NUM_POS 8 /**< STAT_RX_NUM Position */ + #define MXC_F_UART_STAT_RX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_RX_NUM_POS)) /**< STAT_RX_NUM Mask */ + + #define MXC_F_UART_STAT_TX_NUM_POS 16 /**< STAT_TX_NUM Position */ + #define MXC_F_UART_STAT_TX_NUM ((uint32_t)(0x3FUL << MXC_F_UART_STAT_TX_NUM_POS)) /**< STAT_TX_NUM Mask */ + + #define MXC_F_UART_STAT_RX_TO_POS 24 /**< STAT_RX_TO Position */ + #define MXC_F_UART_STAT_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STAT_RX_TO_POS)) /**< STAT_RX_TO Mask */ + +/**@} end of group UART_STAT_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_EN UART_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ + #define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ + #define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_INT_EN_CTS_POS 2 /**< INT_EN_CTS Position */ + #define MXC_F_UART_INT_EN_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_POS)) /**< INT_EN_CTS Mask */ + + #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ + #define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ + + #define MXC_F_UART_INT_EN_RX_FIFO_LVL_POS 4 /**< INT_EN_RX_FIFO_LVL Position */ + #define MXC_F_UART_INT_EN_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_LVL_POS)) /**< INT_EN_RX_FIFO_LVL Mask */ + + #define MXC_F_UART_INT_EN_TX_FIFO_AE_POS 5 /**< INT_EN_TX_FIFO_AE Position */ + #define MXC_F_UART_INT_EN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_AE_POS)) /**< INT_EN_TX_FIFO_AE Mask */ + + #define MXC_F_UART_INT_EN_TX_FIFO_LVL_POS 6 /**< INT_EN_TX_FIFO_LVL Position */ + #define MXC_F_UART_INT_EN_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_LVL_POS)) /**< INT_EN_TX_FIFO_LVL Mask */ + + #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ + #define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ + + #define MXC_F_UART_INT_EN_RX_TO_POS 8 /**< INT_EN_RX_TO Position */ + #define MXC_F_UART_INT_EN_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TO_POS)) /**< INT_EN_RX_TO Mask */ + + #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ + #define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ + +/**@} end of group UART_INT_EN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_FL UART_INT_FL + * @brief Interrupt Status Flags. + * @{ + */ + #define MXC_F_UART_INT_FL_FRAME_POS 0 /**< INT_FL_FRAME Position */ + #define MXC_F_UART_INT_FL_FRAME ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_FRAME_POS)) /**< INT_FL_FRAME Mask */ + + #define MXC_F_UART_INT_FL_PARITY_POS 1 /**< INT_FL_PARITY Position */ + #define MXC_F_UART_INT_FL_PARITY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_PARITY_POS)) /**< INT_FL_PARITY Mask */ + + #define MXC_F_UART_INT_FL_CTS_POS 2 /**< INT_FL_CTS Position */ + #define MXC_F_UART_INT_FL_CTS ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_POS)) /**< INT_FL_CTS Mask */ + + #define MXC_F_UART_INT_FL_RX_OVR_POS 3 /**< INT_FL_RX_OVR Position */ + #define MXC_F_UART_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ + + #define MXC_F_UART_INT_FL_RX_FIFO_LVL_POS 4 /**< INT_FL_RX_FIFO_LVL Position */ + #define MXC_F_UART_INT_FL_RX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_LVL_POS)) /**< INT_FL_RX_FIFO_LVL Mask */ + + #define MXC_F_UART_INT_FL_TX_FIFO_AE_POS 5 /**< INT_FL_TX_FIFO_AE Position */ + #define MXC_F_UART_INT_FL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_AE_POS)) /**< INT_FL_TX_FIFO_AE Mask */ + + #define MXC_F_UART_INT_FL_TX_FIFO_LVL_POS 6 /**< INT_FL_TX_FIFO_LVL Position */ + #define MXC_F_UART_INT_FL_TX_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_LVL_POS)) /**< INT_FL_TX_FIFO_LVL Mask */ + + #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ + #define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ + + #define MXC_F_UART_INT_FL_RX_TO_POS 8 /**< INT_FL_RX_TO Position */ + #define MXC_F_UART_INT_FL_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TO_POS)) /**< INT_FL_RX_TO Mask */ + + #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ + #define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ + +/**@} end of group UART_INT_FL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD0 UART_BAUD0 + * @brief Baud rate register. Integer portion. + * @{ + */ + #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ + #define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ + + #define MXC_F_UART_BAUD0_CLKDIV_POS 16 /**< BAUD0_CLKDIV Position */ + #define MXC_F_UART_BAUD0_CLKDIV ((uint32_t)(0x7UL << MXC_F_UART_BAUD0_CLKDIV_POS)) /**< BAUD0_CLKDIV Mask */ + #define MXC_V_UART_BAUD0_CLKDIV_128 ((uint32_t)0x0UL) /**< BAUD0_CLKDIV_128 Value */ + #define MXC_S_UART_BAUD0_CLKDIV_128 (MXC_V_UART_BAUD0_CLKDIV_128 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_128 Setting */ + #define MXC_V_UART_BAUD0_CLKDIV_64 ((uint32_t)0x1UL) /**< BAUD0_CLKDIV_64 Value */ + #define MXC_S_UART_BAUD0_CLKDIV_64 (MXC_V_UART_BAUD0_CLKDIV_64 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_64 Setting */ + #define MXC_V_UART_BAUD0_CLKDIV_32 ((uint32_t)0x2UL) /**< BAUD0_CLKDIV_32 Value */ + #define MXC_S_UART_BAUD0_CLKDIV_32 (MXC_V_UART_BAUD0_CLKDIV_32 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_32 Setting */ + #define MXC_V_UART_BAUD0_CLKDIV_16 ((uint32_t)0x3UL) /**< BAUD0_CLKDIV_16 Value */ + #define MXC_S_UART_BAUD0_CLKDIV_16 (MXC_V_UART_BAUD0_CLKDIV_16 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_16 Setting */ + #define MXC_V_UART_BAUD0_CLKDIV_8 ((uint32_t)0x4UL) /**< BAUD0_CLKDIV_8 Value */ + #define MXC_S_UART_BAUD0_CLKDIV_8 (MXC_V_UART_BAUD0_CLKDIV_8 << MXC_F_UART_BAUD0_CLKDIV_POS) /**< BAUD0_CLKDIV_8 Setting */ + +/**@} end of group UART_BAUD0_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD1 UART_BAUD1 + * @brief Baud rate register. Decimal Setting. + * @{ + */ + #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ + #define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ + +/**@} end of group UART_BAUD1_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_FIFO UART_FIFO + * @brief FIFO Data buffer. + * @{ + */ + #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ + #define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ + +/**@} end of group UART_FIFO_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_DMA UART_DMA + * @brief DMA Configuration. + * @{ + */ + #define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */ + #define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ + + #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ + #define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ + + #define MXC_F_UART_DMA_TXDMA_LVL_POS 8 /**< DMA_TXDMA_LVL Position */ + #define MXC_F_UART_DMA_TXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LVL_POS)) /**< DMA_TXDMA_LVL Mask */ + + #define MXC_F_UART_DMA_RXDMA_LVL_POS 16 /**< DMA_RXDMA_LVL Position */ + #define MXC_F_UART_DMA_RXDMA_LVL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LVL_POS)) /**< DMA_RXDMA_LVL Mask */ + +/**@} end of group UART_DMA_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_TXFIFO UART_TXFIFO + * @brief Transmit FIFO Status register. + * @{ + */ + #define MXC_F_UART_TXFIFO_DATA_POS 0 /**< TXFIFO_DATA Position */ + #define MXC_F_UART_TXFIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TXFIFO_DATA_POS)) /**< TXFIFO_DATA Mask */ + +/**@} end of group UART_TXFIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _UART_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h new file mode 100644 index 00000000000..ae0139f11d5 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h @@ -0,0 +1,214 @@ +/** + * @file wdt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _WDT_REGS_H_ +#define _WDT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif + +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wdt + * @defgroup wdt_registers WDT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @details Watchdog Timer 0 + */ + +/** + * @ingroup wdt_registers + * Structure type to access the WDT Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: WDT CTRL Register */ + __O uint32_t rst; /**< \b 0x04: WDT RST Register */ +} mxc_wdt_regs_t; + +/* Register offsets for module WDT */ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @{ + */ + #define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ + #define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +/**@} end of group wdt_registers */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL WDT_CTRL + * @brief Watchdog Timer Control Register. + * @{ + */ + #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ + #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ + #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ + #define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ + + #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ + #define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ + + #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ + #define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ + + #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ + #define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ + + #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ + #define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ + +/**@} end of group WDT_CTRL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_RST WDT_RST + * @brief Watchdog Timer Reset Register. + * @{ + */ + #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ + #define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ + #define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ + #define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ + #define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ + #define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ + +/**@} end of group WDT_RST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c new file mode 100644 index 00000000000..2d7f4f204da --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -0,0 +1,146 @@ +/** + * @file system_max32660.c + * @brief System-level initialization implementation file + */ + +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +#include +#include +#include +#include "max32660.h" +#include "gcr_regs.h" +#include "pwrseq_regs.h" +#include "tmr_regs.h" +#include "wdt_regs.h" +#include "mxc_sys.h" +#include "icc.h" + +uint32_t SystemCoreClock = HIRC96_FREQ; + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src,ovr; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL); + + if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) { + base_freq = HFX_FREQ; + } else { + if (clk_src == MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING) { + base_freq = NANORING_FREQ; + } else { + ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); + if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) { + base_freq = HIRC96_FREQ/4; + } else { + if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) { + base_freq = HIRC96_FREQ/2; + } else { + base_freq = HIRC96_FREQ; + } + } + } + } + + // Get the clock divider + div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS; + + SystemCoreClock = base_freq >> div; +} + +/* This function is called before C runtime initialization and can be + * implemented by the application for early initializations. If a value other + * than '0' is returned, the C runtime initialization will be skipped. + * + * You may over-ride this function in your program by defining a custom + * PreInit(), but care should be taken to reproduce the initilization steps + * or a non-functional system may result. + */ +__weak int PreInit(void) +{ + /* Switch system clock to HIRC, 96 MHz*/ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); + + /* Enable cache here to reduce boot time */ + MXC_ICC_Enable(); + + return 0; +} + +/* Override this function for early platform initialization +*/ +__weak void low_level_init(void) +{ + +} + +/* This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +__weak void SystemInit(void) +{ + MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ + +#if (__FPU_PRESENT == 1) + /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ + /* Grant full access, per "Table B3-24 CPACR bit assignments". */ + /* DDI0403D "ARMv7-M Architecture Reference Manual" */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; + __DSB(); + __ISB(); +#endif + + /* Disable clocks to peripherals by default to reduce power */ + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); + + /* Early platform initialization */ + low_level_init(); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h new file mode 100644 index 00000000000..f8eda9c44a0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/dma.h @@ -0,0 +1,426 @@ +/** + * @file dma.h + * @brief Direct Memory Access (DMA) driver function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#ifndef _DMA_H_ +#define _DMA_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_errors.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup dma Direct Memory Access (DMA) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + + +/** + * @brief Enumeration for the DMA Channel's priority level. + * + */ +typedef enum { + MXC_DMA_PRIO_HIGH = MXC_V_DMA_CFG_PRI_HIGH, ///< High Priority */ + MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CFG_PRI_MEDHIGH, ///< Medium High Priority */ + MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CFG_PRI_MEDLOW, ///< Medium Low Priority */ + MXC_DMA_PRIO_LOW = MXC_V_DMA_CFG_PRI_LOW, ///< Low Priority */ +} mxc_dma_priority_t; + +/** @brief DMA request select */ +typedef enum { + MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, ///< Memory to Memory DMA Request Selection + MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, ///< SPI0 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, ///< SPI1 Receive DMA Request Selection + MXC_DMA_REQUEST_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, ///< UART0 Receive DMA Request Selection + MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, ///< UART1 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, ///< I2C0 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, ///< I2C1 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, ///< SPI0 Transmit DMA Request Selection + MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, ///< SPI1 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, ///< UART0 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, ///< UART1 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, ///< I2C0 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, ///< I2C1 Transmit DMA Request Selection +} mxc_dma_reqsel_t; + +/** @brief Enumeration for the DMA prescaler */ +typedef enum { + MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, ///< Prescaler disabled + MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, ///< Divide by 256 + MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, ///< Divide by 65,536 + MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, ///< Divide by 16,777,216 +} mxc_dma_prescale_t; + +/** @brief Enumeration for the DMA timeout value */ +typedef enum { + MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, ///< DMA timeout of 4 clocks + MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, ///< DMA timeout of 8 clocks + MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, ///< DMA timeout of 16 clocks + MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, ///< DMA timeout of 32 clocks + MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, ///< DMA timeout of 64 clocks + MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, ///< DMA timeout of 128 clocks + MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, ///< DMA timeout of 256 clocks + MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, ///< DMA timeout of 512 clocks +} mxc_dma_timeout_t; + +/** @brief DMA transfer data width */ +typedef enum { + /* Using the '_V_' define instead of the '_S_' since these same values will be used to + specify the DSTWD also. The API functions will shift the value the correct amount + prior to writing the cfg register. */ + MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, ///< DMA transfer in bytes + MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words + MXC_DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, ///< DMA transfer in 32-bit words +} mxc_dma_width_t; + +/** + * @brief The basic configuration information to set up a DMA channel + * and prepare it for transfers. + * + */ +typedef struct { + int ch; ///< The channel to load the configuration data into + mxc_dma_reqsel_t reqsel;///< The request select line to be used (mem2mem, peripheral) + mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) + mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) + int srcinc_en; ///< Whether to increment the source address during the transfer + int dstinc_en; ///< Whether to increment the source address during the transfer +} mxc_dma_config_t; + +/** + * @brief The information needed to complete a DMA transfer + * + */ +typedef struct { + int ch; ///< The channel to use for the transfer + void* source; ///< Pointer to the source address, if applicable + void* dest; ///< Pointer to the destination address, if applicable + int len; ///< Number of bytes to transfer +} mxc_dma_srcdst_t; + +/** + * @brief The advanced configuration options, these are optional but could + * be needed in cases where multiple DMA channels are running concurrently + * or DMA is being used with low bandwidth peripherals. + * + */ +typedef struct { + int ch; ///< The channel to use for the transfer + mxc_dma_priority_t prio; ///< The DMA priority for the channel + unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer + mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout + mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer + unsigned int burst_size; ///< Number of bytes moved in a single burst +} mxc_dma_adv_config_t; + +/** + * @brief The callback called on completion of a DMA_MemCpy() transfer + * + * @param dest Pointer to the destination of the copy + */ +typedef void (*mxc_dma_complete_cb_t) (void* dest); + +/** + * @brief The callback called on completion of a transfer, + * @note This callback is used with MXC_DMA_DoTransfer() + * to allow the user to chain an unlimited number of + * DMA Transfers. + * + * @param trans Struct of the completed transfer + * + * @return Returns the next transfer to be completed, or NULL + * if no more transfers will be done + */ +typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t) (mxc_dma_srcdst_t dest); + +/* **** Function Prototypes **** */ +/*************************/ +/* Low Level Functions */ +/*************************/ +/** + * @brief Initialize DMA resources + * @details This initialization is required before using the DMA driver functions. + * @return #E_NO_ERROR if successful + */ +int MXC_DMA_Init (void); + +/** + * @brief Request DMA channel + * @details Returns a handle to the first free DMA channel, which can be used via API calls + * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. + * @return Non-negative channel handle (inclusive of zero). + * @return #E_NONE_AVAIL All channels in use. + * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. + * @return #E_BUSY DMA is currently busy (locked), try again later. + */ +int MXC_DMA_AcquireChannel (void); + +/** + * @brief Release DMA channel + * @details Stops any DMA operation on the channel and returns it to the pool of free channels. + * + * @param ch channel handle to release + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ReleaseChannel (int ch); + +/** + * @brief Configure the DMA channel + * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() + * + * @param config Struct containing DMA configuration parameters + * @param srcdst Struct containing pointers and length of DMA operation + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ConfigChannel (mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); + +/** + * @brief Configure the DMA channel with more advanced parameters + * + * @param advConfig Struct containing advanced DMA parameters + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_AdvConfigChannel (mxc_dma_adv_config_t advConfig); + +/** + * @brief Set channel source, destination, and count for the transfer + * @param srcdst Struct containing the channel, source, destination, and count for the channel + * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetSrcDst (mxc_dma_srcdst_t srcdst); + +/** + * @brief Get channel source, destination, and count for transfer + * + * @param srcdst Pointer to struct with the correct channel number + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_DMA_GetSrcDst (mxc_dma_srcdst_t *srcdst); + +/** + * @brief Set channel reload source, destination, and count for the transfer + * @param srcdstReload Struct containing the channel, source, destination, and count for the channel + * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetSrcReload (mxc_dma_srcdst_t srcdstReload); + +/** + * @brief Get channel reload source, destination, and count for transfer + * + * @param srcdstReload Pointer to struct with the correct channel number + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_DMA_GetSrcReload (mxc_dma_srcdst_t *srcdstReload); + +/** + * @brief Set channel interrupt callback + * @param ch channel handle + * @param callback Pointer to a function to call when the channel + * interrupt flag is set and interrupts are enabled or + * when DMA is shutdown by the driver. + * @details Configures the channel interrupt callback. The @p callback + * function is called for two conditions: + * -# When the channel's interrupt flag is set and DMA interrupts + * are enabled. + * -# If the driver calls the MXC_DMA_Shutdown() function. The + * callback function prototype is: + * @code + * void callback_fn(int ch, int reason); + * @endcode + * @p ch indicates the channel that generated the callback, @p + * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN + * if the DMA is being shutdown. + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR + * otherwise + */ +int MXC_DMA_SetCallback (int ch, void (*callback) (int, int)); + +/** + * @brief Set channel interrupt + * @note Each channel has two interrupts (complete, and count to zero). + * To enable complete, pass true for chdis. To enable count to zero, + * pass true for ctz. + * @param ch Channel Handle + * @param chdis Enable channel complete interrupt + * @param ctz Enable channel count to zero interrupt. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetChannelInterruptEn (int ch, bool chdis, bool ctz); + +/** + * @brief Enable channel interrupt + * @note Each channel has two interrupts (complete, and count to zero) + which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param ch channel handle + * @param flags The flags to enable + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ChannelEnableInt (int ch, int flags); + +/** + * @brief Disable channel interrupt + * @param ch channel handle + * @param flags The flags to disable + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ChannelDisableInt (int ch, int flags); + +/** + * @brief Read channel interrupt flags + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise + */ +int MXC_DMA_ChannelGetFlags (int ch); + +/** + * @brief Clear channel interrupt flags + * @param ch channel handle + * @param flags The flags to clear + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ChannelClearFlags (int ch, int flags); + +/** + * @brief Enable channel interrupt + * @note Each channel has two interrupts (complete, and count to zero) + which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_EnableInt (int ch); + +/** + * @brief Disable channel interrupt + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_DisableInt (int ch); + +/** + * @brief Start transfer + * @param ch channel handle + * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_Start (int ch); + +/** + * @brief Stop DMA transfer, irrespective of status (complete or in-progress) + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_Stop (int ch); + +/** + * @brief Get a pointer to the DMA channel registers + * @param ch channel handle + * @details If direct access to DMA channel registers is required, this + * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). + * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise + */ +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs (int ch); + +/** + * @brief Interrupt handler function + * @details Call this function as the ISR for each DMA channel under driver control. + * Interrupt flags for channel ch will be automatically cleared before return. + */ +void MXC_DMA_Handler(); + +/*************************/ +/* High Level Functions */ +/*************************/ + +/** + * @brief Performs a memcpy, using DMA, optionally asynchronous + * @note The user must have the DMA interrupt enabled and call + * MXC_DMA_Handler() from the ISR. + * + * @param dest pointer to destination memory + * @param src pointer to source memory + * @param len number of bytes to copy + * @param callback function to call when transfer is complete + * + * @return see \ref MXC_Error_Codes + */ +int MXC_DMA_MemCpy (void* dest, void* src, int len, mxc_dma_complete_cb_t callback); + +/** + * @brief Performs a memcpy, using DMA, optionally asynchronous + * @note The user must have the DMA interrupt enabled and call + * MXC_DMA_Handler() from the ISR. + * + * @param config The channel config struct + * @param firstSrcDst The source, destination, and count for the first transfer + * @param callback function is called when transfer is complete + * + * @return see \ref MXC_Error_Codes + */ +int MXC_DMA_DoTransfer (mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); +/** + * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver + */ + +/**@} end of group dma */ +#ifdef __cplusplus +} +#endif + +#endif /* _DMA_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h new file mode 100644 index 00000000000..adafe86b0a4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/flc.h @@ -0,0 +1,189 @@ +/** + * @file flc.h + * @brief Flash Controller driver. + * @details This driver can be used to operate on the embedded flash memory. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#ifndef _FLC_H_ +#define _FLC_H_ + +/* **** Includes **** */ +#include "flc_regs.h" +#include "mxc_sys.h" +#include "mxc_errors.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup flc Flash Controller (FLC) + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/// Bit mask that can be used to find the starting address of a page in flash +#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) + +/// Calculate the address of a page in flash from the page number +#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) + +/***** Function Prototypes *****/ + +/** + * @brief Initializes the Flash Controller for erase/write operations + * @return #E_NO_ERROR if successful. + */ +int MXC_FLC_Init(); + +/** + * @brief Checks if Flash Controller is busy. + * @details Reading or executing from flash is not possible if flash is busy + * with an erase or write operation. + * @return If non-zero, flash operation is in progress + */ +int MXC_FLC_Busy (void); + +/** + * @brief Erases the entire flash array. + * @note This function must be executed from RAM. + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_MassErase (void); + +/** + * @brief Erases the page of flash at the specified address. + * @note This function must be executed from RAM. + * @param address Any address within the page to erase. + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_PageErase (uint32_t address); + +/** + * @brief Read Data out of Flash from an address + * + * @param[in] address The address to read from + * @param buffer The buffer to read the data into + * @param[in] len The length of the buffer + * + */ +void MXC_FLC_Read (int address, void* buffer, int len); + +/** + * @brief Writes data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param length Number of bytes to be written. + * @param buffer Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write (uint32_t address, uint32_t length, uint32_t *buffer); + +/** + * @brief Writes 32 bits of data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param data Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write32 (uint32_t address, uint32_t data); + +/** + * @brief Writes 128 bits of data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param data Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write128 (uint32_t address, uint32_t *data); + +/** + * @brief Enable flash interrupts + * @param flags Interrupts to enable + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_EnableInt (uint32_t flags); + +/** + * @brief Disable flash interrupts + * @param flags Interrupts to disable + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_DisableInt (uint32_t flags); + +/** + * @brief Retrieve flash interrupt flags + * @return Interrupt flags registers + */ +int MXC_FLC_GetFlags (void); + +/** + * @brief Clear flash interrupt flags + * @note Provide the bit position to clear, even if the flag is write-0-to-clear + * @param flags Flag bit(s) to clear + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_ClearFlags (uint32_t flags); + +/** + * @brief Unlock info block + * + * @param[in] address The address in the info block needing written to + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_UnlockInfoBlock (uint32_t address); + +/** + * @brief Lock info block + * + * @param[in] address The address in the info block that was written to + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_LockInfoBlock (uint32_t address); + +/**@} end of group flc */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h new file mode 100644 index 00000000000..28b81a266e2 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/gpio.h @@ -0,0 +1,310 @@ +/** + * @file gpio.h + * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +/* **** Includes **** */ +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup gpio General-Purpose Input/Output (GPIO) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ +/** + * @defgroup gpio_port_pin Port and Pin Definitions + * @ingroup gpio + * @{ + * @defgroup gpio_port Port Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) ///< Port 0 Define +/**@} end of gpio_port group*/ +/** + * @defgroup gpio_pin Pin Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) ///< Pin 0 Define +#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) ///< Pin 1 Define +#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) ///< Pin 2 Define +#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) ///< Pin 3 Define +#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) ///< Pin 4 Define +#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) ///< Pin 5 Define +#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) ///< Pin 6 Define +#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) ///< Pin 7 Define +#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) ///< Pin 8 Define +#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) ///< Pin 9 Define +#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) ///< Pin 10 Define +#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) ///< Pin 11 Define +#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) ///< Pin 12 Define +#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) ///< Pin 13 Define +/**@} end of gpio_pin group */ +/**@} end of gpio_port_pin group */ + +/** + * @brief Type alias for a GPIO callback function with prototype: + * @code + void callback_fn(void *cbdata); + * @endcode + * @param cbdata A void pointer to the data type as registered when + * MXC_GPIO_RegisterCallback() was called. + */ +typedef void (*mxc_gpio_callback_fn) (void *cbdata); + +/** + * @brief Enumeration type for the GPIO Function Type + */ +typedef enum { + MXC_GPIO_FUNC_IN, ///< GPIO Input + MXC_GPIO_FUNC_OUT, ///< GPIO Output + MXC_GPIO_FUNC_ALT1, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT2, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT3, ///< Alternate Function Selection + MXC_GPIO_FUNC_ALT4, ///< Alternate Function Selection +} mxc_gpio_func_t; + +/** + * @brief Enumeration type for the voltage level on a given pin. + */ +typedef enum { + MXC_GPIO_VSSEL_VDDIO, ///< Set pin to VIDDIO voltage + MXC_GPIO_VSSEL_VDDIOH, ///< Set pin to VIDDIOH voltage +} mxc_gpio_vssel_t; + +/** + * @brief Enumeration type for the type of GPIO pad on a given pin. + */ +typedef enum { + MXC_GPIO_PAD_NONE, ///< No pull-up or pull-down + MXC_GPIO_PAD_PULL_UP, ///< Set pad to weak pull-up + MXC_GPIO_PAD_PULL_DOWN, ///< Set pad to weak pull-down +} mxc_gpio_pad_t; + +/** + * @brief Structure type for configuring a GPIO port. + */ +typedef struct { + mxc_gpio_regs_t* port; ///< Pointer to GPIO regs + uint32_t mask; ///< Pin mask (multiple pins may be set) + mxc_gpio_func_t func; ///< Function type + mxc_gpio_pad_t pad; ///< Pad type + mxc_gpio_vssel_t vssel; ///< Voltage select +} mxc_gpio_cfg_t; + +/** + * @brief Enumeration type for the interrupt modes. + */ +typedef enum { + MXC_GPIO_INT_LEVEL, ///< Interrupt is level sensitive + MXC_GPIO_INT_EDGE ///< Interrupt is edge sensitive +} mxc_gpio_int_mode_t; + +/** + * @brief Enumeration type for the interrupt polarity. + */ +typedef enum { + MXC_GPIO_INT_FALLING, ///< Interrupt triggers on falling edge + MXC_GPIO_INT_HIGH, ///< Interrupt triggers when level is high + MXC_GPIO_INT_RISING, ///< Interrupt triggers on rising edge + MXC_GPIO_INT_LOW, ///< Interrupt triggers when level is low + MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge +} mxc_gpio_int_pol_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_GPIO_Init (uint32_t portMask); + +/** + * @brief Shutdown GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_GPIO_Shutdown (uint32_t portMask); + +/** + * @brief Reset GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_GPIO_Reset (uint32_t portMask); + +/** + * @brief Configure GPIO pin(s). + * @param cfg Pointer to configuration structure describing the pin. + * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_GPIO_Config (const mxc_gpio_cfg_t *cfg); + +/** + * @brief Gets the pin(s) input state. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to read + * @return The requested pin state. + */ +uint32_t MXC_GPIO_InGet (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Sets the pin(s) to a high level output. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to set + */ +void MXC_GPIO_OutSet (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Clears the pin(s) to a low level output. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to clear + */ +void MXC_GPIO_OutClr (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Gets the pin(s) output state. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to read the output state of + * @return The state of the requested pin. + * + */ +uint32_t MXC_GPIO_OutGet (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Write the pin(s) to a desired output level. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to set output level of + * @param val Desired output level of the pin(s). This will be masked + * with the configuration mask. + */ +void MXC_GPIO_OutPut (mxc_gpio_regs_t* port, uint32_t mask, uint32_t val); + +/** + * @brief Toggles the the pin(s) output level. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to toggle + */ +void MXC_GPIO_OutToggle (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Configure GPIO interrupt(s) + * @param cfg Pointer to configuration structure describing the pin. + * @param pol Requested interrupt polarity. + * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_GPIO_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); + +/** + * @brief Enables the specified GPIO interrupt + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to enable interrupts for + * + */ +void MXC_GPIO_EnableInt (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Disables the specified GPIO interrupt. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to disable interrupts for + */ +void MXC_GPIO_DisableInt (mxc_gpio_regs_t* port, uint32_t mask); + +/** + * @brief Gets the interrupt(s) status on a GPIO port + * + * @param port Pointer to the port requested + * + * @return The requested interrupt status. + */ +uint32_t MXC_GPIO_GetFlags (mxc_gpio_regs_t* port); + +/** + * @brief Gets the interrupt(s) status on a GPIO port + * + * @param port Pointer to the port requested + * @param flags The flags to clear + */ +void MXC_GPIO_ClearFlags (mxc_gpio_regs_t* port, uint32_t flags); + +/** + * @brief Registers a callback for the interrupt on a given port and pin. + * @param cfg Pointer to configuration structure describing the pin + * @param callback A pointer to a function of type #callback_fn. + * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs. + * + */ +void MXC_GPIO_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); + +/** + * @brief GPIO IRQ Handler. @note If a callback is registered for a given + * interrupt, the callback function will be called. + * + * @param port Number of the port that generated the interrupt service routine. + * + */ +void MXC_GPIO_Handler (unsigned int port); + +/** + * @brief Set Voltage select for pins to VDDIO or VDDIOH + * + * @param port The GPIO port + * @param[in] vssel VDDIO or VDDIOH to set the voltatge to + * @param[in] mask Pins in the GPIO port that will be set to the voltage. + * + * @return #E_NO_ERROR if everything is successful. See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_GPIO_SetVSSEL (mxc_gpio_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h new file mode 100644 index 00000000000..9ad334617bf --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/i2s.h @@ -0,0 +1,191 @@ +/** + * @file i2s.h + * @brief I2S (Inter-Integrated Sound) driver function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#ifndef _I2S_H_ +#define _I2S_H_ + +/* **** Includes **** */ +#include "mxc_sys.h" +#include "dma.h" +#include "spimss_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup i2s Inter-Integrated Sound (I2S) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +typedef enum { + I2S_MAP_A = 0, + I2S_MAP_B = 1, +} mxc_i2s_sys_map_t; + +typedef enum { + LEFT_JUSTIFIED= 0, + RIGHT_JUSTIFIED = 1, +} mxc_i2s_justify_t; + +typedef enum { + STEREO_MODE = 0, + MONO_MODE = 1, +} mxc_i2s_audio_mode_t; + +/** @brief I2S audio directions */ +typedef enum { + AUDIO_OUT = 1, + AUDIO_IN = 2, +} mxc_i2s_direction_t; + + +/** @brief I2S Configuration Struct */ +typedef struct { + mxc_i2s_sys_map_t map; + mxc_i2s_justify_t justify; + mxc_i2s_audio_mode_t audio_mode; + mxc_i2s_direction_t audio_direction; + uint16_t sample_rate; + unsigned int start_immediately; + unsigned int dma_reload_en; + void *src_addr; + void *dst_addr; + uint32_t length; +} mxc_i2s_config_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize I2S resources + * + * @param config see \ref mxc_i2s_config_t I2S Config Struct + * @param dma_ctz_cb Function pointer to Count-to-Zero callback function. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int)); + +/** + * @brief Release I2S + * @details De-configures the I2S protocol and stops DMA request + * @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise + */ +int MXC_I2S_Shutdown(void); + +/** + * @brief Mute I2S Output + * @details Sets I2S data to zero, continues sending clock and accessing DMA + * @return \c #E_NO_ERROR + */ +int MXC_I2S_Mute(void); + +/** + * @brief Unmute I2S Output + * @details Restores I2S data + * @return \c #E_NO_ERROR + */ +int MXC_I2S_Unmute(void); + +/** + * @brief Pause I2S Output + * @details Similar to mute, but stops FIFO and DMA access, clocks continue + * @return \c #E_NO_ERROR + */ +int MXC_I2S_Pause(void); + +/** + * @brief Unpause I2S Output + * @details Similar to mute, but restarts FIFO and DMA access + * @return \c #E_NO_ERROR + */ +int MXC_I2S_Unpause(void); + +/** + * @brief Stops I2S Output + * @details Similar to pause, but also halts clock + * @return \c #E_NO_ERROR + */ +int MXC_I2S_Stop(void); + +/** + * @brief Starts I2S Output + * @details Starts I2S Output, automatically called by configure if requested + * @return \c #E_NO_ERROR + */ +int MXC_I2S_Start(void); + +/** + * @brief Clears DMA Interrupt Flags + * @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb + * @return \c #E_NO_ERROR + */ +int MXC_I2S_DMA_ClearFlags(void); + +/** + * @brief Set DMA Addr (Source or Dest) and bytes to transfer + * @param src_addr The address to read data from (Audio Out) + * @param dst_addr The address to write data to (Audio In) + * @param count The length of the transfer in bytes + * @details Sets the address to read/write data in memory and the length of + * the transfer. The unused addr parameter is ignored. + * @return \c #E_NO_ERROR + */ +int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count); + +/** + * @brief Sets the DMA reload address and count + * @param src_addr The address to read data from (Audio Out) + * @param dst_addr The address to write data to (Audio In) + * @param count The length of the transfer in bytes + * @details If DMA reload is enabled, when the DMA has transfered $count bytes + * (a CTZ event occurs) the src, dst, and count registers will be + * set to these. The DMA reload flag clears after a reload occurs. + * @return \c #E_NO_ERROR + */ +int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count); +/**@} end of group i2s */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _I2S_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h new file mode 100644 index 00000000000..fb7a6bc0710 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/icc.h @@ -0,0 +1,94 @@ +/** + * @file icc.h + * @brief Instruction Controller Cache(ICC) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _ICC_H_ +#define _ICC_H_ + +/* **** Includes **** */ +#include +#include "icc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup icc ICC + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for the Cache ID Register + */ +typedef enum { + ICC_INFO_RELNUM, ///< Identifies the RTL release version + ICC_INFO_PARTNUM, ///< Specifies the value of C_ID Port Number + ICC_INFO_ID ///< Specifies the value of Cache ID +} mxc_icc_info_t; + +/** + * @brief Reads the data from the Cache Id Register. + * @param cid Enumeration type for Cache Id Register. + * @retval Returns the contents of Cache Id Register. + */ +int MXC_ICC_ID (mxc_icc_info_t cid); + +/** + * @brief Enable the instruction cache controller. + */ +void MXC_ICC_Enable (void); + +/** + * @brief Disable the instruction cache controller. + */ +void MXC_ICC_Disable (void); + +/** + * @brief Flush the instruction cache controller. + */ +void MXC_ICC_Flush (void); + +/**@} end of group icc */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h new file mode 100644 index 00000000000..ead39aea0a8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h @@ -0,0 +1,346 @@ +/** + * @file lp.h + * @brief Low power function prototypes and data types. + */ + + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $ + * $Revision: 38105 $ + * + *************************************************************************** */ + +// Define to prevent redundant inclusion +#ifndef _LP_H_ +#define _LP_H_ + +/***** Includes *****/ +#include "pwrseq_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup pwrseq Low Power (LP) + * @ingroup periphlibs + * @{ + */ + +/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */ +typedef enum { + MXC_LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */ + MXC_LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */ + MXC_LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */ +} mxc_lp_ovr_t; + +/** + * @brief Clears the low power wakeup flags + */ +void MXC_LP_ClearWakeStatus(void); + +/** + * @brief Enables power to RAM addresses 0x20010000-0x20017FFF. + */ +void MXC_LP_EnableSRAM3(void); + +/** + * @brief Enables power to RAM addresses 0x20008000-0x2000FFFF. + */ +void MXC_LP_EnableSRAM2(void); + +/** + * @brief Enables power to RAM addresses 0x20004000-0x20007FFF. + */ +void MXC_LP_EnableSRAM1(void); + +/** + * @brief Enables power to RAM addresses 0x20000000-0x20003FFF. + */ +void MXC_LP_EnableSRAM0(void); + +/** + * @brief Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed. + */ +void MXC_LP_DisableSRAM3(void); + +/** + * @brief Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed. + */ +void MXC_LP_DisableSRAM2(void); + +/** + * @brief Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed. + */ +void MXC_LP_DisableSRAM1(void); + +/** + * @brief Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed. + */ +void MXC_LP_DisableSRAM0(void); + +/** + * @brief Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void MXC_LP_EnableICacheLightSleep(void); + +/** + * @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void MXC_LP_EnableSysRAM3LightSleep(void); + +/** + * @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void MXC_LP_EnableSysRAM2LightSleep(void); + +/** + * @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void MXC_LP_EnableSysRAM1LightSleep(void); + +/** + * @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void MXC_LP_EnableSysRAM0LightSleep(void); + +/** + * @brief Places the instruction cache in active mode. + */ +void MXC_LP_DisableICacheLightSleep(void); + +/** + * @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode. + */ +void MXC_LP_DisableSysRAM3LightSleep(void); + +/** + * @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode. + */ +void MXC_LP_DisableSysRAM2LightSleep(void); + +/** + * @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode. + */ +void MXC_LP_DisableSysRAM1LightSleep(void); + +/** + * @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode. + */ +void MXC_LP_DisableSysRAM0LightSleep(void); + +/** + * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. + * Call this function multiple times to enable pins on multiple ports. This function does not configure + * the GPIO pins nor does it setup their interrupt functionality. + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. + */ +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask); + +/** + * @brief Disables the selected GPIO port and its selected pins as a wake up source. + * Call this function multiple times to disable pins on multiple ports. + * @param port The port to configure as wakeup sources. + * @param mask The pins to configure as wakeup sources. + */ +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask); + +/** + * @brief Enables the RTC alarm to wake up the device from any low power mode. + */ +void MXC_LP_EnableRTCAlarmWakeup(void); + +/** + * @brief Disables the RTC alarm from waking up the device. + */ +void MXC_LP_DisableRTCAlarmWakeup(void); + +/** + * @brief Places the device into SLEEP mode. This function returns once any interrupt occurs. + * @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again + */ +void MXC_LP_EnterSleepMode(void); + +/** + * @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur. + * @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again +*/ +void MXC_LP_EnterDeepSleepMode(void); + +/** + * @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC or external interrupt occur. + * @note MXC_LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again + */ +void MXC_LP_EnterBackupMode(void); + +/** + * @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. + */ +void MXC_LP_EnterShutDownMode(void); + +/** + * @brief Set operating voltage and change the clock to match the new voltage. + * @param system reset configuration struct + */ +int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr); + +/** + * @brief Enables Data Retention to RAM addresses 0x20000000-0x20003FFF. + */ +void MXC_LP_EnableSRamRet0(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20000000-0x20003FFF. + */ +void MXC_LP_DisableSRamRet0(void); + +/** + * @brief Enables Data Retention to RAM addresses 0x20004000-0x20007FFF. + */ +void MXC_LP_EnableSRamRet1(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20004000-0x20007FFF. + */ +void MXC_LP_DisableSRamRet1(void); + +/** + * @brief Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF. + */ +void MXC_LP_EnableSRamRet2(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF. + */ +void MXC_LP_DisableSRamRet2(void); + +/** + * @brief Enables Data Retention to RAM addresses 0x20010000-0x20017FFF. + */ +void MXC_LP_EnableSRamRet3(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20010000-0x20017FFF. + */ +void MXC_LP_DisableSRamRet3(void); + +/** + * @brief Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time. + */ +void MXC_LP_EnableBlockDetect(void); + +/** + * @brief Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time + */ +void MXC_LP_DisableBlockDetect(void); + +/** + * @brief RAM Retention Regulator Enable for BACKUP Mode + */ +void MXC_LP_EnableRamRetReg(void); + +/** + * @brief RAM Retention Regulator Disabels for BACKUP Mode + */ +void MXC_LP_DisableRamRetReg(void); + +/** + * @brief Enables Fast wake up from deepsleep + */ +void MXC_LP_EnableFastWk(void); + +/** + * @brief Disables Fast wake up from deepsleep + */ +void MXC_LP_DisableFastWk(void); + +/** + * @brief Turns on band gap during deepsleep and backup mode. + */ +void MXC_LP_EnableBandGap(void); + +/** + * @brief Turns off band gap during deepsleep and backup mode. + */ +void MXC_LP_DisableBandGap(void); + +/** + * @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void MXC_LP_EnableVCorePORSignal(void); + +/** + * @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void MXC_LP_DisableVCorePORSignal(void); + +/** + * @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void MXC_LP_EnableLDO(void); + +/** + * @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void MXC_LP_DisableLDO(void); + +/** + * @brief Enables V CORE Supply Voltage Monitor + */ +void MXC_LP_EnableVCoreSVM(void); + +/** + * @brief Disables V CORE Supply Voltage Monitor + */ +void MXC_LP_DisableVCoreSVM(void); + + +/** + * @brief Enables VDDIO Power-On-Reset Monitor + */ +void MXC_LP_EnableVDDIOPorMonitor(void); + +/** + * @brief Disables VDDIO Power-On-Reset Monitor + */ +void MXC_LP_DisableVDDIOPorMonitor(void); +/**@} end of group pwrseq */ + +#ifdef __cplusplus +} +#endif + +#endif /* _LP_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h new file mode 100644 index 00000000000..cc919767d6c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/msr.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +* +******************************************************************************** +*/ + +/** +* \file +* \brief Magnetic Stripe Reader driver +* \details This driver can be used to configure and operate the Magnetic Stripe +* Reader. It reads and decodes magnetic stripe data that is encoded +* according to the ISO/IEC standard 7811. +* \details This file defines the driver API including data types and function +* prototypes. +*/ + +#ifndef _MSR_H_ +#define _MSR_H_ + +/***** Definitions *****/ + +/// Number of tracks on a card +#ifndef MSR_NUM_TRACKS +#define MSR_NUM_TRACKS 3 +#endif + +#define MSR_MAX_SAMPLES 1536 + +// Assuming nominal bit density of 210 bpi and 3.375 inch length +#define MSR_MAX_RAW_LEN_BITS (709) +#define MSR_MAX_RAW_LEN_BYTES ((MSR_MAX_RAW_LEN_BITS + 7) / 8) +#define MSR_MAX_RAW_LEN_HALFWORDS ((MSR_MAX_RAW_LEN_BITS + 15) / 16) + +/// Maximum size in bytes of decoded track characters (5-bit min to 8-bit max) +#define MSR_MAX_DEC_LEN (MSR_MAX_RAW_LEN_BITS / 5) + +/// Swipe direction: the card was swiped in the forward direction +#define MSR_FORWARD 0 +/// Swipe direction: the card was swiped in the reverse direction +#define MSR_REVERSE 1 + +/// Error codes +#define MSR_ERR_OK 0x00 +#define MSR_ERR_BAD_LEN 0x01 +#define MSR_ERR_START_SEN 0x02 +#define MSR_ERR_END_SEN 0x04 +#define MSR_ERR_OUTLIER 0x08 +#define MSR_ERR_PARAM 0x10 +#define MSR_ERR_LRC 0x40 +#define MSR_ERR_PARITY 0x80 + +/// Structure to contain result of a track decode +typedef struct { + uint8_t error_code; /**< Error code value */ + uint8_t parity_errs; /**< Number of characters with parity errors */ + uint8_t lrc; /**< LRC check value. A value of '0' indicates a + successful LRC check. Any other value should be + considered a failure. */ + uint8_t direction; /**< Swipe direction determined from decode */ + uint8_t len; /**< Number or decoded characters. This does not include + the sentinels or the LRC. */ + uint16_t speed; + uint8_t data[MSR_MAX_DEC_LEN]; /**< The decoded data */ +} msr_decoded_track_t; + +/// MSR sample fields +typedef union { + struct { + uint16_t time : 9; + uint16_t amp : 7; + }; + uint16_t value; +} msr_sample_t; + +/// Structure to contain raw MSR samples +typedef struct { + uint16_t len; + msr_sample_t data[MSR_MAX_SAMPLES]; +} msr_samples_t; + +/***** Function Prototypes *****/ + +/** +* \brief Initializes magnetic card reader hardware +* \returns #E_NO_ERROR if everything is successful +*/ +int msr_init (void); + +/** +* \brief Initializes specified track +* \param track track number (1 to 3) +*/ +void msr_init_track (unsigned int track); + +/** +* \brief Enables magnetic card reader +* \pre The reader should be initialized by calling msr_init() and then +* waiting at least 100 us before calling this function. +*/ +void msr_enable (void); + +/** +* \brief Disables magnetic card reader +*/ +void msr_disable (void); + +/** +* \brief Task used to execute driver functionality. +* \details This function executes the internal driver functionality that +* processes MSR events and reads stripe data. This function is used +* when MSR interrupt servicing is disabled. +* \returns 1 if all tracking reading is complete, 0 otherwise +*/ +int msr_task (void); + +/** +* \brief Decodes the specified track of data +* \param track track number (1 to 3) +* \param decoded_track track decode results +* \returns number of characters decoded +* \note This function has significant stack usage. +*/ +unsigned int msr_track_decode (unsigned int track, msr_decoded_track_t * decoded_track); + +/** +* \brief Registers an application callback function +* \details The callback function will be called after completion of the read +* of all enabled card tracks +* \details Unregistering of the callback can be performed by calling this +* function function with a NULL parameter. +* \param func application callback function +*/ +void msr_set_complete_callback (void (*func) (void)); + +/** +* \brief Retrieves the raw (undecoded) sample data for the specified track +* of data +* \param track track number (1 to 3) +* \param samples pointer to where the sample data will be copied +* \returns number of samples retrieved +*/ +unsigned int mcr_get_track_samples (unsigned int track, msr_samples_t * samples); + +#endif /* _MSR_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h new file mode 100644 index 00000000000..b77a9b87647 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_assert.h @@ -0,0 +1,109 @@ +/** + * @file mxc_assert.h + * @brief Assertion checks for debugging. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ASSERT_H_ +#define _MXC_ASSERT_H_ + +/* **** Includes **** */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_assertions Assertion Checks for Debugging + * @brief Assertion checks for debugging. + * @{ + */ +/* **** Definitions **** */ +/** + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +///@cond +#ifdef MXC_ASSERT_ENABLE +/** + * Macro that checks the expression for true and generates an assertion. + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT(expr) \ +if (!(expr)) \ +{ \ + mxc_assert(#expr, __FILE__, __LINE__); \ +} +/** + * Macro that generates an assertion with the message "FAIL". + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__); +#else +#define MXC_ASSERT(expr) +#define MXC_ASSERT_FAIL() +#endif +///@endcond +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Assert an error when the given expression fails during debugging. + * @param expr String with the expression that failed the assertion. + * @param file File containing the failed assertion. + * @param line Line number for the failed assertion. + * @note This is defined as a weak function and can be overridden at the + * application layer to print the debugging information. + * @code + * printf("%s, file: %s, line %d\n", expr, file, line); + * @endcode + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +void mxc_assert (const char *expr, const char *file, int line); + +/**@} end of group MXC_Assertions*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_ASSERT_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h new file mode 100644 index 00000000000..d2db0f1a068 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_delay.h @@ -0,0 +1,130 @@ +/** + * @file mxc_delay.h + * @brief Asynchronous delay routines based on the SysTick Timer. +*/ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _DELAY_H_ +#define _DELAY_H_ + +/** + * @ingroup devicelibs + * @defgroup MXC_delay Delay Utility Functions + * @brief Asynchronous delay routines based on the SysTick Timer + * @{ + */ + +/***** Definitions *****/ +/** + * Macro used to specify a microsecond timing parameter in seconds. + * \code + * x = SEC(3) // 3 seconds -> x = 3,000,000 + * \endcode + */ +#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL) +/** + * Macro used to specify a microsecond timing parameter in milliseconds. + * \code + * x = MSEC(3) // 3ms -> x = 3,000 + * \endcode + */ +#define MXC_DELAY_MSEC(ms) (ms * 1000UL) +/** + * Macro used to specify a microsecond timing parameter. + * \code + * x = USEC(3) // 3us -> x = 3 + * \endcode + */ +#define MXC_DELAY_USEC(us) (us) + +/** + * @brief The callback routine used by MXC_DelayAsync() when the delay is complete + * or aborted early. + * + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_delay_complete_t) (int result); + +/***** Function Prototypes *****/ + +/** + * @brief Blocks and delays for the specified number of microseconds. + * @details Uses the SysTick to create the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @param us microseconds to delay + * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_Delay (unsigned long us); + +/** + * @brief Starts a non-blocking delay for the specified number of + * microseconds. + * @details Uses the SysTick to time the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @note MXC_Delay_handler() must be called from the SysTick interrupt service + * routine or at a rate greater than the SysTick overflow rate. + * @param us microseconds to delay + * @param callback Function pointer to the function called once the delay expires. + * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another + * delay request. + */ +int MXC_DelayAsync (unsigned long us, mxc_delay_complete_t callback); + +/** + * @brief Returns the status of a non-blocking delay request + * @pre Start the asynchronous delay by calling MXC_Delay_start(). + * @return #E_BUSY until the requested delay time has expired. + */ +int MXC_DelayCheck (void); + +/** + * @brief Stops an asynchronous delay previously started. + * @pre Start the asynchronous delay by calling MXC_Delay_start(). + */ +void MXC_DelayAbort (void); + +/** + * @brief Processes the delay interrupt. + * @details This function must be called from the SysTick IRQ or polled at a + * rate greater than the SysTick overflow rate. + */ +void MXC_DelayHandler (void); + +/**@} end of group MXC_delay */ + +#endif /* _DELAY_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h new file mode 100644 index 00000000000..d0be9b60789 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + ******************************************************************************/ + +/** + * @file mxc_device.h + * @brief contains device and revision specific definitions + */ + +#ifndef _MXC_DEVICE_H_ +#define _MXC_DEVICE_H_ + +#include "max32660.h" +#include "mxc_errors.h" + + +#ifndef TARGET + #error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#if MBED_VERSION && MBED_VERSION < 51200 +#define TARGET_NAME STRING_NAME(TARGET) +#endif + +// Define which revisions of the IP we are using +#ifndef TARGET_REV + #error TARGET_REV NOT DEFINED +#endif + +#if(TARGET_REV == 0x4131) + // A1 + #define MXC_PBM_REV 0 + #define MXC_TMR_REV 0 + #define MXC_UART_REV 1 +#else + +#error TARGET_REV NOT SUPPORTED + +#endif // if(TARGET_REV == ...) + +#endif /* _MXC_DEVICE_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h new file mode 100644 index 00000000000..f2afb9a7e90 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_errors.h @@ -0,0 +1,92 @@ +/** + * @file mxc_errors.h + * @brief List of common error return codes for Maxim Integrated libraries. +*/ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ERRORS_H_ +#define _MXC_ERRORS_H_ + +/** + * @ingroup syscfg + * @defgroup MXC_Error_Codes Error Codes + * @brief A list of common error codes used by the API. + * @note A Negative Error Convention is used to avoid conflict with + * positive, Non-Error, returns. + * @{ + */ + +/** No Error */ +#define E_NO_ERROR 0 +/** No Error, success */ +#define E_SUCCESS 0 +/** Pointer is NULL */ +#define E_NULL_PTR -1 +/** No such device */ +#define E_NO_DEVICE -2 +/** Parameter not acceptable */ +#define E_BAD_PARAM -3 +/** Value not valid or allowed */ +#define E_INVALID -4 +/** Module not initialized */ +#define E_UNINITIALIZED -5 +/** Busy now, try again later */ +#define E_BUSY -6 +/** Operation not allowed in current state */ +#define E_BAD_STATE -7 +/** Generic error */ +#define E_UNKNOWN -8 +/** General communications error */ +#define E_COMM_ERR -9 +/** Operation timed out */ +#define E_TIME_OUT -10 +/** Expected response did not occur */ +#define E_NO_RESPONSE -11 +/** Operations resulted in unexpected overflow */ +#define E_OVERFLOW -12 +/** Operations resulted in unexpected underflow */ +#define E_UNDERFLOW -13 +/** Data or resource not available at this time */ +#define E_NONE_AVAIL -14 +/** Event was shutdown */ +#define E_SHUTDOWN -15 +/** Event was aborted */ +#define E_ABORT -16 +/** The requested operation is not supported */ +#define E_NOT_SUPPORTED -17 +/**@} end of MXC_Error_Codes group */ + +#endif /* _MXC_ERRORS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h new file mode 100644 index 00000000000..76bbd083032 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_i2c.h @@ -0,0 +1,869 @@ +/** +* @file i2c.h +* @brief Inter-integrated circuit (I2C) communications interface driver. +*/ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_I2C_H_ +#define _MXC_I2C_H_ + +#include +#include "mxc_sys.h" +#include "i2c_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup i2c I2C + * @ingroup periphlibs + * @{ + */ + +typedef struct _i2c_req_t mxc_i2c_req_t; + +/** + * @brief The callback used by the MXC_I2C_ReadByteInteractive() function. + * + * The callback routine used by the MXC_I2C_ReadByteInteractive() function. This + * function allows the application to determine whether the byte received + * should be acknowledged or not. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte The byte received. + * + * @return 0 if the byte should not be acknowledged (NACK), non-zero to + * acknowledge the byte. + */ +typedef int (*mxc_i2c_getAck_t) (mxc_i2c_regs_t* i2c, unsigned char byte); + +/** + * @brief The callback routine used by the MXC_I2C_MasterTransactionAsync() + * function to indicate the transaction has completed. + * + * @param req The details of the transaction. + * @param result 0 if all bytes are acknowledged, 1 if any byte + * transmitted is not acknowledged, negative if error. + * See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_i2c_complete_cb_t) (mxc_i2c_req_t* req, int result); + +/** + * @brief The callback routine used by the I2C Read/Write FIFO DMA + * functions to indicate the transaction has completed. + * + * @param len The length of data actually read/written + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_i2c_dma_complete_cb_t) (int len, int result); + +/** + * @brief The information required to perform a complete I2C transaction as + * the bus master. + * + * The information required to perform a complete I2C transaction as the bus + * master. This structure is used by the MXC_I2C_MasterTransaction() and + * MXC_I2C_MasterTransactionAsync() functions. + */ +struct _i2c_req_t { + mxc_i2c_regs_t* i2c; ///< Pointer to I2C registers (selects the + ///< I2C block used.) + unsigned int addr; ///< The 7-bit or 10-bit address of the slave. + unsigned char* tx_buf; ///< The buffer containing the bytes to write. + unsigned int tx_len; ///< The number of bytes to write. On return + ///< from the function, this will be set to + ///< the number of bytes actually transmitted. + unsigned char* rx_buf; ///< The buffer to read the data into. + unsigned int rx_len; ///< The number of bytes to read. On return + ///< from the function, this will be set to + ///< the number of bytes actually received. + int restart; ///< Controls whether the transaction is + ///< terminated with a stop or repeated start + ///< condition. Use 0 for a stop, non-zero + ///< for repeated start. + mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the + ///< transaction is complete or an error has + ///< occurred. This field may be set to NULL + ///< if no indication is necessary. This + ///< field is only used by the + ///< MXC_I2C_MasterTransactionAsync() function. + ///< MXC_I2C_MasterTransaction() ignores the + ///< callback field. +}; + +/** + * @brief The list of events reported by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync() functions. + * + * The list of events reported by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync() functions. It is up to the calling + * application to handle these events. + */ +typedef enum { + MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master + ///< requesting a write to the slave. + MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master + ///< requesting a read from the slave. + MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its + ///< threshold level. + MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its + ///< threshold level. + MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended. + MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the + ///< transmit FIFO was empty. + MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive + ///< FIFO was already full. +} mxc_i2c_slave_event_t; + +/** + * @brief The callback routine used by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync functions to handle the various I2C + * slave events. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param event The event that occurred to trigger this callback. + * @param data This field is used to pass Success/Fail for the + * MXC_I2C_EVT_TRANS_COMP event. + * + * @return The return value is only used in the case of an MXC_I2C_EVT_RX_THRESH + * event. In this case, the return specifies if the last byte + * received should be acknowledged or not. Return 0 to acknowledge, + * non-zero to not acknowledge. The return value is ignored for all + * other event types. + */ +typedef int (*mxc_i2c_slave_handler_t) (mxc_i2c_regs_t* i2c, + mxc_i2c_slave_event_t event, void* data); + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable I2C peripheral. + * @note This function sets the I2C Speed to 100kHz, if another speed is + * desired use the MXC_I2C_SetFrequency() function to set it. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param masterMode Whether to put the device in master or slave mode. Use + * non-zero + * for master mode, and zero for slave mode. + * @param slaveAddr 7-bit or 10-bit address to use when in slave mode. + * This parameter is ignored when masterMode is non-zero. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Init (mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr); + +/** + * @brief Set slave address for I2C instances acting as slaves on the bus. + * @note Set idx to zero, multiple I2C instances acting as slaves on the + * bus is not yet supported. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param slaveAddr 7-bit or 10-bit address to use when in slave mode. + * This parameter is ignored when masterMode is non-zero. + * @param idx Index of the I2C slave. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx); + +/** + * @brief Disable and shutdown I2C peripheral. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Shutdown (mxc_i2c_regs_t* i2c); + +/** + * @brief Set the frequency of the I2C interface. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param hz The desired frequency in Hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_SetFrequency (mxc_i2c_regs_t* i2c, unsigned int hz); + +/** + * @brief Get the frequency of the I2C interface. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The I2C bus frequency in Hertz + */ +unsigned int MXC_I2C_GetFrequency (mxc_i2c_regs_t* i2c); + +/** + * @brief Checks if the given I2C bus can be placed in sleep more. + * + * This functions checks to see if there are any on-going I2C transactions in + * progress. If there are transactions in progress, the application should + * wait until the I2C bus is free before entering a low-power state. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_ReadyForSleep (mxc_i2c_regs_t* i2c); + +/** + * @brief Enables or disables clock stretching by the slave. + * + * Enables or disables clock stretching by the slave. This function has no + * affect when operating as the master. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param enable Enables clock stretching if non-zero, disables if zero. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetClockStretching (mxc_i2c_regs_t* i2c, int enable); + +/** + * @brief Determines if clock stretching has been enabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Zero if clock stretching is disabled, non-zero otherwise + */ +int MXC_I2C_GetClockStretching (mxc_i2c_regs_t* i2c); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Generate a start (or repeated start) condition on the I2C bus. + * + * Generate a start (or repeated start) condition on the I2C bus. This + * function may opt to delay the actual generation of the start condition + * until data is actually transferred. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Start (mxc_i2c_regs_t* i2c); + +/** + * @brief Generate a stop condition on the I2C bus. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Stop (mxc_i2c_regs_t* i2c); + +/** + * @brief Write a single byte to the I2C bus. + * + * Write a single byte to the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the write phase of an I2C transaction). If any + * bytes are pending in the FIFO (i.e. in the case of clock stretching), this + * function will return E_OVERFLOW. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte The byte to transmit. + * + * @return 0 if byte is acknowledged, 1 if not acknowledged, negative if + * error. See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_WriteByte (mxc_i2c_regs_t* i2c, unsigned char byte); + +/** + * @brief Read a single byte from the I2C bus. + * + * Read a single byte from the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the read phase of an I2C transaction). If the FIFO + * is empty, this function will return E_UNDERFLOW. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte Pointer to the byte to read into. + * @param ack Whether or not to acknowledge the byte once received. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_ReadByte (mxc_i2c_regs_t* i2c, unsigned char* byte, int ack); + +/** + * @brief Read a single byte from the I2C bus. + * + * Read a single byte from the I2C bus. After the byte is received, the + * provided callback will be used to determine if the byte should be + * acknowledged or not before continuing with the rest of the transaction. + * This function assumes the I2C bus is already in the proper state (i.e. a + * start condition has already been generated and the bus is in the read + * phase of an I2C transaction). This function must be called with clock + * stretching enabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte Pointer to the byte to read into. + * @param getAck A function to be called to determine whether or not + * to acknowledge the byte once received. A non-zero + * return value will acknowledge the byte. If this + * parameter is set to NULL or its return value is 0, + * the byte received will not be acknowledged (i.e., it + * will be NACKed). + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_ReadByteInteractive (mxc_i2c_regs_t* i2c, unsigned char* byte, + mxc_i2c_getAck_t getAck); + +/** + * @brief Write multiple bytes to the I2C bus. + * + * Write multiple bytes to the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the write phase of an I2C transaction). + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to transmit. + * @param len The number of bytes to write. On return from the + * function, this will be set to the number of bytes + * actually transmitted. + * + * @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not + * acknowledged, negative if error. See \ref MXC_Error_Codes for the + * list of error return codes. + */ +int MXC_I2C_Write (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len); + +/** + * @brief Read multiple bytes from the I2C bus. + * + * Read multiple byte from the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the read phase of an I2C transaction). + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. On return from the + * function, this will be set to the number of bytes + * actually received. + * @param ack Whether or not to acknowledge the last byte once it is + * received. All previous bytes will be acknowledged. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Read (mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, + int ack); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +int MXC_I2C_ReadRXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, + unsigned int len); + +/** + * @brief Unloads bytes from the receive FIFO using DMA for longer reads. + * + * @note The operation is not complete until the callback has been called + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values. + */ +int MXC_I2C_ReadRXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, + unsigned int len, mxc_i2c_dma_complete_cb_t callback); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The number of bytes available. + */ +int MXC_I2C_GetRXFIFOAvailable (mxc_i2c_regs_t* i2c); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +int MXC_I2C_WriteTXFIFO (mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, + unsigned int len); + +/** + * @brief Loads bytes into the transmit FIFO using DMA for longer writes. + * + * @note The operation is not complete until the callback has been called + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_I2C_WriteTXFIFODMA (mxc_i2c_regs_t* i2c, unsigned char* bytes, + unsigned int len, mxc_i2c_dma_complete_cb_t callback); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The number of bytes available. + */ +int MXC_I2C_GetTXFIFOAvailable (mxc_i2c_regs_t* i2c); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_ClearRXFIFO (mxc_i2c_regs_t* i2c); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_ClearTXFIFO (mxc_i2c_regs_t* i2c); + +/** + * @brief Get the presently set interrupt flags. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Pointer to the variable to store the current status of the interrupt flags in intfl0. + * @param flags1 Pointer to the variable to store the current status of the interrupt flags in intfl0. + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_I2C_GetFlags (mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); + +/** + * @brief Clears the Interrupt Flags. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Flags to clear in the intfl0 interrupt register. + * @param flags1 Flags to clear in the intfl1 interrupt register. + */ +void MXC_I2C_ClearFlags (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Enable Interrupts. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Interrupts to be enabled in int->en0 + * @param flags1 Interrupts to be enabled in int->en1 + */ +void MXC_I2C_EnableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Disable Interrupts. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Interrupts to be disabled in int->en0 + * @param flags1 Interrupts to be disabled in int->en1 + */ +void MXC_I2C_DisableInt (mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Enables the slave preload mode + * + * Use this mode to preload the slave TX FIFO with data that can be sent when + * the slave is addressed for a read operation without software intervention. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c); + +/** + * @brief Disable the slave preload mode + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c); + +/** + * @brief Enables the slave to respond to the general call address + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c); + +/** + * @brief Prevents the slave from responding to the general call address + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c); + +/** + * @brief Set the I2C Timeout + * + * The I2C timeout determines the amount of time the master will wait while the + * slave is stretching the clock, and the amount of time the slave will stretch + * the clock while waiting for software to unload the fifo. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param timeout Timeout in uS + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout); + +/** + * @brief Get the current I2C timeout + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The current timeout in uS + */ +unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c); + +/** + * @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle. + * + * Attempts to recover and reset an I2C bus by sending I2C clocks. During + * each clock cycle, the SDA line is cycled to determine if the master has + * control of the line. The following steps are performed to create one SCL + * clock cycle: + * 1. Drive SCL low + * 2. Verify SCL is low + * 3. Drive SDA low + * 4. Verify SDA is low + * 5. Release SDA allowing it to return high + * 6. Verify SDA is high + * 7. Release SCL allowing it to return high. + * 8. Verify SCL is high + * If any of the steps fail, the bus is considered to still be busy and the + * sequence is repeated up to the requested number of times. If all steps + * succeed, a final stop condition is generated on the I2C bus. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param retries Number of times to attempt the clock cycle sequence. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Recover (mxc_i2c_regs_t* i2c, unsigned int retries); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking I2C Master transaction. + * + * Performs a blocking I2C transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * Steps 3-6 will be skipped if req->tx_len and req->rx_len are both 0. + * Steps 2-4 will be skipped if req->tx_len equals 0. + * Steps 4-6 will be skipped if req->rx_len equals 0. + * + * @param req Pointer to details of the transaction + * + * @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not + * acknowledged, negative if error. See \ref MXC_Error_Codes for the + * list of error return codes. + */ +int MXC_I2C_MasterTransaction (mxc_i2c_req_t* req); + +/** + * @brief Performs a non-blocking I2C Master transaction. + * + * Performs a non-blocking I2C transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * 8. Execute req->callback to indicate the transaction is complete. + * Steps 3-6 will be skipped if tx_len and rx_len are both 0. + * Steps 2-4 will be skipped if tx_len equals 0. + * Steps 4-6 will be skipped if rx_len equals 0. + * + * @note MXC_I2C_AsyncHandler() must be called periodically for this function + * to operate properly. Ideally from the I2C ISR. + * + * @param req Pointer to details of the transaction. The memory + * used by this parameter must remain available until + * the callback is executed. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_MasterTransactionAsync (mxc_i2c_req_t* req); + +/** + * @brief Performs a non-blocking I2C Master transaction using DMA for reduced time + * in the ISR. + * + * Performs a non-blocking I2C transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * 8. Execute req->callback to indicate the transaction is complete. + * Steps 3-6 will be skipped if tx_len and rx_len are both 0. + * Steps 2-4 will be skipped if tx_len equals 0. + * Steps 4-6 will be skipped if rx_len equals 0. + * + * @note MXC_I2C_AsyncHandler() must be called periodically for this function + * to operate properly. Ideally from the I2C ISR. + * + * @param req Pointer to details of the transaction. The memory + * used by this parameter must remain available until + * the callback is executed. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_MasterTransactionDMA (mxc_i2c_req_t* req); + +/** + * @brief Performs a blocking I2C Slave transaction. + * + * Performs a blocking I2C transaction. This function will block until a + * complete transaction with this slave has been performed. A transaction + * begins with the master addressing the slave and ends with a repeated start + * condition, a stop condition, or a bus error. The provided callback + * function will be called for these events: + * - A slave address match occurs with the master requesting a write to + * the slave. + * - A slave address match occurs with the master requesting a read from + * the slave. + * - The receive FIFO crosses the set threshold (see + * MXC_I2C_SetRXThreshold()). The callback code should unload the receive + * FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data. + * The return value of the callback function will determine if the + * last byte received should be acknowledged or not. Return 0 to + * acknowledge, non-zero to not acknowledge. + * - The transmit FIFO crosses the set threshold (see + * MXC_I2C_SetTXThreshold()). If the master is expected to read more + * data from this slave, the callback code should add data to the + * transmit FIFO (see MXC_I2C_WriteFIFO()). + * - The transaction ends. If the master was writing to the slave, the + * receive FIFO may still contain valid data that needs to be + * retreived (see MXC_I2C_ReadFIFO()). + * - The transmit FIFO underflows because the master requests data when + * the transmit FIFO is empty. + * - The receive FIFO overflows because the master writes data while the + * receive FIFO was full. + * + * If clock stretching is disabled, careful attention must be paid to the timing + * of the callback to avoid losing data on write or unintentionally nacking a read. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param callback The function to be called when an I2C event occurs. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SlaveTransaction (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); + +/** + * @brief Performs a non-blocking I2C Slave transaction. + * + * Performs a non-blocking I2C transaction. This request will remain active + * until a complete transaction with this slave has been performed. A + * transaction begins with the masterMXC_I2C_MasterTransactionDMA addressing the + * slave and ends with a repeated start condition, a stop condition, or a bus + * error. The provided callback function will be called for these events: + * - A slave address match occurs with the master requesting a write to + * the slave. + * - A slave address match occurs with the master requesting a read from + * the slave. + * - The receive FIFO crosses the set threshold (see + * MXC_I2C_SetRXThreshold()). The callback code should unload the receive + * FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data. + * The return value of the callback function will determine if the + * last byte received should be acknowledged or not. Return 0 to + * acknowledge, non-zero to not acknowledge. + * - The transmit FIFO crosses the set threshold (see + * MXC_I2C_SetTXThreshold()). If the master is expected to read more + * data from this slave, the callback code should add data to the + * transmit FIFO (see MXC_I2C_WriteFIFO()). + * - The transaction ends. If the master was writing to the slave, the + * receive FIFO may still contain valid data that needs to be + * retreived (see MXC_I2C_ReadFIFO()). + * - The transmit FIFO underflows because the master requests data when + * the transmit FIFO is empty. + * - The receive FIFO overflows because the master writes data while the + * receive FIFO was full. + * + * If clock stretching is disabled, careful attention must be paid to the timing + * of the callback to avoid losing data on write or unintentionally nacking a read. + * + * @note MXC_I2C_AsyncHandler() must be called peridocally for this function + * to operate properly. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param callback The function to be called when an I2C event occurs. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SlaveTransactionAsync (mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback); + +/** + * @brief Set the receive threshold level. + * + * When operating as a master, the function sets the receive threshold level + * for when the master should unload the receive FIFO. Smaller values may + * consume more CPU cycles, but decrease the chances of the master delaying + * the generation of I2C bus clocks because it has no room in the FIFO to + * receive data. Larger values may consume fewer CPU cycles, but risk delays + * of the I2C clock. When operating as a slave, this function sets the number + * of bytes the slave transaction functions should receive before issuing a + * call to their callback function. Smaller values may consume more CPU + * cycles, but reduce the risk of missing data from the master due to the + * recieve FIFO being full. Larger values may reduce the number of CPU + * cycles, but may cause bytes sent from the master to be missed. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetRXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_I2C_GetRXThreshold (mxc_i2c_regs_t* i2c); + +/** + * @brief Set the transmit threshold level. + * + * When operating as a master, the function sets the transmit threshold level + * for when the master should add additional bytes to the transmit FIFO. + * Larger values may consume more CPU cycles, but decrease the chances of the + * master delaying the generation of I2C bus clocks because it has no data in + * the FIFO to transmit. Smaller values may consume fewer CPU cycles, but + * risk delays of the I2C clock. When operating as a slave, this function + * sets the number of bytes the slave transaction functions should transmit + * before issuing a call to their callback function. Larger values may + * consume more CPU cycles, but reduce the risk of not having data ready when + * the master requests it. Smaller values may reduce the number of CPU + * cycles, but may cause the master to read from an empty FIFO. (The master + * will read 0xFF in this case.) + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetTXThreshold (mxc_i2c_regs_t* i2c, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_I2C_GetTXThreshold (mxc_i2c_regs_t* i2c); + +/** + * @brief Abort any asynchronous requests in progress. + * + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AbortAsync (mxc_i2c_regs_t* i2c); + +/** + * @brief The processing function for asynchronous transactions. + * + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the I2C interrupt + * handler or periodically by the application if I2C interrupts are disabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AsyncHandler (mxc_i2c_regs_t* i2c); + +/** + * @brief The processing function for DMA transactions. + * + * When using the DMA functions, the application must call this + * function periodically. This can be done from within the DMA Interrupt Handler. + * + * @param ch DMA channel + * @param error Error status + */ +void MXC_I2C_DMACallback (int ch, int error); + + +/**@} end of group i2c */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_I2C_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h new file mode 100644 index 00000000000..455398a4de0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_lock.h @@ -0,0 +1,104 @@ +/** + * @file mxc_lock.h + * @brief Exclusive access lock utility functions. +*/ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_LOCK_H_ +#define _MXC_LOCK_H_ + +// To enable disable this module +#define USE_LOCK_IN_DRIVERS 0 + +#if USE_LOCK_IN_DRIVERS + +/* **** Includes **** */ +#include "mxc_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_lock_utilities Exclusive Access Locks + * @brief Lock functions to obtain and release a variable for exclusive + * access. These functions are marked interrupt safe if they are + * interrupt safe. + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Attempts to acquire the lock. + * @details This in an interrupt safe function that can be used as a mutex. + * The lock variable must remain in scope until the lock is + * released. Will not block if another thread has already acquired + * the lock. + * @param lock Pointer to variable that is used for the lock. + * @param value Value to be place in the lock. Can not be 0. + * + * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. + */ +int MXC_GetLock (uint32_t *lock, uint32_t value); + +/** + * @brief Free the given lock. + * @param[in,out] lock Pointer to the variable used for the lock. When the lock + * is free, the value pointed to by @p lock is set to zero. + */ +void MXC_FreeLock (uint32_t *lock); + +/**@} end of group mxc_lock_utilities */ + +#ifdef __cplusplus +} +#endif + + +#else // USE_LOCK_IN_DRIVERS + +#define MXC_GetLock(x, y) E_NO_ERROR +#define MXC_FreeLock(x) + +#endif // USE_LOCK_IN_DRIVERS + +#endif /* _MXC_LOCK_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h new file mode 100644 index 00000000000..4fc112179c2 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_pins.h @@ -0,0 +1,85 @@ +/** + * @file mxc_pins.h + * @brief This file contains constant pin configurations for the peripherals. + */ + +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + + +#ifndef _MXC_PINS_H_ +#define _MXC_PINS_H_ + +#include "gpio.h" + +/***** Global Variables *****/ + +typedef enum { + MAP_A, + MAP_B, + MAP_C +} sys_map_t; + +// Predefined GPIO Configurations +extern const mxc_gpio_cfg_t gpio_cfg_swda; +extern const mxc_gpio_cfg_t gpio_cfg_swdb; + +extern const mxc_gpio_cfg_t gpio_cfg_i2c0; +extern const mxc_gpio_cfg_t gpio_cfg_i2c1; + + +extern const mxc_gpio_cfg_t gpio_cfg_uart0; +extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart1a; +extern const mxc_gpio_cfg_t gpio_cfg_uart1b; +extern const mxc_gpio_cfg_t gpio_cfg_uart1c; +extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; + + +extern const mxc_gpio_cfg_t gpio_cfg_spi0; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_ss; +extern const mxc_gpio_cfg_t gpio_cfg_spi1a; +extern const mxc_gpio_cfg_t gpio_cfg_spi1a_ss; +extern const mxc_gpio_cfg_t gpio_cfg_spi1b; +extern const mxc_gpio_cfg_t gpio_cfg_spi1b_ss; + +// Timers are only defined once, depending on package, each timer could be mapped to other pins +extern const mxc_gpio_cfg_t gpio_cfg_tmr0; +extern const mxc_gpio_cfg_t gpio_cfg_32kcal; + +extern const mxc_gpio_cfg_t gpio_cfg_i2s0a; +extern const mxc_gpio_cfg_t gpio_cfg_i2s0b; + + +#endif /* _MXC_PINS_H_ */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h new file mode 100644 index 00000000000..fe4c440149c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_spi.h @@ -0,0 +1,648 @@ +/** + * @file spi.h + * @brief Serial Peripheral Interface (SPI) communications driver. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ +#ifndef _SPI_H_ +#define _SPI_H_ + +/***** includes *******/ +#include "spi_regs.h" +#include "mxc_sys.h" +#include "mxc_assert.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "mxc_lock.h" + + +/***** Definitions *****/ + +/** + * @defgroup spi SPI + * @ingroup periphlibs + * @{ + */ + +/** + * @brief The list of SPI Widths supported + * + * The SPI Width can be set on a per-transaction basis. + * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is + * given. + * + * Using a MAX31865 RTD-to-SPI IC, read back the temperature + * The IC requires a SPI Read to be executed as + * 1. Assert SS + * 2. Write an 8bit register address + * 3. Read back the 8 bit register + * 4. Deassert SS + * This can be accomplished with the STANDARD_HALFDUPLEX width + * 1. set txData to the address, txLen=1 + * 2. set rxData to a buffer of 1 byte, rxLen=1 + * 3. The driver will transmit the txData, and after completion of + * txData begin to recieve data, padding MOSI with DefaultTXData + * + */ +typedef enum { + SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex + SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex + SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex + SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex +} mxc_spi_width_t; + +/** + * @brief The list of SPI modes + * + * SPI supports four combinations of clock and phase polarity + * + * Clock polarity is controlled using the bit SPIn_CTRL2.cpol + * and determines if the clock is active high or active low + * + * Clock phase determines when the data must be stable for sampling + * + */ +typedef enum { + SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 + SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 + SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 + SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 +} mxc_spi_mode_t; + +typedef struct _mxc_spi_req_t mxc_spi_req_t; + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*spi_complete_cb_t) (void * req, int result); + +/** + * @brief The information required to perform a complete SPI transaction + * + * This structure is used by blocking, async, and DMA based transactions. + * @param "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. + */ +struct _mxc_spi_req_t { + mxc_spi_regs_t* spi; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + uint32_t txCnt; ///< Number of bytes actually transmitted from txData + uint32_t rxCnt; ///< Number of bytes stored in rxData + + spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete +}; + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable SPI peripheral. + * + * This function initializes everything necessary to call a SPI transaction function. + * Some parameters are set to defaults as follows: + * SPI Mode - 0 + * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set) + * + * These parameters can be modified after initialization using low level functions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param masterMode Whether to put the device in master or slave mode. Use + * non-zero for master mode, and zero for slave mode. + * @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use + * non-zero if the pins are needed (if Quad Mode will + * be used), and zero if they are not needed (quad mode + * will never be used). + * @param numSlaves The number of slaves used, if in master mode. This + * is used to obtain control of the necessary SS pins. + * In slave mode this is ignored and SS1 is used. + * @param ssPolarity This field sets the SS active polarity for each + * slave, each bit position corresponds to each SS line. + * @param hz The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. Used in + * master mode only. + * @param drv_ssel Hardware block able to drive SS pin, or it can be leaved as it is + * To upper layer firmware drive it. + * 1:Driver will drive SS pin, 0:Driver will NOT drive it + * + * @return If successful, the actual clock frequency is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_Init (mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); + +/** + * @brief Disable and shutdown SPI peripheral. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_Shutdown (mxc_spi_regs_t* spi); + +/** + * @brief Checks if the given SPI bus can be placed in sleep mode. + * + * This functions checks to see if there are any on-going SPI transactions in + * progress. If there are transactions in progress, the application should + * wait until the SPI bus is free before entering a low-power state. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ReadyForSleep (mxc_spi_regs_t* spi); + +/** + * @brief Set the frequency of the SPI interface. + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param hz The desired frequency in Hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SetFrequency (mxc_spi_regs_t* spi, unsigned int hz); + +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi); + +/** + * @brief Get the frequency of the SPI interface. + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The SPI bus frequency in Hertz + */ +unsigned int MXC_SPI_GetFrequency (mxc_spi_regs_t* spi); + +/** + * @brief Sets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param dataSize The number of bits per character + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDataSize (mxc_spi_regs_t* spi, int dataSize); + +/** + * @brief Gets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetDataSize (mxc_spi_regs_t* spi); + + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Sets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param ssIdx Slave select index + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetSlave (mxc_spi_regs_t* spi, int ssIdx); + +/** + * @brief Gets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return slave slect + */ +int MXC_SPI_GetSlave (mxc_spi_regs_t* spi); + +/** + * @brief Sets the SPI width used for transmissions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetWidth (mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth); + +/** + * @brief Gets the SPI width used for transmissions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Spi Width \ref mxc_spi_width_t + */ +mxc_spi_width_t MXC_SPI_GetWidth (mxc_spi_regs_t* spi); + +/** + * @brief Sets the spi mode using clock polarity and clock phase + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spiMode \ref mxc_spi_mode_t + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode); + +/** + * @brief Gets the spi mode + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return mxc_spi_mode_t \ref mxc_spi_mode_t + */ +mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi); + +/** + * @brief Starts a SPI Transmission + * + * This function is applicable in Master mode only + * + * The user must ensure that there are no ongoing transmissions before + * calling this function + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_StartTransmission (mxc_spi_regs_t* spi); + +/** + * @brief Checks the SPI Peripheral for an ongoing transmission + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetActive (mxc_spi_regs_t* spi); + +/** + * @brief Aborts an ongoing SPI Transmission + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_AbortTransmission (mxc_spi_regs_t* spi); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +unsigned int MXC_SPI_ReadRXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, + unsigned int len); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_SPI_GetRXFIFOAvailable (mxc_spi_regs_t* spi); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +unsigned int MXC_SPI_WriteTXFIFO (mxc_spi_regs_t* spi, unsigned char* bytes, + unsigned int len); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_SPI_GetTXFIFOAvailable (mxc_spi_regs_t* spi); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearRXFIFO (mxc_spi_regs_t* spi); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearTXFIFO (mxc_spi_regs_t* spi); + +/** + * @brief Set the receive threshold level. + * + * RX FIFO Receive threshold. Smaller values will cause + * interrupts to occur more often, but reduce the possibility + * of losing data because of a FIFO overflow. Larger values + * will reduce the time required by the ISR, but increase the + * possibility of data loss. Passing an invalid value will + * cause the driver to use the value already set in the + * appropriate register. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetRXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_SPI_GetRXThreshold (mxc_spi_regs_t* spi); + +/** + * @brief Set the transmit threshold level. + * + * TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetTXThreshold (mxc_spi_regs_t* spi, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_SPI_GetTXThreshold (mxc_spi_regs_t* spi); + +/** + * @brief Gets the interrupt flags that are currently set + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The interrupt flags + */ +unsigned int MXC_SPI_GetFlags (mxc_spi_regs_t* spi); + +/** + * @brief Clears the interrupt flags that are currently set + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearFlags (mxc_spi_regs_t* spi); + +/** + * @brief Enables specific interrupts + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param mask The interrupts to be enabled + */ +void MXC_SPI_EnableInt (mxc_spi_regs_t* spi, unsigned int mask); + +/** + * @brief Disables specific interrupts + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param mask The interrupts to be disabled + */ +void MXC_SPI_DisableInt (mxc_spi_regs_t* spi, unsigned int mask); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking SPI transaction. + * + * Performs a blocking SPI transaction. + * These actions will be performed in Master Mode: + * 1. Assert the specified SS + * 2. In Full Duplex Modes, send TX data while receiving RX Data + * if rxLen > txLen, pad txData with DefaultTXData + * if txLen > rxLen, discard rxData where rxCnt > rxLen + * 3. In Half Duplex Modes, send TX Data, then receive RX Data + * 4. Deassert the specified SS + * + * These actions will be performed in Slave Mode: + * 1. Fill FIFO with txData + * 2. Wait for SS Assert + * 3. If needed, pad txData with DefaultTXData + * 4. Unload RX FIFO as needed + * 5. On SS Deassert, return + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransaction (mxc_spi_req_t* req); + +/** + * @brief Setup an interrupt-driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransactionAsync (mxc_spi_req_t* req); + +/** + * @brief Setup a DMA driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and + * set up to load/unload the FIFOs with as few interrupt-based events as + * possible. The channel will be reset and returned to the system at the end of + * the transaction. + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransactionDMA (mxc_spi_req_t* req); + +/** + * @brief Performs a blocking SPI transaction. + * + * Performs a blocking SPI transaction. + * These actions will be performed in Slave Mode: + * 1. Fill FIFO with txData + * 2. Wait for SS Assert + * 3. If needed, pad txData with DefaultTXData + * 4. Unload RX FIFO as needed + * 5. On SS Deassert, return + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransaction (mxc_spi_req_t* req); + +/** + * @brief Setup an interrupt-driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * @param req Pointer to details of the transactionz + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransactionAsync (mxc_spi_req_t* req); + +/** + * @brief Setup a DMA driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and + * set up to load/unload the FIFOs with as few interrupt-based events as + * possible. The channel will be reset and returned to the system at the end of + * the transaction. + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransactionDMA (mxc_spi_req_t* req); + +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDefaultTXData (mxc_spi_regs_t* spi, unsigned int defaultTXData); + +/** + * @brief Abort any asynchronous requests in progress. + * + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_AbortAsync (mxc_spi_regs_t* spi); + +/** + * @brief The processing function for asynchronous transactions. + * + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the SPI interrupt + * handler or periodically by the application if SPI interrupts are disabled. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_AsyncHandler (mxc_spi_regs_t* spi); +/**@} end of group spi */ + +#ifdef __cplusplus +} +#endif + +#endif /* _PT_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h new file mode 100644 index 00000000000..29a791d4d48 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_sys.h @@ -0,0 +1,167 @@ +/** + * @file mxc_sys.h + * @brief System level header file. + */ + +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + ******************************************************************************/ + +#ifndef _MXC_MXC_SYS_H_ +#define _MXC_MXC_SYS_H_ + +#include "mxc_device.h" +#include "gcr_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ +typedef enum { + MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ + MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ + MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ + MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, /**< Reset TIMER0 */ + MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, /**< Reset TIMER1 */ + MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, /**< Reset TIMER2 */ + MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ + MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, /**< Reset SPI0 */ + MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ + MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ + MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ + MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ + MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ + MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, /**< System reset */ + /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ + MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ +} mxc_sys_reset_t; + +/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ +typedef enum { + MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PCLK_DIS0_DMAD_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ + MXC_SYS_PERIPH_CLOCK_SPI0 = MXC_F_GCR_PCLK_DIS0_SPI0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PCLK_DIS0_SPI1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ + MXC_SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PCLK_DIS0_UART0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ + MXC_SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PCLK_DIS0_UART1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ + MXC_SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PCLK_DIS0_I2C0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T1 clock */ + MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T2 clock */ + MXC_SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PCLK_DIS0_I2C1D_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ + /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ + MXC_SYS_PERIPH_CLOCK_FLCD = (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT1 clock */ + MXC_SYS_PERIPH_CLOCK_ICACHE = (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ +} mxc_sys_periph_clock_t; + +/** @brief Enumeration to select System Clock source */ +typedef enum { + MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */ + MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */ + MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ + MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */ +} mxc_sys_system_clock_t; + +/***** Function Prototypes *****/ + +/** + * @brief Determines if the selected peripheral clock is enabled. + * @param clock Enumeration for desired clock. + * @returns 0 is the clock is disabled, non 0 if the clock is enabled. + */ +int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock); + +/** + * @brief Disables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock); + +/** + * @brief Enables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock); + +/** + * @brief Enables the 32kHz oscillator + * @param mxc_sys_cfg Not used, may be NULL. + */ +void MXC_SYS_RTCClockEnable (void); + +/** + * @brief Disables the 32kHz oscillator + * @returns E_NO_ERROR if everything is successful + */ +int MXC_SYS_RTCClockDisable(); + +/** + * @brief Enable System Clock Source without switching to it + * @param clock The clock to enable + * @return E_NO_ERROR if everything is successful + */ +int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock); + +/** + * @brief Disable System Clock Source + * @param clock The clock to disable + * @return E_NO_ERROR if everything is successful + */ +int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock); + +/** + * @brief Select the system clock. + * @param clock Enumeration for desired clock. + * @param tmr Optional tmr pointer for timeout. NULL if undesired. + * @returns E_NO_ERROR if everything is successful. + */ +int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock); + +/** + * @brief Wait for a clock to enable with timeout + * @param ready The clock to wait for + * @return E_NO_ERROR if ready, E_TIME_OUT if timeout + */ +int MXC_SYS_Clock_Timeout (uint32_t ready); +/** + * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. + * @param Enumeration for what to reset. Can reset multiple items at once. + */ +void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset); + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_MXC_SYS_H_*/ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h new file mode 100644 index 00000000000..2320fc2fccc --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/rtc.h @@ -0,0 +1,199 @@ +/** + * @file rtc.h + * @brief Real Time Clock (RTC) functions and prototypes. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _RTC_H_ +#define _RTC_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "rtc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup rtc Real Time Clock (RTC) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ +/** + * @brief Bitmasks for each of the RTC's Frequency. + */ +typedef enum { + MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, ///< 1Hz (Compensated) + MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, ///< 512Hz (Compensated) + MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, ///< 4Khz + MXC_RTC_F_32KHZ = 32, ///< 32Khz +} mxc_rtc_freq_sel_t; + +/** + * @brief Bitmasks for each of the RTC's interrupt enables. + */ +typedef enum { + MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_ADE, ///< Long-interval alarm interrupt enable + MXC_RTC_INT_EN_SHORT = MXC_F_RTC_CTRL_ASE, ///< Short-interval alarm interrupt enable + MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDYE, ///< Timer ready interrupt enable +} mxc_rtc_int_en_t; + +/** + * @brief Bitmasks for each of the RTC's interrupt flags. + */ +typedef enum { + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_ALDF, ///< Long-interval alarm interrupt flag + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_ALSF, ///< Short-interval alarm interrupt flag + MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, ///< Timer ready interrupt flag +} mxc_rtc_int_fl_t; + +/** + * @brief Set Time-of-Day alarm value and enable Interrupt + * @param ras 20-bit value 0-0xFFFFF + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_SetTimeofdayAlarm (uint32_t ras); + +/** + * @brief Set Sub-Second alarm value and enable interrupt, + * @brief this is to be called after the init_rtc() function + * @param rssa 32-bit value 0-0xFFFFFFFF + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_SetSubsecondAlarm (uint32_t rssa); + +/** + * @brief Start the Real Time Clock + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_Start (void); +/** + * @brief Stop the Real Time Clock + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_Stop (void); + +/** + * @brief Initialize the sec and ssec registers and enable RTC + * @param sec set the RTC Sec counter (32-bit) + * @param ssec set the RTC Sub-second counter (8-bit) + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_Init (uint32_t sec, uint8_t ssec); + +/** + * @brief Allow generation of Square Wave on the SQW pin + * @param fq Frequency output selection + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_SquareWaveStart (mxc_rtc_freq_sel_t fq); + +/** + * @brief Stop the generation of square wave + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_SquareWaveStop (void); + +/** + * @brief Set Trim register value + * @param trm set the RTC Trim (8-bit, +/- 127) + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_Trim (int8_t trm); + +/** + * @brief Enable Interurpts + * @param mask The bitwise OR of interrupts to enable. + * See #mxc_rtc_int_en_t for available choices. + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_EnableInt (uint32_t mask); + +/** + * @brief Disable Interurpts + * @param mask The mask of interrupts to disable. + * See #mxc_rtc_int_en_t for available choices. + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_DisableInt (uint32_t mask); + +/** + * @brief Gets interrupt flags. + * @retval The bitwise OR of any interrupts flags that are + * currently set. See \ref mxc_rtc_int_fl_t for the list + * of possible flags. + */ +int MXC_RTC_GetFlags (void); + +/** + * @brief Clear interrupt flags. + * @param flags The bitwise OR of the interrupts flags to cleear. + * See #mxc_rtc_int_fl_t for the list of possible flags. + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_ClearFlags (int flags); + +/** + * @brief Get SubSecond + * @retval Returns subsecond value + */ +int MXC_RTC_GetSubSecond (void); + +/** + * @brief Get Second + * @retval returns second value + */ +int MXC_RTC_GetSecond (void); + +/** + * @brief Get the time using nuclear fusion. Or atomically. Something like that. + * @param sec pointer to store seconds value + * @param subsec pointer to store subseconds value + * @retval returns Success or Fail, see \ref MXC_Error_Codes + */ +int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec); + +/**@} end of group rtc */ +#ifdef __cplusplus +} +#endif + +#endif /* _RTC_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h new file mode 100644 index 00000000000..c6bcf2b39fd --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/spimss.h @@ -0,0 +1,210 @@ +/** + * @file spimss.h + * @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _SPIMSS_H_ +#define _SPIMSS_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_sys.h" +#include "mxc_pins.h" +#include "gpio.h" +#include "spimss_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spimss SPIMSS + * @ingroup spimss + * @{ + */ + +/* **** Definitions **** */ + + +/** + * @brief Enumeration type for setting the number data lines to use for communication. + */ +typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED + DUMMY_1, /**< NOT USED */ + DUMMY_2, /**< NOT USED */ + DUMMY_3, /**< NOT USED */ +} mxc_spimss_width_t; + +/** + * @brief Structure type representing a SPI Master Transaction request. + */ +typedef struct mxc_spimss_req mxc_spimss_req_t; + +/** + * @brief Callback function type used in asynchronous SPI Master communication requests. + * @details The function declaration for the SPI Master callback is: + * @code + * void callback(spi_req_t * req, int error_code); + * @endcode + * | | | + * | -----: | :----------------------------------------- | + * | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. | + * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | + * @note Callback will execute in interrupt context + */ +typedef void (*mxc_spimss_callback_fn)(mxc_spimss_req_t * req, int error_code); + +/** + * @brief Structure definition for an SPI Master Transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + */ +struct mxc_spimss_req { + uint8_t ssel; /**< Not Used*/ + uint8_t deass; /**< Not Used*/ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + mxc_spimss_width_t width; /**< Not Used */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + mxc_spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */ +}; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the spi. + * @param spi Pointer to spi module to initialize. + * @param mode SPI mode for clock phase and polarity. + * @param freq Desired clock frequency. + * @param sys_cfg System configuration object + * @param drv_ssel 1 SSEL will be drive by driver + * 0 SSEL will NOT be drive by driver + * + * @return \c #E_NO_ERROR if successful, appropriate error otherwise + */ +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel); + +/** + * @brief Shutdown SPI module. + * @param spi Pointer to SPI regs. + * + * @return \c #E_NO_ERROR if successful, appropriate error otherwise + */ +int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi); + +/** + * @brief Execute a master transaction. + * @param spi Pointer to spi module. + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); + +/** + * @brief Execute SPI transaction based on interrupt handler + * @param spi The spi + * + */ +void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi); + +/** + * @brief Execute a slave transaction. + * @param spi Pointer to spi module. + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); + +/** + * @brief Asynchronously read/write SPI Master data + * + * @param spi Pointer to spi module + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); + +/** + * @brief Asynchronously read/write SPI Slave data + * + * @param spi Pointer to spi module + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req); + +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPIMSS_SetDefaultTXData (mxc_spimss_req_t* spi, unsigned int defaultTXData); + +/** + * @brief Aborts an Asynchronous request + * + * @param req Pointer to spi request + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req); + +/**@} end of group spimss */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPIMSS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h new file mode 100644 index 00000000000..f60a0d8e29a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/tmr.h @@ -0,0 +1,343 @@ +/** + * @file tmr.h + * @brief Timer (TMR) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _TMR_H_ +#define _TMR_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "tmr_regs.h" +#include "mxc_sys.h" +#include "gcr_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup tmr Timer (TMR) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Timer prescaler values + */ +typedef enum { + TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV_BY_1, ///< Divide input clock by 1 + TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV_BY_2, ///< Divide input clock by 2 + TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV_BY_4, ///< Divide input clock by 4 + TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV_BY_8, ///< Divide input clock by 8 + TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV_BY_16, ///< Divide input clock by 16 + TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV_BY_32, ///< Divide input clock by 32 + TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV_BY_64, ///< Divide input clock by 64 + TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV_BY_128, ///< Divide input clock by 128 + TMR_PRES_256 = MXC_S_TMR_CN_PRES_DIV_BY_256, ///< Divide input clock by 256 + TMR_PRES_512 = MXC_S_TMR_CN_PRES_DIV_BY_512, ///< Divide input clock by 512 + TMR_PRES_1024 = MXC_S_TMR_CN_PRES_DIV_BY_1024, ///< Divide input clock by 1024 + TMR_PRES_2048 = MXC_S_TMR_CN_PRES_DIV_BY_2048, ///< Divide input clock by 2048 + TMR_PRES_4096 = MXC_S_TMR_CN_PRES_DIV_BY_4096, ///< Divide input clock by 4096 + TMR_PRES_8192 = MXC_S_TMR_CN_PRES_DIV_BY_8192 ///< Divide input clock by 8192 +} mxc_tmr_pres_t; + +/** + * @brief Timer modes + */ +typedef enum { + TMR_MODE_ONESHOT = MXC_S_TMR_CN_TMODE_ONE_SHOT, ///< Timer Mode ONESHOT + TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, ///< Timer Mode CONTINUOUS + TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, ///< Timer Mode COUNTER + TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, ///< Timer Mode PWM + TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, ///< Timer Mode CAPTURE + TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, ///< Timer Mode COMPARE + TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, ///< Timer Mode GATED + TMR_MODE_CAPTURE_COMPARE = MXC_S_TMR_CN_TMODE_CAPCOMP ///< Timer Mode CAPTURECOMPARE +} mxc_tmr_mode_t; + +/** + * @brief Timer bit mode + * + */ +typedef enum { + TMR_BIT_MODE_32, ///< Timer Mode 32 bit + TMR_BIT_MODE_16A, ///< Timer Mode Lower 16 bit + TMR_BIT_MODE_16B, ///< Timer Mode Upper 16 bit +} mxc_tmr_bit_mode_t; + +/** + * @brief Timer units of time enumeration + */ +typedef enum { + TMR_UNIT_NANOSEC, ///< Nanosecond Unit Indicator + TMR_UNIT_MICROSEC, ///< Microsecond Unit Indicator + TMR_UNIT_MILLISEC, ///< Millisecond Unit Indicator + TMR_UNIT_SEC, ///< Second Unit Indicator +} mxc_tmr_unit_t; + +/** + * @brief Clock settings + * @note 8M and 32M clocks can be used for Timers 0,1,2 and 3 + * 32K and 80K clocks can only be used for Timers 4 and 5 + */ +typedef enum { + MXC_TMR_HFIO_CLK, ///< HFIO Clock + MXC_TMR_NANORING_CLK, ///< 8KHz Nanoring Clock + MXC_TMR_EXT_CLK, ///< External Clock +} mxc_tmr_clock_t; + +/** + * @brief Timer Configuration + */ +typedef struct { + mxc_tmr_pres_t pres; ///< Desired timer prescaler + mxc_tmr_mode_t mode; ///< Desired timer mode + mxc_tmr_bit_mode_t bitMode; ///< Desired timer bits + mxc_tmr_clock_t clock; ///< Desired clock source + uint32_t cmp_cnt; ///< Compare register value in timer ticks + unsigned pol; ///< Polarity (0 or 1) +} mxc_tmr_cfg_t; + +/* **** Definitions **** */ +typedef void (*mxc_tmr_complete_t) (int error); + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize timer module clock. + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_Init (mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg); + +/** + * @brief Shutdown timer module clock. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Shutdown (mxc_tmr_regs_t *tmr); + +/** + * @brief Start the timer counting. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Start (mxc_tmr_regs_t* tmr); + +/** + * @brief Stop the timer. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Stop (mxc_tmr_regs_t* tmr); + +/** + * @brief Set the value of the first transition in PWM mode + * @param tmr Pointer to timer module to initialize. + * @param pwm New pwm count. + * @note Will block until safe to change the period count. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_SetPWM (mxc_tmr_regs_t* tmr, uint32_t pwm); + +/** + * @brief Get the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current compare count. + */ +uint32_t MXC_TMR_GetCompare (mxc_tmr_regs_t* tmr); + +/** + * @brief Get the timer capture count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the most recent capture count. + */ +uint32_t MXC_TMR_GetCapture (mxc_tmr_regs_t* tmr); + +/** + * @brief Get the timer count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current count. + */ +uint32_t MXC_TMR_GetCount (mxc_tmr_regs_t* tmr); + +/** + * @brief Calculate count for required frequency. + * @param tmr Timer + * @param clock Clock source. + * @param prescalar prescalar + * @param frequency required frequency. + * @return Returns the period count. + */ +uint32_t MXC_TMR_GetPeriod (mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency); + +/** + * @brief Clear the timer interrupt. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_ClearFlags (mxc_tmr_regs_t* tmr); + +/** + * @brief Get the timer interrupt status. + * @param tmr Pointer to timer module to initialize. + * @return Returns the interrupt status. 1 if interrupt has occured. + */ +uint32_t MXC_TMR_GetFlags (mxc_tmr_regs_t* tmr); + +/** + * @brief enable interupt + * + * @param tmr The timer + */ +void MXC_TMR_EnableInt (mxc_tmr_regs_t* tmr); + +/** + * @brief disable interupt + * + * @param tmr The timer + */ +void MXC_TMR_DisableInt (mxc_tmr_regs_t* tmr); + +/** + * @brief Set the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @param cmp_cnt New compare count. + * @note In PWM Mode use this to set the value of the second transition. + */ +void MXC_TMR_SetCompare (mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); + +/** + * @brief Set the timer count. + * @param tmr Pointer to timer module to initialize. + * @param cnt New count. + */ +void MXC_TMR_SetCount (mxc_tmr_regs_t *tmr, uint32_t cnt); + +/** + * @brief Dealay for a set periord of time measured in microseconds + * + * @param tmr The timer + * @param us microseconds to delay for + */ +void MXC_TMR_Delay (mxc_tmr_regs_t *tmr, unsigned long us); + +/** + * @brief Start a timer that will time out after a certain number of microseconds + * @note This uses the 32-it Timer + * + * @param tmr The timer + * @param us microseconds to time out after + */ +void MXC_TMR_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); + +/** + * @brief Check on time out timer + * + * @param tmr The timer + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_TO_Check (mxc_tmr_regs_t *tmr); + +/** + * @brief Stop the Timeout timer + * + * @param tmr The timer + */ +void MXC_TMR_TO_Stop (mxc_tmr_regs_t *tmr); + +/** + * @brief Clear timeout timer back to zero + * + * @param tmr The timer + */ +void MXC_TMR_TO_Clear (mxc_tmr_regs_t *tmr); + +/** + * @brief Get elapsed time of timeout timer + * + * @param tmr The timer + * + * @return Time that has elapsed in timeout timer + */ +unsigned int MXC_TMR_TO_Elapsed (mxc_tmr_regs_t *tmr); + +/** + * @brief Amount of time remaining until timeour + * + * @param tmr The timer + * + * @return Time that is left until timeout + */ +unsigned int MXC_TMR_TO_Remaining (mxc_tmr_regs_t *tmr); + +/** + * @brief Start stopwatch + * + * @param tmr The timer + */ +void MXC_TMR_SW_Start (mxc_tmr_regs_t *tmr); + +/** + * @brief Stopwatch stop + * + * @param tmr The timer + * + * @return the time when the stopwatch is stopped. + */ +unsigned int MXC_TMR_SW_Stop (mxc_tmr_regs_t *tmr); + +/** + * @brief Get time from timer + * + * @param tmr The timer + * @param ticks The ticks + * @param time The time + * @param units The units + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_GetTime (mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); + +/**@} end of group tmr */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h new file mode 100644 index 00000000000..35de287738a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/uart.h @@ -0,0 +1,690 @@ +/** + * @file uart.h + * @brief (UART) communications driver. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_UART_H_ +#define _MXC_UART_H_ + +/***** Definitions *****/ +#include "uart_regs.h" +#include "mxc_sys.h" +#include "mxc_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup uart UART + * @ingroup periphlibs + * @{ + */ + +typedef struct _mxc_uart_req_t mxc_uart_req_t; +/** + * @brief The list of UART stop bit lengths supported + * + */ +typedef enum { + MXC_UART_STOP_1, ///< UART Stop 1 clock cycle + MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) +} mxc_uart_stop_t; + +/** + * @brief The list of UART Parity options supported + * + */ +typedef enum { + MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN, ///< UART Parity Even + MXC_UART_PARITY_ODD, ///< UART Parity Odd + MXC_UART_PARITY_MARK, ///< UART Parity Mark + MXC_UART_PARITY_SPACE, ///< UART Parity Space + MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based + MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based + MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based + MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based + MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based + MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based + MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based + MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based +} mxc_uart_parity_t; + +/** + * @brief The list of UART flow control options supported + * + */ +typedef enum { + MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled + MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low + MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High +} mxc_uart_flow_t; + + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_uart_complete_cb_t) (mxc_uart_req_t* req, int result); + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param num The number of characters actually copied + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_uart_dma_complete_cb_t) (mxc_uart_req_t* req, int num, int result); + +/** + * @brief The information required to perform a complete UART transaction + * + * @note This structure is used by blocking, async, and DMA based transactions. + */ +struct _mxc_uart_req_t { + mxc_uart_regs_t* uart; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + uint32_t txCnt; ///< Number of bytes actually transmitted from txData + uint32_t rxCnt; ///< Number of bytes stored in rxData + + mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete +}; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable UART peripheral. + * + * This function initializes everything necessary to call a UART transaction function. + * Some parameters are set to defaults as follows: + * UART Data Size - 8 bits + * UART Stop Bits - 1 bit + * UART Parity - None + * UART Flow Control - None + * UART Clock - 7.37MHz Clock (for baud > 7372800, PCLK is used) + * + * These parameters can be modified after initialization using low level functions + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. + * @param map Selects which pin map to use. + * + * @return If successful, the actual clock frequency is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map); + +/** + * @brief Disable and shutdown UART peripheral. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Shutdown (mxc_uart_regs_t* uart); + +/** + * @brief Checks if the given UART bus can be placed in sleep more. + * + * @note This functions checks to see if there are any on-going UART transactions in + * progress. If there are transactions in progress, the application should + * wait until the UART bus is free before entering a low-power state. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart); + +/** + * @brief Set the frequency of the UART interface. + * + * + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The desired baud rate + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud); + +/** + * @brief Get the frequency of the UART interface. + * + * @note This function is applicable in Master mode only + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The UART baud rate + */ +int MXC_UART_GetFrequency (mxc_uart_regs_t* uart); + +/** + * @brief Sets the number of bits per character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param dataSize The number of bits per character (5-8 bits/character are valid) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize); + +/** + * @brief Sets the number of stop bits sent at the end of a character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param stopBits The number of stop bits used + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits); + +/** + * @brief Sets the type of parity generation used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param parity see \ref mxc_uart_parity_t UART Parity Types for details + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity); + +/** + * @brief Sets the flow control used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flowCtrl see \ref mxc_uart_flow_t UART Flow Control Types for details + * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); + +/** + * @brief Sets the clock source for the baud rate generator + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param usePCLK Non-zero values will use the PCLK as the bit clock instead + * of the default 7.37MHz clock source. The baud rate generator + * will automatically be reconfigured to the closest possible + * baud rate. + * + * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes + * for a list of return codes. + */ +int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK); + +/** + * @brief Enables or Disables the built-in null modem + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param nullModem Non-zero values will enable the null modem function, + * which swaps TXD/RXD and also swaps RTS/CTS, if used. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Transmits a Break Frame (all bits 0) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SendBreak (mxc_uart_regs_t* uart); + +/** + * @brief Checks the UART Peripheral for an ongoing transmission + * + * @note This function is applicable in Master mode only + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_GetActive (mxc_uart_regs_t* uart); + +/** + * @brief Aborts an ongoing UART Transmission + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart); + +/** + * @brief Reads the next available character. This function will block until a character + * is available or a UART error occurs. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart); + +/** + * @brief Writes a character on the UART. This function will block until the character + * has been placed in the TX FIFO or a UART error occurs. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param character The character to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character); + +/** + * @brief Reads the next available character. If no character is available, this function + * will return an error. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart); + +/** + * @brief Writes a character on the UART. If the character cannot be written because the + * transmit FIFO is currently full, this function returns an error. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param character The character to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character); + +/** + * @brief Reads the next available character + * @note This function blocks until len characters are received + * See MXC_UART_TransactionAsync() for a non-blocking version + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param buffer Buffer to store data in + * @param len Number of characters + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len); + +/** + * @brief Writes a byte on the UART + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param byte The buffer of characters to write + * @param len The number of characters to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len); + +/** + * @brief Unloads bytes from the receive FIFO user DMA for longer reads. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len); + +/** + * @brief Loads bytes into the transmit FIFO using DMA for longer writes + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the write is complete + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart); + +/** + * @brief Set the receive threshold level. + * + * @note RX FIFO Receive threshold. Smaller values will cause + * interrupts to occur more often, but reduce the possibility + * of losing data because of a FIFO overflow. Larger values + * will reduce the time required by the ISR, but increase the + * possibility of data loss. Passing an invalid value will + * cause the driver to use the value already set in the + * appropriate register. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart); + +/** + * @brief Set the transmit threshold level. + * + * @note TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart); + +/** + * @brief Gets the interrupt flags that are currently set + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The interrupt flags + */ +unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart); + +/** + * @brief Clears the interrupt flags that are currently set + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flags mask of flags to clear + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags); + +/** + * @brief Enables specific interrupts + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param mask The interrupts to be enabled + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask); + +/** + * @brief Disables specific interrupts + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param mask The interrupts to be disabled + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask); + +/** + * @brief Gets the status flags that are currently set + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The status flags + */ +unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart); + +int MXC_UART_Busy(mxc_uart_regs_t* uart); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking UART transaction. + * + * @note Performs a blocking UART transaction as follows. + * If tx_len is non-zero, transmit TX data + * Once tx_len has been sent, if rx_len is non-zero, receive data + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_Transaction (mxc_uart_req_t* req); + +/** + * @brief Setup an interrupt-driven UART transaction + * + * @note The TX FIFO will be filled with txData if necessary + * Relevant interrupts will be enabled + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_TransactionAsync (mxc_uart_req_t* req); + +/** + * @brief Setup a DMA driven UART transaction + * + * @note The TX FIFO will be filled with txData if necessary + * Relevant interrupts will be enabled. + * The DMA channel indicated by the request will be set up to load/unload the FIFOs + * with as few interrupt-based events as possible. The channel will be reset and + * returned to the system at the end of the transaction. + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_TransactionDMA (mxc_uart_req_t* req); + +/** + * @brief The processing function for DMA transactions. + * + * When using the DMA functions, the application must call this + * function periodically. This can be done from within the DMA Interrupt Handler. + * + * @param ch DMA channel + * @param error Error status + */ +void MXC_UART_DMACallback (int ch, int error); + +/** + * @brief Async callback + * + * @param uart The uart + * @param[in] retVal The ret value + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal); + +/** + * @brief stop any async callbacks + * + * @param uart The uart + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncStop (mxc_uart_regs_t* uart); + +/** + * @brief Abort any asynchronous requests in progress. + * + * @note Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AbortAsync (mxc_uart_regs_t* uart); + +/** + * @brief The processing function for asynchronous transactions. + * + * @note When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the UART interrupt + * handler or periodically by the application if UART interrupts are disabled. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart); + +/**@} end of group uart */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_UART_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h new file mode 100644 index 00000000000..fc66d6731ab --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/wdt.h @@ -0,0 +1,185 @@ +/** + * @file wdt.h + * @brief Watchdog timer (WDT) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _WDT_H_ +#define _WDT_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "wdt_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup wdt Watchdog Timer (WDT) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** @brief Watchdog period enumeration. + Used to configure the period of the watchdog interrupt */ +typedef enum { + MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, ///< Period 2^31 + MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, ///< Period 2^30 + MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, ///< Period 2^29 + MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, ///< Period 2^28 + MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, ///< Period 2^27 + MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, ///< Period 2^26 + MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, ///< Period 2^25 + MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, ///< Period 2^24 + MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, ///< Period 2^23 + MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, ///< Period 2^22 + MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, ///< Period 2^21 + MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, ///< Period 2^20 + MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, ///< Period 2^19 + MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, ///< Period 2^18 + MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, ///< Period 2^17 + MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, ///< Period 2^16 +} mxc_wdt_period_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the Watchdog Timer + * @param wdt Pointer to the watchdog registers + * @return See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_WDT_Init (mxc_wdt_regs_t* wdt); + +/** + * @brief Shutdown the Watchdog Timer + * @param wdt Pointer to the watchdog registers + * @return See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt); + +/** + * @brief Set the period of the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + * @param period Enumeration of the desired watchdog period. + */ +void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period); + +/** + * @brief Set the period of the watchdog reset. + * @param wdt Pointer to watchdog registers. + * @param period Enumeration of the desired watchdog period. + */ +void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period); + +/** + * @brief Enable the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_Enable (mxc_wdt_regs_t* wdt); + +/** + * @brief Disable the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_Disable (mxc_wdt_regs_t* wdt); + +/** + * @brief Enable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt); + +/** + * @brief Enable the watchdog reset. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt); + +/** + * @brief Enable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt); + +/** + * @brief Enable the watchdog reset. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt); + +/** + * @brief Reset the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt); + +/** + * @brief Get the status of the reset flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. + */ +int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt); + +/** + * @brief Clears the reset flag. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt); + +/** + * @brief Get the status of the interrupt flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the interrupt is pending, 0 otherwise. + */ +int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt); + +/** + * @brief Clears the interrupt flag. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt); + +/**@} end of group wdt */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_H_ */ \ No newline at end of file diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c new file mode 100644 index 00000000000..02bd982ffe8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_me11.c @@ -0,0 +1,171 @@ +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/****** Includes *******/ +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" +#include "dma_reva.h" +#include "dma_regs.h" + +/***** Definitions *****/ + +/******* Globals *******/ + +/****** Functions ******/ + +int MXC_DMA_Init(void) +{ + if(!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + } + + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t*) MXC_DMA); +} + +int MXC_DMA_AcquireChannel(void) +{ + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t*) MXC_DMA); +} + +int MXC_DMA_ReleaseChannel(int ch) +{ + return MXC_DMA_RevA_ReleaseChannel(ch); +} + +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_ConfigChannel(config, srcdst); +} + +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) +{ + return MXC_DMA_RevA_AdvConfigChannel(advConfig); +} + +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_SetSrcDst(srcdst); +} + +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst) +{ + return MXC_DMA_RevA_GetSrcDst(srcdst); +} + +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_SetSrcReload(srcdst); +} + +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst) +{ + return MXC_DMA_RevA_GetSrcReload(srcdst); +} + +int MXC_DMA_SetCallback(int ch, void(*callback)(int, int)) +{ + return MXC_DMA_RevA_SetCallback(ch, callback); +} + +int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) +{ + return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); +} + +int MXC_DMA_ChannelEnableInt(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelEnableInt(ch, flags); +} + +int MXC_DMA_ChannelDisableInt(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelDisableInt(ch, flags); +} + +int MXC_DMA_ChannelGetFlags(int ch) +{ + return MXC_DMA_RevA_ChannelGetFlags(ch); +} + +int MXC_DMA_ChannelClearFlags(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelClearFlags(ch, flags); +} + +int MXC_DMA_EnableInt(int ch) +{ + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); +} + +int MXC_DMA_DisableInt(int ch) +{ + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t*) MXC_DMA, ch); +} + +int MXC_DMA_Start(int ch) +{ + return MXC_DMA_RevA_Start(ch); +} + +int MXC_DMA_Stop(int ch) +{ + return MXC_DMA_RevA_Stop(ch); +} + +mxc_dma_ch_regs_t* MXC_DMA_GetCHRegs(int ch) +{ + return MXC_DMA_RevA_GetCHRegs(ch); +} + +void MXC_DMA_Handler(void) +{ + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t*) MXC_DMA); +} + +int MXC_DMA_MemCpy(void* dest, void* src, int len, mxc_dma_complete_cb_t callback) +{ + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t*) MXC_DMA, dest, src, len, callback); +} + +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) +{ + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t*) MXC_DMA, config, firstSrcDst, callback); +} + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c new file mode 100644 index 00000000000..724453c8a62 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -0,0 +1,585 @@ +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ +#ifdef __CC_ARM // Keil +#pragma diag_suppress 68 // integer conversion resulted in a change of sign +#endif + +/****** Includes *******/ +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" +#include "dma_reva.h" +#include "dma_reva_regs.h" + +/***** Definitions *****/ +#define CHECK_HANDLE(x)((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) + +typedef struct { + void* userCallback; // user given callback + void* dest; // memcpy destination +} mxc_dma_highlevel_t; + +typedef struct { + unsigned int valid; // Flag to invalidate this resource + unsigned int instance; // Hardware instance of this DMA controller + unsigned int id; // Channel ID, which matches the index into the underlying hardware + mxc_dma_reva_ch_regs_t *regs; // Pointer to the registers for this channel + void(*cb)(int, int); // Pointer to a callback function type +} mxc_dma_channel_t; + +/******* Globals *******/ +static unsigned int dma_initialized[MXC_DMA_INSTANCES] = {0}; +static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS]; +static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS]; + +#if USE_LOCK_IN_DRIVERS + static uint32_t dma_lock; +#endif + +/****** Functions ******/ +static void memcpy_callback(int ch, int error); +static void transfer_callback(int ch, int error); + +int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma) +{ + int i, numCh, offset; +#if TARGET_NUM == 32665 + numCh = MXC_DMA_CH_OFFSET; + offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); +#else + numCh = MXC_DMA_CHANNELS; + offset = 0; +#endif + + if(dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { + return E_BAD_STATE; + } + +#ifndef __riscv + /* Initialize mutex */ + MXC_FreeLock(&dma_lock); + + if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } +#endif + + /* Ensure all channels are disabled at start, clear flags, init handles */ + dma->inten = 0; + + for(i = offset; i < (offset + numCh); i++) { + dma_resource[i].valid = 0; + dma_resource[i].instance = 0; + dma_resource[i].id = i; + dma_resource[i].regs = (mxc_dma_reva_ch_regs_t*) &(dma->ch[(i % numCh)]); + dma_resource[i].regs->ctrl = 0; + dma_resource[i].regs->status = dma_resource[i].regs->status; + + dma_resource[i].cb = NULL; + } + + dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]++; +#ifndef __riscv + MXC_FreeLock(&dma_lock); +#endif + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma) +{ + int i, channel, numCh, offset; + + /* Check for initialization */ + if(!dma_initialized[MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma)]) { + return E_BAD_STATE; + } + +#if TARGET_NUM == 32665 + numCh = MXC_DMA_CH_OFFSET; + offset = MXC_DMA_CH_OFFSET * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); +#else + numCh = MXC_DMA_CHANNELS; + offset = 0; +#endif + +#ifndef __riscv + /* If DMA is locked return busy */ + if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } +#endif + /* Default is no channel available */ + channel = E_NONE_AVAIL; + + for(i = offset; i < (offset + numCh); i++) { + if(!dma_resource[i].valid) { + /* Found one */ + channel = i; + dma_resource[i].valid = 1; + dma_resource[i].regs->ctrl = 0; + dma_resource[i].regs->cntrld = 0; /* Used by DMA_Start() to conditionally set RLDEN */ + break; + } + } +#ifndef __riscv + MXC_FreeLock(&dma_lock); +#endif + + return channel; +} + +int MXC_DMA_RevA_ReleaseChannel(int ch) +{ + if(CHECK_HANDLE(ch)) { + if(MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + + dma_resource[ch].valid = 0; + dma_resource[ch].regs->ctrl = 0; + dma_resource[ch].regs->status = dma_resource[ch].regs->status; + MXC_FreeLock(&dma_lock); + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) +{ + if(CHECK_HANDLE(config.ch)) { + /* Designed to be safe, not speedy. Should not be called often */ + dma_resource[config.ch].regs->ctrl = + ((config.srcinc_en ? MXC_F_DMA_REVA_CTRL_SRCINC : 0) | + (config.dstinc_en ? MXC_F_DMA_REVA_CTRL_DSTINC : 0) | + config.reqsel | + (config.srcwd << MXC_F_DMA_REVA_CTRL_SRCWD_POS) | + (config.dstwd << MXC_F_DMA_REVA_CTRL_DSTWD_POS)); + } + else { + return E_BAD_PARAM; + } + + return MXC_DMA_RevA_SetSrcDst(srcdst); +} + + +int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) +{ + if(CHECK_HANDLE(advConfig.ch) &&(advConfig.burst_size > 0)) { + dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here + /* Designed to be safe, not speedy. Should not be called often */ + dma_resource[advConfig.ch].regs->ctrl |= + ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | + advConfig.prio | advConfig.tosel | advConfig.pssel | + (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & MXC_F_DMA_REVA_CTRL_BURST_SIZE)); + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + + +int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst) +{ + if(CHECK_HANDLE(srcdst.ch)) { + dma_resource[srcdst.ch].regs->src = (unsigned int) srcdst.source; + dma_resource[srcdst.ch].regs->dst = (unsigned int) srcdst.dest; + dma_resource[srcdst.ch].regs->cnt = srcdst.len; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + + +int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t* srcdst) +{ + if (CHECK_HANDLE(srcdst->ch)) { + srcdst->source = (void*) dma_resource[srcdst->ch].regs->src; + srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dst; + srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_REVA_CNTRLD_EN; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + + +int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst) +{ + if(CHECK_HANDLE(srcdst.ch)) { + dma_resource[srcdst.ch].regs->srcrld = (unsigned int) srcdst.source; + dma_resource[srcdst.ch].regs->dstrld = (unsigned int) srcdst.dest; + + if(dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_REVA_CTRL_EN) { + /* If channel is already running, set RLDEN to enable next reload */ + dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_REVA_CNTRLD_EN | srcdst.len; + } + else { + /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ + dma_resource[srcdst.ch].regs->cntrld = srcdst.len; + } + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + + +int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t* srcdst) +{ + if (CHECK_HANDLE(srcdst->ch)) { + srcdst->source = (void*) dma_resource[srcdst->ch].regs->srcrld; + srcdst->dest = (void*) dma_resource[srcdst->ch].regs->dstrld; + srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_REVA_CNTRLD_EN; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + + +int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)) +{ + if(CHECK_HANDLE(ch)) { + /* Callback for interrupt handler, no checking is done, as NULL is valid for(none) */ + dma_resource[ch].cb = callback; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) +{ + if(CHECK_HANDLE(ch)) { + if(chdis){ + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_DIS_IE); + } + if(ctz){ + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_CTZ_IE); + } + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + + +int MXC_DMA_RevA_GetChannelInterruptEn(int ch) +{ + return E_NOT_SUPPORTED; +} + +int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags) +{ + if(CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl |= (flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags) +{ + if(CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl &= ~(flags &(MXC_F_DMA_REVA_CTRL_DIS_IE|MXC_F_DMA_REVA_CTRL_CTZ_IE)); + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch) +{ + if(CHECK_HANDLE(ch)) { + #if TARGET_NUM == 32665 + ch %= MXC_DMA_CH_OFFSET; + #endif + dma->inten |= (1 << ch); + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch) +{ + if(CHECK_HANDLE(ch)) { + #if TARGET_NUM == 32665 + ch %= MXC_DMA_CH_OFFSET; + #endif + dma->inten &= ~(1 << ch); + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_ChannelGetFlags(int ch) +{ + if(CHECK_HANDLE(ch)) { + return dma_resource[ch].regs->status; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags) +{ + if(CHECK_HANDLE(ch)) { + dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_Start(int ch) +{ + if(CHECK_HANDLE(ch)) { + MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevA_ChannelGetFlags(ch)); + + if(dma_resource[ch].regs->cntrld) { + dma_resource[ch].regs->ctrl |= (MXC_F_DMA_REVA_CTRL_EN | MXC_F_DMA_REVA_CTRL_RLDEN); + } + else { + dma_resource[ch].regs->ctrl |= MXC_F_DMA_REVA_CTRL_EN; + } + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_DMA_RevA_Stop(int ch) +{ + if(CHECK_HANDLE(ch)) { + dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_REVA_CTRL_EN; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch) +{ + if(CHECK_HANDLE(ch)) { + return(mxc_dma_ch_regs_t*) dma_resource[ch].regs; + } + else { + return NULL; + } +} + +void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma) +{ + int numCh = MXC_DMA_CHANNELS / MXC_DMA_INSTANCES; + int offset = numCh * MXC_DMA_GET_IDX((mxc_dma_regs_t*) dma); + /* Do callback, if enabled */ + for(int i = offset; i < (offset + numCh); i++) { + if(CHECK_HANDLE(i)) { + if(dma->intfl &(0x1 << (i % numCh))) { + if(dma_resource[i].cb != NULL) { + dma_resource[i].cb(i, E_NO_ERROR); + } + + MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevA_ChannelGetFlags(i)); + break; + } + } + } +} + +void memcpy_callback(int ch, int error) +{ + mxc_dma_complete_cb_t callback; + callback = (mxc_dma_complete_cb_t) memcpy_resource[ch].userCallback; + + if(error != E_NO_ERROR) { + callback(NULL); + } + + callback(memcpy_resource[ch].dest); + + callback = NULL; + MXC_DMA_ReleaseChannel(ch); +} + +int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback) +{ + int retval; + mxc_dma_config_t config; + mxc_dma_srcdst_t transfer; + int channel; + + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + if(memcpy_resource[channel].userCallback != NULL) { + // We acquired a channel we haven't cleared yet + MXC_DMA_ReleaseChannel(channel); + return E_UNKNOWN; + } + + transfer.ch = channel; + transfer.source = src; + transfer.dest = dest; + transfer.len = len; + + config.ch = channel; + config.reqsel = MXC_DMA_REQUEST_MEMTOMEM; + config.srcwd = MXC_DMA_WIDTH_WORD; + config.dstwd = MXC_DMA_WIDTH_WORD; + config.srcinc_en = 1; + config.dstinc_en = 1; + + retval = MXC_DMA_ConfigChannel(config, transfer); + + if(retval != E_NO_ERROR) { + return retval; + } + + retval = MXC_DMA_EnableInt(channel); + + if(retval != E_NO_ERROR) { + return retval; + } + + retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); + + if(retval != E_NO_ERROR) { + return retval; + } + + MXC_DMA_SetCallback(channel, memcpy_callback); + + memcpy_resource[channel].userCallback = (void*) callback; + memcpy_resource[channel].dest = dest; + + return MXC_DMA_Start(channel); +} + +void transfer_callback(int ch, int error) +{ + // Unimplemented + // Check for reason + // Call user callback for next transfer + // determine whether to load into the transfer slot or reload slot + // continue on or stop + while(1); +} + +int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) +{ + int retval, channel; + + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t*) dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + if(memcpy_resource[channel].userCallback != NULL) { + // We acquired a channel we haven't cleared yet + MXC_DMA_ReleaseChannel(channel); + return E_UNKNOWN; + } + + retval = MXC_DMA_ConfigChannel(config, firstSrcDst); + + if(retval != E_NO_ERROR) { + return retval; + } + + retval = MXC_DMA_EnableInt(channel); + + if(retval != E_NO_ERROR) { + return retval; + } + + retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_REVA_CTRL_CTZ_IE); + + if(retval != E_NO_ERROR) { + return retval; + } + + MXC_DMA_SetCallback(channel, transfer_callback); + + memcpy_resource[channel].userCallback = (void*) callback; + + return MXC_DMA_Start(channel); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h new file mode 100644 index 00000000000..b6d4d401423 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva.h @@ -0,0 +1,65 @@ +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/****** Includes *******/ +#include "dma_reva_regs.h" +#include + +/***** Definitions *****/ + +/******* Globals *******/ + +/****** Functions ******/ +int MXC_DMA_RevA_Init(mxc_dma_reva_regs_t *dma); +int MXC_DMA_RevA_AcquireChannel(mxc_dma_reva_regs_t* dma); +int MXC_DMA_RevA_ReleaseChannel(int ch); +int MXC_DMA_RevA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); +int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); +int MXC_DMA_RevA_SetSrcDst(mxc_dma_srcdst_t srcdst); +int MXC_DMA_RevA_GetSrcDst(mxc_dma_srcdst_t *srcdst); +int MXC_DMA_RevA_SetSrcReload(mxc_dma_srcdst_t srcdst); +int MXC_DMA_RevA_GetSrcReload(mxc_dma_srcdst_t *srcdst); +int MXC_DMA_RevA_SetCallback(int ch, void(*callback)(int, int)); +int MXC_DMA_RevA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); +int MXC_DMA_RevA_ChannelEnableInt(int ch, int flags); +int MXC_DMA_RevA_ChannelDisableInt(int ch, int flags); +int MXC_DMA_RevA_ChannelGetFlags(int ch); +int MXC_DMA_RevA_ChannelClearFlags(int ch, int flags); +int MXC_DMA_RevA_EnableInt(mxc_dma_reva_regs_t *dma, int ch); +int MXC_DMA_RevA_DisableInt(mxc_dma_reva_regs_t *dma, int ch); +int MXC_DMA_RevA_Start(int ch); +int MXC_DMA_RevA_Stop(int ch); +mxc_dma_ch_regs_t* MXC_DMA_RevA_GetCHRegs(int ch); +void MXC_DMA_RevA_Handler(mxc_dma_reva_regs_t *dma); +int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t* dma, void* dest, void* src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t* dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h new file mode 100644 index 00000000000..96b9078731e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/DMA/dma_reva_regs.h @@ -0,0 +1,532 @@ +/** + * @file dma_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _DMA_REVA_REGS_H_ +#define _DMA_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dma + * @defgroup dma_registers DMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @details DMA Controller Fully programmable, chaining capable DMA channels. + */ + +/** + * @ingroup dma_registers + * Structure type to access the DMA Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x100: DMA CTRL Register */ + __IO uint32_t status; /**< \b 0x104: DMA STATUS Register */ + __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ + __IO uint32_t srcrld; /**< \b 0x114: DMA SRCRLD Register */ + __IO uint32_t dstrld; /**< \b 0x118: DMA DSTRLD Register */ + __IO uint32_t cntrld; /**< \b 0x11C: DMA CNTRLD Register */ +} mxc_dma_reva_ch_regs_t; + +typedef struct { + __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ + __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO mxc_dma_reva_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ +} mxc_dma_reva_regs_t; + +/* Register offsets for module DMA */ +/** + * @ingroup dma_registers + * @defgroup DMA_Register_Offsets Register Offsets + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @{ + */ + #define MXC_R_DMA_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ + #define MXC_R_DMA_REVA_STATUS ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ + #define MXC_R_DMA_REVA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ + #define MXC_R_DMA_REVA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ + #define MXC_R_DMA_REVA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ + #define MXC_R_DMA_REVA_SRCRLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ + #define MXC_R_DMA_REVA_DSTRLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ + #define MXC_R_DMA_REVA_CNTRLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ + #define MXC_R_DMA_REVA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ + #define MXC_R_DMA_REVA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ + #define MXC_R_DMA_REVA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +/**@} end of group dma_registers */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTEN DMA_INTEN + * @brief DMA Control Register. + * @{ + */ + #define MXC_F_DMA_REVA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ + #define MXC_F_DMA_REVA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ + #define MXC_F_DMA_REVA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ + #define MXC_F_DMA_REVA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ + #define MXC_F_DMA_REVA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH4_POS 4 /**< INTEN_CH4 Position */ + #define MXC_F_DMA_REVA_INTEN_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH4_POS)) /**< INTEN_CH4 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH5_POS 5 /**< INTEN_CH5 Position */ + #define MXC_F_DMA_REVA_INTEN_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH5_POS)) /**< INTEN_CH5 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH6_POS 6 /**< INTEN_CH6 Position */ + #define MXC_F_DMA_REVA_INTEN_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH6_POS)) /**< INTEN_CH6 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH7_POS 7 /**< INTEN_CH7 Position */ + #define MXC_F_DMA_REVA_INTEN_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH7_POS)) /**< INTEN_CH7 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH8_POS 8 /**< INTEN_CH8 Position */ + #define MXC_F_DMA_REVA_INTEN_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH8_POS)) /**< INTEN_CH8 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH9_POS 9 /**< INTEN_CH9 Position */ + #define MXC_F_DMA_REVA_INTEN_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH9_POS)) /**< INTEN_CH9 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH10_POS 10 /**< INTEN_CH10 Position */ + #define MXC_F_DMA_REVA_INTEN_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH10_POS)) /**< INTEN_CH10 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH11_POS 11 /**< INTEN_CH11 Position */ + #define MXC_F_DMA_REVA_INTEN_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH11_POS)) /**< INTEN_CH11 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH12_POS 12 /**< INTEN_CH12 Position */ + #define MXC_F_DMA_REVA_INTEN_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH12_POS)) /**< INTEN_CH12 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH13_POS 13 /**< INTEN_CH13 Position */ + #define MXC_F_DMA_REVA_INTEN_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH13_POS)) /**< INTEN_CH13 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH14_POS 14 /**< INTEN_CH14 Position */ + #define MXC_F_DMA_REVA_INTEN_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH14_POS)) /**< INTEN_CH14 Mask */ + + #define MXC_F_DMA_REVA_INTEN_CH15_POS 15 /**< INTEN_CH15 Position */ + #define MXC_F_DMA_REVA_INTEN_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTEN_CH15_POS)) /**< INTEN_CH15 Mask */ + +/**@} end of group DMA_INTEN_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTFL DMA_INTFL + * @brief DMA Interrupt Register. + * @{ + */ + #define MXC_F_DMA_REVA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ + #define MXC_F_DMA_REVA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ + #define MXC_F_DMA_REVA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ + #define MXC_F_DMA_REVA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ + #define MXC_F_DMA_REVA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH4_POS 4 /**< INTFL_CH4 Position */ + #define MXC_F_DMA_REVA_INTFL_CH4 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH4_POS)) /**< INTFL_CH4 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH5_POS 5 /**< INTFL_CH5 Position */ + #define MXC_F_DMA_REVA_INTFL_CH5 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH5_POS)) /**< INTFL_CH5 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH6_POS 6 /**< INTFL_CH6 Position */ + #define MXC_F_DMA_REVA_INTFL_CH6 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH6_POS)) /**< INTFL_CH6 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH7_POS 7 /**< INTFL_CH7 Position */ + #define MXC_F_DMA_REVA_INTFL_CH7 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH7_POS)) /**< INTFL_CH7 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH8_POS 8 /**< INTFL_CH8 Position */ + #define MXC_F_DMA_REVA_INTFL_CH8 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH8_POS)) /**< INTFL_CH8 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH9_POS 9 /**< INTFL_CH9 Position */ + #define MXC_F_DMA_REVA_INTFL_CH9 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH9_POS)) /**< INTFL_CH9 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH10_POS 10 /**< INTFL_CH10 Position */ + #define MXC_F_DMA_REVA_INTFL_CH10 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH10_POS)) /**< INTFL_CH10 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH11_POS 11 /**< INTFL_CH11 Position */ + #define MXC_F_DMA_REVA_INTFL_CH11 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH11_POS)) /**< INTFL_CH11 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH12_POS 12 /**< INTFL_CH12 Position */ + #define MXC_F_DMA_REVA_INTFL_CH12 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH12_POS)) /**< INTFL_CH12 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH13_POS 13 /**< INTFL_CH13 Position */ + #define MXC_F_DMA_REVA_INTFL_CH13 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH13_POS)) /**< INTFL_CH13 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH14_POS 14 /**< INTFL_CH14 Position */ + #define MXC_F_DMA_REVA_INTFL_CH14 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH14_POS)) /**< INTFL_CH14 Mask */ + + #define MXC_F_DMA_REVA_INTFL_CH15_POS 15 /**< INTFL_CH15 Position */ + #define MXC_F_DMA_REVA_INTFL_CH15 ((uint32_t)(0x1UL << MXC_F_DMA_REVA_INTFL_CH15_POS)) /**< INTFL_CH15 Mask */ + +/**@} end of group DMA_INTFL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CTRL DMA_CTRL + * @brief DMA Channel Control Register. + * @{ + */ + #define MXC_F_DMA_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ + #define MXC_F_DMA_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + + #define MXC_F_DMA_REVA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ + #define MXC_F_DMA_REVA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ + + #define MXC_F_DMA_REVA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ + #define MXC_F_DMA_REVA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ + #define MXC_V_DMA_REVA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ + #define MXC_S_DMA_REVA_CTRL_PRI_HIGH (MXC_V_DMA_REVA_CTRL_PRI_HIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ + #define MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ + #define MXC_S_DMA_REVA_CTRL_PRI_MEDHIGH (MXC_V_DMA_REVA_CTRL_PRI_MEDHIGH << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ + #define MXC_V_DMA_REVA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ + #define MXC_S_DMA_REVA_CTRL_PRI_MEDLOW (MXC_V_DMA_REVA_CTRL_PRI_MEDLOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ + #define MXC_V_DMA_REVA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ + #define MXC_S_DMA_REVA_CTRL_PRI_LOW (MXC_V_DMA_REVA_CTRL_PRI_LOW << MXC_F_DMA_REVA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ + + #define MXC_F_DMA_REVA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ + #define MXC_F_DMA_REVA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_REVA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_REVA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX ((uint32_t)0x3UL) /**< CTRL_REQUEST_SPI2RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_UART0RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_UART1RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_ADC (MXC_V_DMA_REVA_CTRL_REQUEST_ADC << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_UART2RX (MXC_V_DMA_REVA_CTRL_REQUEST_UART2RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI3RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX ((uint32_t)0x10UL) /**< CTRL_REQUEST_SPI_MSS0RX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0RX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0RX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 ((uint32_t)0x11UL) /**< CTRL_REQUEST_USBRXEP1 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP1 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP1 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 ((uint32_t)0x12UL) /**< CTRL_REQUEST_USBRXEP2 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP2 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP2 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 ((uint32_t)0x13UL) /**< CTRL_REQUEST_USBRXEP3 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP3 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP3 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 ((uint32_t)0x14UL) /**< CTRL_REQUEST_USBRXEP4 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP4 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP4 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 ((uint32_t)0x15UL) /**< CTRL_REQUEST_USBRXEP5 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP5 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP5 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 ((uint32_t)0x16UL) /**< CTRL_REQUEST_USBRXEP6 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP6 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP6 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 ((uint32_t)0x17UL) /**< CTRL_REQUEST_USBRXEP7 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP7 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP7 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 ((uint32_t)0x18UL) /**< CTRL_REQUEST_USBRXEP8 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP8 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP8 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 ((uint32_t)0x19UL) /**< CTRL_REQUEST_USBRXEP9 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP9 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP9 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 ((uint32_t)0x1AUL) /**< CTRL_REQUEST_USBRXEP10 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP10 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP10 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 ((uint32_t)0x1BUL) /**< CTRL_REQUEST_USBRXEP11 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBRXEP11 (MXC_V_DMA_REVA_CTRL_REQUEST_USBRXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBRXEP11 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX ((uint32_t)0x23UL) /**< CTRL_REQUEST_SPI2TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI2TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI2TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_UART0TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_UART1TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_REVA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_UART2TX (MXC_V_DMA_REVA_CTRL_REQUEST_UART2TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI3TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI3TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI3TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI3TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX ((uint32_t)0x30UL) /**< CTRL_REQUEST_SPI_MSS0TX Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX (MXC_V_DMA_REVA_CTRL_REQUEST_SPI_MSS0TX << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI_MSS0TX Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 ((uint32_t)0x31UL) /**< CTRL_REQUEST_USBTXEP1 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP1 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP1 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP1 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 ((uint32_t)0x32UL) /**< CTRL_REQUEST_USBTXEP2 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP2 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP2 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP2 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 ((uint32_t)0x33UL) /**< CTRL_REQUEST_USBTXEP3 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP3 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP3 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP3 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 ((uint32_t)0x34UL) /**< CTRL_REQUEST_USBTXEP4 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP4 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP4 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP4 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 ((uint32_t)0x35UL) /**< CTRL_REQUEST_USBTXEP5 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP5 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP5 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP5 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 ((uint32_t)0x36UL) /**< CTRL_REQUEST_USBTXEP6 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP6 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP6 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP6 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 ((uint32_t)0x37UL) /**< CTRL_REQUEST_USBTXEP7 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP7 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP7 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP7 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 ((uint32_t)0x38UL) /**< CTRL_REQUEST_USBTXEP8 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP8 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP8 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP8 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 ((uint32_t)0x39UL) /**< CTRL_REQUEST_USBTXEP9 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP9 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP9 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP9 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 ((uint32_t)0x3AUL) /**< CTRL_REQUEST_USBTXEP10 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP10 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP10 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP10 Setting */ + #define MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 ((uint32_t)0x3BUL) /**< CTRL_REQUEST_USBTXEP11 Value */ + #define MXC_S_DMA_REVA_CTRL_REQUEST_USBTXEP11 (MXC_V_DMA_REVA_CTRL_REQUEST_USBTXEP11 << MXC_F_DMA_REVA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_USBTXEP11 Setting */ + + #define MXC_F_DMA_REVA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ + #define MXC_F_DMA_REVA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ + + #define MXC_F_DMA_REVA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ + #define MXC_F_DMA_REVA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_REVA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO4 (MXC_V_DMA_REVA_CTRL_TO_PER_TO4 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO8 (MXC_V_DMA_REVA_CTRL_TO_PER_TO8 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO16 (MXC_V_DMA_REVA_CTRL_TO_PER_TO16 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO32 (MXC_V_DMA_REVA_CTRL_TO_PER_TO32 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO64 (MXC_V_DMA_REVA_CTRL_TO_PER_TO64 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO128 (MXC_V_DMA_REVA_CTRL_TO_PER_TO128 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO256 (MXC_V_DMA_REVA_CTRL_TO_PER_TO256 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_PER_TO512 (MXC_V_DMA_REVA_CTRL_TO_PER_TO512 << MXC_F_DMA_REVA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ + + #define MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ + #define MXC_F_DMA_REVA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ + #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ + #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ + #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ + #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ + #define MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ + #define MXC_S_DMA_REVA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_REVA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_REVA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ + + #define MXC_F_DMA_REVA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ + #define MXC_F_DMA_REVA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ + #define MXC_V_DMA_REVA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ + #define MXC_S_DMA_REVA_CTRL_SRCWD_BYTE (MXC_V_DMA_REVA_CTRL_SRCWD_BYTE << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ + #define MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ + #define MXC_S_DMA_REVA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_REVA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ + #define MXC_V_DMA_REVA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ + #define MXC_S_DMA_REVA_CTRL_SRCWD_WORD (MXC_V_DMA_REVA_CTRL_SRCWD_WORD << MXC_F_DMA_REVA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ + + #define MXC_F_DMA_REVA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ + #define MXC_F_DMA_REVA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ + + #define MXC_F_DMA_REVA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ + #define MXC_F_DMA_REVA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_REVA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ + #define MXC_V_DMA_REVA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ + #define MXC_S_DMA_REVA_CTRL_DSTWD_BYTE (MXC_V_DMA_REVA_CTRL_DSTWD_BYTE << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ + #define MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ + #define MXC_S_DMA_REVA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_REVA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ + #define MXC_V_DMA_REVA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ + #define MXC_S_DMA_REVA_CTRL_DSTWD_WORD (MXC_V_DMA_REVA_CTRL_DSTWD_WORD << MXC_F_DMA_REVA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ + + #define MXC_F_DMA_REVA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ + #define MXC_F_DMA_REVA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ + + #define MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ + #define MXC_F_DMA_REVA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ + + #define MXC_F_DMA_REVA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ + #define MXC_F_DMA_REVA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ + + #define MXC_F_DMA_REVA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ + #define MXC_F_DMA_REVA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ + +/**@} end of group DMA_CTRL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_STATUS DMA_STATUS + * @brief DMA Channel Status Register. + * @{ + */ + #define MXC_F_DMA_REVA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ + #define MXC_F_DMA_REVA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ + + #define MXC_F_DMA_REVA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ + #define MXC_F_DMA_REVA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ + + #define MXC_F_DMA_REVA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ + #define MXC_F_DMA_REVA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ + + #define MXC_F_DMA_REVA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ + #define MXC_F_DMA_REVA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ + + #define MXC_F_DMA_REVA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ + #define MXC_F_DMA_REVA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ + + #define MXC_F_DMA_REVA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ + #define MXC_F_DMA_REVA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_REVA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ + +/**@} end of group DMA_STATUS_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC DMA_SRC + * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or + * 4, depending on the data width of each AHB cycle. For peripheral transfers, some + * or all of the actual address bits are fixed. If SRCINC=0, this register remains + * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the + * register is reloaded with the contents of DMA_SRC_RLD. + * @{ + */ + #define MXC_F_DMA_REVA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ + #define MXC_F_DMA_REVA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST DMA_DST + * @brief Destination Device Address. For peripheral transfers, some or all of the actual + * address bits are fixed. If DSTINC=1, this register is incremented on every AHB + * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the + * data width of each AHB cycle. In the case where a count-to-zero condition occurs + * while RLDEN=1, the register is reloaded with DMA_DST_RLD. + * @{ + */ + #define MXC_F_DMA_REVA_DST_ADDR_POS 0 /**< DST_ADDR Position */ + #define MXC_F_DMA_REVA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_REVA_DST_ADDR_POS)) /**< DST_ADDR Mask */ + +/**@} end of group DMA_DST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT DMA_CNT + * @brief DMA Counter. The user loads this register with the number of bytes to transfer. + * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will + * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter + * reaches 0, a count-to-zero condition is triggered. + * @{ + */ + #define MXC_F_DMA_REVA_CNT_CNT_POS 0 /**< CNT_CNT Position */ + #define MXC_F_DMA_REVA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNT_CNT_POS)) /**< CNT_CNT Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRCRLD DMA_SRCRLD + * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC + * upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_REVA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ + #define MXC_F_DMA_REVA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ + +/**@} end of group DMA_SRCRLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DSTRLD DMA_DSTRLD + * @brief Destination Address Reload Value. The value of this register is loaded into + * DMA0_DST upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_REVA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ + #define MXC_F_DMA_REVA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_REVA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ + +/**@} end of group DMA_DSTRLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNTRLD DMA_CNTRLD + * @brief DMA Channel Count Reload Register. + * @{ + */ + #define MXC_F_DMA_REVA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ + #define MXC_F_DMA_REVA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_REVA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ + + #define MXC_F_DMA_REVA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ + #define MXC_F_DMA_REVA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_REVA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ + +/**@} end of group DMA_CNTRLD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _DMA_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c new file mode 100644 index 00000000000..5a38e3faf8d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.c @@ -0,0 +1,170 @@ +/** + * @file flc.h + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc.h" +#include "stdlib.h" + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// Length is number of 32-bit words +int MXC_FLC_Com_VerifyData(uint32_t address, uint32_t length, uint32_t* data) +{ + volatile uint32_t* ptr; + + + for (ptr = (uint32_t*) address; ptr < (((uint32_t*)(address)) + length); ptr++, data++) { + if (*ptr != *data) { + return E_BAD_STATE; + } + } + + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_Com_Write(uint32_t address, uint32_t length, uint32_t* buffer) +{ + int err; + uint32_t bytes_written; + + uint32_t current_data_32; + uint8_t* current_data = (uint8_t*) ¤t_data_32; + uint8_t* buffer8 = (uint8_t*)buffer; + + // Align the address to a word boundary and read/write if we have to + if (address & 0x3) { + + // Figure out how many bytes we have to write to round up the address + bytes_written = 4 - (address & 0x3); + + // Save the data currently in the flash + memcpy(current_data, (void*)(address & (~0x3)), 4); + + // Modify current_data to insert the data from buffer + memcpy(¤t_data[4 - bytes_written], buffer8, bytes_written); + + // Write the modified data + if ((err = MXC_FLC_Write32(address - (address % 4), current_data_32)) != E_NO_ERROR) { + return err; + } + + address += bytes_written; + length -= bytes_written; + buffer8 += bytes_written; + } + + // Align the address to a 4-word (128bit) boundary + while ((length >= 4) && ((address & 0xF) != 0)) { + memcpy(current_data, buffer8, 4); + if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { + return err; + } + + address += 4; + length -= 4; + buffer8 += 4; + } + + if (length >= 16) { + uint32_t buff128[4]; + while (length >= 16) { + memcpy(buff128, buffer8, 16); + if ((err = MXC_FLC_Write128(address, buff128)) != E_NO_ERROR) { + return err; + } + + address += 16; + length -= 16; + buffer8 += 16; + } + + } + + while (length >= 4) { + memcpy(current_data, buffer8, 4); + if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { + return err; + } + + address += 4; + length -= 4; + buffer8 += 4; + } + + if (length > 0) { + // Save the data currently in the flash + memcpy(current_data, (void*)(address), 4); + + // Modify current_data to insert the data from buffer + memcpy(current_data, buffer8, length); + + if ((err = MXC_FLC_Write32(address, current_data_32)) != E_NO_ERROR) { + return err; + } + } + + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +void MXC_FLC_Com_Read(int address, void* buffer, int len) +{ + memcpy(buffer, (void*) address, len); +} + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h new file mode 100644 index 00000000000..b612393416d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_common.h @@ -0,0 +1,72 @@ +/** + * @file flc.h + * @brief Flash Controller driver. + * @details This driver can be used to operate on the embedded flash memory. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + + +/* **** Includes **** */ +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup flc Flash Controller (FLC) + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + + + +/***** Function Prototypes *****/ + +int MXC_FLC_Com_VerifyData (uint32_t address, uint32_t length, uint32_t * data); + +int MXC_FLC_Com_Write (uint32_t address, uint32_t length, uint32_t *buffer); + +void MXC_FLC_Com_Read (int address, void* buffer, int len); + +/**@} end of group flc */ + + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c new file mode 100644 index 00000000000..7891e950e98 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_me11.c @@ -0,0 +1,305 @@ +/** + * @file flc.h + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc.h" +#include "flc_reva.h" +#include "flc_common.h" + +//****************************************************************************** +void MXC_FLC_ME11_Flash_Operation(void) +{ + /* Flush all instruction caches */ + MXC_GCR->scon |= MXC_F_GCR_SCON_ICC0_FLUSH; + + /* Wait for flush to complete */ + while(MXC_GCR->scon & MXC_F_GCR_SCON_ICC0_FLUSH) { + } +} + +//****************************************************************************** +int MXC_FLC_ME11_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) +{ + + // flash base start from 0x00000000 + if ( addr < MXC_FLASH_MEM_SIZE ) { + *flc = MXC_FLC; + } + else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *flc = MXC_FLC; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_ME11_GetPhysicalAddress(uint32_t addr, uint32_t *result) +{ + // flash base start from 0x00000000 + if ( addr < MXC_FLASH_MEM_SIZE ) { + *result = addr & (MXC_FLASH_MEM_SIZE-1); + } + else if((addr >= MXC_INFO_MEM_BASE) && (addr <(MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *result = (addr & (MXC_INFO_MEM_SIZE-1)) + MXC_FLASH_MEM_SIZE; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** + +int MXC_FLC_Init() +{ + return E_NO_ERROR; +} + +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_Busy(void) +{ + return MXC_FLC_RevA_Busy(); +} + +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_ME11_PageErase(uint32_t address) +{ + int err; + uint32_t addr; + mxc_flc_regs_t *flc = NULL; + + // Get FLC Instance + if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t*) flc, addr); + // Flush the cache + MXC_FLC_ME11_Flash_Operation(); + + return err; +} + +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_ME11_Write128(uint32_t address, uint32_t *data) +{ + int err; + mxc_flc_regs_t *flc = NULL; + uint32_t addr; + + // Address checked if it is 128-bit aligned + if(address & 0xF) { + return E_BAD_PARAM; + } + + // Get FLC Instance + if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if((err = MXC_FLC_ME11_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + if((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t*) flc, addr, data)) != E_NO_ERROR) { + return err; + } + + // Flush the cache + MXC_FLC_ME11_Flash_Operation(); + + if((err= MXC_FLC_Com_VerifyData(address, 4, data)) !=E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_ME11_Write32(uint32_t address, uint32_t data) +{ + uint32_t addr, aligned; + int err; + mxc_flc_regs_t *flc = NULL; + + // Address checked if it is byte addressable + if(address & 0x3) { + return E_BAD_PARAM; + } + + // Align address to 128-bit word + aligned = address & 0xfffffff0; + + // Get FLC Instance + if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if((err = MXC_FLC_ME11_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_Write32((mxc_flc_reva_regs_t*) flc, address, data, addr); + +} + +int MXC_FLC_ME11_MassErase(void) +{ + int err; + mxc_flc_regs_t *flc; + + flc = MXC_FLC; + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t*) flc); + + if(err != E_NO_ERROR) { + return err; + } + + MXC_FLC_ME11_Flash_Operation(); + + return E_NO_ERROR; + + +} +int MXC_FLC_ME11_UnlockInfoBlock(uint32_t address) +{ + int err; + mxc_flc_regs_t *flc; + + if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t*) flc, address); +} +int MXC_FLC_ME11_LockInfoBlock(uint32_t address) +{ + int err; + mxc_flc_regs_t *flc; + + if((err = MXC_FLC_ME11_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t*) flc, address); +} +/* ****************************************************************************** */ +int MXC_FLC_MassErase(void) +{ + return MXC_FLC_ME11_MassErase(); +} + +int MXC_FLC_PageErase(uint32_t address) +{ + return MXC_FLC_ME11_PageErase(address); +} + +int MXC_FLC_Write32(uint32_t address, uint32_t data) +{ + return MXC_FLC_ME11_Write32(address, data); +} + +int MXC_FLC_Write128(uint32_t address, uint32_t *data) +{ + return MXC_FLC_ME11_Write128(address, data); +} + +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer) +{ + return MXC_FLC_Com_Write(address, length, buffer); +} +void MXC_FLC_Read(int address, void* buffer, int len) +{ + MXC_FLC_Com_Read(address, buffer, len); +} + +int MXC_FLC_EnableInt(uint32_t flags) +{ + return MXC_FLC_RevA_EnableInt(flags); +} + +int MXC_FLC_DisableInt(uint32_t flags) +{ + return MXC_FLC_RevA_DisableInt(flags); +} + +int MXC_FLC_GetFlags(void) +{ + return MXC_FLC_RevA_GetFlags(); +} + +int MXC_FLC_ClearFlags(uint32_t flags) +{ + return MXC_FLC_RevA_ClearFlags(flags); +} + +int MXC_FLC_UnlockInfoBlock(uint32_t address) +{ + return MXC_FLC_ME11_UnlockInfoBlock(address); +} + +int MXC_FLC_LockInfoBlock(uint32_t address) +{ + return MXC_FLC_ME11_LockInfoBlock(address); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c new file mode 100644 index 00000000000..4e380c62ee4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.c @@ -0,0 +1,378 @@ +/** + * @file flc.h + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc_reva.h" +#include "flc.h" + +/** + * @ingroup flc + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +static int MXC_busy_flc(mxc_flc_reva_regs_t* flc) +{ + return (flc->ctrl & (MXC_F_FLC_REVA_CTRL_WR | MXC_F_FLC_REVA_CTRL_ME | MXC_F_FLC_REVA_CTRL_PGE)); +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +static int MXC_prepare_flc(mxc_flc_reva_regs_t* flc) +{ + /* Check if the flash controller is busy */ + if (MXC_busy_flc(flc)) { + return E_BUSY; + } + + // Set flash clock divider to generate a 1MHz clock from the APB clock + flc->clkdiv = SystemCoreClock / 1000000; + + /* Clear stale errors */ + if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { + flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; + } + + /* Unlock flash */ + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_UNLOCK) | MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED; + + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_RevA_Busy(void) +{ + uint32_t flc_cn = 0; + int i; + mxc_flc_reva_regs_t *flc; + + for (i = 0; i < MXC_FLC_INSTANCES; i++) { + flc = (mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC (i); + flc_cn = MXC_busy_flc (flc); + + if (flc_cn != 0) { + break; + } + } + + return flc_cn; +} +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc) +{ + int err; + + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { + return err; + } + + /* Write mass erase code */ + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL; + + /* Issue mass erase command */ + flc->ctrl |= MXC_F_FLC_REVA_CTRL_ME; + + /* Wait until flash operation is complete */ + while (MXC_busy_flc(flc)); + + /* Lock flash */ + flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; + + /* Check access violations */ + if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { + flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; + return E_BAD_STATE; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc, uint32_t addr) +{ + int err; + + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { + return err; + } + + /* Write page erase code */ + flc->ctrl = (flc->ctrl & ~MXC_F_FLC_REVA_CTRL_ERASE_CODE) | MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE; + /* Issue page erase command */ + flc->addr = addr; + flc->ctrl |= MXC_F_FLC_REVA_CTRL_PGE; + + /* Wait until flash operation is complete */ + while (MXC_FLC_Busy()); + + /* Lock flash */ + flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; + + /* Check access violations */ + if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { + flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; + return E_BAD_STATE; + } + + return E_NO_ERROR; +} + + + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t* flc, uint32_t logicAddr, uint32_t data, uint32_t physicalAddr) +{ + int err, i = 0; + uint32_t byte; + volatile uint32_t* ptr; + uint32_t current_data[4] = {0, 0, 0, 0}; + + // Address checked if it is byte addressable + if (logicAddr & 0x3) { + return E_BAD_PARAM; + } + + // Check if the location trying to be written has 1's in to be written to 0's + if ((* (uint32_t*) logicAddr & data) != data) { + return E_BAD_STATE; + } + + // Get byte idx within 128-bit word + byte = (logicAddr & 0xf); + // Align address to 128-bit word + logicAddr = logicAddr & 0xfffffff0; + + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { + return err; + } + + // Get current data stored in flash + for (ptr = (uint32_t*) logicAddr; ptr < (uint32_t*)(logicAddr + 16); ptr++, i++) { + current_data[i] = *ptr; + } + + // write the data + flc->addr = physicalAddr; + + if (byte < 4) { + current_data[0] = data; + } + else if (byte < 8) { + current_data[1] = data; + } + else if (byte < 12) { + current_data[2] = data; + } + else { + current_data[3] = data; + } + + return MXC_FLC_Write128(logicAddr, current_data); +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section=".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data) +{ + int err; + + // Address checked if it is 128-bit aligned + if (addr & 0xF) { + return E_BAD_PARAM; + } + + if ((err = MXC_prepare_flc(flc)) != E_NO_ERROR) { + return err; + } + + // write 128-bits + flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_WDTH; + + // write the data + flc->addr = addr; + flc->data[0] = data[0]; + flc->data[1] = data[1]; + flc->data[2] = data[2]; + flc->data[3] = data[3]; + flc->ctrl |= MXC_F_FLC_REVA_CTRL_WR; + + /* Wait until flash operation is complete */ + while ((flc->ctrl & MXC_F_FLC_REVA_CTRL_PEND)!=0){} + while (MXC_busy_flc (flc)){} + + /* Lock flash */ + flc->ctrl &= ~MXC_F_FLC_REVA_CTRL_UNLOCK; + + /* Check access violations */ + if (flc->intr & MXC_F_FLC_REVA_INTR_AF) { + flc->intr &= ~MXC_F_FLC_REVA_INTR_AF; + return E_BAD_STATE; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_EnableInt(uint32_t mask) +{ + mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); + + if (!mask) { + /* No bits set? Wasn't something we can enable. */ + return E_BAD_PARAM; + } + + /* Apply enables and write back, preserving the flags */ + ((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr |= mask; + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_DisableInt(uint32_t mask) +{ + mask &= (MXC_F_FLC_REVA_INTR_DONEIE | MXC_F_FLC_REVA_INTR_AFIE); + + if (!mask) { + /* No bits set? Wasn't something we can disable. */ + return E_BAD_PARAM; + } + + /* Apply disables and write back, preserving the flags */ + ((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr &= ~mask; + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_GetFlags(void) +{ + return (((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr & (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF)); +} + +//****************************************************************************** +int MXC_FLC_RevA_ClearFlags(uint32_t mask) +{ + mask &= (MXC_F_FLC_REVA_INTR_DONE | MXC_F_FLC_REVA_INTR_AF); + + if (!mask) { + /* No bits set? Wasn't something we can clear. */ + return E_BAD_PARAM; + } + + /* Both flags are write zero clear */ + ((mxc_flc_reva_regs_t*) MXC_FLC_GET_FLC(0))->intr ^= mask; + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) +{ + if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { + return E_BAD_PARAM; + } + + /* Make sure the info block is locked */ + flc->actrl = 0x1234; + + /* Write the unlock sequence */ + flc->actrl = 0x3a7f5ca3; + flc->actrl = 0xa1e34f20; + flc->actrl = 0x9608b2c1; + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address) +{ + if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { + return E_BAD_PARAM; + } + + flc->actrl = 0xDEADBEEF; + return E_NO_ERROR; +} +/**@} end of group flc */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h new file mode 100644 index 00000000000..80c7083a65a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva.h @@ -0,0 +1,85 @@ +/** + * @file flc.h + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc.h" +#include "flc_reva_regs.h" + +/** + * @ingroup flc + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +int MXC_FLC_RevA_Busy (void); + +int MXC_FLC_RevA_MassErase (mxc_flc_reva_regs_t *flc); + +int MXC_FLC_RevA_PageErase (mxc_flc_reva_regs_t *flc,uint32_t addr); + +int MXC_FLC_RevA_Write32 (mxc_flc_reva_regs_t *flc, uint32_t locgialAddr, uint32_t data, uint32_t physicalAddr); + +int MXC_FLC_RevA_Write128 (mxc_flc_reva_regs_t *flc, uint32_t addr, uint32_t *data); + +int MXC_FLC_RevA_EnableInt (uint32_t mask); + +int MXC_FLC_RevA_DisableInt (uint32_t mask); + +int MXC_FLC_RevA_GetFlags (void); + +int MXC_FLC_RevA_ClearFlags (uint32_t mask); + +int MXC_FLC_RevA_UnlockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); + +int MXC_FLC_RevA_LockInfoBlock (mxc_flc_reva_regs_t *flc, uint32_t address); +/**@} end of group flc */ + + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h new file mode 100644 index 00000000000..7a3fc60ea7a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/FLC/flc_reva_regs.h @@ -0,0 +1,246 @@ +/** + * @file flc_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _FLC_REVA_REGS_H_ +#define _FLC_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc_reva + * @defgroup flc_reva_registers FLC_REVA_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC_REVA Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_reva_registers + * Structure type to access the FLC_REVA Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC_REVA ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC_REVA CLKDIV Register */ + __IO uint32_t ctrl; /**< \b 0x08: FLC_REVA CTRL Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC_REVA INTR Register */ + __IO uint32_t eccdata; /**< \b 0x028: FLC_REVA ECCDATA Register */ + __R uint32_t rsv_0x2c; + __IO uint32_t data[4]; /**< \b 0x30: FLC_REVA DATA Register */ + __O uint32_t actrl; /**< \b 0x40: FLC_REVA ACTRL Register */ +} mxc_flc_reva_regs_t; + +/* Register offsets for module FLC_REVA */ +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_Register_Offsets Register Offsets + * @brief FLC_REVA Peripheral Register Offsets from the FLC_REVA Base Peripheral Address. + * @{ + */ + #define MXC_R_FLC_REVA_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC_REVA Base Address: 0x0000 */ + #define MXC_R_FLC_REVA_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC_REVA Base Address: 0x0004 */ + #define MXC_R_FLC_REVA_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC_REVA Base Address: 0x0008 */ + #define MXC_R_FLC_REVA_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC_REVA Base Address: 0x0024 */ + #define MXC_R_FLC_REVA_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC_REVA Base Address: 0x0028 */ + #define MXC_R_FLC_REVA_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC_REVA Base Address: 0x0030 */ + #define MXC_R_FLC_REVA_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC_REVA Base Address: 0x0040 */ +/**@} end of group flc_reva_registers */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_ADDR FLC_REVA_ADDR + * @brief Flash Write Address. + * @{ + */ + #define MXC_F_FLC_REVA_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ + #define MXC_F_FLC_REVA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_REVA_ADDR_Register */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_CLKDIV FLC_REVA_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ + #define MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ + #define MXC_F_FLC_REVA_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_REVA_CLKDIV_Register */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_CTRL FLC_REVA_CTRL + * @brief Flash Control Register. + * @{ + */ + #define MXC_F_FLC_REVA_CTRL_WR_POS 0 /**< CTRL_WR Position */ + #define MXC_F_FLC_REVA_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WR_POS)) /**< CTRL_WR Mask */ + + #define MXC_F_FLC_REVA_CTRL_ME_POS 1 /**< CTRL_ME Position */ + #define MXC_F_FLC_REVA_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_ME_POS)) /**< CTRL_ME Mask */ + + #define MXC_F_FLC_REVA_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ + #define MXC_F_FLC_REVA_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ + + #define MXC_F_FLC_REVA_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ + #define MXC_F_FLC_REVA_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ + + #define MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ + #define MXC_F_FLC_REVA_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ + #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ + #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_NOP (MXC_V_FLC_REVA_CTRL_ERASE_CODE_NOP << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ + #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ + #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ + #define MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ + #define MXC_S_FLC_REVA_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_REVA_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_REVA_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ + + #define MXC_F_FLC_REVA_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ + #define MXC_F_FLC_REVA_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ + + #define MXC_F_FLC_REVA_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ + #define MXC_F_FLC_REVA_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ + + #define MXC_F_FLC_REVA_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ + #define MXC_F_FLC_REVA_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_REVA_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ + #define MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ + #define MXC_S_FLC_REVA_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ + #define MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ + #define MXC_S_FLC_REVA_CTRL_UNLOCK_LOCKED (MXC_V_FLC_REVA_CTRL_UNLOCK_LOCKED << MXC_F_FLC_REVA_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ + +/**@} end of group FLC_REVA_CTRL_Register */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_INTR FLC_REVA_INTR + * @brief Flash Interrupt Register. + * @{ + */ + #define MXC_F_FLC_REVA_INTR_DONE_POS 0 /**< INTR_DONE Position */ + #define MXC_F_FLC_REVA_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONE_POS)) /**< INTR_DONE Mask */ + + #define MXC_F_FLC_REVA_INTR_AF_POS 1 /**< INTR_AF Position */ + #define MXC_F_FLC_REVA_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AF_POS)) /**< INTR_AF Mask */ + + #define MXC_F_FLC_REVA_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ + #define MXC_F_FLC_REVA_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ + + #define MXC_F_FLC_REVA_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ + #define MXC_F_FLC_REVA_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_REVA_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ + +/**@} end of group FLC_REVA_INTR_Register */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_ECCDATA FLC_REVA_ECCDATA + * @brief ECC Data Register. + * @{ + */ + #define MXC_F_FLC_REVA_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ + #define MXC_F_FLC_REVA_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ + + #define MXC_F_FLC_REVA_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ + #define MXC_F_FLC_REVA_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_REVA_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ + +/**@} end of group FLC_REVA_ECCDATA_Register */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_DATA FLC_REVA_DATA + * @brief Flash Write Data. + * @{ + */ + #define MXC_F_FLC_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ + #define MXC_F_FLC_REVA_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_REVA_DATA_Register */ + +/** + * @ingroup flc_reva_registers + * @defgroup FLC_REVA_ACTRL FLC_REVA_ACTRL + * @brief Access Control Register. Writing the ACTRL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = + * 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of + * any word will disable access to system and user information block. Readback of + * this register is always zero. + * @{ + */ + #define MXC_F_FLC_REVA_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ + #define MXC_F_FLC_REVA_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_REVA_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ + +/**@} end of group FLC_REVA_ACTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c new file mode 100644 index 00000000000..a2bd8b5da61 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c @@ -0,0 +1,107 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_assert.h" +#include "gpio.h" +#include + +/* **** Globals **** */ +static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void*); +static void* cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; +static uint8_t initialized = 0; + +/* **** Functions **** */ +int MXC_GPIO_Common_Init(uint32_t portmask) +{ + if (!initialized) { + int i, j; + + for (i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) { + // Initialize call back arrays + for (j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) { + callback[i][j] = NULL; + } + } + + initialized = 1; + } + + return E_NO_ERROR; +} + +void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t* cfg, mxc_gpio_callback_fn func, void* cbdata) +{ + uint32_t mask; + unsigned int pin; + + mask = cfg->mask; + pin = 0; + + while (mask) { + if (mask & 1) { + callback[MXC_GPIO_GET_IDX(cfg->port)][pin] = func; + cbparam[MXC_GPIO_GET_IDX(cfg->port)][pin] = cbdata; + } + + pin++; + mask >>= 1; + } +} + +void MXC_GPIO_Common_Handler(unsigned int port) +{ + uint32_t stat; + unsigned int pin; + + MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES); + + mxc_gpio_regs_t* gpio = MXC_GPIO_GET_GPIO(port); + + stat = MXC_GPIO_GetFlags(gpio); + MXC_GPIO_ClearFlags(gpio, stat); + + pin = 0; + + while (stat) { + if (stat & 1) { + if (callback[port][pin]) { + callback[port][pin](cbparam[port][pin]); + } + } + + pin++; + stat >>= 1; + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h new file mode 100644 index 00000000000..28720d601dc --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h @@ -0,0 +1,52 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* **** Function Prototypes **** */ + +int MXC_GPIO_Common_Init (uint32_t portmask); +void MXC_GPIO_Common_RegisterCallback (const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); +void MXC_GPIO_Common_Handler (unsigned int port); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c new file mode 100644 index 00000000000..15de33f37b6 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c @@ -0,0 +1,211 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_errors.h" +#include "gpio.h" +#include "gpio_reva.h" +#include "gpio_common.h" +#include +#include "mxc_sys.h" + +/* **** Functions **** */ + +int MXC_GPIO_Init(uint32_t portmask) +{ + int retval = MXC_GPIO_Common_Init(portmask); + + if(portmask & MXC_GPIO_PORT_0) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); + } + + return MXC_GPIO_Common_Init(portmask) + retval; +} + +int MXC_GPIO_Shutdown(uint32_t portmask) +{ + if(portmask & MXC_GPIO_PORT_0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); + } + + return E_NO_ERROR; +} + +int MXC_GPIO_Reset(uint32_t portmask) +{ + if(portmask & MXC_GPIO_PORT_0) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); + } + + return E_NO_ERROR; +} + +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = cfg->port; + + // Set the GPIO type + switch(cfg->func) { + case MXC_GPIO_FUNC_IN: + gpio->out_en_clr = cfg->mask; + gpio->en0_set = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + + case MXC_GPIO_FUNC_OUT: + gpio->out_en_set = cfg->mask; + gpio->en0_set = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + + case MXC_GPIO_FUNC_ALT1: + gpio->en0_clr = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + + case MXC_GPIO_FUNC_ALT2: + gpio->en0_clr = cfg->mask; + gpio->en1_set = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + + case MXC_GPIO_FUNC_ALT3: + gpio->en0_set = cfg->mask; + gpio->en1_set = cfg->mask; + // gpio->en2_set |= cfg->mask; + break; + + default: + return E_BAD_PARAM; + } + + // Configure the pad + switch(cfg->pad) { + case MXC_GPIO_PAD_NONE: + gpio->pad_cfg1 &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_UP: + gpio->pad_cfg1 |= cfg->mask; + gpio->ps |= cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_DOWN: + gpio->pad_cfg1 |= cfg->mask; + gpio->ps &= ~cfg->mask; + break; + + default: + return E_BAD_PARAM; + } + + // Configure the vssel + MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); + + return E_NO_ERROR; +} + +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) +{ + return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t*) port, mask); +} + +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t*) port, mask); +} + +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t*) port, mask); +} + +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) +{ + return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t*) port, mask); +} + +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) +{ + MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t*) port, mask, val); +} + +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t*) port, mask); +} + +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) +{ + return MXC_GPIO_RevA_IntConfig(cfg, pol); +} + +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t*) port, mask); +} + +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t*) port, mask); +} + +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata) +{ + MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata); +} + +void MXC_GPIO_Handler(unsigned int port) +{ + MXC_GPIO_Common_Handler(port); +} + +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) +{ + MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t*) port, flags); +} + +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) +{ + return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t*) port); +} + +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) +{ + return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t*) port, vssel, mask); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c new file mode 100644 index 00000000000..72fb8a170d6 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c @@ -0,0 +1,201 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_errors.h" +#include "gpio.h" +#include "gpio_reva.h" +#include "gpio_common.h" +#include + +/* **** Functions **** */ +uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + return (port->in & mask); +} + +void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + port->out_set = mask; +} + +void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + port->out_clr = mask; +} + +uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + return (port->out & mask); +} + +void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val) +{ + port->out = (port->out & ~mask) | (val & mask); +} + +void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + port->out ^= mask; +} + +int MXC_GPIO_RevA_IntConfig(const mxc_gpio_cfg_t* cfg, mxc_gpio_int_pol_t pol) +{ + mxc_gpio_reva_regs_t *gpio = (mxc_gpio_reva_regs_t*) cfg->port; + + switch (pol) { + case MXC_GPIO_INT_HIGH: + gpio->intpol &= ~cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode &= ~cfg->mask; + break; + + case MXC_GPIO_INT_FALLING: /* MXC_GPIO_INT_HIGH */ + gpio->intpol &= ~cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode |= cfg->mask; + break; + + case MXC_GPIO_INT_LOW: /* MXC_GPIO_INT_LOW */ + gpio->intpol |= cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode &= ~cfg->mask; + break; + + case MXC_GPIO_INT_RISING: /* MXC_GPIO_INT_LOW */ + gpio->intpol |= cfg->mask; + gpio->dualedge &= ~cfg->mask; + gpio->intmode |= cfg->mask; + break; + + case MXC_GPIO_INT_BOTH: + gpio->dualedge |= cfg->mask; + gpio->intmode |= cfg->mask; + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + port->inten_set = mask; +} + +void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask) +{ + port->inten_clr = mask; +} + +void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags) +{ + port->intfl_clr = flags; +} + +uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port) +{ + return port->intfl; +} + +int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask) +{ + // Configure the vssel + switch (vssel) { + case MXC_GPIO_VSSEL_VDDIO: + port->vssel &= ~mask; + break; + + case MXC_GPIO_VSSEL_VDDIOH: + port->vssel |= mask; + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask) +{ + switch (func) { + case MXC_GPIO_FUNC_IN: + port->outen_clr = mask; + port->en0_set = mask; + port->en1_clr = mask; + port->en2_clr = mask; + break; + + case MXC_GPIO_FUNC_OUT: + port->outen_set = mask; + port->en0_set = mask; + port->en1_clr = mask; + port->en2_clr = mask; + break; + + case MXC_GPIO_FUNC_ALT1: + port->en0_clr = mask; + port->en1_clr = mask; + port->en2_clr = mask; + break; + + case MXC_GPIO_FUNC_ALT2: + port->en0_clr = mask; + port->en1_set = mask; + port->en2_clr = mask; + break; + + #if TARGET_NUM != 32650 + case MXC_GPIO_FUNC_ALT3: + port->en0_clr = mask; + port->en1_clr = mask; + port->en2_set = mask; + break; + + case MXC_GPIO_FUNC_ALT4: + port->en0_clr = mask; + port->en1_set = mask; + port->en2_set = mask; + break; + #endif + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h new file mode 100644 index 00000000000..b9c7b200d77 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.h @@ -0,0 +1,73 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "gpio_reva_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + + + +/** + * @brief Enumeration type for the pullup strength on a given pin. + */ +typedef enum { + MXC_GPIO_PS_NONE, /**< No pull-up or pull-down strength required*/ + MXC_GPIO_PS_PULL_SELECT, /**< Selct pull-up or pull-down strength*/ +} mxc_gpio_ps_t; + +/* **** Function Prototypes **** */ + +uint32_t MXC_GPIO_RevA_InGet (mxc_gpio_reva_regs_t* port, uint32_t mask); +void MXC_GPIO_RevA_OutSet (mxc_gpio_reva_regs_t* port, uint32_t mask); +void MXC_GPIO_RevA_OutClr (mxc_gpio_reva_regs_t* port, uint32_t mask); +uint32_t MXC_GPIO_RevA_OutGet (mxc_gpio_reva_regs_t* port, uint32_t mask); +void MXC_GPIO_RevA_OutPut (mxc_gpio_reva_regs_t* port, uint32_t mask, uint32_t val); +void MXC_GPIO_RevA_OutToggle (mxc_gpio_reva_regs_t* port, uint32_t mask); +int MXC_GPIO_RevA_IntConfig (const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); +void MXC_GPIO_RevA_EnableInt (mxc_gpio_reva_regs_t* port, uint32_t mask); +void MXC_GPIO_RevA_DisableInt (mxc_gpio_reva_regs_t* port, uint32_t mask); +void MXC_GPIO_RevA_ClearFlags (mxc_gpio_reva_regs_t* port, uint32_t flags); +uint32_t MXC_GPIO_RevA_GetFlags (mxc_gpio_reva_regs_t* port); +#if TARGET_NUM != 32650 +int MXC_GPIO_RevA_SetVSSEL (mxc_gpio_reva_regs_t* port, mxc_gpio_vssel_t vssel, uint32_t mask); +#endif +int MXC_GPIO_RevA_SetAF (mxc_gpio_reva_regs_t* port, mxc_gpio_func_t func, uint32_t mask); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h new file mode 100644 index 00000000000..27a20b1094a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_regs.h @@ -0,0 +1,690 @@ +/** + * @file gpio_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GPIO_REVA_REGS_H_ +#define _GPIO_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers GPIO_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @details Individual I/O for each GPIO + */ + +/** + * @ingroup gpio_registers + * Structure type to access the GPIO Registers. + */ +typedef struct { + __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ + __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ + __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ + __IO uint32_t outen; /**< \b 0x0C: GPIO OUTEN Register */ + __IO uint32_t outen_set; /**< \b 0x10: GPIO OUTEN_SET Register */ + __IO uint32_t outen_clr; /**< \b 0x14: GPIO OUTEN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO IN Register */ + __IO uint32_t intmode; /**< \b 0x28: GPIO INTMODE Register */ + __IO uint32_t intpol; /**< \b 0x2C: GPIO INTPOL Register */ + __IO uint32_t inen; /**< \b 0x30: GPIO INEN Register */ + __IO uint32_t inten; /**< \b 0x34: GPIO INTEN Register */ + __IO uint32_t inten_set; /**< \b 0x38: GPIO INTEN_SET Register */ + __IO uint32_t inten_clr; /**< \b 0x3C: GPIO INTEN_CLR Register */ + __I uint32_t intfl; /**< \b 0x40: GPIO INTFL Register */ + __R uint32_t rsv_0x44; + __IO uint32_t intfl_clr; /**< \b 0x48: GPIO INTFL_CLR Register */ + __IO uint32_t wken; /**< \b 0x4C: GPIO WKEN Register */ + __IO uint32_t wken_set; /**< \b 0x50: GPIO WKEN_SET Register */ + __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ + __R uint32_t rsv_0x58; + __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ + __IO uint32_t padctrl0; /**< \b 0x60: GPIO PADCTRL0 Register */ + __IO uint32_t padctrl1; /**< \b 0x64: GPIO PADCTRL1 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ + __R uint32_t rsv_0x80_0xa7[10]; + __IO uint32_t hysen; /**< \b 0xA8: GPIO HYSEN Register */ + __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ + __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ + __R uint32_t rsv_0xbc; + __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ +} mxc_gpio_reva_regs_t; + +/* Register offsets for module GPIO */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ + #define MXC_R_GPIO_REVA_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ + #define MXC_R_GPIO_REVA_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ + #define MXC_R_GPIO_REVA_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ + #define MXC_R_GPIO_REVA_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ + #define MXC_R_GPIO_REVA_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ + #define MXC_R_GPIO_REVA_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ + #define MXC_R_GPIO_REVA_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ + #define MXC_R_GPIO_REVA_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ + #define MXC_R_GPIO_REVA_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ + #define MXC_R_GPIO_REVA_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ + #define MXC_R_GPIO_REVA_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ + #define MXC_R_GPIO_REVA_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ + #define MXC_R_GPIO_REVA_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ + #define MXC_R_GPIO_REVA_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ + #define MXC_R_GPIO_REVA_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ + #define MXC_R_GPIO_REVA_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ + #define MXC_R_GPIO_REVA_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ + #define MXC_R_GPIO_REVA_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ + #define MXC_R_GPIO_REVA_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ + #define MXC_R_GPIO_REVA_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ + #define MXC_R_GPIO_REVA_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ + #define MXC_R_GPIO_REVA_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ + #define MXC_R_GPIO_REVA_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ + #define MXC_R_GPIO_REVA_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ + #define MXC_R_GPIO_REVA_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ + #define MXC_R_GPIO_REVA_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ + #define MXC_R_GPIO_REVA_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ + #define MXC_R_GPIO_REVA_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ + #define MXC_R_GPIO_REVA_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ + #define MXC_R_GPIO_REVA_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ + #define MXC_R_GPIO_REVA_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ + #define MXC_R_GPIO_REVA_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ + #define MXC_R_GPIO_REVA_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ + #define MXC_R_GPIO_REVA_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ + #define MXC_R_GPIO_REVA_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ + #define MXC_R_GPIO_REVA_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ +/**@} end of group gpio_registers */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0 GPIO_EN0 + * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * GPIO pin on the associated port. + * @{ + */ + #define MXC_F_GPIO_REVA_EN0_GPIO_EN_POS 0 /**< EN0_GPIO_REVA_EN Position */ + #define MXC_F_GPIO_REVA_EN0_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS)) /**< EN0_GPIO_EN Mask */ + #define MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN0_GPIO_EN_ALTERNATE Value */ + #define MXC_S_GPIO_REVA_EN0_GPIO_EN_ALTERNATE (MXC_V_GPIO_REVA_EN0_GPIO_EN_ALTERNATE << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_ALTERNATE Setting */ + #define MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN0_GPIO_EN_GPIO Value */ + #define MXC_S_GPIO_REVA_EN0_GPIO_EN_GPIO (MXC_V_GPIO_REVA_EN0_GPIO_EN_GPIO << MXC_F_GPIO_REVA_EN0_GPIO_EN_POS) /**< EN0_GPIO_EN_GPIO Setting */ + +/**@} end of group GPIO_EN0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_SET GPIO_EN0_SET + * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * register sets the bits in the same positions in GPIO_EN to 1, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ + #define MXC_F_GPIO_REVA_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ + +/**@} end of group GPIO_EN0_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR + * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ + #define MXC_F_GPIO_REVA_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ + +/**@} end of group GPIO_EN0_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN GPIO_OUTEN + * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one + * GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_REVA_OUTEN_EN_POS 0 /**< OUTEN_EN Position */ + #define MXC_F_GPIO_REVA_OUTEN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_EN_POS)) /**< OUTEN_EN Mask */ + #define MXC_V_GPIO_REVA_OUTEN_EN_DIS ((uint32_t)0x0UL) /**< OUTEN_EN_DIS Value */ + #define MXC_S_GPIO_REVA_OUTEN_EN_DIS (MXC_V_GPIO_REVA_OUTEN_EN_DIS << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_DIS Setting */ + #define MXC_V_GPIO_REVA_OUTEN_EN_EN ((uint32_t)0x1UL) /**< OUTEN_EN_EN Value */ + #define MXC_S_GPIO_REVA_OUTEN_EN_EN (MXC_V_GPIO_REVA_OUTEN_EN_EN << MXC_F_GPIO_REVA_OUTEN_EN_POS) /**< OUTEN_EN_EN Setting */ + +/**@} end of group GPIO_OUTEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET + * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits + * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ + #define MXC_F_GPIO_REVA_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ + +/**@} end of group GPIO_OUTEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR + * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more + * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ + #define MXC_F_GPIO_REVA_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ + +/**@} end of group GPIO_OUTEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT GPIO_OUT + * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the + * associated port. This register can be written either directly, or by using the + * GPIO_OUT_SET and GPIO_OUT_CLR registers. + * @{ + */ + #define MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ + #define MXC_F_GPIO_REVA_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ + #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ + #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_LOW (MXC_V_GPIO_REVA_OUT_GPIO_OUT_LOW << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ + #define MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ + #define MXC_S_GPIO_REVA_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_REVA_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_REVA_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ + +/**@} end of group GPIO_OUT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits + * in the same positions in GPIO_OUT to 1, without affecting other bits in that + * register. + * @{ + */ + #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ + #define MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ + #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ + #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ + #define MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ + #define MXC_S_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_REVA_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_REVA_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ + +/**@} end of group GPIO_OUT_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_OUT to 0, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ + #define MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ + +/**@} end of group GPIO_OUT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN GPIO_IN + * @brief GPIO Input Register. Read-only register to read from the logic states of the + * GPIO pins on this port. + * @{ + */ + #define MXC_F_GPIO_REVA_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ + #define MXC_F_GPIO_REVA_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ + +/**@} end of group GPIO_IN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTMODE GPIO_INTMODE + * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt + * mode setting for the associated GPIO pin on this port. + * @{ + */ + #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS 0 /**< INTMODE_GPIO_INTMODE Position */ + #define MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS)) /**< INTMODE_GPIO_INTMODE Mask */ + #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL ((uint32_t)0x0UL) /**< INTMODE_GPIO_INTMODE_LEVEL Value */ + #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_LEVEL << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_LEVEL Setting */ + #define MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE ((uint32_t)0x1UL) /**< INTMODE_GPIO_INTMODE_EDGE Value */ + #define MXC_S_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE (MXC_V_GPIO_REVA_INTMODE_GPIO_INTMODE_EDGE << MXC_F_GPIO_REVA_INTMODE_GPIO_INTMODE_POS) /**< INTMODE_GPIO_INTMODE_EDGE Setting */ + +/**@} end of group GPIO_INTMODE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTPOL GPIO_INTPOL + * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the + * interrupt polarity setting for one GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS 0 /**< INTPOL_GPIO_INTPOL Position */ + #define MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS)) /**< INTPOL_GPIO_INTPOL Mask */ + #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING ((uint32_t)0x0UL) /**< INTPOL_GPIO_INTPOL_FALLING Value */ + #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_FALLING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_FALLING Setting */ + #define MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING ((uint32_t)0x1UL) /**< INTPOL_GPIO_INTPOL_RISING Value */ + #define MXC_S_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING (MXC_V_GPIO_REVA_INTPOL_GPIO_INTPOL_RISING << MXC_F_GPIO_REVA_INTPOL_GPIO_INTPOL_POS) /**< INTPOL_GPIO_INTPOL_RISING Setting */ + +/**@} end of group GPIO_INTPOL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN GPIO_INTEN + * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO + * interrupt enable for the associated pin on the GPIO port. + * @{ + */ + #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS 0 /**< INTEN_GPIO_REVA_INTEN Position */ + #define MXC_F_GPIO_REVA_INTEN_GPIO_INTEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS)) /**< INTEN_GPIO_INTEN Mask */ + #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS ((uint32_t)0x0UL) /**< INTEN_GPIO_INTEN_DIS Value */ + #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_DIS (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_DIS << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_DIS Setting */ + #define MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN ((uint32_t)0x1UL) /**< INTEN_GPIO_INTEN_EN Value */ + #define MXC_S_GPIO_REVA_INTEN_GPIO_INTEN_EN (MXC_V_GPIO_REVA_INTEN_GPIO_INTEN_EN << MXC_F_GPIO_REVA_INTEN_GPIO_INTEN_POS) /**< INTEN_GPIO_INTEN_EN Setting */ + +/**@} end of group GPIO_INTEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET + * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets + * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS 0 /**< INTEN_SET_GPIO_INTEN_SET Position */ + #define MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS)) /**< INTEN_SET_GPIO_INTEN_SET Mask */ + #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO ((uint32_t)0x0UL) /**< INTEN_SET_GPIO_INTEN_SET_NO Value */ + #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_NO << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_NO Setting */ + #define MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET ((uint32_t)0x1UL) /**< INTEN_SET_GPIO_INTEN_SET_SET Value */ + #define MXC_S_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET (MXC_V_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_SET << MXC_F_GPIO_REVA_INTEN_SET_GPIO_INTEN_SET_POS) /**< INTEN_SET_GPIO_INTEN_SET_SET Setting */ + +/**@} end of group GPIO_INTEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR + * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS 0 /**< INTEN_CLR_GPIO_INTEN_CLR Position */ + #define MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS)) /**< INTEN_CLR_GPIO_INTEN_CLR Mask */ + #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO ((uint32_t)0x0UL) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Value */ + #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_NO << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_NO Setting */ + #define MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Value */ + #define MXC_S_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR (MXC_V_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_CLEAR << MXC_F_GPIO_REVA_INTEN_CLR_GPIO_INTEN_CLR_POS) /**< INTEN_CLR_GPIO_INTEN_CLR_CLEAR Setting */ + +/**@} end of group GPIO_INTEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL GPIO_INTFL + * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending + * interrupt status for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS 0 /**< INTFL_GPIO_INTFL Position */ + #define MXC_F_GPIO_REVA_INTFL_GPIO_INTFL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS)) /**< INTFL_GPIO_INTFL Mask */ + #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO ((uint32_t)0x0UL) /**< INTFL_GPIO_INTFL_NO Value */ + #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_NO (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_NO << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_NO Setting */ + #define MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING ((uint32_t)0x1UL) /**< INTFL_GPIO_INTFL_PENDING Value */ + #define MXC_S_GPIO_REVA_INTFL_GPIO_INTFL_PENDING (MXC_V_GPIO_REVA_INTFL_GPIO_INTFL_PENDING << MXC_F_GPIO_REVA_INTFL_GPIO_INTFL_POS) /**< INTFL_GPIO_INTFL_PENDING Setting */ + +/**@} end of group GPIO_INTFL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR + * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ + #define MXC_F_GPIO_REVA_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ + +/**@} end of group GPIO_INTFL_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN GPIO_WKEN + * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup + * enable for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS 0 /**< WKEN_GPIO_WKEN Position */ + #define MXC_F_GPIO_REVA_WKEN_GPIO_WKEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS)) /**< WKEN_GPIO_WKEN Mask */ + #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_DIS ((uint32_t)0x0UL) /**< WKEN_GPIO_REVA_WKEN_DIS Value */ + #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_DIS (MXC_V_GPIO_WKEN_REVA_GPIO_WKEN_DIS << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_DIS Setting */ + #define MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN ((uint32_t)0x1UL) /**< WKEN_GPIO_WKEN_EN Value */ + #define MXC_S_GPIO_REVA_WKEN_GPIO_WKEN_EN (MXC_V_GPIO_REVA_WKEN_GPIO_WKEN_EN << MXC_F_GPIO_REVA_WKEN_GPIO_WKEN_POS) /**< WKEN_GPIO_WKEN_EN Setting */ + +/**@} end of group GPIO_WKEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET + * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the + * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_REVA_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ + #define MXC_F_GPIO_REVA_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ + +/**@} end of group GPIO_WKEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR + * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears + * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ + #define MXC_F_GPIO_REVA_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ + +/**@} end of group GPIO_WKEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE + * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual + * edge mode for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS 0 /**< DUALEDGE_GPIO_DUALEDGE Position */ + #define MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS)) /**< DUALEDGE_GPIO_DUALEDGE Mask */ + #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO ((uint32_t)0x0UL) /**< DUALEDGE_GPIO_DUALEDGE_NO Value */ + #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_NO << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_NO Setting */ + #define MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN ((uint32_t)0x1UL) /**< DUALEDGE_GPIO_DUALEDGE_EN Value */ + #define MXC_S_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN (MXC_V_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_EN << MXC_F_GPIO_REVA_DUALEDGE_GPIO_DUALEDGE_POS) /**< DUALEDGE_GPIO_DUALEDGE_EN Setting */ + +/**@} end of group GPIO_DUALEDGE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 + * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS 0 /**< PADCTRL0_GPIO_PADCTRL0 Position */ + #define MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS)) /**< PADCTRL0_GPIO_PADCTRL0 Mask */ + #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Value */ + #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_IMPEDANCE Setting */ + #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU ((uint32_t)0x1UL) /**< PADCTRL0_GPIO_PADCTRL0_PU Value */ + #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PU << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PU Setting */ + #define MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD ((uint32_t)0x2UL) /**< PADCTRL0_GPIO_PADCTRL0_PD Value */ + #define MXC_S_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD (MXC_V_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_PD << MXC_F_GPIO_REVA_PADCTRL0_GPIO_PADCTRL0_POS) /**< PADCTRL0_GPIO_PADCTRL0_PD Setting */ + +/**@} end of group GPIO_PADCTRL0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 + * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS 0 /**< PADCTRL1_GPIO_PADCTRL1 Position */ + #define MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS)) /**< PADCTRL1_GPIO_PADCTRL1 Mask */ + #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Value */ + #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_IMPEDANCE << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_IMPEDANCE Setting */ + #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU ((uint32_t)0x1UL) /**< PADCTRL1_GPIO_PADCTRL1_PU Value */ + #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PU << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PU Setting */ + #define MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD ((uint32_t)0x2UL) /**< PADCTRL1_GPIO_PADCTRL1_PD Value */ + #define MXC_S_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD (MXC_V_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_PD << MXC_F_GPIO_REVA_PADCTRL1_GPIO_PADCTRL1_POS) /**< PADCTRL1_GPIO_PADCTRL1_PD Setting */ + +/**@} end of group GPIO_PADCTRL1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1 GPIO_EN1 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ + #define MXC_F_GPIO_REVA_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ + #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ + #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ + #define MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ + #define MXC_S_GPIO_REVA_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_REVA_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_REVA_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ + +/**@} end of group GPIO_EN1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ + #define MXC_F_GPIO_REVA_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ + +/**@} end of group GPIO_EN1_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ + #define MXC_F_GPIO_REVA_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ + +/**@} end of group GPIO_EN1_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2 GPIO_EN2 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ + #define MXC_F_GPIO_REVA_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ + #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ + #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ + #define MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ + #define MXC_S_GPIO_REVA_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_REVA_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_REVA_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ + +/**@} end of group GPIO_EN2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ + #define MXC_F_GPIO_REVA_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ + +/**@} end of group GPIO_EN2_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN2 to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_REVA_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ + #define MXC_F_GPIO_REVA_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_EN2_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_HYSEN GPIO_HYSEN + * @brief GPIO Input Hysteresis Enable. + * @{ + */ + #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS 0 /**< HYSEN_GPIO_HYSEN Position */ + #define MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_HYSEN_GPIO_HYSEN_POS)) /**< HYSEN_GPIO_HYSEN Mask */ + +/**@} end of group GPIO_HYSEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_SRSEL GPIO_SRSEL + * @brief GPIO Slew Rate Enable Register. + * @{ + */ + #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS 0 /**< SRSEL_GPIO_SRSEL Position */ + #define MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS)) /**< SRSEL_GPIO_SRSEL Mask */ + #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST ((uint32_t)0x0UL) /**< SRSEL_GPIO_SRSEL_FAST Value */ + #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_FAST << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_FAST Setting */ + #define MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW ((uint32_t)0x1UL) /**< SRSEL_GPIO_SRSEL_SLOW Value */ + #define MXC_S_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW (MXC_V_GPIO_REVA_SRSEL_GPIO_SRSEL_SLOW << MXC_F_GPIO_REVA_SRSEL_GPIO_SRSEL_POS) /**< SRSEL_GPIO_SRSEL_SLOW Setting */ + +/**@} end of group GPIO_SRSEL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS0 GPIO_DS0 + * @brief GPIO Drive Strength Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS 0 /**< DS0_GPIO_DS0 Position */ + #define MXC_F_GPIO_REVA_DS0_GPIO_DS0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS)) /**< DS0_GPIO_DS0 Mask */ + #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD ((uint32_t)0x0UL) /**< DS0_GPIO_DS0_LD Value */ + #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_LD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_LD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_LD Setting */ + #define MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD ((uint32_t)0x1UL) /**< DS0_GPIO_DS0_HD Value */ + #define MXC_S_GPIO_REVA_DS0_GPIO_DS0_HD (MXC_V_GPIO_REVA_DS0_GPIO_DS0_HD << MXC_F_GPIO_REVA_DS0_GPIO_DS0_POS) /**< DS0_GPIO_DS0_HD Setting */ + +/**@} end of group GPIO_DS0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS1 GPIO_DS1 + * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS 0 /**< DS1_GPIO_DS1 Position */ + #define MXC_F_GPIO_REVA_DS1_GPIO_DS1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_DS1_GPIO_DS1_POS)) /**< DS1_GPIO_DS1 Mask */ + +/**@} end of group GPIO_DS1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PS GPIO_PS + * @brief GPIO Pull Select Mode. + * @{ + */ + #define MXC_F_GPIO_REVA_PS_ALL_POS 0 /**< PS_ALL Position */ + #define MXC_F_GPIO_REVA_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_PS_ALL_POS)) /**< PS_ALL Mask */ + +/**@} end of group GPIO_PS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_VSSEL GPIO_VSSEL + * @brief GPIO Voltage Select. + * @{ + */ + #define MXC_F_GPIO_REVA_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ + #define MXC_F_GPIO_REVA_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_REVA_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ + +/**@} end of group GPIO_VSSEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c new file mode 100644 index 00000000000..bf20b140a18 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_me11.c @@ -0,0 +1,394 @@ +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_pins.h" +#include "mxc_delay.h" +#include "i2c_regs.h" +#include "dma_regs.h" +#include "mxc_i2c.h" +#include "i2c_reva.h" + + +/* **** Definitions **** */ +#define MXC_I2C_FASTPLUS_SPEED 1000000 + +/* **** Variable Declaration **** */ +uint32_t interruptCheck = MXC_F_I2C_INTFL0_AMI | MXC_F_I2C_INTFL0_DNRERI; + +/* **** Function Prototypes **** */ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ +int MXC_I2C_Init(mxc_i2c_regs_t* i2c, int masterMode, unsigned int slaveAddr) +{ + if(i2c == NULL) { + return E_NULL_PTR; + } + + MXC_I2C_Shutdown(i2c); // Clear everything out + + if(i2c == MXC_I2C0) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); + MXC_GPIO_Config(&gpio_cfg_i2c0); + } + else if(i2c == MXC_I2C1) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); + MXC_GPIO_Config(&gpio_cfg_i2c1); + } + else { + return E_NO_DEVICE; + } + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t*) i2c, masterMode, slaveAddr); +} + +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t* i2c, unsigned int slaveAddr, int idx) +{ + if(i2c == NULL) { + return E_NULL_PTR; + } + + if(idx != 0) { + // Multiple slaves are not supported yet + return E_NOT_SUPPORTED; + } + + if(slaveAddr > MXC_F_I2C_SLADDR_SLA) { + // Only support addresses up to 10 bits + return E_BAD_PARAM; + } + + i2c->sladdr = 0; + + if(slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + // Set for 10bit addressing mode + i2c->sladdr = MXC_F_I2C_SLADDR_EA; + } + + i2c->sladdr |= slaveAddr; + + return E_NO_ERROR; +} + +int MXC_I2C_Shutdown(mxc_i2c_regs_t* i2c) +{ + // Configure GPIO for I2C + if(i2c == MXC_I2C0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); + } + else if(i2c == MXC_I2C1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); + } + else { + return E_NO_DEVICE; + } + + + int i2cNum = MXC_I2C_GET_IDX(i2c); + + // Reconcile this with MXC_SYS_I2C_Init when we figure out what to do abotu system level things + switch(i2cNum) { + case 0: + MXC_GCR->rst0 |= MXC_F_GCR_RST0_I2C0; + break; + + case 1: + MXC_GCR->rst1 |= MXC_F_GCR_RST1_I2C1; + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_I2C_SetFrequency(mxc_i2c_regs_t* i2c, unsigned int hz) +{ + + // ME13 doesn't support high speed more + if(hz > MXC_I2C_FASTPLUS_SPEED) { + return E_NOT_SUPPORTED; + } + + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t*) i2c, hz); +} + +unsigned int MXC_I2C_GetFrequency(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t* i2c, int enable) +{ + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t*) i2c, enable); +} + +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t*) i2c); +} + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ +int MXC_I2C_Start(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_Stop(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_WriteByte(mxc_i2c_regs_t* i2c, unsigned char byte) +{ + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t*) i2c, byte); +} + +int MXC_I2C_ReadByte(mxc_i2c_regs_t* i2c, unsigned char* byte, int ack) +{ + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t*) i2c, byte, ack); +} + +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t* i2c, unsigned char* byte, mxc_i2c_getAck_t getAck) +{ + return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t*) i2c, byte, (mxc_i2c_reva_getAck_t) getAck); +} + +int MXC_I2C_Write(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len) +{ + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t*) i2c, bytes, len); +} + +int MXC_I2C_Read(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +{ + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t*) i2c, bytes, len, ack); +} + +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +{ + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len); +} + +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +{ + uint8_t i2cNum; + mxc_dma_config_t config; + + i2cNum = MXC_I2C_GET_IDX(i2c); + + switch(i2cNum) { + case 0: + config.reqsel = MXC_DMA_REQUEST_I2C0RX; + break; + + case 1: + config.reqsel = MXC_DMA_REQUEST_I2C1RX; + break; + } + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); +} + +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +{ + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t*) i2c, bytes, len); +} + +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_dma_complete_cb_t callback) +{ + uint8_t i2cNum; + mxc_dma_config_t config; + + i2cNum = MXC_I2C_GET_IDX(i2c); + + switch(i2cNum) { + case 0: + config.reqsel = MXC_DMA_REQUEST_I2C0TX; + break; + + case 1: + config.reqsel = MXC_DMA_REQUEST_I2C1TX; + break; + } + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t*) i2c, bytes, len, (mxc_i2c_reva_dma_complete_cb_t) callback, config, MXC_DMA); +} + +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_GetFlags(mxc_i2c_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +{ + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); +} + +void MXC_I2C_ClearFlags(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); +} + +void MXC_I2C_EnableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); +} + +void MXC_I2C_DisableInt(mxc_i2c_regs_t* i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t*) i2c, flags0, flags1); +} + +void MXC_I2C_EnablePreload (mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_DisablePreload (mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_EnableGeneralCall (mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_EnableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_DisableGeneralCall (mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_DisableGeneralCall ((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_SetTimeout (mxc_i2c_regs_t* i2c, unsigned int timeout) +{ + MXC_I2C_RevA_SetTimeout ((mxc_i2c_reva_regs_t*) i2c, timeout); +} + +unsigned int MXC_I2C_GetTimeout (mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetTimeout ((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_Recover(mxc_i2c_regs_t* i2c, unsigned int retries) +{ + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t*) i2c, retries); +} + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +int MXC_I2C_MasterTransaction(mxc_i2c_req_t* req) +{ + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t*) req); +} + +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t* req) +{ + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t*) req); +} + +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t* req) +{ + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t*) req, MXC_DMA); +} + +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +{ + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); +} + +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t* i2c, mxc_i2c_slave_handler_t callback) +{ + return MXC_I2C_RevA_SlaveTransactionAsync((mxc_i2c_reva_regs_t*) i2c, (mxc_i2c_reva_slave_handler_t) callback, interruptCheck); +} + +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +{ + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes); +} + +unsigned int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t*) i2c); +} + +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t* i2c, unsigned int numBytes) +{ + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t*) i2c, numBytes); +} + +unsigned int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t* i2c) +{ + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t*) i2c); +} + +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t* i2c) +{ + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t*) i2c, interruptCheck); +} + +void MXC_I2C_DMACallback(int ch, int error) +{ + MXC_I2C_RevA_DMACallback(ch, error); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c new file mode 100644 index 00000000000..56d335f4d43 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.c @@ -0,0 +1,1348 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "i2c_regs.h" +#include "mxc_i2c.h" +#include "i2c_reva.h" +#include "dma.h" + +/* **** Variable Declaration **** */ +typedef struct { + mxc_i2c_reva_req_t *req; + int master; // 1 for Master, 0 for slave + int channelTx; // DMA channel for TX transaction + int channelRx; // DMA channel for RX transaction + int writeDone; // Write done flag + int readDone; // Flag done flag +} mxc_i2c_reva_req_state_t; + +static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES]; + +void* AsyncRequests[MXC_I2C_INSTANCES]; +unsigned int AsyncWritten[MXC_I2C_INSTANCES]; +unsigned int AsyncRead[MXC_I2C_INSTANCES]; + +/* **** Function Prototypes **** */ +void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); +void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); +int MXC_I2C_RevA_DMAHandler (mxc_i2c_reva_req_t* req); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ +int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr) +{ + int err; + + if(i2c == NULL) { + return E_NULL_PTR; + } + + if ((err = MXC_I2C_Recover ((mxc_i2c_regs_t*) i2c, 16)) != E_NO_ERROR) { + return err; + } + + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; + + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + // Set the thresholds here and allow the user to change them as needed + MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 6); // set RX threshold to 6 bytes + + if (!masterMode) { + MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t*) i2c, slaveAddr, 0); + states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 0; + } + else { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE; + states[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)].master = 1; + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + if (idx != 0) { + // Multiple slaves are not supported yet + return E_NOT_SUPPORTED; + } + + if (slaveAddr > MXC_F_I2C_REVA_SLAVE_ADDR) { + // Only support addresses up to 10 bits + return E_BAD_PARAM; + } + + i2c->slave = 0; + + if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + // Set for 10bit addressing mode + i2c->slave = MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN; + } + + i2c->slave |= slaveAddr; + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c) +{ + return E_NOT_SUPPORTED; +} + +int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz) +{ + unsigned int ticksTotal, hiClks, lowClks; + + if (i2c == NULL) { + return E_NULL_PTR; + } + + if (hz > MXC_I2C_REVA_FASTPLUS_SPEED) { + // We're going to enable high speed + int hsLowClks, hsHiClks; + + // Calculate the period of SCL and set up 33% duty cycle + ticksTotal = PeripheralClock / hz; + hsLowClks = (ticksTotal * 2) / 3 - 1; + hsHiClks = ticksTotal / 3 - 1; + + // For rounding errors, adjust by 1 clock tick + if (ticksTotal % 1) { + hsHiClks++; + } + + // If we're too slow for high speed, bail out + if ((hsHiClks > 0xF) || (hsLowClks > 0xF)) { + return E_BAD_PARAM; + } + + hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz + } + + // Calculate the period of SCL, 50% duty cycle + ticksTotal = PeripheralClock / hz; + hiClks = (ticksTotal >> 1) - 1; + lowClks = (ticksTotal >> 1) - 1; + + // Adjust for rounding errors + if (ticksTotal % 1) { + hiClks++; + } + + // Check for maximum/minimum supported speeds + if ( (hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) { + return E_BAD_PARAM; + } + + i2c->clklo = lowClks & MXC_F_I2C_REVA_CLKLO_LO; + i2c->clkhi = hiClks & MXC_F_I2C_REVA_CLKHI_HI; + + // Return the actual speed set, since it won't be exactly what's requested + return MXC_I2C_GetFrequency ((mxc_i2c_regs_t*) i2c); +} + +unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c) +{ + unsigned int sclCycles = 0; + + // Calculate the speed based on what we've written into registers + sclCycles = (i2c->clklo & MXC_F_I2C_REVA_CLKLO_LO) + (i2c->clkhi & MXC_F_I2C_REVA_CLKHI_HI); + + return PeripheralClock / sclCycles; +} + +int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c) +{ + if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + return E_BAD_PARAM; + } + + if (AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] != NULL) { + return E_BUSY; + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + if (enable) { + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; + } + else { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS; + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + return ! ( (i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS); +} + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ +int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + // If we have an incomplete transfer, we need to do a restart + if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + } + else { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP); + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + if (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) { + return E_OVERFLOW; + } + + // I'm depending on an interrupt flag here + // This might cause issues with the transaction level functions to come + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); + i2c->fifo = byte; + + while (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)); + + return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR; +} + +int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack) +{ + if ((i2c == NULL) || (byte == NULL)) { + return E_NULL_PTR; + } + + if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + return E_UNDERFLOW; + } + + *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + + if(ack) { + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK; + } else { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_IRXM_ACK; + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck) +{ + if ((i2c == NULL) || (byte == NULL)) { + return E_NULL_PTR; + } + + if (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) { + return E_UNDERFLOW; + } + + *byte = (uint8_t) (i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA); + + if (getAck == NULL) { + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; + } + else { + i2c->ctrl |= (!!getAck ((mxc_i2c_reva_regs_t*) i2c, *byte)) << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS; + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len) +{ + int notAcked = 0; + unsigned written = 0; + + if (i2c == NULL) { + return E_NULL_PTR; + } + + if ((bytes == NULL) || (len == NULL)) { + return E_NULL_PTR; + } + + for (; written < *len; written++) { + int retVal = MXC_I2C_WriteByte ((mxc_i2c_regs_t*) i2c, bytes[written]); + + if (retVal >= 0) { + notAcked += retVal; + } + else { + *len = written; + return retVal; + } + } + + *len = written; + notAcked = (notAcked > 0) ? 1 : 0; + return notAcked; +} + +int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack) +{ + unsigned read = 0; + + if (i2c == NULL) { + return E_NULL_PTR; + } + + if ((bytes == NULL) || (len == NULL)) { + return E_NULL_PTR; + } + + for (; read < *len-1; read++) { + int retVal = MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), 1); + + if (retVal != E_NO_ERROR) { + *len = read; + return retVal; + } + } + + read++; + *len = read; + return MXC_I2C_ReadByte ((mxc_i2c_regs_t*) i2c, & (bytes[read]), ack); +} + +int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +{ + unsigned read = 0; + + if ((i2c == NULL) || (bytes == NULL)) { + return E_NULL_PTR; + } + + while ( (len > read) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) { + bytes[read++] = i2c->fifo; + } + + return read; +} + +int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +{ + uint8_t i2cNum; + uint8_t channel; + mxc_dma_srcdst_t srcdst; + + if ((i2c == NULL) || (bytes == NULL)) { + return E_NULL_PTR; + } + + i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.ch = channel; + + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + + config.srcinc_en = 0; + config.dstinc_en = 1; + + srcdst.ch = channel; + srcdst.dest = bytes; + srcdst.len = len; + + states[i2cNum].channelRx = channel; + MXC_DMA_ConfigChannel(config, srcdst); + + if (states[i2cNum].master) { + MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); + } + + else { + MXC_DMA_SetCallback(channel, NULL); + } + + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + //MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; + MXC_DMA_SetChannelInterruptEn(channel, 0, 1); + i2c->dma |= MXC_F_I2C_REVA_DMA_RX_EN; + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) +{ + if(i2c == NULL) { + return E_NULL_PTR; + } + + return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS; +} + +int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len) +{ + unsigned written = 0; + + if ((i2c == NULL) || (bytes == NULL)) { + return E_NULL_PTR; + } + + while ( (len > written) && (! (i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) { + i2c->fifo = bytes[written++]; + } + + return written; +} + +int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, \ + mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma) +{ + uint8_t i2cNum; + uint8_t channel; + mxc_dma_srcdst_t srcdst; + + if ((i2c == NULL) || (bytes == NULL)) { + return E_NULL_PTR; + } + + i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)i2c); + + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.ch = channel; + + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + + config.srcinc_en = 1; + config.dstinc_en = 0; + + srcdst.ch = channel; + srcdst.source = bytes; + srcdst.len = len; + + states[i2cNum].channelTx = channel; + MXC_DMA_ConfigChannel(config, srcdst); + + if (states[i2cNum].master) { + MXC_DMA_SetCallback(channel, MXC_I2C_RevA_DMACallback); + } + else { + MXC_DMA_SetCallback(channel, NULL); + } + + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + // MXC_DMA->ch[channel].cfg |= MXC_F_DMA_CFG_CTZIEN; + MXC_DMA_SetChannelInterruptEn(channel, 0, 1); + i2c->dma |= MXC_F_I2C_REVA_DMA_TX_EN; + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + return txFIFOlen - ( (i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS); +} + +void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c) +{ + i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH; + + while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH); +} + +void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c) +{ + i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH; + + while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH); +} + +int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + + if ((flags0 == NULL) || (flags1 == NULL)) { + return E_BAD_PARAM; + } + + *flags0 = i2c->intfl0; + *flags1 = i2c->intfl1; + + return E_NO_ERROR; +} + +void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +{ + i2c->intfl0 = flags0; + i2c->intfl1 = flags1; +} + +void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +{ + i2c->inten0 |= flags0; + i2c->inten1 |= flags1; +} + +void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1) +{ + i2c->inten0 &= ~flags0; + i2c->inten1 &= ~flags1; +} + +int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries) +{ + int err; + unsigned int i; + + if(i2c == NULL) { + return E_NULL_PTR; + } + + err = E_COMM_ERR; + + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN; + int swBit = i2c->ctrl & MXC_F_I2C_REVA_CTRL_BB_MODE; + + if(i2c == NULL) { + return E_NULL_PTR; + } + + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_BB_MODE; + + // Follow the procedure detailed in the header file + // Delay 10uS between each step to give the line/slaves time to react + for (i = 0; i < retries; i++) { + MXC_Delay (10); + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT; + + MXC_Delay(10); + + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; + continue; // Give up and try again + } + + MXC_Delay (10); + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT; + + MXC_Delay(10); + + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA) { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; + continue; // Give up and try again + } + + MXC_Delay (10); + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT; + + MXC_Delay(10); + + if (! (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) { + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT; + continue; // Give up and try again + } + + MXC_Delay (10); + i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT; + + MXC_Delay(10); + + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) { + err = E_NO_ERROR; // We have control + break; + } + } + + if (swBit == 0) { + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_BB_MODE; + } + + i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_EN; + + return err; +} + +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c) +{ + i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; +} + +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c) +{ + i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE; +} + +void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c) +{ + i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; +} + +void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c) +{ + i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS; +} + +void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout) +{ + i2c->timeout |= (timeout & 0xFFFF); +} + +unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c) +{ + return (i2c->timeout & 0xFFFF); +} + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req) +{ + mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access + unsigned int written = 0; + unsigned int read = 0; + + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + return E_NOT_SUPPORTED; + } + + if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + return E_BAD_PARAM; + } + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { + return E_BAD_STATE; + } + + // if(!read | write) + // Start + // send addr w/ write bit + // if(Write) + // send tx_len data + // return if error (or NACK) + // if(Read) + // if(Write) + // send restart + // else + // send start + // send addr w/ read bit + // read rx_len bytes acking all + // stop or restart + // return good or error + + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + i2c->inten0 = 0; + i2c->inten1 = 0; + + if ((req->rx_len == 0) || (req->tx_len != 0)) { + // Load the slave address with write bit set + i2c->fifo = (req->addr << 1) & ~0x1; + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + } + + while (req->tx_len > written) { + if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { + written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; + } + + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + req->tx_len = written; + MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + return E_COMM_ERR; + } + } + + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0); + + if (req->rx_len != 0) { + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } + else { + i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read + } + + MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); + + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + + while (req->rx_len > read) { + if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { + read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; + } + + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + req->rx_len = read; + MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + return E_COMM_ERR; + } + + if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { + if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } + else { + i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read + } + + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + } + + if (req->restart) { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + } + else { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + } + + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)); // Wait for Transaction to finish + while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)); // Wait for Transaction to finish + + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP; + + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + return E_COMM_ERR; + } + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req) +{ + int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*)(req->i2c)); + mxc_i2c_reva_regs_t* i2c = req->i2c; + + if (i2cNum < 0) { + return E_BAD_PARAM; + } + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { + return E_BAD_STATE; + } + + if (AsyncRequests[i2cNum] == NULL) { + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + return E_NOT_SUPPORTED; + } + + AsyncRequests[i2cNum] = (void*) req; + AsyncWritten[i2cNum] = 0; + AsyncRead[i2cNum] = 0; + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + if ((req->rx_len == 0) || (req->tx_len != 0)) { + i2c->fifo = (req->addr << 1) & ~0x1; // Load the slave address with write bit set + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; + } + + i2c->inten0 = MXC_I2C_REVA_ERROR | MXC_F_I2C_REVA_INTEN0_TX_THD; + return E_NO_ERROR; + } + else { + return E_BUSY; + } +} + +int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma) +{ + int i2cNum; + + mxc_i2c_reva_regs_t* i2c = req->i2c; // Save off pointer for faster access + i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + + if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) { + return E_NOT_SUPPORTED; + } + + if (i2cNum < 0) { + return E_BAD_PARAM; + } + + if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) { + return E_BAD_STATE; + } + + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + return E_BAD_PARAM; + } + + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 2); + MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); + + states[i2cNum].req = req; + + states[i2cNum].channelTx = 0xFF; + states[i2cNum].channelRx = 0xFF; + + #if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + #else + MXC_DMA_Init(); + #endif + + //tx + if ((req->tx_buf != NULL) && !(states[i2cNum].writeDone)) { + i2c->fifo = ((req->addr) << 1) & ~0x1; // Load the slave address with write bit set + + #if TARGET_NUM == 32665 + MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL, dma); + #else + MXC_I2C_WriteTXFIFODMA ((mxc_i2c_regs_t*) i2c, req->tx_buf, req->tx_len, NULL); + #endif + } + else { + states[i2cNum].writeDone = 1; + } + + if (req->rx_buf != NULL) { + while(states[i2cNum].writeDone != 1); //Ensure DMA transmit has finished before attempting to receive + + if ( (states[i2cNum].writeDone) && (!states[i2cNum].readDone)) { + if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } + else { + i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read + } + + MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed + + while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART); + + i2c->fifo = ((req->addr) << 1) | 0x1; // Load the slave address with write bit set + + #if TARGET_NUM == 32665 + MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL, dma); + #else + MXC_I2C_ReadRXFIFODMA ((mxc_i2c_regs_t*) i2c, req->rx_buf, req->rx_len, NULL); + #endif + } + } + else { + states[i2cNum].readDone = 1; + } + + return E_NO_ERROR; +} + +void MXC_I2C_RevA_DMACallback(int ch, int error) +{ + mxc_i2c_reva_req_t *temp_req; + + for (int i = 0; i < MXC_I2C_INSTANCES; i ++) { + if (states[i].channelTx == ch) { + //save the request + temp_req = states[i].req; + states[i].writeDone = 1; + + if (states[i].readDone) { + if (temp_req->restart) { + (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + } + else { + (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + } + + MXC_DMA_ReleaseChannel(states[i].channelRx); + MXC_DMA_ReleaseChannel(states[i].channelTx); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_NO_ERROR); + } + } + } + + else if (states[i].channelRx == ch) { + //save the request + states[i].readDone = 1; + temp_req = states[i].req; + + if (states[i].writeDone) { + if (temp_req->restart) { + (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + } + else { + (temp_req->i2c)->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + } + + MXC_DMA_ReleaseChannel(states[i].channelRx); + MXC_DMA_ReleaseChannel(states[i].channelTx); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_NO_ERROR); + } + } + } + } +} + +int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +{ + unsigned int interruptEnables = interruptCheck; + int retVal = E_NO_ERROR; + + if (MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c) < 0) { + return E_BAD_PARAM; + } + + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { + return E_BAD_STATE; + } + + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + + // Callback called on + // Slave Address Match (distinguish read/write) + // RX Threshold + // TX Threshold + // Done + // TX Underflow + // RX Overflow + // + // Event Codes + // I2C_EVT_MASTER_WR + // I2C_EVT_MASTER_RD + // I2C_EVT_RX_THRESH + // I2C_EVT_TX_THRESH + // I2C_EVT_TRANS_COMP + // I2C_EVT_UNDERFLOW + // I2C_EVT_OVERFLOW + + while (interruptEnables > 0) { + interruptEnables = MXC_I2C_RevA_SlaveAsyncHandler(i2c, callback, interruptEnables, &retVal); + } + + return retVal; +} + +int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck) +{ + int i2cnum = MXC_I2C_GET_IDX((mxc_i2c_regs_t*) i2c); + + if (i2cnum < 0) { + return E_BAD_PARAM; + } + + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { + return E_BAD_STATE; + } + + if (AsyncRequests[i2cnum] != NULL) { + return E_BUSY; + } + + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_SetTXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set TX threshold to 2 bytes + MXC_I2C_SetRXThreshold ((mxc_i2c_regs_t*) i2c, 1); // set RX threshold to 6 bytes + AsyncRequests[i2cnum] = (void *) callback; + + i2c->inten0 = interruptCheck; + + return E_NO_ERROR; +} + +int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +{ + unsigned int rxFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS; + + if (numBytes > rxFIFOlen) { + return E_BAD_PARAM; + } + + i2c->rxctrl0 = (i2c->rxctrl0 & ~MXC_F_I2C_REVA_RXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS); + return E_NO_ERROR; +} + +unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c) +{ + return (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS; +} + +int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes) +{ + unsigned int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >> MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS; + + if (numBytes > txFIFOlen) { + return E_BAD_PARAM; + } + + i2c->txctrl0 = (i2c->txctrl0 & ~MXC_F_I2C_REVA_TXCTRL0_THD_LVL) | (numBytes << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS); + return E_NO_ERROR; +} + +unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c) +{ + return (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_THD_LVL) >> MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS; +} + +void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal) +{ + // Don't need to check for return value as this function is not accessible to user + // i2c is already cheked for NULL from where this function is being called + mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)]; + + if (req->callback != NULL) { + req->callback(req, retVal); + } +} + +void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c) +{ + i2c->inten0 = 0; + i2c->inten1 = 0; + + // Don't need to check for return value as this function is not accessible to user + // i2c is already cheked for NULL from where this function is being called + AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; +} + +void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c) +{ + // Don't need to check for return value as this function is not accessible to user + // i2c is already cheked for NULL from where this function is being called + MXC_I2C_RevA_AsyncCallback(i2c, E_ABORT); + MXC_I2C_RevA_AsyncStop(i2c); +} + +void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum) +{ + unsigned int written = AsyncWritten[i2cNum]; + unsigned int read = AsyncRead[i2cNum]; + mxc_i2c_reva_regs_t* i2c = (mxc_i2c_reva_regs_t*) MXC_I2C_GET_BASE (i2cNum); + mxc_i2c_reva_req_t* req = (mxc_i2c_reva_req_t*) AsyncRequests[i2cNum]; + + if (req->tx_len > written) { + if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) { + written += MXC_I2C_WriteTXFIFO ((mxc_i2c_regs_t*) i2c, &req->tx_buf[written], req->tx_len - written); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; + } + + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + req->tx_len = written; + MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); + MXC_I2C_RevA_AsyncStop (i2c); + } + } + + if (req->rx_len > read) { + if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) { + read += MXC_I2C_ReadRXFIFO ((mxc_i2c_regs_t*) i2c, &req->rx_buf[read], req->rx_len - read); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; + } + + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + req->rx_len = read; + MXC_I2C_Stop ((mxc_i2c_regs_t*) i2c); + MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); + MXC_I2C_RevA_AsyncStop (i2c); + } + + if ( (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len < read)) { + if ( (req->rx_len-read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } + else { + i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read + } + + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE; + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + } + + if ( (req->tx_len == written) && (read == 0)) { + i2c->inten0 &= ~MXC_F_I2C_REVA_INTEN0_TX_THD; + i2c->inten0 |= MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE; + + if ( (req->rx_len) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) { + i2c->rxctrl1 = 0; + } + else { + i2c->rxctrl1 = (req->rx_len); // 0 for 256, otherwise number of bytes to read + } + + MXC_I2C_Start ((mxc_i2c_regs_t*) i2c); // Start or Restart as needed + + i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit. + } + + if ( (req->tx_len == written) && (req->rx_len == read)) { + i2c->inten0 &= ~ (MXC_F_I2C_REVA_INTEN0_RX_THD | MXC_F_I2C_REVA_INTEN0_DONE); + + if (req->restart) { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART; + } + else { + i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP; + } + + if (i2c->intfl0 & MXC_I2C_REVA_ERROR) { + MXC_I2C_RevA_AsyncCallback (i2c, E_COMM_ERR); + } + else { + MXC_I2C_RevA_AsyncCallback(i2c, E_NO_ERROR); + } + + MXC_I2C_RevA_AsyncStop(i2c); + } + + AsyncWritten[i2cNum] = written; + AsyncRead[i2cNum] = read; +} + +unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal) +{ + uint32_t tFlags = i2c->intfl0; + *retVal = E_NO_ERROR; + + uint32_t readFlag = i2c->ctrl & MXC_F_I2C_REVA_CTRL_READ; + // Callback called on + // Slave Address Match (distinguish read/write) + // RX Threshold + // TX Threshold + // Done + // TX Underflow + // RX Overflow + // + // Event Codes + // I2C_EVT_MASTER_WR + // I2C_EVT_MASTER_RD + // I2C_EVT_RX_THRESH + // I2C_EVT_TX_THRESH + // I2C_EVT_TRANS_COMP + // I2C_EVT_UNDERFLOW + // I2C_EVT_OVERFLOW + if (!(interruptEnables & (MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH | MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH| MXC_F_I2C_REVA_INTFL0_ADDR_MATCH))) { + // The STOPERR/STARTERR interrupt that's enabled here could fire before we are addressed + // (fires anytime a stop/start is detected out of sequence). + if (tFlags & MXC_I2C_REVA_ERROR) { + *retVal = E_COMM_ERR; + callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + MXC_I2C_ClearFlags ((mxc_i2c_regs_t*) i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts + MXC_I2C_ClearTXFIFO ((mxc_i2c_regs_t*) i2c); + MXC_I2C_ClearRXFIFO ((mxc_i2c_regs_t*) i2c); + interruptEnables = 0; + AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + } + + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV)) { + if (tFlags & MXC_F_I2C_REVA_INTFL0_RX_THD) { + callback (i2c, MXC_I2C_REVA_EVT_RX_THRESH, NULL); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD; + } + + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_RX_OV) { + callback (i2c, MXC_I2C_REVA_EVT_OVERFLOW, NULL); + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_RX_OV; + } + } + + if (interruptEnables & (MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT)) { + if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_THD) { + callback (i2c, MXC_I2C_REVA_EVT_TX_THRESH, NULL); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD; + } + + if (i2c->intfl1 & MXC_F_I2C_REVA_INTFL1_TX_UN) { + callback (i2c, MXC_I2C_REVA_EVT_UNDERFLOW, NULL); + i2c->intfl1 = MXC_F_I2C_REVA_INTFL1_TX_UN; + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT) { + *retVal = E_NO_ERROR; + callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT; + interruptEnables = 0; + AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + } + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_STOP) { + *retVal = E_NO_ERROR; + callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_STOP; + interruptEnables = 0; + AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + } + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH) { + callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH) { + callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } + + if (tFlags & MXC_F_I2C_REVA_INTFL0_ADDR_MATCH){ + if (readFlag & MXC_F_I2C_REVA_CTRL_READ) { + callback (i2c, MXC_I2C_REVA_EVT_MASTER_RD, NULL); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_TX_THD | MXC_F_I2C_REVA_INTFL1_TX_UN | MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT | MXC_I2C_REVA_ERROR; + } + else { + callback (i2c, MXC_I2C_REVA_EVT_MASTER_WR, NULL); + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_ADDR_MATCH; + interruptEnables = MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL1_RX_OV | MXC_I2C_REVA_ERROR; + } + } else if (tFlags & MXC_I2C_REVA_ERROR) { + *retVal = E_COMM_ERR; + callback (i2c, MXC_I2C_REVA_EVT_TRANS_COMP, retVal); + MXC_I2C_RevA_ClearFlags(i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK); // clear all i2c interrupts + MXC_I2C_RevA_ClearTXFIFO(i2c); + MXC_I2C_RevA_ClearRXFIFO(i2c); + interruptEnables = 0; + AsyncRequests[MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c)] = NULL; + } + + return interruptEnables; +} + +void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck) +{ + int i2cNum = MXC_I2C_GET_IDX ((mxc_i2c_regs_t*) i2c); + int slaveRetVal; + + if (i2cNum < 0) { + return; + } + + if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE) { + MXC_I2C_RevA_MasterAsyncHandler (i2cNum); + } + else { + mxc_i2c_reva_slave_handler_t callback = (mxc_i2c_reva_slave_handler_t) AsyncRequests[i2cNum]; + i2c->inten0 = MXC_I2C_RevA_SlaveAsyncHandler (i2c, callback, i2c->inten0, &slaveRetVal); + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h new file mode 100644 index 00000000000..c32f66eb711 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva.h @@ -0,0 +1,157 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#ifndef _I2C_REVA_H_ +#define _I2C_REVA_H_ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "i2c_regs.h" +#include "i2c_reva_regs.h" +#include "dma.h" + + +/* **** Definitions **** */ +#define MXC_I2C_REVA_MAX_ADDR_WIDTH 0x7F +#define MXC_I2C_REVA_STD_MODE 100000 +#define MXC_I2C_REVA_FAST_SPEED 400000 +#define MXC_I2C_REVA_FASTPLUS_SPEED 1000000 +#define MXC_I2C_REVA_HS_MODE 3400000 + +#define MXC_I2C_REVA_INTFL0_MASK 0x00FFFFFF +#define MXC_I2C_REVA_INTFL1_MASK 0x00000007 + +#define MXC_I2C_REVA_MAX_FIFO_TRANSACTION 256 + +#define MXC_I2C_REVA_ERROR (MXC_F_I2C_REVA_INTFL0_ARB_ERR | MXC_F_I2C_REVA_INTFL0_TO_ERR | MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR | \ + MXC_F_I2C_REVA_INTFL0_DATA_ERR | MXC_F_I2C_REVA_INTFL0_DNR_ERR | MXC_F_I2C_REVA_INTFL0_START_ERR | \ + MXC_F_I2C_REVA_INTFL0_STOP_ERR) + +typedef struct _i2c_reva_req_t mxc_i2c_reva_req_t; +typedef int (*mxc_i2c_reva_getAck_t) (mxc_i2c_reva_regs_t* i2c, unsigned char byte); +typedef void (*mxc_i2c_reva_complete_cb_t) (mxc_i2c_reva_req_t* req, int result); +typedef void (*mxc_i2c_reva_dma_complete_cb_t) (int len, int result); +struct _i2c_reva_req_t { + mxc_i2c_reva_regs_t* i2c; + unsigned int addr; + unsigned char* tx_buf; + unsigned int tx_len; + unsigned char* rx_buf; + unsigned int rx_len; + int restart; + mxc_i2c_reva_complete_cb_t callback; +}; +typedef enum { + MXC_I2C_REVA_EVT_MASTER_WR, + MXC_I2C_REVA_EVT_MASTER_RD, + MXC_I2C_REVA_EVT_RX_THRESH, + MXC_I2C_REVA_EVT_TX_THRESH, + MXC_I2C_REVA_EVT_TRANS_COMP, + MXC_I2C_REVA_EVT_UNDERFLOW, + MXC_I2C_REVA_EVT_OVERFLOW, +} mxc_i2c_reva_slave_event_t; +typedef int (*mxc_i2c_reva_slave_handler_t) (mxc_i2c_reva_regs_t* i2c, + mxc_i2c_reva_slave_event_t event, void* data); +/* **** Variable Declaration **** */ + +/* **** Function Prototypes **** */ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ +int MXC_I2C_RevA_Init (mxc_i2c_reva_regs_t* i2c, int masterMode, unsigned int slaveAddr); +int MXC_I2C_RevA_SetSlaveAddr (mxc_i2c_reva_regs_t* i2c, unsigned int slaveAddr, int idx); +int MXC_I2C_RevA_Shutdown (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_SetFrequency (mxc_i2c_reva_regs_t* i2c, unsigned int hz); +unsigned int MXC_I2C_RevA_GetFrequency (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_ReadyForSleep (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_SetClockStretching (mxc_i2c_reva_regs_t* i2c, int enable); +int MXC_I2C_RevA_GetClockStretching (mxc_i2c_reva_regs_t* i2c); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ +int MXC_I2C_RevA_Start (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_Stop (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_WriteByte (mxc_i2c_reva_regs_t* i2c, unsigned char byte); +int MXC_I2C_RevA_ReadByte (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, int ack); +int MXC_I2C_RevA_ReadByteInteractive (mxc_i2c_reva_regs_t* i2c, unsigned char* byte, mxc_i2c_reva_getAck_t getAck); +int MXC_I2C_RevA_Write (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len); +int MXC_I2C_RevA_Read (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int* len, int ack); +int MXC_I2C_RevA_ReadRXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); +int MXC_I2C_RevA_ReadRXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); +int MXC_I2C_RevA_GetRXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_WriteTXFIFO (mxc_i2c_reva_regs_t* i2c, volatile unsigned char* bytes, unsigned int len); +int MXC_I2C_RevA_WriteTXFIFODMA (mxc_i2c_reva_regs_t* i2c, unsigned char* bytes, unsigned int len, mxc_i2c_reva_dma_complete_cb_t callback, mxc_dma_config_t config, mxc_dma_regs_t* dma); +int MXC_I2C_RevA_GetTXFIFOAvailable (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_ClearRXFIFO (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_ClearTXFIFO (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_GetFlags (mxc_i2c_reva_regs_t* i2c, unsigned int *flags0, unsigned int *flags1); +void MXC_I2C_RevA_ClearFlags (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_DisableInt (mxc_i2c_reva_regs_t* i2c, unsigned int flags0, unsigned int flags1); +void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_EnableGeneralCall (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_DisableGeneralCall (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_SetTimeout (mxc_i2c_reva_regs_t* i2c, unsigned int timeout); +unsigned int MXC_I2C_RevA_GetTimeout (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_Recover (mxc_i2c_reva_regs_t* i2c, unsigned int retries); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ +int MXC_I2C_RevA_MasterTransaction (mxc_i2c_reva_req_t* req); +int MXC_I2C_RevA_MasterTransactionAsync (mxc_i2c_reva_req_t* req); +int MXC_I2C_RevA_MasterTransactionDMA (mxc_i2c_reva_req_t* req, mxc_dma_regs_t* dma); +int MXC_I2C_RevA_SlaveTransaction (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); +int MXC_I2C_RevA_SlaveTransactionAsync (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, uint32_t interruptCheck); +int MXC_I2C_RevA_SetRXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetRXThreshold (mxc_i2c_reva_regs_t* i2c); +int MXC_I2C_RevA_SetTXThreshold (mxc_i2c_reva_regs_t* i2c, unsigned int numBytes); +unsigned int MXC_I2C_RevA_GetTXThreshold (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_AsyncCallback (mxc_i2c_reva_regs_t* i2c, int retVal); +void MXC_I2C_RevA_AsyncStop (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_AbortAsync (mxc_i2c_reva_regs_t* i2c); +void MXC_I2C_RevA_MasterAsyncHandler (int i2cNum); +unsigned int MXC_I2C_RevA_SlaveAsyncHandler (mxc_i2c_reva_regs_t* i2c, mxc_i2c_reva_slave_handler_t callback, unsigned int interruptEnables, int* retVal); +void MXC_I2C_RevA_AsyncHandler (mxc_i2c_reva_regs_t* i2c, uint32_t interruptCheck); +void MXC_I2C_RevA_DMACallback (int ch, int error); + +#endif /* _I2C_REVA_H_ */ \ No newline at end of file diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h new file mode 100644 index 00000000000..d4a3ee29813 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/I2C/i2c_reva_regs.h @@ -0,0 +1,580 @@ +/** + * @file i2c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _I2C_REVA_REGS_H_ +#define _I2C_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2c + * @defgroup i2c_registers I2C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @details Inter-Integrated Circuit. + */ + +/** + * @ingroup i2c_registers + * Structure type to access the I2C Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: I2C CTRL Register */ + __IO uint32_t status; /**< \b 0x04: I2C STATUS Register */ + __IO uint32_t intfl0; /**< \b 0x08: I2C INTFL0 Register */ + __IO uint32_t inten0; /**< \b 0x0C: I2C INTEN0 Register */ + __IO uint32_t intfl1; /**< \b 0x10: I2C INTFL1 Register */ + __IO uint32_t inten1; /**< \b 0x14: I2C INTEN1 Register */ + __IO uint32_t fifolen; /**< \b 0x18: I2C FIFOLEN Register */ + __IO uint32_t rxctrl0; /**< \b 0x1C: I2C RXCTRL0 Register */ + __IO uint32_t rxctrl1; /**< \b 0x20: I2C RXCTRL1 Register */ + __IO uint32_t txctrl0; /**< \b 0x24: I2C TXCTRL0 Register */ + __IO uint32_t txctrl1; /**< \b 0x28: I2C TXCTRL1 Register */ + __IO uint32_t fifo; /**< \b 0x2C: I2C FIFO Register */ + __IO uint32_t mstctrl; /**< \b 0x30: I2C MSTCTRL Register */ + __IO uint32_t clklo; /**< \b 0x34: I2C CLKLO Register */ + __IO uint32_t clkhi; /**< \b 0x38: I2C CLKHI Register */ + __IO uint32_t hsclk; /**< \b 0x3C: I2C HSCLK Register */ + __IO uint32_t timeout; /**< \b 0x40: I2C TIMEOUT Register */ + __R uint32_t rsv_0x44; + __IO uint32_t dma; /**< \b 0x48: I2C DMA Register */ + __IO uint32_t slave; /**< \b 0x4C: I2C SLAVE Register */ +} mxc_i2c_reva_regs_t; + +/* Register offsets for module I2C */ +/** + * @ingroup i2c_registers + * @defgroup I2C_Register_Offsets Register Offsets + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @{ + */ + #define MXC_R_I2C_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ + #define MXC_R_I2C_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ + #define MXC_R_I2C_REVA_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ + #define MXC_R_I2C_REVA_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ + #define MXC_R_I2C_REVA_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ + #define MXC_R_I2C_REVA_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ + #define MXC_R_I2C_REVA_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ + #define MXC_R_I2C_REVA_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ + #define MXC_R_I2C_REVA_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ + #define MXC_R_I2C_REVA_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ + #define MXC_R_I2C_REVA_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ + #define MXC_R_I2C_REVA_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ + #define MXC_R_I2C_REVA_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ + #define MXC_R_I2C_REVA_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ + #define MXC_R_I2C_REVA_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ + #define MXC_R_I2C_REVA_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ + #define MXC_R_I2C_REVA_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ + #define MXC_R_I2C_REVA_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ + #define MXC_R_I2C_REVA_SLAVE ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +/**@} end of group i2c_registers */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CTRL I2C_CTRL + * @brief Control Register0. + * @{ + */ + #define MXC_F_I2C_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ + #define MXC_F_I2C_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + + #define MXC_F_I2C_REVA_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ + #define MXC_F_I2C_REVA_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ + + #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ + #define MXC_F_I2C_REVA_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ + + #define MXC_F_I2C_REVA_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ + #define MXC_F_I2C_REVA_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ + + #define MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ + #define MXC_F_I2C_REVA_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ + + #define MXC_F_I2C_REVA_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ + #define MXC_F_I2C_REVA_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ + + #define MXC_F_I2C_REVA_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ + #define MXC_F_I2C_REVA_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ + + #define MXC_F_I2C_REVA_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ + #define MXC_F_I2C_REVA_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ + + #define MXC_F_I2C_REVA_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ + #define MXC_F_I2C_REVA_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ + + #define MXC_F_I2C_REVA_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ + #define MXC_F_I2C_REVA_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ + + #define MXC_F_I2C_REVA_CTRL_READ_POS 11 /**< CTRL_READ Position */ + #define MXC_F_I2C_REVA_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_READ_POS)) /**< CTRL_READ Mask */ + + #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ + #define MXC_F_I2C_REVA_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ + + #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ + #define MXC_F_I2C_REVA_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ + + #define MXC_F_I2C_REVA_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ + #define MXC_F_I2C_REVA_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ + +/**@} end of group I2C_CTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_STATUS I2C_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_I2C_REVA_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ + #define MXC_F_I2C_REVA_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + + #define MXC_F_I2C_REVA_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ + #define MXC_F_I2C_REVA_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ + + #define MXC_F_I2C_REVA_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ + #define MXC_F_I2C_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + + #define MXC_F_I2C_REVA_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ + #define MXC_F_I2C_REVA_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ + + #define MXC_F_I2C_REVA_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ + #define MXC_F_I2C_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + + #define MXC_F_I2C_REVA_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ + #define MXC_F_I2C_REVA_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ + +/**@} end of group I2C_STATUS_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTFL0 I2C_INTFL0 + * @brief Interrupt Status Register. + * @{ + */ + #define MXC_F_I2C_REVA_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ + #define MXC_F_I2C_REVA_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ + + #define MXC_F_I2C_REVA_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ + #define MXC_F_I2C_REVA_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ + + #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ + + #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ + + #define MXC_F_I2C_REVA_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ + #define MXC_F_I2C_REVA_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ + + #define MXC_F_I2C_REVA_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ + #define MXC_F_I2C_REVA_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ + + #define MXC_F_I2C_REVA_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ + #define MXC_F_I2C_REVA_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ + + #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ + #define MXC_F_I2C_REVA_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ + + #define MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ + #define MXC_F_I2C_REVA_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ + + #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ + #define MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ + + #define MXC_F_I2C_REVA_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ + #define MXC_F_I2C_REVA_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ + + #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ + + #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ + +/**@} end of group I2C_INTFL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTEN0 I2C_INTEN0 + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_I2C_REVA_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ + #define MXC_F_I2C_REVA_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ + + #define MXC_F_I2C_REVA_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ + #define MXC_F_I2C_REVA_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ + + #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ + + #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ + + #define MXC_F_I2C_REVA_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ + #define MXC_F_I2C_REVA_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ + + #define MXC_F_I2C_REVA_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ + #define MXC_F_I2C_REVA_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ + + #define MXC_F_I2C_REVA_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ + #define MXC_F_I2C_REVA_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ + + #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ + #define MXC_F_I2C_REVA_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ + + #define MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ + #define MXC_F_I2C_REVA_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ + + #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ + #define MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ + + #define MXC_F_I2C_REVA_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ + #define MXC_F_I2C_REVA_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_REVA_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ + + #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ + + #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ + #define MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ + +/**@} end of group I2C_INTEN0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTFL1 I2C_INTFL1 + * @brief Interrupt Status Register 1. + * @{ + */ + #define MXC_F_I2C_REVA_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ + #define MXC_F_I2C_REVA_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ + + #define MXC_F_I2C_REVA_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ + #define MXC_F_I2C_REVA_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ + + #define MXC_F_I2C_REVA_INTFL1_START_POS 2 /**< INTFL1_START Position */ + #define MXC_F_I2C_REVA_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTFL1_START_POS)) /**< INTFL1_START Mask */ + +/**@} end of group I2C_INTFL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTEN1 I2C_INTEN1 + * @brief Interrupt Staus Register 1. + * @{ + */ + #define MXC_F_I2C_REVA_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ + #define MXC_F_I2C_REVA_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ + + #define MXC_F_I2C_REVA_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ + #define MXC_F_I2C_REVA_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ + + #define MXC_F_I2C_REVA_INTEN1_START_POS 2 /**< INTEN1_START Position */ + #define MXC_F_I2C_REVA_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_INTEN1_START_POS)) /**< INTEN1_START Mask */ + +/**@} end of group I2C_INTEN1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFOLEN I2C_FIFOLEN + * @brief FIFO Configuration Register. + * @{ + */ + #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ + #define MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ + + #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ + #define MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ + +/**@} end of group I2C_FIFOLEN_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RXCTRL0 I2C_RXCTRL0 + * @brief Receive Control Register 0. + * @{ + */ + #define MXC_F_I2C_REVA_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ + #define MXC_F_I2C_REVA_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ + + #define MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ + #define MXC_F_I2C_REVA_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ + + #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ + #define MXC_F_I2C_REVA_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ + +/**@} end of group I2C_RXCTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RXCTRL1 I2C_RXCTRL1 + * @brief Receive Control Register 1. + * @{ + */ + #define MXC_F_I2C_REVA_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ + #define MXC_F_I2C_REVA_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ + + #define MXC_F_I2C_REVA_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ + #define MXC_F_I2C_REVA_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ + +/**@} end of group I2C_RXCTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TXCTRL0 I2C_TXCTRL0 + * @brief Transmit Control Register 0. + * @{ + */ + #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ + #define MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ + #define MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ + #define MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ + #define MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ + #define MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ + #define MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ + #define MXC_F_I2C_REVA_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ + + #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS 8 /**< TXCTRL0_THD_LVL Position */ + #define MXC_F_I2C_REVA_TXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL0_THD_LVL_POS)) /**< TXCTRL0_THD_LVL Mask */ + +/**@} end of group I2C_TXCTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TXCTRL1 I2C_TXCTRL1 + * @brief Transmit Control Register 1. + * @{ + */ + #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ + #define MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_REVA_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ + + #define MXC_F_I2C_REVA_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ + #define MXC_F_I2C_REVA_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_REVA_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ + +/**@} end of group I2C_TXCTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO I2C_FIFO + * @brief Data Register. + * @{ + */ + #define MXC_F_I2C_REVA_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ + #define MXC_F_I2C_REVA_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group I2C_FIFO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_MSTCTRL I2C_MSTCTRL + * @brief Master Control Register. + * @{ + */ + #define MXC_F_I2C_REVA_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ + #define MXC_F_I2C_REVA_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ + + #define MXC_F_I2C_REVA_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ + #define MXC_F_I2C_REVA_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ + + #define MXC_F_I2C_REVA_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ + #define MXC_F_I2C_REVA_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ + + #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ + #define MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ + +/**@} end of group I2C_MSTCTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLKLO I2C_CLKLO + * @brief Clock Low Register. + * @{ + */ + #define MXC_F_I2C_REVA_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ + #define MXC_F_I2C_REVA_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ + +/**@} end of group I2C_CLKLO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLKHI I2C_CLKHI + * @brief Clock high Register. + * @{ + */ + #define MXC_F_I2C_REVA_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ + #define MXC_F_I2C_REVA_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_REVA_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ + +/**@} end of group I2C_CLKHI_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_HSCLK I2C_HSCLK + * @brief Clock high Register. + * @{ + */ + #define MXC_F_I2C_REVA_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ + #define MXC_F_I2C_REVA_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ + + #define MXC_F_I2C_REVA_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ + #define MXC_F_I2C_REVA_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_REVA_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ + +/**@} end of group I2C_HSCLK_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TIMEOUT I2C_TIMEOUT + * @brief Timeout Register + * @{ + */ + #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ + #define MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_REVA_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ + +/**@} end of group I2C_TIMEOUT_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_DMA I2C_DMA + * @brief DMA Register. + * @{ + */ + #define MXC_F_I2C_REVA_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ + #define MXC_F_I2C_REVA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + + #define MXC_F_I2C_REVA_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ + #define MXC_F_I2C_REVA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + +/**@} end of group I2C_DMA_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_SLAVE I2C_SLAVE + * @brief Slave Address Register. + * @{ + */ + #define MXC_F_I2C_REVA_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ + #define MXC_F_I2C_REVA_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_REVA_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ + + #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ + #define MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_REVA_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ + +/**@} end of group I2C_SLAVE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _I2C_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c new file mode 100644 index 00000000000..7a2c66485bb --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.c @@ -0,0 +1,46 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "icc.h" +#include "icc_reva.h" + +void MXC_ICC_Com_Flush(void) +{ + MXC_ICC_Disable(); + MXC_ICC_Enable(); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h new file mode 100644 index 00000000000..72e18408385 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_common.h @@ -0,0 +1,50 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Flush the instruction cache controller. + */ +void MXC_ICC_Com_Flush(void); + +/**@} end of group icc */ + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c new file mode 100644 index 00000000000..f5565a426a4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_me11.c @@ -0,0 +1,63 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "icc.h" +#include "icc_reva.h" +#include "icc_common.h" + +/* **** Functions **** */ + +int MXC_ICC_ID (mxc_icc_info_t cid) +{ + return MXC_ICC_RevA_ID ((mxc_icc_reva_regs_t*) MXC_ICC, cid); +} + +void MXC_ICC_Enable (void) +{ + MXC_ICC_RevA_Enable ((mxc_icc_reva_regs_t*) MXC_ICC); +} + +void MXC_ICC_Disable (void) +{ + MXC_ICC_RevA_Disable ((mxc_icc_reva_regs_t*) MXC_ICC); +} + +void MXC_ICC_Flush (void) +{ + MXC_ICC_Com_Flush(); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c new file mode 100644 index 00000000000..5852ec4dd55 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.c @@ -0,0 +1,91 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "icc.h" +#include "icc_reva_regs.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ +static int MXC_ICC_Ready(mxc_icc_reva_regs_t* icc) +{ + return (icc->ctrl & MXC_F_ICC_REVA_CTRL_RDY); +} + +int MXC_ICC_RevA_ID(mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid) +{ + if(icc == NULL) { + return E_NULL_PTR; + } + + switch(cid) { + case ICC_INFO_RELNUM: + return ((icc->info & MXC_F_ICC_REVA_INFO_RELNUM) >> MXC_F_ICC_REVA_INFO_RELNUM_POS); + + case ICC_INFO_PARTNUM: + return ((icc->info & MXC_F_ICC_REVA_INFO_PARTNUM) >> MXC_F_ICC_REVA_INFO_PARTNUM_POS); + + case ICC_INFO_ID: + return ((icc->info & MXC_F_ICC_REVA_INFO_ID) >> MXC_F_ICC_REVA_INFO_ID_POS); + + default: + return E_BAD_PARAM; + } +} + +void MXC_ICC_RevA_Enable(mxc_icc_reva_regs_t *icc) +{ + // Invalidate cache and wait until ready + icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; + icc->invalidate = 1; + + while(!(MXC_ICC_Ready(icc))); + + // Enable Cache + icc->ctrl |= MXC_F_ICC_REVA_CTRL_EN; + while(!(MXC_ICC_Ready(icc))); +} + +void MXC_ICC_RevA_Disable(mxc_icc_reva_regs_t* icc) +{ + // Disable Cache + icc->ctrl &= ~MXC_F_ICC_REVA_CTRL_EN; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h new file mode 100644 index 00000000000..9cda9cdcaa9 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva.h @@ -0,0 +1,50 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software");, + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "icc.h" +#include "icc_reva_regs.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +int MXC_ICC_RevA_ID (mxc_icc_reva_regs_t* icc, mxc_icc_info_t cid); +void MXC_ICC_RevA_Enable (mxc_icc_reva_regs_t* icc); +void MXC_ICC_RevA_Disable (mxc_icc_reva_regs_t* icc); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h new file mode 100644 index 00000000000..dcdcad947e6 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/ICC/icc_reva_regs.h @@ -0,0 +1,159 @@ +/** + * @file icc_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _ICC_REVA_REGS_H_ +#define _ICC_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc_reva + * @defgroup icc_reva_registers ICC_REVA_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC_REVA Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_reva_registers + * Structure type to access the ICC_REVA Registers. + */ +typedef struct { + __I uint32_t info; /**< \b 0x0000: ICC_REVA INFO Register */ + __I uint32_t sz; /**< \b 0x0004: ICC_REVA SZ Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t ctrl; /**< \b 0x0100: ICC_REVA CTRL Register */ + __R uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC_REVA INVALIDATE Register */ +} mxc_icc_reva_regs_t; + +/* Register offsets for module ICC_REVA */ +/** + * @ingroup icc_reva_registers + * @defgroup ICC_REVA_Register_Offsets Register Offsets + * @brief ICC_REVA Peripheral Register Offsets from the ICC_REVA Base Peripheral Address. + * @{ + */ + #define MXC_R_ICC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC_REVA Base Address: 0x0000 */ + #define MXC_R_ICC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC_REVA Base Address: 0x0004 */ + #define MXC_R_ICC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC_REVA Base Address: 0x0100 */ + #define MXC_R_ICC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC_REVA Base Address: 0x0700 */ +/**@} end of group icc_reva_registers */ + +/** + * @ingroup icc_reva_registers + * @defgroup ICC_REVA_INFO ICC_REVA_INFO + * @brief Cache ID Register. + * @{ + */ + #define MXC_F_ICC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ + #define MXC_F_ICC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ + + #define MXC_F_ICC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ + #define MXC_F_ICC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ + + #define MXC_F_ICC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ + #define MXC_F_ICC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ + +/**@} end of group ICC_REVA_INFO_Register */ + +/** + * @ingroup icc_reva_registers + * @defgroup ICC_REVA_SZ ICC_REVA_SZ + * @brief Memory Configuration Register. + * @{ + */ + #define MXC_F_ICC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ + #define MXC_F_ICC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ + + #define MXC_F_ICC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ + #define MXC_F_ICC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ + +/**@} end of group ICC_REVA_SZ_Register */ + +/** + * @ingroup icc_reva_registers + * @defgroup ICC_REVA_CTRL ICC_REVA_CTRL + * @brief Cache Control and Status Register. + * @{ + */ + #define MXC_F_ICC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ + #define MXC_F_ICC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + + #define MXC_F_ICC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ + #define MXC_F_ICC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +/**@} end of group ICC_REVA_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c new file mode 100644 index 00000000000..7f7d7ae7f6f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/LP/lp_me11.c @@ -0,0 +1,395 @@ +/** + * @file lp.c + * @brief Low power functions + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + + +/***** Includes *****/ +#include "lp.h" +#include "pwrseq_regs.h" +#include "mxc_errors.h" +#include "gcr_regs.h" +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_pins.h" +#include "mxc_sys.h" +#include "flc.h" +#include "mxc_delay.h" + +/***** Functions *****/ +void MXC_LP_ClearWakeStatus(void) +{ + MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF; + + /* These flags are slow to clear, so block until they do */ + while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en)); +} + +void MXC_LP_EnableSRAM3(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF; +} + +void MXC_LP_DisableSRAM3(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF; +} + +void MXC_LP_EnableSRAM2(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF; +} + +void MXC_LP_DisableSRAM2(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF; +} + +void MXC_LP_EnableSRAM1(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF; +} + +void MXC_LP_DisableSRAM1(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF; +} + +void MXC_LP_EnableSRAM0(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF; +} + +void MXC_LP_DisableSRAM0(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF; +} + +void MXC_LP_EnableICacheLightSleep(void) +{ + MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_ICACHE_RET); +} + +void MXC_LP_DisableICacheLightSleep(void) +{ + MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_ICACHE_RET); +} + +void MXC_LP_EnableSysRAM3LightSleep(void) +{ + MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM3_LS); +} + +void MXC_LP_DisableSysRAM3LightSleep(void) +{ + MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM3_LS); +} + +void MXC_LP_EnableSysRAM2LightSleep(void) +{ + MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM2_LS); +} + +void MXC_LP_DisableSysRAM2LightSleep(void) +{ + MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM2_LS); +} + +void MXC_LP_EnableSysRAM1LightSleep(void) +{ + MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM1_LS); +} + +void MXC_LP_DisableSysRAM1LightSleep(void) +{ + MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM1_LS); +} + +void MXC_LP_EnableSysRAM0LightSleep(void) +{ + MXC_GCR->mem_ctrl |= (MXC_F_GCR_MEM_CTRL_RAM0_LS); +} + +void MXC_LP_DisableSysRAM0LightSleep(void) +{ + MXC_GCR->mem_ctrl &= ~(MXC_F_GCR_MEM_CTRL_RAM0_LS); +} + +void MXC_LP_EnableRTCAlarmWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_RTCWK_EN; +} + +void MXC_LP_DisableRTCAlarmWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWK_EN; +} + +void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWK_EN; + //switch(port) + //{ + /*case 0:*/ MXC_PWRSEQ->lpwk_en |= mask; //break; + //} +} + +void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask) +{ + //switch(port) + //{ + /* case 0:*/ MXC_PWRSEQ->lpwk_en &= ~mask; //break; + //} + + if(MXC_PWRSEQ->lpwk_en == 0) + { + MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWK_EN; + } +} + +void MXC_LP_EnterSleepMode(void) +{ + // Clear SLEEPDEEP bit + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + // Go into Sleep mode and wait for an interrupt to wake the processor + __WFI(); +} + +void MXC_LP_EnterDeepSleepMode(void) +{ + // Set SLEEPDEEP bit + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + // Auto-powerdown 96 MHz oscillator when in deep sleep + MXC_GCR->pm |= MXC_F_GCR_PM_HFIOPD; + // Go into Deepsleep mode and wait for an interrupt to wake the processor + __WFI(); +} + +void MXC_LP_EnterBackupMode(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; + while(1); +} + +void MXC_LP_EnterShutdownMode(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN; + while(1); +} + +int MXC_LP_SetOperatingVoltage(mxc_lp_ovr_t ovr) +{ + uint32_t current_clock, div; + int error; + + // Ensure part is operating from internal LDO for core power + if(MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_LDO_DIS) { + return E_BAD_STATE; + } + + // Select the 8KHz nanoring (no guarantee 32KHz is attached) as system clock source + current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; + if(current_clock == MXC_SYS_CLOCK_HIRC) { + error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_NANORING); + if(error != E_NO_ERROR) { + return error; + } + } + + // Set flash wait state for any clock so its not to low after clock changes. + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x5UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + + // Set the OVR bits + MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR); + MXC_PWRSEQ->lp_ctrl |= ovr; + + // Set LVE bit + if(ovr == MXC_LP_OVR_0_9) { + MXC_FLC->ctrl |= MXC_F_FLC_CTRL_LVE; + + } else { + MXC_FLC->ctrl &= ~(MXC_F_FLC_CTRL_LVE); + } + + // Revert the clock to original state if it was HIRC + if(current_clock == MXC_SYS_CLOCK_HIRC) { + error = MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC); + if(error != E_NO_ERROR) { + return error; + } + } + + // Update SystemCoreClock variable + SystemCoreClockUpdate(); + + // Get the clock divider + div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; + + // Set Flash Wait States + if(ovr == MXC_LP_OVR_0_9) { + if(div == 0) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + + } else { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + } + + } else if(ovr == MXC_LP_OVR_1_0) { + if(div == 0) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + + } else { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + } + + } else { + if(div == 0) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x4UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + + } else if(div == 1) { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x2UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + + } else { + MXC_GCR->mem_ctrl = (MXC_GCR->mem_ctrl & ~(MXC_F_GCR_MEM_CTRL_FWS)) | (0x1UL << MXC_F_GCR_MEM_CTRL_FWS_POS); + } + } + + // Caller must perform peripheral reset + + return E_NO_ERROR; + +} + +void MXC_LP_EnableSRamRet0(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0; +} + +void MXC_LP_DisableSRamRet0(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0; +} + +void MXC_LP_EnableSRamRet1(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1; +} + +void MXC_LP_DisableSRamRet1(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1; +} + +void MXC_LP_EnableSRamRet2(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2; +} + +void MXC_LP_DisableSRamRet2(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2; +} + +void MXC_LP_EnableSRamRet3(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3; +} + +void MXC_LP_DisableSRamRet3(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3; +} + +void MXC_LP_EnableBlockDetect(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; +} + +void MXC_LP_DisableBlockDetect(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; +} + +void MXC_LP_EnableRamRetReg(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN; +} + +void MXC_LP_DisableRamRetReg(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN; +} + +void MXC_LP_EnableFastWk(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN; +} + +void MXC_LP_DisableFastWk(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN; +} + +void MXC_LP_EnableBandGap(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF; +} + +void MXC_LP_DisableBandGap(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF; +} + +void MXC_LP_EnableVCorePORSignal(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS; +} + +void MXC_LP_DisableVCorePORSignal(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS; +} + +void MXC_LP_EnableLDO(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS; +} + +void MXC_LP_DisableLDO(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS; +} + +void MXC_LP_EnableVCoreSVM(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS; +} + +void MXC_LP_DisableVCoreSVM(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS; +} + +void MXC_LP_EnableVDDIOPorMonitoF(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS; +} + +void MXC_LP_DisableVDDIOPorMonitor(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c new file mode 100644 index 00000000000..8dedda1a5fe --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_me11.c @@ -0,0 +1,119 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +#include "mxc_device.h" +#include "rtc_regs.h" +#include "rtc.h" +#include "mxc_sys.h" +#include "mxc_pins.h" +#include "mxc_delay.h" +#include "gpio_regs.h" +#include "mxc_errors.h" +#include "rtc_reva.h" + +/* ***** Functions ***** */ + +int MXC_RTC_EnableInt (uint32_t mask) +{ + return MXC_RTC_RevA_EnableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask); +} + +int MXC_RTC_DisableInt (uint32_t mask) +{ + return MXC_RTC_RevA_DisableInt ((mxc_rtc_reva_regs_t*) MXC_RTC, mask); +} + +int MXC_RTC_SetTimeofdayAlarm (uint32_t ras) +{ + return MXC_RTC_RevA_SetTimeofdayAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, ras); +} + +int MXC_RTC_SetSubsecondAlarm (uint32_t rssa) +{ + return MXC_RTC_RevA_SetSubsecondAlarm ((mxc_rtc_reva_regs_t*) MXC_RTC, rssa); +} + +int MXC_RTC_Start (void) +{ + return MXC_RTC_RevA_Start ((mxc_rtc_reva_regs_t*) MXC_RTC); +} + +int MXC_RTC_Stop (void) +{ + return MXC_RTC_RevA_Stop ((mxc_rtc_reva_regs_t*) MXC_RTC); +} + +int MXC_RTC_Init (uint32_t sec, uint8_t ssec) +{ + // Enable clock + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; + + return MXC_RTC_RevA_Init ((mxc_rtc_reva_regs_t*) MXC_RTC, sec, ssec); +} + +int MXC_RTC_SquareWave (mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +{ + MXC_GPIO_Config (&gpio_cfg_32kcal); + + return MXC_RTC_RevA_SquareWave ((mxc_rtc_reva_regs_t*) MXC_RTC, sqe, ft); +} + +int MXC_RTC_Trim (int8_t trm) +{ + return MXC_RTC_RevA_Trim ((mxc_rtc_reva_regs_t*) MXC_RTC, trm); +} + +int MXC_RTC_GetFlags (void) +{ + return MXC_RTC_RevA_GetFlags(); +} + +int MXC_RTC_ClearFlags (int flags) +{ + return MXC_RTC_RevA_ClearFlags (flags); +} + +int MXC_RTC_GetSubSecond (void) +{ + return MXC_RTC_RevA_GetSubSecond(); +} + +int MXC_RTC_GetSecond (void) +{ + return MXC_RTC_RevA_GetSecond(); +} + +int MXC_RTC_GetTime (uint32_t* sec, uint32_t* subsec) +{ + return MXC_RTC_RevA_GetTime (sec, subsec); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c new file mode 100644 index 00000000000..6719a4bc433 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.c @@ -0,0 +1,374 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +#include +#include "mxc_device.h" +#include "rtc.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gpio_regs.h" +#include "mxc_errors.h" +#include "rtc_reva.h" + +#if TARGET_NUM == 32650 + #include "pwrseq_regs.h" +#endif + +int MXC_RTC_CheckBusy(void) +{ + // Time-out transfer if it takes > BUSY_TIMEOUT microseconds + MXC_DelayAsync(MXC_DELAY_USEC(MXC_BUSY_TIMEOUT), NULL); + + while (MXC_RTC_REVA_IS_BUSY) { + if (MXC_DelayCheck() != E_BUSY) { + return E_BUSY; + } + } + + MXC_DelayAbort(); + return E_SUCCESS; +} + +int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask) +{ + mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); + + if (!mask) { + /* No bits set? Wasn't something we can enable. */ + return E_BAD_PARAM; + } + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= mask; + + return E_SUCCESS; +} + +int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask) +{ + mask &= (MXC_RTC_INT_EN_LONG | MXC_RTC_INT_EN_SHORT | MXC_RTC_INT_EN_READY); + + if (!mask) { + /* No bits set? Wasn't something we can enable. */ + return E_BAD_PARAM; + } + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~mask; + + return E_SUCCESS; +} + +int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras) +{ + // ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0); + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->toda = (ras << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS) & MXC_F_RTC_REVA_TODA_TOD_ALARM; + + return E_SUCCESS; +} + +int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa) +{ + // ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0); + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->sseca = (rssa << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_REVA_SSECA_SSEC_ALARM; + + return E_SUCCESS; +} + +int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc) +{ + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + // Can only write if WE=1 and BUSY=0 + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 1 + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + + return E_SUCCESS; +} + +int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc) +{ + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + // Can only write if WE=1 and BUSY=0 + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_EN; // setting RTCE = 0 + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + + return E_SUCCESS; +} + +int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec) +{ + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl = MXC_F_RTC_REVA_CTRL_WR_EN; // Allow Writes + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl = MXC_RTC_REVA_CTRL_RESET_DEFAULT; // Start with a Clean Register + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Set Write Enable, allow writing to reg. + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ssec = ssec; + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->sec = sec; + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Prevent Writing... + + return E_SUCCESS; +} + +int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft) +{ + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; // Allow writing to registers + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + if (sqe == MXC_RTC_REVA_SQUARE_WAVE_ENABLED) { + if (ft == MXC_RTC_F_32KHZ) { // if 32KHz output is selected... + rtc->oscctrl |= MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Enable 32KHz wave + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_SQW_EN; // Enable output on the pin + } + else { // if 1Hz, 512Hz, 4KHz output is selected + + rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~ MXC_F_RTC_REVA_CTRL_SQW_SEL; + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= (MXC_F_RTC_REVA_CTRL_SQW_EN | ft); // Enable Sq. wave, + } + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_EN; // Enable Real Time Clock + } + else { // Turn off the square wave output on the pin + + rtc->oscctrl &= ~MXC_F_RTC_REVA_OSCCTRL_SQW_32K; // Must make sure that the 32KHz is disabled + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_SQW_EN; // No sq. wave output + } + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register + + return E_SUCCESS; +} + +int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trim) +{ + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_REVA_CTRL_WR_EN; + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + MXC_SETFIELD (rtc->trim, MXC_F_RTC_REVA_TRIM_TRIM, trim << MXC_F_RTC_REVA_TRIM_TRIM_POS); + + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_REVA_CTRL_WR_EN; // Disable Writing to register + + return E_SUCCESS; +} + +int MXC_RTC_RevA_GetFlags(void) +{ + return MXC_RTC->ctrl & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY); +} + +int MXC_RTC_RevA_ClearFlags(int flags) +{ + if (MXC_RTC_CheckBusy()) { + return E_BUSY; + } + + MXC_RTC->ctrl &= ~(flags & (MXC_RTC_INT_FL_LONG | MXC_RTC_INT_FL_SHORT | MXC_RTC_INT_FL_READY)); + + return E_SUCCESS; +} + +int MXC_RTC_RevA_GetSubSecond(void) +{ +#if TARGET_NUM == 32650 + int ssec; + if(ChipRevision > 0xA1){ + ssec = ((MXC_PWRSEQ->ctrl >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF); + }else{ + ssec = MXC_RTC->ssec; + } + return ssec; +#else + return MXC_RTC->ssec; +#endif +} + +int MXC_RTC_RevA_GetSecond(void) +{ + return MXC_RTC->sec; +} + +int MXC_RTC_RevA_GetTime(uint32_t* sec, uint32_t* subsec) +{ + uint32_t temp_sec; + + if (sec == NULL || subsec == NULL) { + return E_NULL_PTR; + } + + do { + // Check if an update is about to happen. + if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + return E_BUSY; + } + + // Read the seconds count. + temp_sec = MXC_RTC_RevA_GetSecond(); + + // Check if an update is about to happen. + if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + return E_BUSY; + } + + // Read the sub-seconds count. + *subsec = MXC_RTC_RevA_GetSubSecond(); + + // Check if an update is about to happen. + if (!(MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RDY)) { + return E_BUSY; + } + + // Read the seconds count. + *sec = MXC_RTC_RevA_GetSecond(); + + // Repeat until a steady state is reached. + } + while (temp_sec != *sec); + + return E_NO_ERROR; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h new file mode 100644 index 00000000000..b8d216ea522 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva.h @@ -0,0 +1,66 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +#include "mxc_device.h" +#include "rtc_reva_regs.h" +#include "rtc.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gpio.h" +#include "mxc_errors.h" + +typedef enum { + MXC_RTC_REVA_SQUARE_WAVE_DISABLED, ///< Sq. wave output disabled + MXC_RTC_REVA_SQUARE_WAVE_ENABLED, ///< Sq. wave output enabled +} mxc_rtc_reva_sqwave_en_t; + +#define MXC_RTC_REVA_CTRL_RESET_DEFAULT (0x0000UL) +#define MXC_RTC_REVA_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_BUSY) +#define MXC_RTC_REVA_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_REVA_CTRL_RTCE) + +#define MXC_BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit + +int MXC_RTC_RevA_Init (mxc_rtc_reva_regs_t *rtc, uint32_t sec, uint8_t ssec); +int MXC_RTC_RevA_EnableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask); +int MXC_RTC_RevA_DisableInt (mxc_rtc_reva_regs_t *rtc, uint32_t mask); +int MXC_RTC_RevA_SetTimeofdayAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t ras); +int MXC_RTC_RevA_SetSubsecondAlarm (mxc_rtc_reva_regs_t *rtc, uint32_t rssa); +int MXC_RTC_RevA_Start (mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_Stop (mxc_rtc_reva_regs_t *rtc); +int MXC_RTC_RevA_SquareWave (mxc_rtc_reva_regs_t *rtc, mxc_rtc_reva_sqwave_en_t sqe, mxc_rtc_freq_sel_t ft); +int MXC_RTC_RevA_Trim (mxc_rtc_reva_regs_t *rtc, int8_t trm); +int MXC_RTC_RevA_GetFlags (void); +int MXC_RTC_RevA_ClearFlags (int flags); +int MXC_RTC_RevA_GetSubSecond (void); +int MXC_RTC_RevA_GetSecond (void); +int MXC_RTC_RevA_GetTime (uint32_t* sec, uint32_t* subsec); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h new file mode 100644 index 00000000000..584b929568b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/RTC/rtc_reva_regs.h @@ -0,0 +1,244 @@ +/** + * @file rtc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _RTC_REVA_REGS_H_ +#define _RTC_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC_Registers + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @details Real Time Clock and Alarm. + */ + +/** + * @ingroup rtc_registers + * Structure type to access the RTC Registers. + */ +typedef struct { + __IO uint32_t sec; /**< \b 0x00: RTC SEC Register */ + __IO uint32_t ssec; /**< \b 0x04: RTC SSEC Register */ + __IO uint32_t toda; /**< \b 0x08: RTC TODA Register */ + __IO uint32_t sseca; /**< \b 0x0C: RTC SSECA Register */ + __IO uint32_t ctrl; /**< \b 0x10: RTC CTRL Register */ + __IO uint32_t trim; /**< \b 0x14: RTC TRIM Register */ + __IO uint32_t oscctrl; /**< \b 0x18: RTC OSCCTRL Register */ +} mxc_rtc_reva_regs_t; + +/* Register offsets for module RTC */ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @{ + */ + #define MXC_R_RTC_REVA_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ + #define MXC_R_RTC_REVA_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ + #define MXC_R_RTC_REVA_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ + #define MXC_R_RTC_REVA_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ + #define MXC_R_RTC_REVA_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ + #define MXC_R_RTC_REVA_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ + #define MXC_R_RTC_REVA_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +/**@} end of group rtc_registers */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SEC RTC_SEC + * @brief RTC Second Counter. This register contains the 32-bit second counter. + * @{ + */ + #define MXC_F_RTC_REVA_SEC_SEC_POS 0 /**< SEC_SEC Position */ + #define MXC_F_RTC_REVA_SEC_SEC ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SEC_SEC_POS)) /**< SEC_SEC Mask */ + +/**@} end of group RTC_SEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSEC RTC_SSEC + * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented + * when this register rolls over from 0xFF to 0x00. + * @{ + */ + #define MXC_F_RTC_REVA_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ + #define MXC_F_RTC_REVA_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ + +/**@} end of group RTC_SSEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TODA RTC_TODA + * @brief Time-of-day Alarm. + * @{ + */ + #define MXC_F_RTC_REVA_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ + #define MXC_F_RTC_REVA_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_REVA_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ + +/**@} end of group RTC_TODA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSECA RTC_SSECA + * @brief RTC sub-second alarm. This register contains the reload value for the sub- + * second alarm. + * @{ + */ + #define MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ + #define MXC_F_RTC_REVA_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_REVA_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ + +/**@} end of group RTC_SSECA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL RTC_CTRL + * @brief RTC Control Register. + * @{ + */ + #define MXC_F_RTC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ + #define MXC_F_RTC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + + #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ + #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ + + #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ + #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ + + #define MXC_F_RTC_REVA_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ + #define MXC_F_RTC_REVA_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + + #define MXC_F_RTC_REVA_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ + #define MXC_F_RTC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + + #define MXC_F_RTC_REVA_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ + #define MXC_F_RTC_REVA_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ + + #define MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS 6 /**< CTRL_TOD_ALARM Position */ + #define MXC_F_RTC_REVA_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_TOD_ALARM_POS)) /**< CTRL_TOD_ALARM Mask */ + + #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS 7 /**< CTRL_SSEC_ALARM Position */ + #define MXC_F_RTC_REVA_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SSEC_ALARM_POS)) /**< CTRL_SSEC_ALARM Mask */ + + #define MXC_F_RTC_REVA_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ + #define MXC_F_RTC_REVA_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ + + #define MXC_F_RTC_REVA_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ + #define MXC_F_RTC_REVA_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ + #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ + #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ + #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ + #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ + #define MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ + #define MXC_S_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_REVA_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ + #define MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_SQW_SEL_CLKDIV8 Value */ + #define MXC_S_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_REVA_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_REVA_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_CLKDIV8 Setting */ + + #define MXC_F_RTC_REVA_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ + #define MXC_F_RTC_REVA_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ + + #define MXC_F_RTC_REVA_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ + #define MXC_F_RTC_REVA_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_REVA_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ + +/**@} end of group RTC_CTRL_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM RTC_TRIM + * @brief RTC Trim Register. + * @{ + */ + #define MXC_F_RTC_REVA_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ + #define MXC_F_RTC_REVA_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_REVA_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ + + #define MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */ + #define MXC_F_RTC_REVA_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_REVA_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */ + +/**@} end of group RTC_TRIM_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_OSCCTRL RTC_OSCCTRL + * @brief RTC Oscillator Control Register. + * @{ + */ + #define MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ + #define MXC_F_RTC_REVA_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ + + #define MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ + #define MXC_F_RTC_REVA_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_REVA_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ + +/**@} end of group RTC_OSCCTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTC_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c new file mode 100644 index 00000000000..c973b7be32b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_me11.c @@ -0,0 +1,358 @@ +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spi_reva.h" +#include "dma.h" + +/* **** Functions **** */ +int MXC_SPI_Init(mxc_spi_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned drv_ssel) +{ + + if(numSlaves > MXC_SPI_SS_INSTANCES) { + return E_BAD_PARAM; + } + + // Check if frequency is too high + if(hz > PeripheralClock) { + return E_BAD_PARAM; + } + + // Configure GPIO for spi + if(spi == MXC_SPI0) { + MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI0; + while(MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI0); + MXC_GCR->pclk_dis0 &= ~(MXC_F_GCR_PCLK_DIS0_SPI0D); + MXC_GPIO_Config(&gpio_cfg_spi0); + } + else { + return E_NO_DEVICE; + } + + return MXC_SPI_RevA_Init((mxc_spi_reva_regs_t*) spi, masterMode, quadModeUsed, numSlaves, ssPolarity, hz, drv_ssel); +} + +int MXC_SPI_Shutdown(mxc_spi_regs_t* spi) +{ + if(spi != MXC_SPI0) { + return E_NO_DEVICE; + } + + MXC_SPI_RevA_Shutdown((mxc_spi_reva_regs_t*) spi); + // + MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI0D); + + return E_NO_ERROR; +} + +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_ReadyForSleep((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t* spi) +{ + if(spi == MXC_SPI0) { + return PeripheralClock; + } + else { + return E_BAD_PARAM; + } + return E_NO_ERROR; +} + +int MXC_SPI_SetFrequency(mxc_spi_regs_t* spi, unsigned int hz) +{ + return MXC_SPI_RevA_SetFrequency((mxc_spi_reva_regs_t*) spi, hz); +} + +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetFrequency((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_SetDataSize(mxc_spi_regs_t* spi, int dataSize) +{ + return MXC_SPI_RevA_SetDataSize((mxc_spi_reva_regs_t*) spi, dataSize); +} + +int MXC_SPI_GetDataSize(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetDataSize((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_SetSlave(mxc_spi_regs_t* spi, int ssIdx) +{ + return MXC_SPI_RevA_SetSlave((mxc_spi_reva_regs_t*) spi, ssIdx); +} + +int MXC_SPI_GetSlave(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetSlave((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_SetWidth(mxc_spi_regs_t* spi, mxc_spi_width_t spiWidth) +{ + return MXC_SPI_RevA_SetWidth((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_width_t)spiWidth); +} + +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t* spi) +{ + return(mxc_spi_width_t) MXC_SPI_RevA_GetWidth((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_SetMode (mxc_spi_regs_t* spi, mxc_spi_mode_t spiMode) +{ + return MXC_SPI_RevA_SetMode ((mxc_spi_reva_regs_t*) spi, (mxc_spi_reva_mode_t)spiMode); +} + +mxc_spi_mode_t MXC_SPI_GetMode (mxc_spi_regs_t* spi) +{ + return (mxc_spi_mode_t) MXC_SPI_RevA_GetMode((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_StartTransmission(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_StartTransmission((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_GetActive(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetActive((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_AbortTransmission(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_AbortTransmission((mxc_spi_reva_regs_t*) spi); +} + +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes, + unsigned int len) +{ + return MXC_SPI_RevA_ReadRXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len); +} + +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetRXFIFOAvailable((mxc_spi_reva_regs_t*) spi); +} + +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t* spi, unsigned char* bytes, + unsigned int len) +{ + return MXC_SPI_RevA_WriteTXFIFO((mxc_spi_reva_regs_t*) spi, bytes, len); +} + +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetTXFIFOAvailable((mxc_spi_reva_regs_t*) spi); +} + +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t* spi) +{ + MXC_SPI_RevA_ClearRXFIFO((mxc_spi_reva_regs_t*) spi); +} + +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t* spi) +{ + MXC_SPI_RevA_ClearTXFIFO((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes) +{ + return MXC_SPI_RevA_SetRXThreshold((mxc_spi_reva_regs_t*) spi, numBytes); +} + +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetRXThreshold((mxc_spi_reva_regs_t*) spi); +} + +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t* spi, unsigned int numBytes) +{ + return MXC_SPI_RevA_SetTXThreshold((mxc_spi_reva_regs_t*) spi, numBytes); +} + +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetTXThreshold((mxc_spi_reva_regs_t*) spi); +} + +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t* spi) +{ + return MXC_SPI_RevA_GetFlags((mxc_spi_reva_regs_t*) spi); +} + +void MXC_SPI_ClearFlags(mxc_spi_regs_t* spi) +{ + MXC_SPI_RevA_ClearFlags((mxc_spi_reva_regs_t*) spi); +} + +void MXC_SPI_EnableInt(mxc_spi_regs_t* spi, unsigned int mask) +{ + MXC_SPI_RevA_EnableInt((mxc_spi_reva_regs_t*) spi, mask); +} + +void MXC_SPI_DisableInt(mxc_spi_regs_t* spi, unsigned int mask) +{ + MXC_SPI_RevA_DisableInt((mxc_spi_reva_regs_t*) spi, mask); +} + +int MXC_SPI_MasterTransaction(mxc_spi_req_t* req) +{ + return MXC_SPI_RevA_MasterTransaction((mxc_spi_reva_req_t*) req); +} + +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t* req) +{ + return MXC_SPI_RevA_MasterTransactionAsync((mxc_spi_reva_req_t*) req); +} + +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t* req) +{ + int reqselTx = -1; + int reqselRx = -1; + + int spi_num; + + spi_num = MXC_SPI_GET_IDX(req->spi); + MXC_ASSERT(spi_num >= 0); + + if(req->txData != NULL) { + switch(spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + break; + + default: + return E_BAD_PARAM; + } + } + + if(req->rxData != NULL) { + switch(spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1RX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_SPI_RevA_MasterTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA); +} + +int MXC_SPI_SlaveTransaction(mxc_spi_req_t* req) +{ + return MXC_SPI_RevA_SlaveTransaction((mxc_spi_reva_req_t*) req); +} + +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t* req) +{ + return MXC_SPI_RevA_SlaveTransactionAsync((mxc_spi_reva_req_t*) req); +} + +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t* req) +{ + int reqselTx = -1; + int reqselRx = -1; + + int spi_num; + + spi_num = MXC_SPI_GET_IDX(req->spi); + MXC_ASSERT(spi_num >= 0); + + if(req->txData != NULL) { + switch(spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + break; + + default: + return E_BAD_PARAM; + } + } + + if(req->rxData != NULL) { + switch(spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_SPI_RevA_SlaveTransactionDMA((mxc_spi_reva_req_t*) req, reqselTx, reqselRx, MXC_DMA); +} + +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t* spi, unsigned int defaultTXData) +{ + return MXC_SPI_RevA_SetDefaultTXData((mxc_spi_reva_regs_t*) spi, defaultTXData); +} + +void MXC_SPI_AbortAsync(mxc_spi_regs_t* spi) +{ + MXC_SPI_RevA_AbortAsync((mxc_spi_reva_regs_t*) spi); +} + +void MXC_SPI_AsyncHandler(mxc_spi_regs_t* spi) +{ + MXC_SPI_RevA_AsyncHandler((mxc_spi_reva_regs_t*) spi); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c new file mode 100644 index 00000000000..fa62a84fc4c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c @@ -0,0 +1,1332 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ +#ifdef __CC_ARM //Keil +#pragma diag_suppress 188 // enumerated type mixed with another type +#pragma diag_suppress 68 // integer conversion resulted in a change of sign +#endif + + + +#include +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "mxc_spi.h" +#include "spi_reva.h" +#include "dma_reva.h" + +/* **** Definitions **** */ +typedef struct { + mxc_spi_reva_req_t *req; + int started; + unsigned last_size; + unsigned ssDeassert; + unsigned defaultTXData; + int channelTx; + int channelRx; + unsigned drv_ssel; +} spi_req_reva_state_t; + +/* states whether to use call back or not */ +uint8_t async; + +static spi_req_reva_state_t states[MXC_SPI_INSTANCES]; + +static uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); +static uint32_t MXC_SPI_RevA_TransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req); +static uint32_t MXC_SPI_RevA_SlaveTransHandler (mxc_spi_reva_req_t *req); +static void MXC_SPI_RevA_SwapByte (uint8_t * arr, size_t length); +static int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req); + + +int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned drv_ssel) +{ + int spi_num; + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + + states[spi_num].req = NULL; + states[spi_num].last_size = 0; + states[spi_num].ssDeassert = 1; + states[spi_num].defaultTXData = 0; + states[spi_num].drv_ssel = drv_ssel; + + spi->ctrl0 = (MXC_F_SPI_REVA_CTRL0_EN); + spi->sstime = ( (0x1 << MXC_F_SPI_REVA_SSTIME_PRE_POS) | + (0x1 << MXC_F_SPI_REVA_SSTIME_POST_POS) | + (0x1 << MXC_F_SPI_REVA_SSTIME_INACT_POS)); + + //set master + if (masterMode) { + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_MST_MODE; + } + else { + spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_MST_MODE); + } + + MXC_SPI_SetFrequency ((mxc_spi_regs_t*) spi, hz); + + //set slave select polarity + spi->ctrl2 |= ( (!!ssPolarity) << MXC_F_SPI_REVA_CTRL2_SS_POL_POS); + + // Clear the interrupts + spi->intfl = spi->intfl; + + // Driver will drive SS pin? + if (states[spi_num].drv_ssel) { + spi->ctrl0 |= MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0; + } + + //set quad mode + if (quadModeUsed) { + spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD; + } + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi) +{ + int spi_num; + mxc_spi_reva_req_t * temp_req; + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + + //disable and clear interrupts + spi->inten = 0; + spi->intfl = spi->intfl; + + // Disable SPI and FIFOS + spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + spi->dma &= ~ (MXC_F_SPI_REVA_DMA_TX_FIFO_EN | MXC_F_SPI_REVA_DMA_RX_FIFO_EN); + + //call all of the pending callbacks for this spi + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + + if (states[spi_num].req != NULL) { + //save the request + temp_req = states[spi_num].req; + MXC_FreeLock((uint32_t*)(uint32_t*) &states[spi_num].req); + + // Callback if not NULL + if (states[spi_num].req->completeCB != NULL) { + states[spi_num].req->completeCB(temp_req, E_SHUTDOWN); + } + + } + + // Clear registers + spi->ctrl0 = 0; + spi->ctrl1 = 0; + spi->ctrl2 = 0; + spi->sstime = 0; + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + + if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY || (spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) || (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL)) { + return E_BUSY; + } + else { + return E_NO_ERROR; + } +} + +int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz) +{ + int hi_clk, lo_clk, scale; + uint32_t freq_div; + + // Check if frequency is too high + if (hz > PeripheralClock) { + return E_BAD_PARAM; + } + + // Set the clock high and low + freq_div = MXC_SPI_GetPeripheralClock((mxc_spi_regs_t*) spi); + #if TARGET_NUM == 32570 || TARGET_NUM == 32680 + freq_div = (freq_div / hz / 2); + #else + freq_div = (freq_div / hz); + #endif + + hi_clk = freq_div / 2; + lo_clk = freq_div / 2; + scale = 0; + + if (freq_div % 2) { + hi_clk += 1; + } + + while (hi_clk >= 16 && scale < 8) { + hi_clk /= 2; + lo_clk /= 2; + scale ++; + } + + if (scale == 8) { + lo_clk = 15; + hi_clk = 15; + } + + MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_LO, (lo_clk << MXC_F_SPI_REVA_CLKCTRL_LO_POS)); + MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_HI, (hi_clk << MXC_F_SPI_REVA_CLKCTRL_HI_POS)); + MXC_SETFIELD (spi->clkctrl, MXC_F_SPI_REVA_CLKCTRL_CLKDIV, (scale << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)); + + return E_NO_ERROR; +} + +unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi) +{ + if (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) < 0) { + return E_BAD_PARAM; + } + + unsigned scale, lo_clk, hi_clk; + + scale = (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_CLKDIV) >> MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS; + hi_clk= (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_HI) >> MXC_F_SPI_REVA_CLKCTRL_HI_POS; + lo_clk= (spi->clkctrl & MXC_F_SPI_REVA_CLKCTRL_LO) >> MXC_F_SPI_REVA_CLKCTRL_LO_POS; + + return (PeripheralClock / (1 << scale)) / (lo_clk + hi_clk); +} + +int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize) +{ + int spi_num; + + // HW has problem with these two character sizes + if (dataSize == 1 || dataSize > 16) { + return E_BAD_PARAM; + } + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + + // Setup the character size + if (! (spi->stat & MXC_F_SPI_REVA_STAT_BUSY) && states[spi_num].ssDeassert == 1) { + //disable spi to change transfer size + spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + // set bit size + states[spi_num].last_size = dataSize; + + if (dataSize < 16) { + MXC_SETFIELD (spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, dataSize << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); + } + + else { + MXC_SETFIELD (spi->ctrl2, MXC_F_SPI_REVA_CTRL2_NUMBITS, 0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS); //may not be neccessary + } + + //enable spi to change transfer size + spi->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); + } + else { + return E_BAD_STATE; + } + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + if (!(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_NUMBITS)) { + return 16; + } + + return (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_NUMBITS) >> MXC_F_SPI_REVA_CTRL2_NUMBITS_POS; +} + +int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx) +{ + int spi_num; + + // HW has problem with these two character sizes + if (ssIdx >= MXC_SPI_SS_INSTANCES) { + return E_BAD_PARAM; + } + + //check if in master mode + if (! (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE)) { + return E_BAD_STATE; + } + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + if (states[spi_num].drv_ssel) { + // Setup the slave select + // Activate chosen SS pin + spi->ctrl0 |= (1 << ssIdx) << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS; + } + return E_NO_ERROR; +} + +int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi) +{ + int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + return ( (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_SS_ACTIVE) >> MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) >> 1; +} + +int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + spi->ctrl2 &= ~ (MXC_F_SPI_REVA_CTRL2_THREE_WIRE | MXC_F_SPI_REVA_CTRL2_DATA_WIDTH); + + switch (spiWidth) { + + case SPI_REVA_WIDTH_3WIRE: + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_THREE_WIRE; + break; + + case SPI_REVA_WIDTH_STANDARD: + spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_MONO; + break; + + case SPI_REVA_WIDTH_DUAL: + spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL; + break; + + case SPI_REVA_WIDTH_QUAD: + spi->ctrl2 |= MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD; + break; + } + + return E_NO_ERROR; +} + +mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi) +{ + if (spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) { + return SPI_REVA_WIDTH_3WIRE; + } + + if (spi->ctrl2 & MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL) { + return SPI_REVA_WIDTH_DUAL; + } + + if (spi->ctrl2 & MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD) { + return SPI_REVA_WIDTH_QUAD; + } + + return SPI_REVA_WIDTH_STANDARD; +} + +int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode) +{ + int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + switch(spiMode) { + case SPI_REVA_MODE_0: + spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPOL; + break; + + case SPI_REVA_MODE_1: + spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; + break; + + case SPI_REVA_MODE_2: + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 &= ~MXC_F_SPI_REVA_CTRL2_CLKPOL; + break; + + case SPI_REVA_MODE_3: + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPHA; + spi->ctrl2 |= MXC_F_SPI_REVA_CTRL2_CLKPOL; + break; + + default: + break; + } + + return E_NO_ERROR; +} + +mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi) +{ + int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPHA) { + if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { + return SPI_REVA_MODE_3; + } + else { + return SPI_REVA_MODE_2; + } + } + else { + if(spi->ctrl2 & MXC_F_SPI_REVA_CTRL2_CLKPOL) { + return SPI_REVA_MODE_1; + } + } + + return SPI_REVA_MODE_0; +} + +int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi) +{ + int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + (void)spi_num; + + if (MXC_SPI_GetActive ((mxc_spi_regs_t*) spi) == E_BUSY) { + return E_BUSY; + } + + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_START; + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi) +{ + if (spi->stat & MXC_F_SPI_REVA_STAT_BUSY) { + return E_BUSY; + } + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + + // Disable interrupts, clear the flags + spi->inten = 0; + spi->intfl = spi->intfl; + + // Reset the SPI17Y to cancel the on ongoing transaction + spi->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + spi->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); + + // Unlock this SPI + mxc_spi_reva_req_t * temp = states[spi_num].req; + MXC_FreeLock ((uint32_t*) &states[spi_num].req); + + // Callback if not NULL + if (temp->completeCB != NULL) { + temp->completeCB(states[spi_num].req, E_ABORT); + } + + return E_NO_ERROR; +} + +unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, + unsigned int len) +{ + unsigned rx_avail,bits; + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + + if (!bytes || !len) { + return 0; + } + + rx_avail = MXC_SPI_GetRXFIFOAvailable ((mxc_spi_regs_t*) spi); + bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) spi); + + if (len > rx_avail) { + len = rx_avail; + } + + if (bits > 8) { + len &= ~(unsigned) 0x1; + } + + unsigned cnt = 0; + + if (bits <= 8 || len >= 2) { + // Read from the FIFO + while (len) { + if (len > 3) { + memcpy(& ((uint8_t*) bytes) [cnt], (void*) &spi->fifo32, 4); + len -= 4; + cnt += 4; + } + else if (len > 1) { + memcpy(& ((uint8_t*) bytes) [cnt], (void*) &spi->fifo16[0], 2); + len -= 2; + cnt += 2; + + } + else { + ((uint8_t*) bytes) [cnt++] = spi->fifo8[0]; + len -= 1; + } + + // Don't read less than 2 bytes if we are using greater than 8 bit characters + if (len == 1 && bits > 8) { + break; + } + } + } + + return cnt; +} + +unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi) +{ + return (spi->dma & MXC_F_SPI_REVA_DMA_RX_LVL) >> MXC_F_SPI_REVA_DMA_RX_LVL_POS; +} + +unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, + unsigned int len) +{ + unsigned tx_avail,bits; + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + + if (!bytes || !len) { + return 0; + } + + tx_avail = MXC_SPI_GetTXFIFOAvailable ((mxc_spi_regs_t*) spi); + bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) spi); + + if (len > tx_avail) { + len = tx_avail; + } + + if (bits > 8) { + len &= ~(unsigned) 0x1; + } + + unsigned cnt = 0; + + while (len) { + if (len > 3) { + memcpy((void*) &spi->fifo32, & ((uint8_t*) bytes) [cnt], 4); + + len -= 4; + cnt += 4; + + } + else if (len > 1) { + memcpy((void*) &spi->fifo16[0], & ((uint8_t*) bytes) [cnt], 2); + + len -= 2; + cnt += 2; + + } + else if (bits <= 8) { + spi->fifo8[0] = ((uint8_t*) bytes) [cnt++]; + len--; + } + + } + + return cnt; +} + +unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + return MXC_SPI_FIFO_DEPTH - ((spi->dma & MXC_F_SPI_REVA_DMA_TX_LVL) >> MXC_F_SPI_REVA_DMA_TX_LVL_POS); +} + +void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + spi->dma |= MXC_F_SPI_REVA_DMA_RX_FLUSH; +} + +void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + spi->dma |= MXC_F_SPI_REVA_DMA_TX_FLUSH; +} + +int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + + if (numBytes > 32) { + return E_BAD_PARAM; + } + + MXC_SETFIELD (spi->dma, MXC_F_SPI_REVA_DMA_RX_THD_VAL, numBytes << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS); + + return E_NO_ERROR; +} + +unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + return (spi->dma & MXC_F_SPI_REVA_DMA_RX_THD_VAL) >> MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS; +} + +int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + + if (numBytes > 32) { + return E_BAD_PARAM; + } + + MXC_SETFIELD (spi->dma, MXC_F_SPI_REVA_DMA_TX_THD_VAL, numBytes << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS); + + return E_NO_ERROR; +} + +unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + return (spi->dma & MXC_F_SPI_REVA_DMA_TX_THD_VAL) >> MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS; +} + +unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + return spi->intfl; +} + +void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + spi->intfl = spi->intfl; +} + +void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int intEn) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + spi->inten |= intEn; +} + +void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int intDis) +{ + MXC_ASSERT (MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi) >= 0); + spi->inten &= ~ (intDis); +} + +int MXC_SPI_RevA_TransSetup (mxc_spi_reva_req_t * req) +{ + int spi_num; + uint8_t bits; + + if ((!req) || ((req->txData == NULL) && (req->rxData == NULL))) { + return E_BAD_PARAM; + } + + // Setup the number of characters to transact + if (req->txLen > (MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR >> MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS)) { + return E_BAD_PARAM; + } + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); + MXC_ASSERT (spi_num >= 0); + MXC_ASSERT (req->ssIdx < MXC_SPI_SS_INSTANCES); + + bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); + req->txCnt = 0; + req->rxCnt = 0; + + states[spi_num].req = req; + states[spi_num].started = 0; + + // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). + if (states[spi_num].ssDeassert == 1) { + (req->spi)->ctrl0 &= ~ (MXC_F_SPI_REVA_CTRL0_EN); + } + + //if master + if ((req->spi)->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) { + // Setup the slave select + MXC_SPI_SetSlave ((mxc_spi_regs_t*) req->spi, req->ssIdx); + + } + + if (req->rxData != NULL && req->rxLen > 0) { + MXC_SETFIELD ( (req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR, + req->rxLen << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS); + (req->spi)->dma |= MXC_F_SPI_REVA_DMA_RX_FIFO_EN; + } + else { + (req->spi)->ctrl1 &= ~ (MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR); + (req->spi)->dma &= ~ (MXC_F_SPI_REVA_DMA_RX_FIFO_EN); + } + + // Must use TXFIFO and NUM in full duplex//start editing here + if ((mxc_spi_reva_width_t) MXC_SPI_GetWidth ((mxc_spi_regs_t*) req->spi) == SPI_REVA_WIDTH_STANDARD + && ! ( ( (req->spi)->ctrl2 & MXC_F_SPI_REVA_CTRL2_THREE_WIRE) >> MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) { + if (req->txData == NULL) { + // Must have something to send, so we'll use the rx_data buffer initialized to 0. + //SPI_SetDefaultTXData(spi, 0); + memset(req->rxData, states[spi_num].defaultTXData, (bits > 8 ? req->rxLen << 1 : req->rxLen)); + req->txData = req->rxData; + req->txLen = req->rxLen; + } + } + + if(req->txData != NULL && req->txLen > 0) { + MXC_SETFIELD ( (req->spi)->ctrl1, MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR, + req->txLen << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS); + (req->spi)->dma |= MXC_F_SPI_REVA_DMA_TX_FIFO_EN; + } + else { + (req->spi)->ctrl1 &= ~(MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR); + (req->spi)->dma &= ~(MXC_F_SPI_REVA_DMA_TX_FIFO_EN); + } + + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_TX_FLUSH | MXC_F_SPI_REVA_DMA_RX_FLUSH); + (req->spi)->ctrl0 |= (MXC_F_SPI_REVA_CTRL0_EN); + + states[spi_num].ssDeassert = req->ssDeassert; + // Clear master done flag + (req->spi)->intfl = MXC_F_SPI_REVA_INTFL_MST_DONE; + + + return E_NO_ERROR; +} + +uint32_t MXC_SPI_RevA_MasterTransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) +{ + uint32_t retval; + int spi_num; + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + + // Leave slave select asserted at the end of the transaction + if (!req->ssDeassert) { + spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } + + retval = MXC_SPI_RevA_TransHandler(spi, req); + + if (!states[spi_num].started) { + MXC_SPI_StartTransmission ((mxc_spi_regs_t*) spi); + states[spi_num].started = 1; + } + + // Deassert slave select at the end of the transaction + if (req->ssDeassert) { + spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } + + return retval; +} + +uint32_t MXC_SPI_RevA_SlaveTransHandler (mxc_spi_reva_req_t *req) +{ + return MXC_SPI_RevA_TransHandler(req->spi, req); +} + +uint32_t MXC_SPI_RevA_TransHandler (mxc_spi_reva_regs_t *spi, mxc_spi_reva_req_t *req) +{ + int remain, spi_num; + uint32_t int_en = 0; + uint32_t tx_length = 0, rx_length = 0; + uint8_t bits; + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + if (spi_num < 0) { + MXC_ASSERT(0); + } + + bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); + + //MXC_F_SPI_REVA_CTRL2_NUMBITS data bits + // Read/write 2x number of bytes if larger character size + if (bits > 8) { + tx_length = req->txLen * 2; + rx_length = req->rxLen * 2; + } + else { + tx_length = req->txLen; + rx_length = req->rxLen; + } + + if (req->txData != NULL) { + + req->txCnt += MXC_SPI_WriteTXFIFO ((mxc_spi_regs_t*) spi, & (req->txData[req->txCnt]),tx_length - req->txCnt); + } + + remain = tx_length - req->txCnt; + + // Set the TX interrupts + // Write the FIFO //starting here + if (remain) { + if (remain > MXC_SPI_FIFO_DEPTH) { + MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) spi,MXC_SPI_FIFO_DEPTH); + } + else { + MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) spi,remain); + } + + int_en |= MXC_F_SPI_REVA_INTEN_TX_THD; + + } + // Break out if we've transmitted all the bytes and not receiving + if ((req->rxData == NULL) && (req->txCnt == tx_length)) { + spi->inten = 0; + int_en = 0; + MXC_FreeLock((uint32_t*) &states[spi_num].req); + + // Callback if not NULL + if (async && req->completeCB != NULL) { + req->completeCB(req, E_NO_ERROR); + } + } + + // Read the RX FIFO + if (req->rxData != NULL) { + + req->rxCnt += MXC_SPI_ReadRXFIFO ((mxc_spi_regs_t*) spi,& (req->rxData[req->rxCnt]),rx_length - req->rxCnt); + + + remain = rx_length - req->rxCnt; + + if (remain) { + if (remain > MXC_SPI_FIFO_DEPTH) { + MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) spi, 2); + } + else { + MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) spi, remain - 1); + } + + int_en |= MXC_F_SPI_REVA_INTEN_RX_THD; + } + + // Break out if we've received all the bytes and we're not transmitting + if ((req->txData == NULL) && (req->rxCnt == rx_length)) { + spi->inten = 0; + int_en = 0; + MXC_FreeLock((uint32_t*) &states[spi_num].req); + + // Callback if not NULL + if (async && req->completeCB != NULL) { + req->completeCB(req, E_NO_ERROR); + } + } + } + // Break out once we've transmitted and received all of the data + if ((req->rxCnt == rx_length) && (req->txCnt == tx_length)) { + spi->inten = 0; + int_en = 0; + MXC_FreeLock((uint32_t*) &states[spi_num].req); + + // Callback if not NULL + if (async && req->completeCB != NULL) { + req->completeCB(req, E_NO_ERROR); + } + } + + return int_en; +} + +int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req) +{ + int error; + + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { + return error; + } + + async = 0; + + //call master transHandler + while (MXC_SPI_RevA_MasterTransHandler(req->spi, req) != 0); + + while (!((req->spi)->intfl & MXC_F_SPI_REVA_INTFL_MST_DONE)); + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req) +{ + int error; + + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { + return error; + } + + async = 1; + + MXC_SPI_EnableInt ((mxc_spi_regs_t*) req->spi, MXC_SPI_RevA_MasterTransHandler (req->spi,req)); + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma) +{ + int spi_num; + uint8_t channel,error,bits; + mxc_dma_config_t config; + mxc_dma_srcdst_t srcdst; + mxc_dma_adv_config_t advConfig = {0, 0, 0, 0, 0, 0}; + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); + MXC_ASSERT (spi_num >= 0); + + if (req->txData == NULL && req->rxData == NULL) { + return E_BAD_PARAM; + } + + if ((error = MXC_SPI_RevA_TransSetup (req)) != E_NO_ERROR) { + return error; + } + + // Leave slave select asserted at the end of the transaction + if (!req->ssDeassert) { + req->spi->ctrl0 |= MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } + + bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); + + MXC_SPI_RevA_TransHandler(req->spi, req); + + if (bits <= 8) { + MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 1); //set threshold to 1 byte + MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); //set threshold to 0 bytes + } + else { + MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 2); + MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); + } + + #if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + #else + MXC_DMA_Init(); + #endif + + //tx + if (req->txData != NULL) { + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.reqsel = reqselTx; + config.ch = channel; + advConfig.ch = channel; + advConfig.burst_size = 2; + + if (bits <= 8) { + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + } + else { + config.srcwd = MXC_DMA_WIDTH_HALFWORD; + config.dstwd = MXC_DMA_WIDTH_HALFWORD; + } + + config.srcinc_en = 1; + config.dstinc_en = 0; + + srcdst.ch = channel; + srcdst.source = & (req->txData[req->txCnt]); + + if (bits > 8) { + srcdst.len = (req->txLen * 2) - req->txCnt; + } + else { + srcdst.len = (req->txLen) - req->txCnt; + } + + states[spi_num].channelTx = channel; + MXC_DMA_ConfigChannel (config,srcdst); + MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + MXC_DMA_SetChannelInterruptEn(channel, false, true); + //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + + if (bits > 8) { + MXC_DMA_AdvConfigChannel(advConfig); + //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 1 << MXC_F_DMA_CTRL_BURST_SIZE_POS); + } + } + + if (req->rxData != NULL) { + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.reqsel = reqselRx; + config.ch = channel; + config.srcinc_en = 0; + config.dstinc_en = 1; + advConfig.ch = channel; + advConfig.burst_size = 1; + + if (bits <= 8) { + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + } + else { + config.srcwd = MXC_DMA_WIDTH_HALFWORD; + config.dstwd = MXC_DMA_WIDTH_HALFWORD; + } + + + srcdst.ch = channel; + srcdst.dest = req->rxData; + + if (bits <= 8) { + srcdst.len = req->rxLen; + } + else { + srcdst.len = req->rxLen * 2; + } + + states[spi_num].channelRx = channel; + + MXC_DMA_ConfigChannel (config,srcdst); + MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + MXC_DMA_SetChannelInterruptEn(channel, false, true); + //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + + if (bits > 8) { + MXC_DMA_AdvConfigChannel(advConfig); + //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 0 << MXC_F_DMA_CTRL_BURST_SIZE_POS); + } + + } + + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_DMA_TX_EN | MXC_F_SPI_REVA_DMA_DMA_RX_EN); + + + if (!states[spi_num].started) { + MXC_SPI_StartTransmission ((mxc_spi_regs_t*) req->spi); + states[spi_num].started = 1; + } + + // Deassert slave select at the end of the transaction + if (req->ssDeassert) { + req->spi->ctrl0 &= ~MXC_F_SPI_REVA_CTRL0_SS_CTRL; + } + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req) +{ + int error; + + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { + return error; + } + + + async = 0; + + while (MXC_SPI_RevA_SlaveTransHandler(req) != 0); + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req) +{ + int error; + + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { + return error; + } + + async = 1; + + MXC_SPI_EnableInt ((mxc_spi_regs_t*) req->spi,MXC_SPI_RevA_SlaveTransHandler (req)); + + return E_NO_ERROR; +} + +int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma) +{ + int spi_num; + uint8_t channel, error, bits; + mxc_dma_config_t config; + mxc_dma_srcdst_t srcdst; + mxc_dma_adv_config_t advConfig = {0, 0, 0, 0, 0, 0}; + + if (req->txData == NULL && req->rxData == NULL) { + return E_BAD_PARAM; + } + + if ((error = MXC_SPI_RevA_TransSetup(req)) != E_NO_ERROR) { + return error; + } + + bits = MXC_SPI_GetDataSize ((mxc_spi_regs_t*) req->spi); + + MXC_SPI_RevA_TransHandler(req->spi, req); + + if (bits <= 8) { + MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 1); + MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); + } + else { + + MXC_SPI_SetTXThreshold ((mxc_spi_regs_t*) req->spi, 2); + MXC_SPI_SetRXThreshold ((mxc_spi_regs_t*) req->spi, 0); + } + + #if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + #else + MXC_DMA_Init(); + #endif + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*)(req->spi)); + MXC_ASSERT (spi_num >= 0); + + //tx + if (req->txData != NULL) { + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.reqsel = reqselTx; + config.ch = channel; + advConfig.ch = channel; + advConfig.burst_size = 2; + + if (bits <= 8) { + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + } + else { + config.srcwd = MXC_DMA_WIDTH_HALFWORD; + config.dstwd = MXC_DMA_WIDTH_HALFWORD; + } + + config.srcinc_en = 1; + config.dstinc_en = 0; + + srcdst.ch = channel; + srcdst.source = & (req->txData[req->txCnt]); + + if (bits > 8) { + srcdst.len = (req->txLen * 2) - req->txCnt; + } + else { + srcdst.len = (req->txLen) - req->txCnt; + } + + states[spi_num].channelTx = channel; + + MXC_DMA_ConfigChannel (config,srcdst); + MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + MXC_DMA_SetChannelInterruptEn(channel, false, true); + //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + + if (bits > 8) { + MXC_DMA_AdvConfigChannel(advConfig); + //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 1 << MXC_F_DMA_CTRL_BURST_SIZE_POS); + } + } + + if (req->rxData != NULL) { + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.reqsel = reqselRx; + config.ch = channel; + config.srcinc_en = 0; + config.dstinc_en = 1; + advConfig.ch = channel; + advConfig.burst_size = 1; + + if (bits <= 8) { + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + } + else { + config.srcwd = MXC_DMA_WIDTH_HALFWORD; + config.dstwd = MXC_DMA_WIDTH_HALFWORD; + } + + + srcdst.ch = channel; + srcdst.dest = req->rxData; + + if (bits <= 8) { + srcdst.len = req->rxLen; + } + else { + srcdst.len = req->rxLen * 2; + } + + states[spi_num].channelRx = channel; + + MXC_DMA_ConfigChannel (config,srcdst); + MXC_DMA_SetCallback (channel, MXC_SPI_RevA_DMACallback); + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + MXC_DMA_SetChannelInterruptEn(channel, false, true); + //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + + if (bits > 8) { + MXC_DMA_AdvConfigChannel(advConfig); + //MXC_SETFIELD (MXC_DMA->ch[channel].ctrl, MXC_F_DMA_CTRL_BURST_SIZE, 0 << MXC_F_DMA_CTRL_BURST_SIZE_POS); + } + } + + (req->spi)->dma |= (MXC_F_SPI_REVA_DMA_DMA_TX_EN | MXC_F_SPI_REVA_DMA_DMA_RX_EN); + + return E_NO_ERROR; +} + +void MXC_SPI_RevA_DMACallback(int ch, int error) +{ + mxc_spi_reva_req_t * temp_req; + + for (int i = 0; i < MXC_SPI_INSTANCES; i ++) { + if (states[i].channelTx == ch) { + //save the request + temp_req = states[i].req; + MXC_FreeLock((uint32_t*) &states[i].req); + // Callback if not NULL + if (temp_req->completeCB != NULL) { + temp_req->completeCB(temp_req, E_NO_ERROR); + } + break; + } + + else if (states[i].channelRx == ch) { + //save the request + temp_req = states[i].req; + MXC_FreeLock((uint32_t*) &states[i].req); + + if (MXC_SPI_GetDataSize ((mxc_spi_regs_t*) temp_req->spi) > 8) { + MXC_SPI_RevA_SwapByte (temp_req->rxData, temp_req->rxLen); + } + + // Callback if not NULL + if (temp_req->completeCB != NULL) { + temp_req->completeCB(temp_req, E_NO_ERROR); + } + + break; + } + } +} + +int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData) +{ + int spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + states[spi_num].defaultTXData = defaultTXData; + return E_NO_ERROR; +} + +void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi) +{ + MXC_SPI_AbortTransmission ((mxc_spi_regs_t*) spi); +} + +void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi) +{ + int spi_num; + unsigned rx_avail; + uint32_t flags; + + // Clear the interrupt flags + spi->inten = 0; + flags = spi->intfl; + spi->intfl = flags; + + spi_num = MXC_SPI_GET_IDX ((mxc_spi_regs_t*) spi); + + // Figure out if this SPI has an active request + if ( (states[spi_num].req != NULL) && (flags)) { + if ( (spi->ctrl0 & MXC_F_SPI_REVA_CTRL0_MST_MODE) >> MXC_F_SPI_REVA_CTRL0_MST_MODE_POS) { + do { + spi->inten = MXC_SPI_RevA_MasterTransHandler(spi, states[spi_num].req); + rx_avail = MXC_SPI_RevA_GetRXFIFOAvailable(spi); + } + while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); + + } + else { + do { + spi->inten = MXC_SPI_RevA_SlaveTransHandler(states[spi_num].req); + rx_avail = MXC_SPI_RevA_GetRXFIFOAvailable(spi); + } + while (rx_avail > MXC_SPI_RevA_GetRXThreshold(spi)); + + } + } +} + +//call in DMA IRQHANDLER with rxData for transmissions with bits > 8 +void MXC_SPI_RevA_SwapByte(uint8_t* arr, size_t length) +{ + MXC_ASSERT(arr != NULL); + + for (size_t i = 0 ; i < (length * 2); i+=2) { + uint8_t tmp = arr[i]; + arr[i] = arr[i + 1]; + arr[i + 1] = tmp; + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h new file mode 100644 index 00000000000..50291087412 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.h @@ -0,0 +1,118 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spi_regs.h" +#include "spi_reva_regs.h" +#include "mxc_spi.h" +#include "dma.h" + +typedef enum { + SPI_REVA_WIDTH_3WIRE, + SPI_REVA_WIDTH_STANDARD, + SPI_REVA_WIDTH_DUAL, + SPI_REVA_WIDTH_QUAD, +} mxc_spi_reva_width_t; + +typedef enum { + SPI_REVA_MODE_0, + SPI_REVA_MODE_1, + SPI_REVA_MODE_2, + SPI_REVA_MODE_3, +} mxc_spi_reva_mode_t; + +typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t; + +struct _mxc_spi_reva_req_t { + mxc_spi_reva_regs_t* spi; + int ssIdx; + int ssDeassert; + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; + uint32_t rxLen; + uint32_t txCnt; + uint32_t rxCnt; + spi_complete_cb_t completeCB; +}; + +int MXC_SPI_RevA_Init (mxc_spi_reva_regs_t* spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, unsigned drv_ssel); +int MXC_SPI_RevA_Shutdown (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_ReadyForSleep (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetFrequency (mxc_spi_reva_regs_t* spi, unsigned int hz); +unsigned int MXC_SPI_RevA_GetFrequency (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetDataSize (mxc_spi_reva_regs_t* spi, int dataSize); +int MXC_SPI_RevA_GetDataSize (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetSlave (mxc_spi_reva_regs_t* spi, int ssIdx); +int MXC_SPI_RevA_GetSlave (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetWidth (mxc_spi_reva_regs_t* spi, mxc_spi_reva_width_t spiWidth); +mxc_spi_reva_width_t MXC_SPI_RevA_GetWidth (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetMode (mxc_spi_reva_regs_t* spi, mxc_spi_reva_mode_t spiMode); +mxc_spi_reva_mode_t MXC_SPI_RevA_GetMode (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_StartTransmission (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_GetActive (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_AbortTransmission (mxc_spi_reva_regs_t* spi); +unsigned int MXC_SPI_RevA_ReadRXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, + unsigned int len); +unsigned int MXC_SPI_RevA_WriteTXFIFO (mxc_spi_reva_regs_t* spi, unsigned char* bytes, + unsigned int len); +unsigned int MXC_SPI_RevA_GetTXFIFOAvailable (mxc_spi_reva_regs_t* spi); +unsigned int MXC_SPI_RevA_GetRXFIFOAvailable (mxc_spi_reva_regs_t* spi); +void MXC_SPI_RevA_ClearRXFIFO (mxc_spi_reva_regs_t* spi); +void MXC_SPI_RevA_ClearTXFIFO (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetRXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes); +unsigned int MXC_SPI_RevA_GetRXThreshold (mxc_spi_reva_regs_t* spi); +int MXC_SPI_RevA_SetTXThreshold (mxc_spi_reva_regs_t* spi, unsigned int numBytes); +unsigned int MXC_SPI_RevA_GetTXThreshold (mxc_spi_reva_regs_t* spi); +unsigned int MXC_SPI_RevA_GetFlags (mxc_spi_reva_regs_t* spi); +void MXC_SPI_RevA_ClearFlags (mxc_spi_reva_regs_t* spi); +void MXC_SPI_RevA_EnableInt (mxc_spi_reva_regs_t* spi, unsigned int mask); +void MXC_SPI_RevA_DisableInt (mxc_spi_reva_regs_t* spi, unsigned int mask); +int MXC_SPI_RevA_MasterTransaction (mxc_spi_reva_req_t* req); +int MXC_SPI_RevA_MasterTransactionAsync (mxc_spi_reva_req_t* req); +int MXC_SPI_RevA_MasterTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma); +int MXC_SPI_RevA_SlaveTransaction (mxc_spi_reva_req_t* req); +int MXC_SPI_RevA_SlaveTransactionAsync (mxc_spi_reva_req_t* req); +int MXC_SPI_RevA_SlaveTransactionDMA (mxc_spi_reva_req_t* req, int reqselTx, int reqselRx, mxc_dma_regs_t* dma); +void MXC_SPI_RevA_DMACallback (int ch, int error); +int MXC_SPI_RevA_SetDefaultTXData (mxc_spi_reva_regs_t* spi, unsigned int defaultTXData); +void MXC_SPI_RevA_AbortAsync (mxc_spi_reva_regs_t* spi); +void MXC_SPI_RevA_AsyncHandler (mxc_spi_reva_regs_t* spi); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h new file mode 100644 index 00000000000..9dab65ee108 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva_regs.h @@ -0,0 +1,486 @@ +/** + * @file spi_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPI_REVA_REGS_H_ +#define _SPI_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spi + * @defgroup spi_registers SPI_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @details SPI peripheral. + */ + +/** + * @ingroup spi_registers + * Structure type to access the SPI Registers. + */ +typedef struct { + union{ + __IO uint32_t fifo32; /**< \b 0x00: SPI FIFO32 Register */ + __IO uint16_t fifo16[2]; /**< \b 0x00: SPI FIFO16 Register */ + __IO uint8_t fifo8[4]; /**< \b 0x00: SPI FIFO8 Register */ + }; + __IO uint32_t ctrl0; /**< \b 0x04: SPI CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x08: SPI CTRL1 Register */ + __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ + __IO uint32_t sstime; /**< \b 0x10: SPI SSTIME Register */ + __IO uint32_t clkctrl; /**< \b 0x14: SPI CLKCTRL Register */ + __R uint32_t rsv_0x18; + __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ + __IO uint32_t intfl; /**< \b 0x20: SPI INTFL Register */ + __IO uint32_t inten; /**< \b 0x24: SPI INTEN Register */ + __IO uint32_t wkfl; /**< \b 0x28: SPI WKFL Register */ + __IO uint32_t wken; /**< \b 0x2C: SPI WKEN Register */ + __I uint32_t stat; /**< \b 0x30: SPI STAT Register */ +} mxc_spi_reva_regs_t; + +/* Register offsets for module SPI */ +/** + * @ingroup spi_registers + * @defgroup SPI_Register_Offsets Register Offsets + * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. + * @{ + */ + #define MXC_R_SPI_REVA_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ + #define MXC_R_SPI_REVA_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ + #define MXC_R_SPI_REVA_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ + #define MXC_R_SPI_REVA_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ + #define MXC_R_SPI_REVA_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ + #define MXC_R_SPI_REVA_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ + #define MXC_R_SPI_REVA_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ + #define MXC_R_SPI_REVA_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ + #define MXC_R_SPI_REVA_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ + #define MXC_R_SPI_REVA_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ + #define MXC_R_SPI_REVA_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ + #define MXC_R_SPI_REVA_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ + #define MXC_R_SPI_REVA_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ + #define MXC_R_SPI_REVA_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +/**@} end of group spi_registers */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO32 SPI_FIFO32 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI_REVA_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ + #define MXC_F_SPI_REVA_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_REVA_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ + +/**@} end of group SPI_FIFO32_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO16 SPI_FIFO16 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI_REVA_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ + #define MXC_F_SPI_REVA_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_REVA_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ + +/**@} end of group SPI_FIFO16_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO8 SPI_FIFO8 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI_REVA_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ + #define MXC_F_SPI_REVA_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_REVA_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ + +/**@} end of group SPI_FIFO8_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL0 SPI_CTRL0 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI_REVA_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ + #define MXC_F_SPI_REVA_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ + + #define MXC_F_SPI_REVA_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ + #define MXC_F_SPI_REVA_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ + + #define MXC_F_SPI_REVA_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ + #define MXC_F_SPI_REVA_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ + + #define MXC_F_SPI_REVA_CTRL0_START_POS 5 /**< CTRL0_START Position */ + #define MXC_F_SPI_REVA_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_START_POS)) /**< CTRL0_START Mask */ + + #define MXC_F_SPI_REVA_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ + #define MXC_F_SPI_REVA_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ + + #define MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ + #define MXC_F_SPI_REVA_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ + #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ + #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ + #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ + #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ + #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ + #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ + #define MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ + #define MXC_S_SPI_REVA_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_REVA_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_REVA_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ + +/**@} end of group SPI_CTRL0_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL1 SPI_CTRL1 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ + #define MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_REVA_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ + + #define MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ + #define MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_REVA_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ + +/**@} end of group SPI_CTRL1_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL2 SPI_CTRL2 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI_REVA_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ + #define MXC_F_SPI_REVA_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ + + #define MXC_F_SPI_REVA_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ + #define MXC_F_SPI_REVA_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ + + #define MXC_F_SPI_REVA_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ + #define MXC_F_SPI_REVA_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ + #define MXC_V_SPI_REVA_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ + #define MXC_S_SPI_REVA_CTRL2_NUMBITS_0 (MXC_V_SPI_REVA_CTRL2_NUMBITS_0 << MXC_F_SPI_REVA_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ + + #define MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ + #define MXC_F_SPI_REVA_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ + #define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ + #define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ + #define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ + #define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ + #define MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ + #define MXC_S_SPI_REVA_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_REVA_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_REVA_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ + + #define MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ + #define MXC_F_SPI_REVA_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ + + #define MXC_F_SPI_REVA_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ + #define MXC_F_SPI_REVA_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ + #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ + #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ + #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ + #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ + #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ + #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ + #define MXC_V_SPI_REVA_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ + #define MXC_S_SPI_REVA_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI_REVA_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI_REVA_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ + +/**@} end of group SPI_CTRL2_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_SSTIME SPI_SSTIME + * @brief Register for controlling SPI peripheral/Slave Select Timing. + * @{ + */ + #define MXC_F_SPI_REVA_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ + #define MXC_F_SPI_REVA_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ + #define MXC_V_SPI_REVA_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ + #define MXC_S_SPI_REVA_SSTIME_PRE_256 (MXC_V_SPI_REVA_SSTIME_PRE_256 << MXC_F_SPI_REVA_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ + + #define MXC_F_SPI_REVA_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ + #define MXC_F_SPI_REVA_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ + #define MXC_V_SPI_REVA_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ + #define MXC_S_SPI_REVA_SSTIME_POST_256 (MXC_V_SPI_REVA_SSTIME_POST_256 << MXC_F_SPI_REVA_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ + + #define MXC_F_SPI_REVA_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ + #define MXC_F_SPI_REVA_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ + #define MXC_V_SPI_REVA_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ + #define MXC_S_SPI_REVA_SSTIME_INACT_256 (MXC_V_SPI_REVA_SSTIME_INACT_256 << MXC_F_SPI_REVA_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ + +/**@} end of group SPI_SSTIME_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CLKCTRL SPI_CLKCTRL + * @brief Register for controlling SPI clock rate. + * @{ + */ + #define MXC_F_SPI_REVA_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ + #define MXC_F_SPI_REVA_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ + #define MXC_V_SPI_REVA_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ + #define MXC_S_SPI_REVA_CLKCTRL_LO_DIS (MXC_V_SPI_REVA_CLKCTRL_LO_DIS << MXC_F_SPI_REVA_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ + + #define MXC_F_SPI_REVA_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ + #define MXC_F_SPI_REVA_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_REVA_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ + #define MXC_V_SPI_REVA_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ + #define MXC_S_SPI_REVA_CLKCTRL_HI_DIS (MXC_V_SPI_REVA_CLKCTRL_HI_DIS << MXC_F_SPI_REVA_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ + + #define MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ + #define MXC_F_SPI_REVA_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_REVA_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ + +/**@} end of group SPI_CLKCTRL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_DMA SPI_DMA + * @brief Register for controlling DMA. + * @{ + */ + #define MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ + #define MXC_F_SPI_REVA_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_REVA_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ + + #define MXC_F_SPI_REVA_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ + #define MXC_F_SPI_REVA_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ + + #define MXC_F_SPI_REVA_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ + #define MXC_F_SPI_REVA_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ + + #define MXC_F_SPI_REVA_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ + #define MXC_F_SPI_REVA_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_REVA_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ + + #define MXC_F_SPI_REVA_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ + #define MXC_F_SPI_REVA_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ + + #define MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ + #define MXC_F_SPI_REVA_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_REVA_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ + + #define MXC_F_SPI_REVA_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ + #define MXC_F_SPI_REVA_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ + + #define MXC_F_SPI_REVA_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ + #define MXC_F_SPI_REVA_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ + + #define MXC_F_SPI_REVA_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ + #define MXC_F_SPI_REVA_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_REVA_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ + + #define MXC_F_SPI_REVA_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ + #define MXC_F_SPI_REVA_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ + +/**@} end of group SPI_DMA_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INTFL SPI_INTFL + * @brief Register for reading and clearing interrupt flags. All bits are write 1 to + * clear. + * @{ + */ + #define MXC_F_SPI_REVA_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ + #define MXC_F_SPI_REVA_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ + + #define MXC_F_SPI_REVA_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ + #define MXC_F_SPI_REVA_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ + + #define MXC_F_SPI_REVA_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ + #define MXC_F_SPI_REVA_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ + + #define MXC_F_SPI_REVA_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ + #define MXC_F_SPI_REVA_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ + + #define MXC_F_SPI_REVA_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ + #define MXC_F_SPI_REVA_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ + + #define MXC_F_SPI_REVA_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ + #define MXC_F_SPI_REVA_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ + + #define MXC_F_SPI_REVA_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ + #define MXC_F_SPI_REVA_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ + + #define MXC_F_SPI_REVA_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ + #define MXC_F_SPI_REVA_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ + + #define MXC_F_SPI_REVA_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ + #define MXC_F_SPI_REVA_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ + + #define MXC_F_SPI_REVA_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ + #define MXC_F_SPI_REVA_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ + + #define MXC_F_SPI_REVA_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ + #define MXC_F_SPI_REVA_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ + + #define MXC_F_SPI_REVA_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ + #define MXC_F_SPI_REVA_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ + + #define MXC_F_SPI_REVA_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ + #define MXC_F_SPI_REVA_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ + +/**@} end of group SPI_INTFL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INTEN SPI_INTEN + * @brief Register for enabling interrupts. + * @{ + */ + #define MXC_F_SPI_REVA_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ + #define MXC_F_SPI_REVA_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ + + #define MXC_F_SPI_REVA_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ + #define MXC_F_SPI_REVA_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ + + #define MXC_F_SPI_REVA_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ + #define MXC_F_SPI_REVA_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ + + #define MXC_F_SPI_REVA_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ + #define MXC_F_SPI_REVA_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ + + #define MXC_F_SPI_REVA_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ + #define MXC_F_SPI_REVA_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ + + #define MXC_F_SPI_REVA_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ + #define MXC_F_SPI_REVA_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ + + #define MXC_F_SPI_REVA_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ + #define MXC_F_SPI_REVA_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ + + #define MXC_F_SPI_REVA_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ + #define MXC_F_SPI_REVA_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ + + #define MXC_F_SPI_REVA_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ + #define MXC_F_SPI_REVA_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ + + #define MXC_F_SPI_REVA_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ + #define MXC_F_SPI_REVA_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ + + #define MXC_F_SPI_REVA_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ + #define MXC_F_SPI_REVA_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ + + #define MXC_F_SPI_REVA_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ + #define MXC_F_SPI_REVA_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ + + #define MXC_F_SPI_REVA_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ + #define MXC_F_SPI_REVA_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_REVA_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ + +/**@} end of group SPI_INTEN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WKFL SPI_WKFL + * @brief Register for wake up flags. All bits in this register are write 1 to clear. + * @{ + */ + #define MXC_F_SPI_REVA_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ + #define MXC_F_SPI_REVA_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ + + #define MXC_F_SPI_REVA_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ + #define MXC_F_SPI_REVA_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ + + #define MXC_F_SPI_REVA_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ + #define MXC_F_SPI_REVA_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ + + #define MXC_F_SPI_REVA_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ + #define MXC_F_SPI_REVA_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ + +/**@} end of group SPI_WKFL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WKEN SPI_WKEN + * @brief Register for wake up enable. + * @{ + */ + #define MXC_F_SPI_REVA_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ + #define MXC_F_SPI_REVA_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ + + #define MXC_F_SPI_REVA_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ + #define MXC_F_SPI_REVA_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ + + #define MXC_F_SPI_REVA_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ + #define MXC_F_SPI_REVA_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ + + #define MXC_F_SPI_REVA_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ + #define MXC_F_SPI_REVA_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_REVA_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ + +/**@} end of group SPI_WKEN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_STAT SPI_STAT + * @brief SPI Status register. + * @{ + */ + #define MXC_F_SPI_REVA_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ + #define MXC_F_SPI_REVA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_REVA_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ + +/**@} end of group SPI_STAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPI_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c new file mode 100644 index 00000000000..04ee66236c4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_me11.c @@ -0,0 +1,124 @@ +/** + * @file i2s.c + * @brief Inter-Integrated Sound (I2S) driver implementation. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_pins.h" +#include "dma.h" +#include "i2s.h" +#include "i2s_reva.h" +#include "spimss.h" +#include "spimss_regs.h" + +#define I2S_CHANNELS 2 +#define I2S_WIDTH 16 + +int dma_channel = -1; + +int MXC_I2S_Init(const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int)) +{ + if(config->map == I2S_MAP_A) { + MXC_GPIO_Config(&gpio_cfg_spi1a); // SPIMSS: I2S and SPI share pins + } + else if(config->map == I2S_MAP_B) { + MXC_GPIO_Config(&gpio_cfg_spi1b); + } + else { + return E_BAD_PARAM; + } + + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 clock used for SPIMSS + + return MXC_I2S_RevA_Init((mxc_spimss_reva_regs_t*) MXC_SPIMSS, config, dma_ctz_cb); +} + +int MXC_I2S_Shutdown(void) +{ + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); // SPI1 used for SPIMSS + return MXC_I2S_RevA_Shutdown((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_Mute(void) +{ + return MXC_I2S_RevA_Mute((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_Unmute(void) +{ + return MXC_I2S_RevA_Unmute((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_Pause(void) +{ + return MXC_I2S_RevA_Pause((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_Unpause(void) +{ + return MXC_I2S_RevA_Unpause((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_Stop(void) +{ + return MXC_I2S_RevA_Stop((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_Start(void) +{ + return MXC_I2S_RevA_Start((mxc_spimss_reva_regs_t*) MXC_SPIMSS); +} + +int MXC_I2S_DMA_ClearFlags(void) +{ + return MXC_I2S_RevA_DMA_ClearFlags(); +} + +int MXC_I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count) +{ + return MXC_I2S_RevA_DMA_SetAddrCnt(src_addr, dst_addr, count); +} + +int MXC_I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count) +{ + return MXC_I2S_RevA_DMA_SetReload(src_addr, dst_addr, count); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c new file mode 100644 index 00000000000..f992e44a707 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.c @@ -0,0 +1,264 @@ +/** + * @file i2s.c + * @brief Inter-Integrated Sound(I2S) driver implementation. + */ + +/* **************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#include +#include +#include "mxc_errors.h" +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" +#include "i2s.h" +#include "i2s_reva.h" +#include "spimss.h" +#include "spimss_reva.h" + +#define I2S_CHANNELS 2 +#define I2S_WIDTH 16 + +static int dma_channel = -1; + +int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *config, void(*dma_ctz_cb)(int, int)) +{ + unsigned int baud; + uint16_t clkdiv; + uint8_t ctz_en; + int err; + + mxc_dma_config_t dma_config; + mxc_dma_srcdst_t srcdst; + + /* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */ + spimss->ctrl = MXC_F_SPIMSS_REVA_CTRL_MMEN; + spimss->mode = MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 | MXC_F_SPIMSS_REVA_MODE_SS_IO; + spimss->dma = MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8; + + /* Setup I2S register from i2s_cfg_t */ + spimss->i2s_ctrl = config->justify << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS | + config->audio_mode << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS; + + /* Determine divisor for baud rate generator */ + baud = config->sample_rate * I2S_CHANNELS * I2S_WIDTH; + + if((PeripheralClock / 4) < baud) { + return E_BAD_PARAM; + } + + clkdiv = PeripheralClock / (2 * baud); // Peripheral clock in system_max*****.h + + if(clkdiv < 2) { + return E_BAD_PARAM; + } + + spimss->brg = clkdiv; + + /* Prepare SPIMSS DMA register for DMA setup */ + if(dma_ctz_cb == NULL) { + ctz_en = 0; + } else { + ctz_en = 1; + } + + /* Initialize DMA */ + if(config->audio_direction % 2) { + spimss->dma |= MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR; + if((err = MXC_DMA_Init()) != E_NO_ERROR) { + if(err != E_BAD_STATE) { + return err; + } + } + + if((err = MXC_DMA_AcquireChannel()) < 0) { + return err; + } + + dma_channel = err; + + dma_config.ch = dma_channel; + + dma_config.srcwd = MXC_DMA_WIDTH_HALFWORD; + dma_config.dstwd = MXC_DMA_WIDTH_WORD; + #if TARGET_NUM == 32650 + dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSTX; + #endif + + dma_config.srcinc_en = 1; + dma_config.dstinc_en = 0; + + srcdst.ch = dma_channel; + srcdst.source = config->src_addr; + srcdst.len = config->length; + + MXC_DMA_ConfigChannel(dma_config, srcdst); + MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1); + + MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST; + MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS); + + if(ctz_en) { + MXC_DMA_SetCallback(dma_channel, dma_ctz_cb); + MXC_DMA_EnableInt(dma_channel); + } + } + if(config->audio_direction / 2) { + spimss->dma = MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR; + if((err = MXC_DMA_Init()) != E_NO_ERROR) { + if(err != E_BAD_STATE) { //DMA already initialized + return err; + } + } + + if((err = MXC_DMA_AcquireChannel()) < 0) { + return err; + } + + dma_channel = err; + + dma_config.ch = dma_channel; + + dma_config.srcwd = MXC_DMA_WIDTH_WORD; + dma_config.dstwd = MXC_DMA_WIDTH_HALFWORD; + #if TARGET_NUM == 32650 + dma_config.reqsel = MXC_DMA_REQUEST_SPIMSSRX; + #endif + + dma_config.srcinc_en = 0; + dma_config.dstinc_en = 1; + + srcdst.ch = dma_channel; + srcdst.dest = config->dst_addr; + srcdst.len = config->length; + + MXC_DMA_ConfigChannel(dma_config, srcdst); + MXC_DMA_SetChannelInterruptEn(dma_channel, 0, 1); + + MXC_DMA->ch[dma_channel].cfg &= ~MXC_F_DMA_CFG_BRST; + MXC_DMA->ch[dma_channel].cfg |= (0x1f << MXC_F_DMA_CFG_BRST_POS); + + if(ctz_en) { + MXC_DMA_SetCallback(dma_channel, dma_ctz_cb); + MXC_DMA_EnableInt(dma_channel); + } + } + + MXC_I2S_DMA_SetAddrCnt(config->src_addr, config->dst_addr, config->length); + if(config->dma_reload_en) { + MXC_I2S_DMA_SetReload(config->src_addr, config->dst_addr, config->length); + } + + if(config->start_immediately) { + return MXC_I2S_Start(); + } + return E_NO_ERROR; +} + +int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss) +{ + spimss->ctrl = 0; + spimss->i2s_ctrl = 0; + spimss->brg = 0; + spimss->mode = 0; + spimss->dma = 0; + return MXC_DMA_ReleaseChannel(dma_channel); +} + +int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss) +{ + spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE; + return E_NO_ERROR; +} + +int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss) +{ + spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE; + return E_NO_ERROR; +} + +int MXC_I2S_RevA_Pause(mxc_spimss_reva_regs_t *spimss) +{ + spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE; + return E_NO_ERROR; +} + +int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss) +{ + spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE; + return E_NO_ERROR; +} + +int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss) +{ + spimss->ctrl &= ~MXC_F_SPIMSS_REVA_CTRL_ENABLE; + spimss->i2s_ctrl &= ~MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN; + return MXC_DMA_Stop(dma_channel); +} + +int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss) +{ + spimss->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; + spimss->i2s_ctrl |= MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN; + return MXC_DMA_Start(dma_channel); +} + +int MXC_I2S_RevA_DMA_ClearFlags(void) +{ + int flags = MXC_DMA_ChannelGetFlags(dma_channel); + return MXC_DMA_ChannelClearFlags(dma_channel, flags); +} + +int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count) +{ + mxc_dma_srcdst_t srcdst; + srcdst.ch = dma_channel; + srcdst.source = src_addr; + srcdst.dest = dst_addr; + srcdst.len = count; + return MXC_DMA_SetSrcDst(srcdst); +} + +int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count) +{ + mxc_dma_srcdst_t srcdst; + srcdst.ch = dma_channel; + srcdst.source = src_addr; + srcdst.dest = dst_addr; + srcdst.len = count; + return MXC_DMA_SetSrcReload(srcdst); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h new file mode 100644 index 00000000000..84e7c753dc2 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/i2s_reva.h @@ -0,0 +1,52 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include +#include +#include "i2s.h" +#include "spimss_reva_regs.h" + + + +int MXC_I2S_RevA_Init(mxc_spimss_reva_regs_t *spimss, const mxc_i2s_config_t *req, void (*dma_ctz_cb)(int, int)); +int MXC_I2S_RevA_Shutdown(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_Mute(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_Unmute(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_Pause(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_Unpause(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_Stop(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_Start(mxc_spimss_reva_regs_t *spimss); +int MXC_I2S_RevA_DMA_ClearFlags(void); +int MXC_I2S_RevA_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count); +int MXC_I2S_RevA_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c new file mode 100644 index 00000000000..d69d258c5f6 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_me11.c @@ -0,0 +1,131 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spimss_reva_regs.h" +#include "spimss_reva.h" + + /* **** Functions **** */ + +/* ************************************************************************** */ +int MXC_SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_map_t sys_cfg, unsigned drv_ssel) +{ + if (mode > 3) { + return E_BAD_PARAM; + } + + // Check if frequency is too high + if (freq > PeripheralClock) { + return E_BAD_PARAM; + } + + // Configure GPIO for spimss + if (spi == MXC_SPIMSS) { + MXC_GCR->rst0 |= MXC_F_GCR_RST0_SPI1; + while (MXC_GCR->rst0 & MXC_F_GCR_RST0_SPI1); + MXC_GCR->pclk_dis0 &= ~ (MXC_F_GCR_PCLK_DIS0_SPI1D); + if(sys_cfg == MAP_A){ + MXC_GPIO_Config(&gpio_cfg_spi1a); // SPI1A chosen + }else if(sys_cfg == MAP_B){ + MXC_GPIO_Config(&gpio_cfg_spi1b); // SPI1B chosen + }else{ + return E_BAD_PARAM; + } + } else { + return E_NO_DEVICE; + } + + return MXC_SPIMSS_RevA_Init((mxc_spimss_reva_regs_t*) spi, mode, freq, drv_ssel); +} +/* ************************************************************************* */ +int MXC_SPIMSS_Shutdown(mxc_spimss_regs_t *spi) +{ + if(spi != MXC_SPIMSS) { + return E_NO_DEVICE; + } + + MXC_SPIMSS_RevA_Shutdown((mxc_spimss_reva_regs_t*) spi); + // + MXC_GCR->pclk_dis0 |= (MXC_F_GCR_PCLK_DIS0_SPI1D); + + return E_NO_ERROR; +} +/* ************************************************************************** */ +void MXC_SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ +{ + MXC_SPIMSS_RevA_Handler((mxc_spimss_reva_regs_t*) spi); +} + +/* ************************************************************************** */ +int MXC_SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) +{ + return MXC_SPIMSS_RevA_MasterTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); +} + + +/* ************************************************************************** */ +int MXC_SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) +{ + return MXC_SPIMSS_RevA_SlaveTrans((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); +} + +/* ************************************************************************** */ +int MXC_SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) +{ + return MXC_SPIMSS_RevA_MasterTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); +} + +/* ************************************************************************** */ +int MXC_SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, mxc_spimss_req_t *req) +{ + return MXC_SPIMSS_RevA_SlaveTransAsync((mxc_spimss_reva_regs_t*) spi, (spimss_reva_req_t*) req); +} + +/* ************************************************************************* */ +int MXC_SPIMSS_SetDefaultTXData(mxc_spimss_req_t* spi, unsigned int defaultTXData) +{ + return MXC_SPIMSS_RevA_SetDefaultTXData((spimss_reva_req_t*) spi, defaultTXData); +} + +/* ************************************************************************* */ +int MXC_SPIMSS_AbortAsync(mxc_spimss_req_t *req) +{ + return MXC_SPIMSS_RevA_AbortAsync((spimss_reva_req_t*) req); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c new file mode 100644 index 00000000000..cafa7d0b13d --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.c @@ -0,0 +1,515 @@ + /** + * @file spimss.c + * @brief This file contains the function implementations for the + * Serial Peripheral Interface (SPIMSS) peripheral module. + */ + +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "spimss_reva.h" +#include "mxc_lock.h" + +/** + * @ingroup spimss + * @{ + */ + +/* **** Definitions **** */ + + + +/* **** Globals **** */ +typedef struct { + spimss_reva_req_t *req; + unsigned defaultTXData; + unsigned drv_ssel; +} spimss_reva_req_state_t; + +static spimss_reva_req_state_t states[MXC_SPIMSS_INSTANCES]; + + +/* **** Functions **** */ +static int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master); +static uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +static uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +static uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); + +/* ************************************************************************** */ +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel) +{ + int spi_num; + unsigned int spimss_clk; + unsigned int pol, pha; // Polarity and phase of the clock (SPI mode) + + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + states[spi_num].req = NULL; + states[spi_num].defaultTXData = 0; + states[spi_num].drv_ssel = drv_ssel; + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Keep the SPI Disabled (This is the SPI Start) + + // Set the bit rate + spimss_clk = PeripheralClock; + spi->brg = (spimss_clk / freq) >> 1; + + // Set the mode + pol = mode >> 1; // Get the polarity out of the mode input value + pha = mode & 1; // Get the phase out of the mode input value + + spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS); // polarity + + spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_REVA_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS); // phase + + spi->int_fl &= ~(MXC_F_SPIMSS_REVA_INT_FL_IRQ); + + return E_NO_ERROR; +} +/* ************************************************************************* */ +int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi) +{ + int spi_num; + spimss_reva_req_t *temp_req; + + // Disable and turn off the SPI transaction. + spi->ctrl = 0; // Interrupts, SPI transaction all turned off + spi->int_fl = 0; + spi->mode = 0; + + // Reset FIFO counters + spi->dma &= ~(MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT); + + // Call all of the pending callbacks for this SPI + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + if (states[spi_num].req != NULL) { + + // Save the request + temp_req = states[spi_num].req; + + // Unlock this SPI + MXC_FreeLock((uint32_t*)&states[spi_num].req); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + spi->int_fl = 0; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SPIMSS_RevA_TransSetup(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req, int master) +{ + int spi_num; + + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Make sure the Initiation + // of SPI Start is disabled. + + spi->mode |= MXC_F_SPIMSS_REVA_MODE_TX_LJ; // Making sure data is left + // justified. + + if ((req->tx_data == NULL) && (req->rx_data == NULL)) { + return -1; + } + + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + MXC_ASSERT(spi_num >= 0); + + if (req->len == 0) { + return 0; + } + + req->tx_num = 0; + req->rx_num = 0; + + if (MXC_GetLock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + if (master) { // Enable master mode + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_MMEN; // SPI configured as master. + if (states[spi_num].drv_ssel) { + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SS_IO; // SSEL pin is an output. + } + } else { // Enable slave mode + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_MMEN); // SPI configured as slave. + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SS_IO); // SSEL pin is an input. + } + + // Setup the character size + + if (req->bits <16) { + MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , req->bits << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); + + } else { + MXC_SETFIELD(spi->mode, MXC_F_SPIMSS_REVA_MODE_NUMBITS , 0 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS); + + } + + if (req->tx_data == NULL) { + // Must have something to send, so we'll use the rx_data buffer initialized to 0. + memset(req->rx_data, states[spi_num].defaultTXData, (req->bits > 8 ? req->len << 1 : req->len)); + req->tx_data = req->rx_data; + } + + // Clear the TX and RX FIFO + spi->dma |= (MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR | MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR); + + if (states[spi_num].drv_ssel) { + // Setup the slave select + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; // Assert a high on Slave Select, + // to get the line ready for active low later + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi) // From the IRQ +{ + int spi_num; + uint32_t flags; + unsigned int int_enable; + + flags = spi->int_fl; + spi->int_fl = flags; + spi->int_fl|= 0x80; // clear interrupt + + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + + int_enable = 0; + if (states[spi_num].req != NULL) { + if ((spi->ctrl & MXC_F_SPIMSS_REVA_CTRL_MMEN) >> MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) { + int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi, states[spi_num].req); + + } else { + int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi, states[spi_num].req); + } + } + + if (int_enable==1) { + spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE ); + + } +} + +/* ************************************************************************** */ +int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + int error; + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + + if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1)) != E_NO_ERROR) { + return error; + } + + req->callback = NULL; + + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + if (states[spi_num].drv_ssel) { + spi->mode &= ~(MXC_F_SPIMSS_REVA_MODE_SSV); // This will assert the Slave Select. + } + + while (MXC_SPIMSS_RevA_MasterTransHandler(spi,req)!=0) { + ; + } + + if (states[spi_num].drv_ssel) { + spi->mode |= MXC_F_SPIMSS_REVA_MODE_SSV; + } + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... + // stop the transmission... + return E_NO_ERROR; +} + + +/* ************************************************************************** */ +int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + int error; + + if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req,0)) != E_NO_ERROR) { + return error; + } + + while (MXC_SPIMSS_RevA_SlaveTransHandler(spi,req)!=0) { + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + while ((spi->int_fl & MXC_F_SPIMSS_REVA_INT_FL_TXST) == MXC_F_SPIMSS_REVA_INT_FL_TXST) {} + } + + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); // Last of the SPIMSS value has been transmitted... + // stop the transmission... + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + int error; + uint8_t int_enable; + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + + if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 1) )!= E_NO_ERROR) { + return error; + } + + int_enable = MXC_SPIMSS_RevA_MasterTransHandler(spi,req); + + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + if (states[spi_num].drv_ssel) { + spi->mode ^= MXC_F_SPIMSS_REVA_MODE_SSV; // This will assert the Slave Select. + } + + if (int_enable==1) { + spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + int error; + uint8_t int_enable; + if ((error = MXC_SPIMSS_RevA_TransSetup(spi, req, 0)) != E_NO_ERROR) { + return error; + } + + int_enable = MXC_SPIMSS_RevA_SlaveTransHandler(spi,req); + + spi->ctrl |= MXC_F_SPIMSS_REVA_CTRL_ENABLE; // Enable/Start SPI + + if (int_enable==1) { // Trigger a SPI Interrupt + spi->ctrl |= (MXC_F_SPIMSS_REVA_CTRL_IRQE ); + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +uint32_t MXC_SPIMSS_RevA_MasterTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + unsigned start_set = 0; + uint32_t retval; + + if (!start_set) { + start_set = 1; + retval = MXC_SPIMSS_RevA_TransHandler(spi,req); + } + + return retval; +} + +/* ************************************************************************** */ +uint32_t MXC_SPIMSS_RevA_SlaveTransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + return MXC_SPIMSS_RevA_TransHandler(spi,req); +} + +/* ************************************************************************** */ +uint32_t MXC_SPIMSS_RevA_TransHandler(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req) +{ + unsigned tx_avail, rx_avail; + int remain, spi_num; + uint32_t int_en =0; + uint32_t length =req->len; + + spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + if (spi_num < 0) { + MXC_ASSERT(0); + } + + // Note:- spi->dma shows the FIFO TX count and FIFO RX count in + // Words, while the calculation below is in bytes. + if (req->tx_data != NULL) { + + if (req->tx_num < length) { + + // Calculate how many bytes we can write to the FIFO (tx_avail holds that value) + tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); // in bytes + + if ((length - req->tx_num) < tx_avail) { + tx_avail = (length - req->tx_num); // This is for the last spin + } + if (req->bits > 8) { + tx_avail &= ~(unsigned)0x1; + } + // Write the FIFO + while (tx_avail) { + if (req->bits >8) { + spi->data = ((uint16_t*)req->tx_data)[req->tx_num++]; + + tx_avail -= 1; + } else { + spi->data = ((uint8_t*)req->tx_data)[req->tx_num++]; + tx_avail -=1; + } + + } + } + + remain = length - req->tx_num; + + // If there are values remaining to be transmitted, this portion will get + // executed and int_en set, to indicate that this must spin and come back again... + if (remain) { + if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum, + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); + } else { // only one more tx round will be done... Transfer whatever remains, + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)); + } + int_en = 1; // This will act as a trigger for the next round... + } + + // Break out if we've transmitted all the bytes and not receiving + if ((req->rx_data == NULL) && (req->tx_num == length)) { + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); + int_en = 0; + MXC_FreeLock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + } + + // Read the RX FIFO + // Wait for there to be data in the RX FIFO + uint16_t rx_data; + + rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS); + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + + // Read from the FIFO + while (rx_avail) { + rx_data = spi->data; + rx_avail -= 1; + + if (req->rx_data != NULL) { + if (req->bits>8) { + ((uint16_t*)req->rx_data)[req->rx_num] = rx_data; + } else { + ((uint8_t*)req->rx_data)[req->rx_num] = rx_data; + } + } + req->rx_num++; // assume read one byte + + rx_avail = ((spi->dma & MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS); + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + } + + remain = length - req->rx_num; + if (remain) { + if (remain > MXC_SPIMSS_FIFO_DEPTH) { + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)); + } else { + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)); + } + int_en = 1; + } + + // Break out once we've transmitted and received all of the data + if ((req->rx_num == length) && (req->tx_num == length)) { + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); + int_en = 0; + MXC_FreeLock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + + return int_en; +} + +/* ************************************************************************* */ +int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData) +{ + int spi_num = MXC_SPIMSS_GET_IDX((mxc_spimss_regs_t*) spi); + MXC_ASSERT (spi_num >= 0); + states[spi_num].defaultTXData = defaultTXData; + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req) +{ + int spi_num; + mxc_spimss_reva_regs_t *spi; + + // Check the input parameters + if (req == NULL) { + return E_BAD_PARAM; + } + + // Find the request, set to NULL + for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) { + if (req == states[spi_num].req) { + + spi =(mxc_spimss_reva_regs_t *) MXC_SPIMSS_GET_SPI(spi_num); + + // Disable interrupts, clear the flags + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_IRQE | MXC_F_SPIMSS_REVA_CTRL_STR); + + // Disable and turn off the SPI transaction. + spi->ctrl &= ~(MXC_F_SPIMSS_REVA_CTRL_ENABLE); + + // Unlock this SPI + MXC_FreeLock((uint32_t*)&states[spi_num].req); + + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_ABORT); + } + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} +/**@} end of group spimss */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h new file mode 100644 index 00000000000..eb3323d7d7f --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva.h @@ -0,0 +1,104 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include +#include +#include "mxc_errors.h" +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spimss_regs.h" +#include "spimss_reva_regs.h" +#include "spimss.h" + + /** + * @brief Enumeration type for setting the number data lines to use for communication. + */ +typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED + DUMMY_1_RevA, /**< NOT USED */ + DUMMY_2_RevA, /**< NOT USED */ + DUMMY_3_RevA, /**< NOT USED */ +} spimss_reva_width_t; + +/** + * @brief Structure type representing a SPI Master Transaction request. + */ +typedef struct spimss_reva_req spimss_reva_req_t; + +/** + * @brief Callback function type used in asynchronous SPI Master communication requests. + * @details The function declaration for the SPI Master callback is: + * @code + * void callback(spi_req_t * req, int error_code); + * @endcode + * | | | + * | -----: | :----------------------------------------- | + * | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. | + * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | + * @note Callback will execute in interrupt context + * @addtogroup spi_async + */ +typedef void (*spimss_reva_callback_fn)(spimss_reva_req_t * req, int error_code); + +/** + * @brief Structure definition for an SPI Master Transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + * @addtogroup spi_async + */ +struct spimss_reva_req { + uint8_t ssel; /**< Not Used*/ + uint8_t deass; /**< Not Used*/ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + spimss_reva_width_t width; /**< Not Used */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + spimss_reva_callback_fn callback; /**< Callback function if desired, NULL otherwise */ +}; + + +int MXC_SPIMSS_RevA_Init(mxc_spimss_reva_regs_t *spi, unsigned mode, unsigned freq, unsigned drv_ssel); +int MXC_SPIMSS_RevA_Shutdown(mxc_spimss_reva_regs_t *spi); +void MXC_SPIMSS_RevA_Handler(mxc_spimss_reva_regs_t *spi); +int MXC_SPIMSS_RevA_MasterTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +int MXC_SPIMSS_RevA_SlaveTrans(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +int MXC_SPIMSS_RevA_MasterTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +int MXC_SPIMSS_RevA_SlaveTransAsync(mxc_spimss_reva_regs_t *spi, spimss_reva_req_t *req); +int MXC_SPIMSS_RevA_SetDefaultTXData (spimss_reva_req_t* spi, unsigned int defaultTXData); +int MXC_SPIMSS_RevA_AbortAsync(spimss_reva_req_t *req); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h new file mode 100644 index 00000000000..f0281426ca0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPIMSS/spimss_reva_regs.h @@ -0,0 +1,460 @@ +/** + * @file spimss_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPIMSS_REVA_REGS_H_ +#define _SPIMSS_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spimss + * @defgroup spimss_registers SPIMSS_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + * @details Serial Peripheral Interface. + */ + +/** + * @ingroup spimss_registers + * Structure type to access the SPIMSS Registers. + */ +typedef struct { + __IO uint16_t data; /**< \b 0x00: SPIMSS DATA Register */ + __R uint16_t rsv_0x2; + __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ + __IO uint32_t int_fl; /**< \b 0x08: SPIMSS INT_FL Register */ + __IO uint32_t mode; /**< \b 0x0C: SPIMSS MODE Register */ + __R uint32_t rsv_0x10; + __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ + __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ + __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ +} mxc_spimss_reva_regs_t; + +/* Register offsets for module SPIMSS */ +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_Register_Offsets Register Offsets + * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. + * @{ + */ + #define MXC_R_SPIMSS_REVA_DATA ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ + #define MXC_R_SPIMSS_REVA_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: 0x0004 */ + #define MXC_R_SPIMSS_REVA_INT_FL ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: 0x0008 */ + #define MXC_R_SPIMSS_REVA_MODE ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: 0x000C */ + #define MXC_R_SPIMSS_REVA_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: 0x0014 */ + #define MXC_R_SPIMSS_REVA_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: 0x0018 */ + #define MXC_R_SPIMSS_REVA_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: 0x001C */ +/**@} end of group spimss_registers */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DATA SPIMSS_DATA + * @brief SPI 16-bit Data Access + * @{ + */ + #define MXC_F_SPIMSS_REVA_DATA_DATA_POS 0 /**< DATA_DATA Position */ + #define MXC_F_SPIMSS_REVA_DATA_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_REVA_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group SPIMSS_DATA_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_CTRL SPIMSS_CTRL + * @brief SPI Control Register. + * @{ + */ + #define MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ + #define MXC_F_SPIMSS_REVA_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_ENABLE_DISABLE ((uint32_t)0x0UL) /**< CTRL_ENABLE_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_ENABLE_DISABLE (MXC_V_SPIMSS_REVA_CTRL_ENABLE_DISABLE << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_ENABLE_ENABLE ((uint32_t)0x1UL) /**< CTRL_ENABLE_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_ENABLE_ENABLE (MXC_V_SPIMSS_REVA_CTRL_ENABLE_ENABLE << MXC_F_SPIMSS_REVA_CTRL_ENABLE_POS) /**< CTRL_ENABLE_ENABLE Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ + #define MXC_F_SPIMSS_REVA_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_REVA_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */ + #define MXC_S_SPIMSS_REVA_CTRL_MMEN_MASTER (MXC_V_SPIMSS_REVA_CTRL_MMEN_MASTER << MXC_F_SPIMSS_REVA_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ + #define MXC_F_SPIMSS_REVA_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_WOR_DISABLE (MXC_V_SPIMSS_REVA_CTRL_WOR_DISABLE << MXC_F_SPIMSS_REVA_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_WOR_ENABLE (MXC_V_SPIMSS_REVA_CTRL_WOR_ENABLE << MXC_F_SPIMSS_REVA_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ + #define MXC_F_SPIMSS_REVA_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */ + #define MXC_S_SPIMSS_REVA_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */ + #define MXC_S_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_REVA_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_REVA_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ + #define MXC_F_SPIMSS_REVA_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_REVA_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_REVA_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_REVA_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ + #define MXC_F_SPIMSS_REVA_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_REVA_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_REVA_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_REVA_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_STR_POS 6 /**< CTRL_STR Position */ + #define MXC_F_SPIMSS_REVA_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_STR_POS)) /**< CTRL_STR Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_STR_COMPLETE (MXC_V_SPIMSS_REVA_CTRL_STR_COMPLETE << MXC_F_SPIMSS_REVA_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */ + #define MXC_S_SPIMSS_REVA_CTRL_STR_START (MXC_V_SPIMSS_REVA_CTRL_STR_START << MXC_F_SPIMSS_REVA_CTRL_STR_POS) /**< CTRL_STR_START Setting */ + + #define MXC_F_SPIMSS_REVA_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ + #define MXC_F_SPIMSS_REVA_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ + #define MXC_V_SPIMSS_REVA_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_REVA_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_REVA_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_REVA_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */ + +/**@} end of group SPIMSS_CTRL_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_INT_FL SPIMSS_INT_FL + * @brief SPI Interrupt Flag Register. + * @{ + */ + #define MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS 0 /**< INT_FL_SLAS Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS)) /**< INT_FL_SLAS Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_SLAS_SELECTED ((uint32_t)0x0UL) /**< INT_FL_SLAS_SELECTED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_SLAS_SELECTED (MXC_V_SPIMSS_REVA_INT_FL_SLAS_SELECTED << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS) /**< INT_FL_SLAS_SELECTED Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< INT_FL_SLAS_NOTSELECTED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED (MXC_V_SPIMSS_REVA_INT_FL_SLAS_NOTSELECTED << MXC_F_SPIMSS_REVA_INT_FL_SLAS_POS) /**< INT_FL_SLAS_NOTSELECTED Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_TXST_POS 1 /**< INT_FL_TXST Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS)) /**< INT_FL_TXST Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_TXST_IDLE ((uint32_t)0x0UL) /**< INT_FL_TXST_IDLE Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_TXST_IDLE (MXC_V_SPIMSS_REVA_INT_FL_TXST_IDLE << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS) /**< INT_FL_TXST_IDLE Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_TXST_BUSY ((uint32_t)0x1UL) /**< INT_FL_TXST_BUSY Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_TXST_BUSY (MXC_V_SPIMSS_REVA_INT_FL_TXST_BUSY << MXC_F_SPIMSS_REVA_INT_FL_TXST_POS) /**< INT_FL_TXST_BUSY Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_TUND_POS 2 /**< INT_FL_TUND Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS)) /**< INT_FL_TUND Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_TUND_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TUND_NOEVENT Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_TUND_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_TUND_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS) /**< INT_FL_TUND_NOEVENT Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_TUND_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_TUND_OCCURRED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_TUND_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_TUND_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_TUND_POS) /**< INT_FL_TUND_OCCURRED Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS 3 /**< INT_FL_ROVR Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS)) /**< INT_FL_ROVR Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_ROVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ROVR_NOEVENT Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_ROVR_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_ROVR_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS) /**< INT_FL_ROVR_NOEVENT Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_ROVR_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_ROVR_OCCURRED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_ROVR_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_ROVR_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_ROVR_POS) /**< INT_FL_ROVR_OCCURRED Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_ABT_POS 4 /**< INT_FL_ABT Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS)) /**< INT_FL_ABT Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_ABT_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_ABT_NOEVENT Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_ABT_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_ABT_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS) /**< INT_FL_ABT_NOEVENT Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_ABT_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_ABT_OCCURRED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_ABT_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_ABT_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_ABT_POS) /**< INT_FL_ABT_OCCURRED Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_COL_POS 5 /**< INT_FL_COL Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_COL_POS)) /**< INT_FL_COL Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_COL_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_COL_NOEVENT Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_COL_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_COL_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_COL_POS) /**< INT_FL_COL_NOEVENT Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_COL_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_COL_OCCURRED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_COL_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_COL_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_COL_POS) /**< INT_FL_COL_OCCURRED Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS 6 /**< INT_FL_TOVR Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS)) /**< INT_FL_TOVR Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_TOVR_NOEVENT ((uint32_t)0x0UL) /**< INT_FL_TOVR_NOEVENT Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_TOVR_NOEVENT (MXC_V_SPIMSS_REVA_INT_FL_TOVR_NOEVENT << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS) /**< INT_FL_TOVR_NOEVENT Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_TOVR_OCCURRED ((uint32_t)0x1UL) /**< INT_FL_TOVR_OCCURRED Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_TOVR_OCCURRED (MXC_V_SPIMSS_REVA_INT_FL_TOVR_OCCURRED << MXC_F_SPIMSS_REVA_INT_FL_TOVR_POS) /**< INT_FL_TOVR_OCCURRED Setting */ + + #define MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS 7 /**< INT_FL_IRQ Position */ + #define MXC_F_SPIMSS_REVA_INT_FL_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS)) /**< INT_FL_IRQ Mask */ + #define MXC_V_SPIMSS_REVA_INT_FL_IRQ_INACTIVE ((uint32_t)0x0UL) /**< INT_FL_IRQ_INACTIVE Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_IRQ_INACTIVE (MXC_V_SPIMSS_REVA_INT_FL_IRQ_INACTIVE << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS) /**< INT_FL_IRQ_INACTIVE Setting */ + #define MXC_V_SPIMSS_REVA_INT_FL_IRQ_PENDING ((uint32_t)0x1UL) /**< INT_FL_IRQ_PENDING Value */ + #define MXC_S_SPIMSS_REVA_INT_FL_IRQ_PENDING (MXC_V_SPIMSS_REVA_INT_FL_IRQ_PENDING << MXC_F_SPIMSS_REVA_INT_FL_IRQ_POS) /**< INT_FL_IRQ_PENDING Setting */ + +/**@} end of group SPIMSS_INT_FL_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_MODE SPIMSS_MODE + * @brief SPI Mode Register. + * @{ + */ + #define MXC_F_SPIMSS_REVA_MODE_SSV_POS 0 /**< MODE_SSV Position */ + #define MXC_F_SPIMSS_REVA_MODE_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_SSV_POS)) /**< MODE_SSV Mask */ + #define MXC_V_SPIMSS_REVA_MODE_SSV_LO ((uint32_t)0x0UL) /**< MODE_SSV_LO Value */ + #define MXC_S_SPIMSS_REVA_MODE_SSV_LO (MXC_V_SPIMSS_REVA_MODE_SSV_LO << MXC_F_SPIMSS_REVA_MODE_SSV_POS) /**< MODE_SSV_LO Setting */ + #define MXC_V_SPIMSS_REVA_MODE_SSV_HI ((uint32_t)0x1UL) /**< MODE_SSV_HI Value */ + #define MXC_S_SPIMSS_REVA_MODE_SSV_HI (MXC_V_SPIMSS_REVA_MODE_SSV_HI << MXC_F_SPIMSS_REVA_MODE_SSV_POS) /**< MODE_SSV_HI Setting */ + + #define MXC_F_SPIMSS_REVA_MODE_SS_IO_POS 1 /**< MODE_SS_IO Position */ + #define MXC_F_SPIMSS_REVA_MODE_SS_IO ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS)) /**< MODE_SS_IO Mask */ + #define MXC_V_SPIMSS_REVA_MODE_SS_IO_INPUT ((uint32_t)0x0UL) /**< MODE_SS_IO_INPUT Value */ + #define MXC_S_SPIMSS_REVA_MODE_SS_IO_INPUT (MXC_V_SPIMSS_REVA_MODE_SS_IO_INPUT << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS) /**< MODE_SS_IO_INPUT Setting */ + #define MXC_V_SPIMSS_REVA_MODE_SS_IO_OUTPUT ((uint32_t)0x1UL) /**< MODE_SS_IO_OUTPUT Value */ + #define MXC_S_SPIMSS_REVA_MODE_SS_IO_OUTPUT (MXC_V_SPIMSS_REVA_MODE_SS_IO_OUTPUT << MXC_F_SPIMSS_REVA_MODE_SS_IO_POS) /**< MODE_SS_IO_OUTPUT Setting */ + + #define MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS 2 /**< MODE_NUMBITS Position */ + #define MXC_F_SPIMSS_REVA_MODE_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS)) /**< MODE_NUMBITS Mask */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MODE_NUMBITS_BITS16 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS16 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS16 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS16 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MODE_NUMBITS_BITS1 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS1 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS1 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS1 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MODE_NUMBITS_BITS2 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS2 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS2 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS2 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MODE_NUMBITS_BITS3 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS3 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS3 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS3 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MODE_NUMBITS_BITS4 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS4 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS4 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS4 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MODE_NUMBITS_BITS5 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS5 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS5 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS5 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MODE_NUMBITS_BITS6 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS6 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS6 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS6 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MODE_NUMBITS_BITS7 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS7 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS7 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS7 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MODE_NUMBITS_BITS8 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS8 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS8 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS8 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MODE_NUMBITS_BITS9 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS9 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS9 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS9 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MODE_NUMBITS_BITS10 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS10 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS10 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS10 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MODE_NUMBITS_BITS11 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS11 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS11 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS11 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MODE_NUMBITS_BITS12 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS12 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS12 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS12 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MODE_NUMBITS_BITS13 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS13 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS13 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS13 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MODE_NUMBITS_BITS14 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS14 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS14 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS14 Setting */ + #define MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MODE_NUMBITS_BITS15 Value */ + #define MXC_S_SPIMSS_REVA_MODE_NUMBITS_BITS15 (MXC_V_SPIMSS_REVA_MODE_NUMBITS_BITS15 << MXC_F_SPIMSS_REVA_MODE_NUMBITS_POS) /**< MODE_NUMBITS_BITS15 Setting */ + + #define MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS 7 /**< MODE_TX_LJ Position */ + #define MXC_F_SPIMSS_REVA_MODE_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS)) /**< MODE_TX_LJ Mask */ + #define MXC_V_SPIMSS_REVA_MODE_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MODE_TX_LJ_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_MODE_TX_LJ_DISABLE (MXC_V_SPIMSS_REVA_MODE_TX_LJ_DISABLE << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS) /**< MODE_TX_LJ_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_MODE_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MODE_TX_LJ_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_MODE_TX_LJ_ENABLE (MXC_V_SPIMSS_REVA_MODE_TX_LJ_ENABLE << MXC_F_SPIMSS_REVA_MODE_TX_LJ_POS) /**< MODE_TX_LJ_ENABLE Setting */ + +/**@} end of group SPIMSS_MODE_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_BRG SPIMSS_BRG + * @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for + * the SPI Baud Rate Generator. The reload value must be greater than or equal to + * 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by + * 4). + * @{ + */ + #define MXC_F_SPIMSS_REVA_BRG_DIV_POS 0 /**< BRG_DIV Position */ + #define MXC_F_SPIMSS_REVA_BRG_DIV ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_REVA_BRG_DIV_POS)) /**< BRG_DIV Mask */ + +/**@} end of group SPIMSS_BRG_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DMA SPIMSS_DMA + * @brief SPI DMA Register. + * @{ + */ + #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ + #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LVL_ENTRY1 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LVL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LVL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LVL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LVL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LVL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LVL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LVL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_LVL_POS) /**< DMA_TX_FIFO_LVL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS 4 /**< DMA_TX_FIFO_CLR Position */ + #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS)) /**< DMA_TX_FIFO_CLR Mask */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLR_COMPLETE Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_COMPLETE << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_COMPLETE Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLR_START Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_FIFO_CLR_START (MXC_V_SPIMSS_REVA_DMA_TX_FIFO_CLR_START << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CLR_POS) /**< DMA_TX_FIFO_CLR_START Setting */ + + #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + #define MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_REVA_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_REVA_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */ + + #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ + #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL ((uint32_t)(0x7UL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LVL_ENTRY1 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LVL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LVL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LVL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LVL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LVL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LVL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LVL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_LVL_POS) /**< DMA_RX_FIFO_LVL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS 20 /**< DMA_RX_FIFO_CLR Position */ + #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLR_COMPLETE Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_COMPLETE << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_COMPLETE Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLR_START Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_FIFO_CLR_START (MXC_V_SPIMSS_REVA_DMA_RX_FIFO_CLR_START << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CLR_POS) /**< DMA_RX_FIFO_CLR_START Setting */ + + #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_REVA_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + #define MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_REVA_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_REVA_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */ + +/**@} end of group SPIMSS_DMA_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL + * @brief I2S Control Register. + * @{ + */ + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */ + + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */ + + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */ + + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */ + + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ + #define MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */ + #define MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */ + #define MXC_S_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_REVA_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_REVA_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */ + +/**@} end of group SPIMSS_I2S_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPIMSS_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c new file mode 100644 index 00000000000..7f3c9131b59 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_assert.c @@ -0,0 +1,48 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" + +/* **** Definitions **** */ + +/* **** Globals *****/ + +/* **** Functions **** */ + +/* ************************************************************************** */ +__weak void mxc_assert(const char* expr, const char* file, int line) +{ + while (1) {} +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c new file mode 100644 index 00000000000..88963b51731 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_delay.c @@ -0,0 +1,257 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include "mxc_device.h" +#include "mxc_delay.h" +#include "mxc_sys.h" + +#ifdef __riscv + +int MXC_Delay(unsigned long us) +{ + // Check if there is nothing to do + if (us == 0) { + return E_NO_ERROR; + } + + // Calculate number of cycles needed. + uint32_t ticks = (MXC_SYS_RiscVClockRate() / 1000000) * us; + + CSR_SetPCMR(0); // Turn off counter + CSR_SetPCCR(0); // Clear counter register + CSR_SetPCER(1); // Enable counting of cycles + CSR_SetPCMR(3); // Turn on counter + + while(CSR_GetPCCR() < ticks) { + // Wait for counter to reach the tick count. + } + return E_NO_ERROR; +} + +int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback) +{ + return E_NOT_SUPPORTED; +} + +int MXC_DelayCheck(void) +{ + return E_NOT_SUPPORTED; +} + +void MXC_DelayAbort(void) +{ +} + +#else + +/* **** File Scope Variables **** */ +static volatile int overflows = -1; +static uint32_t endtick; +static uint32_t ctrl_save; +static mxc_delay_complete_t cbFunc; + +static void MXC_DelayInit(unsigned long us); +extern void SysTick_Handler(void); + +/* ************************************************************************** */ +__weak void SysTick_Handler(void) +{ + MXC_DelayHandler(); +} + +/* ************************************************************************** */ +void MXC_DelayHandler(void) +{ + // Check and clear overflow flag + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) { + // Decrement overflow flag if delay is still ongoing + if (overflows > 0) { + overflows--; + } + else { + MXC_DelayAbort(); + + if (cbFunc != NULL) { + cbFunc(E_NO_ERROR); + cbFunc = NULL; + } + } + } +} + +/* ************************************************************************** */ +static void MXC_DelayInit(unsigned long us) +{ + uint32_t starttick, reload, ticks, lastticks; + + // Record the current tick value and clear the overflow flag + starttick = SysTick->VAL; + + // Save the state of control register (and clear the overflow flag) + ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk; + + // If the SysTick is not running, configure and start it + if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; + SysTick->VAL = SysTick_VAL_CURRENT_Msk; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_CLKSOURCE_Msk; + starttick = SysTick_VAL_CURRENT_Msk; + reload = SysTick_LOAD_RELOAD_Msk + 1; + } + else { + reload = SysTick->LOAD + 1; // get the current reload value + } + + // Calculate the total number of ticks to delay + ticks = (uint32_t)(((uint64_t) us * (uint64_t) SystemCoreClock) / 1000000); + + // How many overflows of the SysTick will occur + overflows = ticks / reload; + + // How many remaining ticks after the last overflow + lastticks = ticks % reload; + + // Check if there will be another overflow due to the current value of the SysTick + if (lastticks >= starttick) { + overflows++; + endtick = reload - (lastticks - starttick); + } + else { + endtick = starttick - lastticks; + } +} + +/* ************************************************************************** */ +int MXC_DelayAsync(unsigned long us, mxc_delay_complete_t callback) +{ + cbFunc = callback; + + // Check if timeout currently ongoing + if (overflows > 0) { + return E_BUSY; + } + + // Check if there is nothing to do + if (us == 0) { + return E_NO_ERROR; + } + + // Calculate the necessary delay and start the timer + MXC_DelayInit(us); + + // Enable SysTick interrupt if necessary + if (overflows > 0) { + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_DelayCheck(void) +{ + // Check if timeout currently ongoing + if (overflows < 0) { + if (cbFunc != NULL) { + cbFunc(E_NO_ERROR); + cbFunc = NULL; + } + + return E_NO_ERROR; + } + + // Check the global values + if ((overflows == 0) && (SysTick->VAL <= endtick)) { + MXC_DelayAbort(); + + if (cbFunc != NULL) { + cbFunc(E_NO_ERROR); + cbFunc = NULL; + } + + return E_NO_ERROR; + } + + return E_BUSY; +} + +/* ************************************************************************** */ +void MXC_DelayAbort(void) +{ + if (cbFunc != NULL) { + cbFunc(E_ABORT); + cbFunc = NULL; + } + + SysTick->CTRL = ctrl_save; + overflows = -1; +} + +/* ************************************************************************** */ +int MXC_Delay(unsigned long us) +{ + // Check if timeout currently ongoing + if (overflows > 0) { + return E_BUSY; + } + + // Check if there is nothing to do + if (us == 0) { + return E_NO_ERROR; + } + + // Calculate the necessary delay and start the timer + MXC_DelayInit(us); + + // Wait for the number of overflows + while (overflows > 0) { + // If SysTick interrupts are enabled, COUNTFLAG will never be set here and + // overflows will be decremented in the ISR. If SysTick interrupts are + // disabled, overflows is decremented here. + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) { + overflows--; + } + } + + // Wait for the counter value + while (SysTick->VAL > endtick); + + MXC_DelayAbort(); + return E_NO_ERROR; +} + +#endif // __riscv \ No newline at end of file diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c new file mode 100644 index 00000000000..f8f199439ad --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -0,0 +1,83 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_lock.h" + +#if USE_LOCK_IN_DRIVERS + +#ifndef __riscv +/* ************************************************************************** */ +int MXC_GetLock(uint32_t* lock, uint32_t value) +{ + do { + + // Return if the lock is taken by a different thread + if (__LDREXW((volatile unsigned long*) lock) != 0) { + return E_BUSY; + } + + // Attempt to take the lock + } + while (__STREXW(value, (volatile unsigned long*) lock) != 0); + + // Do not start any other memory access until memory barrier is complete + __DMB(); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void MXC_FreeLock(uint32_t* lock) +{ + // Ensure memory operations complete before releasing lock + __DMB(); + *lock = 0; +} +#else // __riscv +/* ************************************************************************** */ +int MXC_GetLock(uint32_t* lock, uint32_t value) +{ + #warning "Unimplemented for RISCV" + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void MXC_FreeLock(uint32_t* lock) +{ + #warning "Unimplemented for RISCV" +} +#endif + +#endif // USE_LOCK_IN_DRIVERS diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c new file mode 100644 index 00000000000..afe7258983c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/pins_me11.c @@ -0,0 +1,76 @@ +/** + * @file mxc_pins.c + * @brief This file contains constant pin configurations for the peripherals. + */ + +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + **************************************************************************** */ + +#include "gpio.h" +#include "mxc_device.h" + +/***** Definitions *****/ + +/***** Global Variables *****/ +const mxc_gpio_cfg_t gpio_cfg_swda = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_swdb = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; + +const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; +const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO}; + + +const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1a = { MXC_GPIO0, (MXC_GPIO_PIN_10|MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1c = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; + +//SPI0 +const mxc_gpio_cfg_t gpio_cfg_spi0 = { MXC_GPIO0, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi0_ss = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +// SPI1A +const mxc_gpio_cfg_t gpio_cfg_spi1a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1a_ss = { MXC_GPIO0, MXC_GPIO_PIN_13, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +//SPI1B +const mxc_gpio_cfg_t gpio_cfg_spi1b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_spi1b_ss = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; + + +// Timers are only defined once, depending on package, each timer could be mapped to other pins +const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; +const mxc_gpio_cfg_t gpio_cfg_32kcal = { MXC_GPIO0, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO}; + +const mxc_gpio_cfg_t gpio_cfg_i2s0a = { MXC_GPIO0, (MXC_GPIO_PIN_10| MXC_GPIO_PIN_11| MXC_GPIO_PIN_12|MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE }; +const mxc_gpio_cfg_t gpio_cfg_i2s0b = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE }; diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c new file mode 100644 index 00000000000..128f439ff98 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SYS/sys_me11.c @@ -0,0 +1,289 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/** + * @file mxc_sys.c + * @brief System layer driver. + * @details This driver is used to control the system layer of the device. + */ + +/* **** Includes **** */ +#include +#include "mxc_errors.h" +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gcr_regs.h" +#include "fcr_regs.h" + +/** + * @ingroup mxc_sys + * @{ + */ + +/* **** Definitions **** */ +#define MXC_SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1) + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************** */ +int MXC_SYS_IsClockEnabled (mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */ + if (clock > 31) { + clock -= 32; + return ! (MXC_GCR->pclk_dis1 & (0x1 << clock)); + } + else { + return ! (MXC_GCR->pclk_dis0 & (0x1 << clock)); + } +} + +/* ************************************************************************** */ +void MXC_SYS_ClockDisable (mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */ + if (clock > 31) { + clock -= 32; + MXC_GCR->pclk_dis1 |= (0x1 << clock); + } + else { + MXC_GCR->pclk_dis0 |= (0x1 << clock); + } +} + +/* ************************************************************************** */ +void MXC_SYS_ClockEnable (mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 for the pclkdis1 register. */ + if (clock > 31) { + clock -= 32; + MXC_GCR->pclk_dis1 &= ~ (0x1 << clock); + } + else { + MXC_GCR->pclk_dis0 &= ~ (0x1 << clock); + } +} +/* ************************************************************************** */ +void MXC_SYS_RTCClockEnable() +{ + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; +} + +/* ************************************************************************** */ +int MXC_SYS_RTCClockDisable (void) +{ + /* Check that the RTC is not the system clock source */ + if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) != MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) { + MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; + return E_NO_ERROR; + } + else { + return E_BAD_STATE; + } +} + +/******************************************************************************/ +int MXC_SYS_ClockSourceEnable (mxc_sys_system_clock_t clock) +{ + switch (clock) { + case MXC_SYS_CLOCK_HIRC: + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN; + return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY); + break; + + case MXC_SYS_CLOCK_HFXIN: + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; + return MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY); + break; + + case MXC_SYS_CLOCK_NANORING: + // MXC_GCR->clk_ctrl |= MXC_F_GCR_CLKCTRL_EXTCLK_EN; + // return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY); + return E_NOT_SUPPORTED; + break; + + default: + return E_BAD_PARAM; + break; + } +} + +/******************************************************************************/ +int MXC_SYS_ClockSourceDisable (mxc_sys_system_clock_t clock) +{ + uint32_t current_clock; + + current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; + + // Don't turn off the clock we're running on + if (clock == current_clock) { + return E_BAD_PARAM; + } + + switch (clock) { + case MXC_SYS_CLOCK_HIRC: + MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC_EN; + break; + + case MXC_SYS_CLOCK_HFXIN: + MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; + break; + + case MXC_SYS_CLOCK_NANORING: + // MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLKCTRL_EXTCLK_EN; + return E_BAD_PARAM; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SYS_Clock_Timeout (uint32_t ready) +{ + // Start timeout, wait for ready + MXC_DelayAsync (MXC_SYS_CLOCK_TIMEOUT, NULL); + + do { + if (MXC_GCR->clk_ctrl & ready) { + MXC_DelayAbort(); + return E_NO_ERROR; + } + } + while (MXC_DelayCheck() == E_BUSY); + + return E_TIME_OUT; +} + +/* ************************************************************************** */ +int MXC_SYS_Clock_Select (mxc_sys_system_clock_t clock) +{ + uint32_t current_clock; + + // Save the current system clock + current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; + + switch (clock) { + case MXC_SYS_CLOCK_HIRC: + + // Enable HIRC clock + if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC_EN)) { + + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN; + + // Check if HIRC clock is ready + if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_HIRC_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set HIRC clock as System Clock + MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HIRC); + + break; + + case MXC_SYS_CLOCK_HFXIN: + + // Enable HFXtal clock + if (! (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_X32K_EN)) { + MXC_GCR->clk_ctrl |=MXC_F_GCR_CLK_CTRL_X32K_EN; + + // Check if HFXtal clock is ready + if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_X32K_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set HFXtal clock as System Clock + MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN); + + break; + + case MXC_SYS_CLOCK_NANORING: + // Enable HIRC clock + // if(!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLKCTRL_EXTCLK_EN)) { + // MXC_GCR->clk_ctrl |=MXC_F_GCR_CLKCTRL_EXTCLK_EN; + + // // Check if HIRC clock is ready + // if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_EXTCLK_RDY) != E_NO_ERROR) { + // return E_TIME_OUT; + // } + // } + + // Set HIRC clock as System Clock + // MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); + MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, MXC_S_GCR_CLK_CTRL_CLKSEL_NANORING); + + break; + + default: + return E_BAD_PARAM; + } + + // Wait for system clock to be ready + if (MXC_SYS_Clock_Timeout (MXC_F_GCR_CLK_CTRL_CLKRDY) != E_NO_ERROR) { + + // Restore the old system clock if timeout + MXC_SETFIELD (MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_CLKSEL, current_clock); + + return E_TIME_OUT; + } + + // Update the system core clock + SystemCoreClockUpdate(); + + return E_NO_ERROR; +} + + +/* ************************************************************************** */ +void MXC_SYS_Reset_Periph (mxc_sys_reset_t reset) +{ + /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 for the rstr1 register. */ + if (reset > 31) { + reset -= 32; + MXC_GCR->rst1 = (0x1 << reset); + } + else { + MXC_GCR->rst0 = (0x1 << reset); + } +} +/**@} end of mxc_sys */ + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c new file mode 100644 index 00000000000..d0b6b1e4a06 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.c @@ -0,0 +1,131 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" +#include "tmr_common.h" + +/* **** Functions **** */ + +void MXC_TMR_Common_Delay(mxc_tmr_regs_t* tmr, unsigned long us) +{ + // Return immediately if delay is 0 + if (!us) { + return; + } + + MXC_TMR_TO_Start(tmr, us); + + while (MXC_TMR_TO_Check(tmr) != E_TIME_OUT) {} +} + +int MXC_TMR_Common_TO_Check(mxc_tmr_regs_t* tmr) +{ + if (MXC_TMR_GetFlags(tmr)) { + return E_TIME_OUT; + } + + return E_NO_ERROR; +} + +void MXC_TMR_Common_TO_Stop(mxc_tmr_regs_t* tmr) +{ + MXC_TMR_Stop(tmr); + MXC_TMR_SetCount(tmr, 0x0); +} + +void MXC_TMR_Common_TO_Clear(mxc_tmr_regs_t* tmr) +{ + MXC_TMR_ClearFlags(tmr); + MXC_TMR_SetCount(tmr, 0x0); +} + +unsigned int MXC_TMR_Common_TO_Remaining(mxc_tmr_regs_t* tmr) +{ + uint32_t remaining_ticks, remaining_time; + mxc_tmr_unit_t units; + + remaining_ticks = MXC_TMR_GetCompare(tmr) - MXC_TMR_GetCount(tmr); + MXC_TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units); + + switch (units) { + case TMR_UNIT_NANOSEC: + default: + return (remaining_time / 1000); + + case TMR_UNIT_MICROSEC: + return (remaining_time); + + case TMR_UNIT_MILLISEC: + return (remaining_time * 1000); + + case TMR_UNIT_SEC: + return (remaining_time * 1000000); + } +} + +void MXC_TMR_Common_SW_Start(mxc_tmr_regs_t* tmr) +{ + MXC_TMR_TO_Start(tmr, 0xFFFFFFFF); +} + +unsigned int MXC_TMR_Common_SW_Stop(mxc_tmr_regs_t* tmr) +{ + unsigned int elapsed = MXC_TMR_TO_Elapsed(tmr); + MXC_TMR_TO_Stop(tmr); + return elapsed; +} + +unsigned int MXC_TMR_Common_TO_Elapsed(mxc_tmr_regs_t* tmr) +{ + uint32_t elapsed; + mxc_tmr_unit_t units; + MXC_TMR_GetTime (tmr, tmr->cnt, &elapsed, &units); + + switch (units) { + case TMR_UNIT_NANOSEC: + default: + return (elapsed / 1000); + + case TMR_UNIT_MICROSEC: + return (elapsed); + + case TMR_UNIT_MILLISEC: + return (elapsed * 1000); + + case TMR_UNIT_SEC: + return (elapsed * 1000000); + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h new file mode 100644 index 00000000000..487716d928a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_common.h @@ -0,0 +1,48 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" + +/* **** Functions **** */ +void MXC_TMR_Common_Delay (mxc_tmr_regs_t *tmr, unsigned long us); +void MXC_TMR_Common_TO_Start (mxc_tmr_regs_t *tmr, unsigned long us); +int MXC_TMR_Common_TO_Check (mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_TO_Stop (mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_TO_Clear (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_TO_Elapsed (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_TO_Remaining (mxc_tmr_regs_t *tmr); +void MXC_TMR_Common_SW_Start (mxc_tmr_regs_t *tmr); +unsigned int MXC_TMR_Common_SW_Stop (mxc_tmr_regs_t *tmr); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c new file mode 100644 index 00000000000..54a0ecd4768 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_me11.c @@ -0,0 +1,234 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +#include "tmr.h" +#include "tmr_reva.h" +#include "tmr_common.h" + +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t* cfg) +{ + int tmr_id = MXC_TMR_GET_IDX(tmr); + + MXC_ASSERT(tmr_id >= 0); + + switch(cfg->clock){ + case MXC_TMR_EXT_CLK: + MXC_GPIO_Config(&gpio_cfg_32kcal); + break; + + case MXC_TMR_HFIO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_HIRC); + break; + + case MXC_TMR_NANORING_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_NANORING); + break; + + default: + return E_BAD_PARAM; + break; + } + + //enable peripheral clock and configure gpio pins + switch(tmr_id) { + case 0: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER0); + while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0); + MXC_GPIO_Config(&gpio_cfg_tmr0); + break; + case 1: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER1); + while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER1); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1); + break; + case 2: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TIMER2); + while(MXC_GCR->rst0 & MXC_F_GCR_RST0_TIMER2); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2); + break; + } + MXC_TMR_RevA_Init((mxc_tmr_reva_regs_t*) tmr, cfg); + return E_NO_ERROR; +} + +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr) +{ + int tmr_id = MXC_TMR_GET_IDX(tmr); + MXC_ASSERT(tmr_id >= 0); + + MXC_TMR_RevA_Shutdown((mxc_tmr_reva_regs_t*) tmr); + + // System settigns + //diasble peripheral clock + switch(tmr_id) { + case 0: + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0); + break; + + case 1: + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1); + break; + + case 2: + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); + break; + } +} + +void MXC_TMR_Start(mxc_tmr_regs_t* tmr) +{ + MXC_TMR_RevA_Start((mxc_tmr_reva_regs_t*) tmr); +} + +void MXC_TMR_Stop(mxc_tmr_regs_t* tmr) +{ + MXC_TMR_RevA_Stop((mxc_tmr_reva_regs_t*) tmr); +} + +int MXC_TMR_SetPWM(mxc_tmr_regs_t* tmr, uint32_t pwm) +{ + return MXC_TMR_RevA_SetPWM((mxc_tmr_reva_regs_t*) tmr, pwm); +} + +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t* tmr) +{ + return MXC_TMR_RevA_GetCompare((mxc_tmr_reva_regs_t*) tmr); +} + +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t* tmr) +{ + return MXC_TMR_RevA_GetCapture((mxc_tmr_reva_regs_t*) tmr); +} + +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t* tmr, mxc_tmr_clock_t clock, uint32_t prescalar, uint32_t frequency) +{ + uint32_t retVal, clkFreq; + switch(clock) { + case MXC_TMR_HFIO_CLK: + clkFreq = PeripheralClock; + break; + case MXC_TMR_NANORING_CLK: + clkFreq = 80000; + break; + case MXC_TMR_EXT_CLK: + clkFreq = HFX_FREQ; + break; + default: + clkFreq = PeripheralClock; + break; + } + if(frequency == 0) { + return 0; + } + else { + retVal = clkFreq / (prescalar * frequency); + return retVal; + } + return retVal; +} + +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t* tmr) +{ + return MXC_TMR_RevA_GetCount((mxc_tmr_reva_regs_t*) tmr); +} + +void MXC_TMR_ClearFlags(mxc_tmr_regs_t* tmr) +{ + MXC_TMR_RevA_ClearFlags((mxc_tmr_reva_regs_t*) tmr); +} + +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t* tmr) +{ + return MXC_TMR_RevA_GetFlags((mxc_tmr_reva_regs_t*) tmr); +} + +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt) +{ + MXC_TMR_RevA_SetCompare((mxc_tmr_reva_regs_t*) tmr, cmp_cnt); +} + +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt) +{ + MXC_TMR_RevA_SetCount((mxc_tmr_reva_regs_t*) tmr, cnt); +} + +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us) +{ + MXC_TMR_Common_Delay(tmr, us); +} + +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us) +{ + MXC_TMR_RevA_TO_Start((mxc_tmr_reva_regs_t*) tmr, us); +} + +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Check(tmr); +} + +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_TO_Stop(tmr); +} + +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_TO_Clear(tmr); +} + +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Elapsed(tmr); +} + +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Remaining(tmr); +} + +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_SW_Start(tmr); +} + +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_SW_Stop(tmr); +} + +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) +{ + return MXC_TMR_RevA_GetTime((mxc_tmr_reva_regs_t*) tmr, ticks, time, units); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c new file mode 100644 index 00000000000..87e71618f1b --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c @@ -0,0 +1,304 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" +#include "tmr_reva.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "mxc_lock.h" + +/* **** Functions **** */ +void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg) +{ + // Clear interrupt flag + tmr->intr = MXC_F_TMR_REVA_INTR_IRQ; + + // Set the prescaler + switch(cfg->pres) { + case TMR_PRES_1: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1); + break; + + case TMR_PRES_2: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV2); + break; + + case TMR_PRES_4: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4); + break; + + case TMR_PRES_8: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8); + break; + + case TMR_PRES_16: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16); + break; + + case TMR_PRES_32: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32); + break; + + case TMR_PRES_64: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV64); + break; + + case TMR_PRES_128: + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); + break; + + case TMR_PRES_256: + tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + break; + + case TMR_PRES_512: + tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4); + break; + + case TMR_PRES_1024: + tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8); + break; + + case TMR_PRES_2048: + tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16); + break; + + case TMR_PRES_4096: + tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); + break; + + default: + tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); + tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); + break; + } + + tmr->cn |= cfg->mode << MXC_F_TMR_REVA_CN_TMODE_POS; + tmr->cn |= (cfg->pol) << MXC_F_TMR_REVA_CN_TPOL_POS; + //enable timer interrupt if needed + tmr->cnt = 0x1; + tmr->cmp = cfg->cmp_cnt; +} + +void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + // Disable timer and clear settings + tmr->cn = 0; +} + +void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + tmr->cn |= MXC_F_TMR_REVA_CN_TEN; +} + +void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + tmr->cn &= ~MXC_F_TMR_REVA_CN_TEN; +} + +int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + if(pwm > (tmr->cmp)) { + return E_BAD_PARAM; + } + + tmr->pwm = pwm; + + return E_NO_ERROR; +} + +uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + return tmr->cmp; +} + +uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + return tmr->pwm;//check this +} + +uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + return tmr->cnt; +} + +void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + tmr->intr = MXC_F_TMR_REVA_INTR_IRQ; +} + +uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + return tmr->intr; +} + +void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + tmr->cmp = cmp_cnt; +} + +void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt) +{ + int tmr_id = MXC_TMR_GET_IDX((mxc_tmr_regs_t*) tmr); + if (tmr_id < 0) { + MXC_ASSERT(0); + } + + tmr->cnt = cnt; +} + +void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us) +{ + uint64_t ticks; + int clk_shift = 0; + + ticks = (uint64_t) us * (uint64_t) PeripheralClock / (uint64_t) 1000000; + + while(ticks > 0xFFFFFFFFUL) { + ticks >>= 1; + ++clk_shift; + } + + mxc_tmr_pres_t prescale = (mxc_tmr_pres_t) clk_shift << MXC_F_TMR_REVA_CN_PRES_POS; + mxc_tmr_cfg_t cfg = {0, 0, 0, 0}; // = (mxc_tmr_cfg_t) {.pres=0, .mode=0, .cmp_cnt=0, .pol=0}; + + // Initialize the timer in one-shot mode + cfg.pres = prescale; + cfg.mode = TMR_MODE_ONESHOT; + cfg.cmp_cnt = ticks; + cfg.pol = 0; + + MXC_TMR_Stop((mxc_tmr_regs_t*) tmr); + MXC_TMR_Init((mxc_tmr_regs_t*) tmr, &cfg); + MXC_TMR_ClearFlags((mxc_tmr_regs_t*) tmr); + MXC_TMR_Start((mxc_tmr_regs_t*) tmr); +} + +int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) +{ + uint64_t temp_time = 0; + uint32_t timerClock = PeripheralClock; + uint32_t prescale = ((tmr->cn & MXC_F_TMR_REVA_CN_PRES) >> MXC_F_TMR_REVA_CN_PRES_POS) + |(((tmr->cn & MXC_F_TMR_REVA_CN_PRES3) >> (MXC_F_TMR_REVA_CN_PRES3_POS)) <<3); + + temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000000); + + if(!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_NANOSEC; + return E_NO_ERROR; + } + + temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / (timerClock / 1000); + + if(!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_MICROSEC; + return E_NO_ERROR; + } + + temp_time = (uint64_t) ticks * 1000 * (1 <<(prescale & 0xF)) / timerClock; + + if(!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_MILLISEC; + return E_NO_ERROR; + } + + temp_time = (uint64_t) ticks * (1 <<(prescale & 0xF)) / timerClock; + + if(!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_SEC; + return E_NO_ERROR; + } + + return E_INVALID; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h new file mode 100644 index 00000000000..9b83bc03e62 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva.h @@ -0,0 +1,58 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "mxc_lock.h" +#include "tmr_reva_regs.h" + +/* **** Functions **** */ +void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t* cfg); +void MXC_TMR_RevA_Shutdown(mxc_tmr_reva_regs_t *tmr); +void MXC_TMR_RevA_Start(mxc_tmr_reva_regs_t* tmr); +void MXC_TMR_RevA_Stop(mxc_tmr_reva_regs_t* tmr); +int MXC_TMR_RevA_SetPWM(mxc_tmr_reva_regs_t* tmr, uint32_t pwm); +uint32_t MXC_TMR_RevA_GetCompare(mxc_tmr_reva_regs_t* tmr); +uint32_t MXC_TMR_RevA_GetCapture(mxc_tmr_reva_regs_t* tmr); +uint32_t MXC_TMR_RevA_GetCount(mxc_tmr_reva_regs_t* tmr); +void MXC_TMR_RevA_ClearFlags(mxc_tmr_reva_regs_t* tmr); +uint32_t MXC_TMR_RevA_GetFlags(mxc_tmr_reva_regs_t* tmr); +void MXC_TMR_RevA_SetCompare(mxc_tmr_reva_regs_t *tmr, uint32_t cmp_cnt); +void MXC_TMR_RevA_SetCount(mxc_tmr_reva_regs_t *tmr, uint32_t cnt); +void MXC_TMR_RevA_TO_Start(mxc_tmr_reva_regs_t *tmr, unsigned long us); +int MXC_TMR_RevA_GetTime(mxc_tmr_reva_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h new file mode 100644 index 00000000000..10b768de178 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/TMR/tmr_reva_regs.h @@ -0,0 +1,209 @@ +/** + * @file tmr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _TMR_REVA_REGS_H_ +#define _TMR_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup tmr + * @defgroup tmr_registers TMR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @details 32-bit reloadable timer that can be used for timing and event counting. + */ + +/** + * @ingroup tmr_registers + * Structure type to access the TMR Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ + __IO uint32_t intr; /**< \b 0x0C: TMR INTR Register */ + __IO uint32_t cn; /**< \b 0x10: TMR CN Register */ + __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ +} mxc_tmr_reva_regs_t; + +/* Register offsets for module TMR */ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @{ + */ + #define MXC_R_TMR_REVA_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ + #define MXC_R_TMR_REVA_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ + #define MXC_R_TMR_REVA_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ + #define MXC_R_TMR_REVA_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ + #define MXC_R_TMR_REVA_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ + #define MXC_R_TMR_REVA_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +/**@} end of group tmr_registers */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTR TMR_INTR + * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the + * associated interrupt. + * @{ + */ + #define MXC_F_TMR_REVA_INTR_IRQ_POS 0 /**< INTR_IRQ Position */ + #define MXC_F_TMR_REVA_INTR_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_REVA_INTR_IRQ_POS)) /**< INTR_IRQ Mask */ + +/**@} end of group TMR_INTR_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CN TMR_CN + * @brief Timer Control Register. + * @{ + */ + #define MXC_F_TMR_REVA_CN_TMODE_POS 0 /**< CN_TMODE Position */ + #define MXC_F_TMR_REVA_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_REVA_CN_TMODE_POS)) /**< CN_TMODE Mask */ + #define MXC_V_TMR_REVA_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ + #define MXC_S_TMR_REVA_CN_TMODE_ONESHOT (MXC_V_TMR_REVA_CN_TMODE_ONESHOT << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ + #define MXC_S_TMR_REVA_CN_TMODE_CONTINUOUS (MXC_V_TMR_REVA_CN_TMODE_CONTINUOUS << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ + #define MXC_S_TMR_REVA_CN_TMODE_COUNTER (MXC_V_TMR_REVA_CN_TMODE_COUNTER << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ + #define MXC_S_TMR_REVA_CN_TMODE_PWM (MXC_V_TMR_REVA_CN_TMODE_PWM << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ + #define MXC_S_TMR_REVA_CN_TMODE_CAPTURE (MXC_V_TMR_REVA_CN_TMODE_CAPTURE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ + #define MXC_S_TMR_REVA_CN_TMODE_COMPARE (MXC_V_TMR_REVA_CN_TMODE_COMPARE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ + #define MXC_S_TMR_REVA_CN_TMODE_GATED (MXC_V_TMR_REVA_CN_TMODE_GATED << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ + #define MXC_V_TMR_REVA_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ + #define MXC_S_TMR_REVA_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_REVA_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_REVA_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ + + #define MXC_F_TMR_REVA_CN_PRES_POS 3 /**< CN_PRES Position */ + #define MXC_F_TMR_REVA_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_REVA_CN_PRES_POS)) /**< CN_PRES Mask */ + #define MXC_V_TMR_REVA_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV1 (MXC_V_TMR_REVA_CN_PRES_DIV1 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV2 (MXC_V_TMR_REVA_CN_PRES_DIV2 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV4 (MXC_V_TMR_REVA_CN_PRES_DIV4 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV8 (MXC_V_TMR_REVA_CN_PRES_DIV8 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV16 (MXC_V_TMR_REVA_CN_PRES_DIV16 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV32 (MXC_V_TMR_REVA_CN_PRES_DIV32 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV64 (MXC_V_TMR_REVA_CN_PRES_DIV64 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ + #define MXC_V_TMR_REVA_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */ + #define MXC_S_TMR_REVA_CN_PRES_DIV128 (MXC_V_TMR_REVA_CN_PRES_DIV128 << MXC_F_TMR_REVA_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ + + #define MXC_F_TMR_REVA_CN_TPOL_POS 6 /**< CN_TPOL Position */ + #define MXC_F_TMR_REVA_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_TPOL_POS)) /**< CN_TPOL Mask */ + + #define MXC_F_TMR_REVA_CN_TEN_POS 7 /**< CN_TEN Position */ + #define MXC_F_TMR_REVA_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_TEN_POS)) /**< CN_TEN Mask */ + + #define MXC_F_TMR_REVA_CN_PRES3_POS 8 /**< CN_PRES3 Position */ + #define MXC_F_TMR_REVA_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PRES3_POS)) /**< CN_PRES3 Mask */ + + #define MXC_F_TMR_REVA_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ + #define MXC_F_TMR_REVA_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ + + #define MXC_F_TMR_REVA_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ + #define MXC_F_TMR_REVA_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ + + #define MXC_F_TMR_REVA_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ + #define MXC_F_TMR_REVA_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ + + #define MXC_F_TMR_REVA_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ + #define MXC_F_TMR_REVA_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_REVA_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ + +/**@} end of group TMR_CN_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_NOLCMP TMR_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ + #define MXC_F_TMR_REVA_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ + #define MXC_F_TMR_REVA_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_REVA_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ + + #define MXC_F_TMR_REVA_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ + #define MXC_F_TMR_REVA_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_REVA_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ + +/**@} end of group TMR_NOLCMP_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c new file mode 100644 index 00000000000..77b23e70f63 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.c @@ -0,0 +1,53 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include "uart_common.h" +#include "uart.h" + +int MXC_UART_Common_ReadCharacter(mxc_uart_regs_t* uart) +{ + // Wait until FIFO has a character ready. + while (MXC_UART_GetRXFIFOAvailable(uart) < 1); + + // Read the character using the non-blocking function. + return MXC_UART_ReadCharacterRaw(uart); +} + +int MXC_UART_Common_WriteCharacter(mxc_uart_regs_t* uart, uint8_t character) +{ + // Wait until FIFO has space for the character. + while (MXC_UART_GetTXFIFOAvailable(uart) < 1); + + // Write the character using the non-blocking function. + return MXC_UART_WriteCharacterRaw(uart, character); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h new file mode 100644 index 00000000000..dbe87010567 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_common.h @@ -0,0 +1,38 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include "uart_regs.h" + +int MXC_UART_Common_ReadCharacter (mxc_uart_regs_t* uart); +int MXC_UART_Common_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character); + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c new file mode 100644 index 00000000000..4cf00221e45 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.c @@ -0,0 +1,373 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include "uart.h" +#include "mxc_device.h" +#include "mxc_pins.h" +#include "mxc_assert.h" +#include "uart_reva.h" +#include "uart_common.h" +#include "dma.h" + +void MXC_UART_DMACallback (int ch, int error) +{ + return MXC_UART_RevA_DMACallback (ch, error); +} + +int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal) +{ + return MXC_UART_RevA_AsyncCallback ((mxc_uart_reva_regs_t*) uart, retVal); +} + +int MXC_UART_AsyncStop (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_AsyncStop ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_Init (mxc_uart_regs_t* uart, unsigned int baud, sys_map_t map) +{ + int retval; + + retval = MXC_UART_Shutdown (uart); + + if (retval) { + return retval; + } + + switch (MXC_UART_GET_IDX (uart)) { + case 0: + MXC_GPIO_Config (&gpio_cfg_uart0); + MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_UART0); + break; + + case 1: + switch (map) { + case MAP_A: + MXC_GPIO_Config (&gpio_cfg_uart1a); + break; + case MAP_B: + MXC_GPIO_Config (&gpio_cfg_uart1b); + break; + case MAP_C: + MXC_GPIO_Config (&gpio_cfg_uart1c); + break; + } + MXC_SYS_ClockEnable (MXC_SYS_PERIPH_CLOCK_UART1); + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevA_Init (((mxc_uart_reva_regs_t*) uart), baud); +} + +int MXC_UART_Shutdown (mxc_uart_regs_t* uart) +{ + switch (MXC_UART_GET_IDX (uart)) { + case 0: + MXC_SYS_Reset_Periph (MXC_SYS_RESET0_UART0); + MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_UART0); + break; + + case 1: + MXC_SYS_Reset_Periph (MXC_SYS_RESET0_UART1); + MXC_SYS_ClockDisable (MXC_SYS_PERIPH_CLOCK_UART1); + break; + + default: + return E_BAD_PARAM; + break; + } + + return E_NO_ERROR; +} + +int MXC_UART_ReadyForSleep (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_ReadyForSleep ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_SetFrequency (mxc_uart_regs_t* uart, unsigned int baud) +{ + return MXC_UART_RevA_SetFrequency ((mxc_uart_reva_regs_t*) uart, baud); +} + +int MXC_UART_GetFrequency (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetFrequency ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_SetDataSize (mxc_uart_regs_t* uart, int dataSize) +{ + return MXC_UART_RevA_SetDataSize ((mxc_uart_reva_regs_t*) uart, dataSize); +} + +int MXC_UART_SetStopBits (mxc_uart_regs_t* uart, mxc_uart_stop_t stopBits) +{ + return MXC_UART_RevA_SetStopBits ((mxc_uart_reva_regs_t*) uart, stopBits); +} + +int MXC_UART_SetParity (mxc_uart_regs_t* uart, mxc_uart_parity_t parity) +{ + return MXC_UART_RevA_SetParity ((mxc_uart_reva_regs_t*) uart, parity); +} + +int MXC_UART_SetFlowCtrl (mxc_uart_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +{ + switch (MXC_UART_GET_IDX (uart)) { + case 0: + MXC_GPIO_Config (&gpio_cfg_uart0_flow); + break; + + case 1: + MXC_GPIO_Config (&gpio_cfg_uart1_flow); + break; + } + + return MXC_UART_RevA_SetFlowCtrl ((mxc_uart_reva_regs_t*) uart, flowCtrl, rtsThreshold); +} + +int MXC_UART_SetClockSource (mxc_uart_regs_t* uart, int usePCLK) +{ + return MXC_UART_RevA_SetClockSource ((mxc_uart_reva_regs_t*) uart, usePCLK); +} + +int MXC_UART_SetNullModem (mxc_uart_regs_t* uart, int nullModem) +{ + return MXC_UART_RevA_SetNullModem ((mxc_uart_reva_regs_t*) uart, nullModem); +} + +int MXC_UART_SendBreak (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_SendBreak ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_GetActive (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetActive ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_AbortTransmission (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_AbortTransmission ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_ReadCharacterRaw (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_ReadCharacterRaw ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_WriteCharacterRaw (mxc_uart_regs_t* uart, uint8_t character) +{ + return MXC_UART_RevA_WriteCharacterRaw ((mxc_uart_reva_regs_t*) uart, character); +} + +int MXC_UART_ReadCharacter (mxc_uart_regs_t* uart) +{ + return MXC_UART_Common_ReadCharacter (uart); +} + +int MXC_UART_WriteCharacter (mxc_uart_regs_t* uart, uint8_t character) +{ + return MXC_UART_Common_WriteCharacter (uart, character); +} + +int MXC_UART_Read (mxc_uart_regs_t* uart, uint8_t* buffer, int* len) +{ + return MXC_UART_RevA_Read ((mxc_uart_reva_regs_t*) uart, buffer, len); +} + +int MXC_UART_Write (mxc_uart_regs_t* uart, uint8_t* byte, int* len) +{ + return MXC_UART_RevA_Write ((mxc_uart_reva_regs_t*) uart, byte, len); +} + +unsigned int MXC_UART_ReadRXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len) +{ + return MXC_UART_RevA_ReadRXFIFO ((mxc_uart_reva_regs_t*) uart, bytes, len); + +} + +int MXC_UART_ReadRXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback) +{ + mxc_dma_config_t config; + + int uart_num = MXC_UART_GET_IDX (uart); + + // Only UART 0, 1 and 2 are supported for DMA transaction + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UART0RX; + break; + + case 1: + config.reqsel = MXC_DMA_REQUEST_UART1RX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevA_ReadRXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config); +} + +unsigned int MXC_UART_GetRXFIFOAvailable (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetRXFIFOAvailable ((mxc_uart_reva_regs_t*) uart); +} + +unsigned int MXC_UART_WriteTXFIFO (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len) +{ + return MXC_UART_RevA_WriteTXFIFO ((mxc_uart_reva_regs_t*) uart, bytes, len); +} + +int MXC_UART_WriteTXFIFODMA (mxc_uart_regs_t* uart, unsigned char* bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback) +{ + mxc_dma_config_t config; + + int uart_num = MXC_UART_GET_IDX (uart); + + // Only UART 0, 1 and 2 are supported for DMA transaction + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UART0TX; + break; + + case 1: + config.reqsel = MXC_DMA_REQUEST_UART1TX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevA_WriteTXFIFODMA ((mxc_uart_reva_regs_t*) uart, MXC_DMA, bytes, len, callback, config); +} + +unsigned int MXC_UART_GetTXFIFOAvailable (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetTXFIFOAvailable ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_ClearRXFIFO (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_ClearRXFIFO ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_ClearTXFIFO (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_ClearTXFIFO ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_SetRXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes) +{ + return MXC_UART_RevA_SetRXThreshold ((mxc_uart_reva_regs_t*) uart, numBytes); +} + +unsigned int MXC_UART_GetRXThreshold (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetRXThreshold ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_SetTXThreshold (mxc_uart_regs_t* uart, unsigned int numBytes) +{ + return MXC_UART_RevA_SetTXThreshold ((mxc_uart_reva_regs_t*) uart, numBytes); +} + +unsigned int MXC_UART_GetTXThreshold (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetTXThreshold ((mxc_uart_reva_regs_t*) uart); +} + +unsigned int MXC_UART_GetFlags (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetFlags ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_ClearFlags (mxc_uart_regs_t* uart, unsigned int flags) +{ + return MXC_UART_RevA_ClearFlags ((mxc_uart_reva_regs_t*) uart, flags); +} + +int MXC_UART_EnableInt (mxc_uart_regs_t* uart, unsigned int mask) +{ + return MXC_UART_RevA_EnableInt ((mxc_uart_reva_regs_t*) uart, mask); +} + +int MXC_UART_DisableInt (mxc_uart_regs_t* uart, unsigned int mask) +{ + return MXC_UART_RevA_DisableInt ((mxc_uart_reva_regs_t*) uart, mask); +} + +unsigned int MXC_UART_GetStatus (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_GetStatus ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_Busy(mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_Busy((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_Transaction (mxc_uart_req_t* req) +{ + return MXC_UART_RevA_Transaction ((mxc_uart_reva_req_t*) req); +} + +int MXC_UART_TransactionAsync (mxc_uart_req_t* req) +{ + return MXC_UART_RevA_TransactionAsync ((mxc_uart_reva_req_t*) req); +} + +int MXC_UART_TransactionDMA (mxc_uart_req_t* req) +{ + return MXC_UART_RevA_TransactionDMA ((mxc_uart_reva_req_t*) req, MXC_DMA); +} + +int MXC_UART_AbortAsync (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_AbortAsync ((mxc_uart_reva_regs_t*) uart); +} + +int MXC_UART_AsyncHandler (mxc_uart_regs_t* uart) +{ + return MXC_UART_RevA_AsyncHandler ((mxc_uart_reva_regs_t*) uart); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.h new file mode 100644 index 00000000000..e78cf89fad9 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_me11.h @@ -0,0 +1,40 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include "mxc_device.h" +#include "mxc_assert.h" +#include "max32660.h" + +int MXC_UART_AsyncCallback (mxc_uart_regs_t* uart, int retVal); +int MXC_UART_AsyncStop (mxc_uart_regs_t* uart); + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c new file mode 100644 index 00000000000..79ede5fc845 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -0,0 +1,1062 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "uart.h" +#include "uart_reva.h" +#include "dma.h" + +/* **** Definitions **** */ +#define MXC_UART_REVA_ERRINT_EN (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | \ + MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ + MXC_F_UART_REVA_INT_EN_RX_OVERRUN) + +#define MXC_UART_REVA_ERRINT_FL (MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR | \ + MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR | \ + MXC_F_UART_REVA_INT_FL_RX_OVERRUN) + +/* **** Variable Declaration **** */ +static void* AsyncRequests[MXC_UART_INSTANCES]; + +// Structure to save DMA state +typedef struct { + mxc_uart_reva_req_t *req; + int channelTx; + int channelRx; +} uart_reva_req_state_t; + +uart_reva_req_state_t states[MXC_UART_INSTANCES]; + +/* **** Function Prototypes **** */ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ +int MXC_UART_RevA_Init (mxc_uart_reva_regs_t* uart, unsigned int baud) +{ + int err; + + // Initialize UART + // Set RX threshold to 1 byte + if ((err = (MXC_UART_SetRXThreshold ((mxc_uart_regs_t*) uart, 1))) != E_NO_ERROR) { + return err; + } + + // Set TX threshold to 2 byte + if ((err = (MXC_UART_SetTXThreshold ((mxc_uart_regs_t*) uart, 2))) != E_NO_ERROR) { + return err; + } + + // Set Datasize to 8 bits + if ((err = (MXC_UART_SetDataSize ((mxc_uart_regs_t*) uart, 8))) != E_NO_ERROR) { + return err; + } + + if ((err = (MXC_UART_SetParity ((mxc_uart_regs_t*) uart, MXC_UART_PARITY_DISABLE))) != E_NO_ERROR) { + return err; + } + + if ((err = (MXC_UART_SetStopBits ((mxc_uart_regs_t*) uart, MXC_UART_STOP_1))) != E_NO_ERROR) { + return err; + } + + uart->ctrl |= MXC_F_UART_REVA_CTRL_ENABLE; + + MXC_UART_SetFrequency ((mxc_uart_regs_t*) uart, baud); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_ReadyForSleep (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)] != NULL) { + return E_BUSY; + } + + return MXC_UART_GetActive ((mxc_uart_regs_t*) uart); +} + +int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud) +{ + float uartDiv; + int periphClock; + int prescale; + int decimalDiv; + + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (uart->ctrl & MXC_F_UART_REVA_CTRL_CLKSEL) { +#ifdef IBRO_FREQ + periphClock = IBRO_FREQ; +#else + return E_BAD_PARAM; +#endif + } + else { + periphClock = PeripheralClock; + } + + uartDiv = (float) periphClock / baud; + + // Find the largest value of prescale that keeps div > 1 + for (prescale = 8; prescale < 128; prescale = prescale << 1) { + if (uartDiv / (float) prescale < 1) { + prescale = prescale >> 1; + break; + } + } + + if (prescale < 8) { + return E_BAD_PARAM; + } + + uartDiv /= prescale; + decimalDiv = (int)((uartDiv - (int) uartDiv) * 128); + + // Work around for Jira Bug: ME10-650 + if (decimalDiv > 3) { + decimalDiv -= 3; + } + else { + decimalDiv += 3; + } + + switch (prescale) { + case 8: + prescale = 4; + break; + + case 16: + prescale = 3; + break; + + case 32: + prescale = 2; + break; + + case 64: + prescale = 1; + break; + + case 128: + prescale = 0; + break; + + default: + return E_UNKNOWN; + break; + } + + prescale <<= MXC_F_UART_REVA_BAUD0_FACTOR_POS; + decimalDiv <<= MXC_F_UART_REVA_BAUD1_DBAUD_POS; + + MXC_SETFIELD (uart->baud0, MXC_F_UART_REVA_BAUD0_FACTOR, prescale); + MXC_SETFIELD (uart->baud0, MXC_F_UART_REVA_BAUD0_IBAUD, (((int) uartDiv) << MXC_F_UART_REVA_BAUD0_IBAUD_POS)); + MXC_SETFIELD (uart->baud1, MXC_F_UART_REVA_BAUD1_DBAUD, decimalDiv); + + return MXC_UART_GetFrequency ((mxc_uart_regs_t*) uart); +} + +int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart) +{ + int periphClock = 0; + float uartDiv = 0; + float decimalDiv = 0; + + if (uart->ctrl & MXC_F_UART_REVA_CTRL_CLKSEL) { +#ifdef IBRO_FREQ + periphClock = IBRO_FREQ; +#else + return E_BAD_PARAM; +#endif + } + else { + periphClock = PeripheralClock; + } + + uartDiv += uart->baud0 & MXC_F_UART_REVA_BAUD0_IBAUD; + decimalDiv = uart->baud1 & MXC_F_UART_REVA_BAUD1_DBAUD; + + // Based on work around for Jira Bug: ME10-650 + // No way to tell if the SetFrequency function added or + // subtracted 3 in this range + if(decimalDiv > 3 && decimalDiv <= 6) { + decimalDiv -= 3; + } + else { + decimalDiv += 3; + } + + uartDiv += decimalDiv / (float)128; + uartDiv *= (1 << (7 - (uart->baud0 & MXC_F_UART_REVA_BAUD0_FACTOR))); + + return (int) ( (float) periphClock / uartDiv); +} + +int MXC_UART_RevA_SetDataSize (mxc_uart_reva_regs_t* uart, int dataSize) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (dataSize < 5 || dataSize > 8) { + return E_BAD_PARAM; + } + + dataSize = (dataSize - 5) << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS; + + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_CHAR_SIZE, dataSize); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_SetStopBits (mxc_uart_reva_regs_t* uart, mxc_uart_stop_t stopBits) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + switch (stopBits) { + case MXC_UART_STOP_1: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, 0 << MXC_F_UART_REVA_CTRL_STOPBITS_POS); + break; + + case MXC_UART_STOP_2: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_STOPBITS, 1 << MXC_F_UART_REVA_CTRL_STOPBITS_POS); + break; + + default: + return E_BAD_PARAM; + break; + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parity) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + switch (parity) { + case MXC_UART_PARITY_DISABLE: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 0 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS ); + break; + + case MXC_UART_PARITY_EVEN: + case MXC_UART_PARITY_EVEN_0: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_EVEN_1: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_EVEN); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_ODD: + case MXC_UART_PARITY_ODD_0: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_ODD_1: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_ODD); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_MARK: + case MXC_UART_PARITY_MARK_0: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_MARK_1: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_MARK); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_SPACE: + case MXC_UART_PARITY_SPACE_0: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 0 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + case MXC_UART_PARITY_SPACE_1: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY_EN, 1 << MXC_F_UART_REVA_CTRL_PARITY_EN_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARITY, MXC_S_UART_REVA_CTRL_PARITY_SPACE); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_PARMD, 1 << MXC_F_UART_REVA_CTRL_PARMD_POS); + break; + + default: + return E_BAD_PARAM; + break; + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + switch (flowCtrl) { + case MXC_UART_FLOW_DIS: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 0 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); + break; + + case MXC_UART_FLOW_EN_LOW: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, 0 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS); + break; + + case MXC_UART_FLOW_EN_HIGH: + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_CTRL, 1 << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS); + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_FLOW_POL, 1 << MXC_F_UART_REVA_CTRL_FLOW_POL_POS); + break; + + default: + return E_BAD_PARAM; + break; + } + + if (rtsThreshold < 1 || rtsThreshold > MXC_UART_FIFO_DEPTH) { + return E_BAD_PARAM; + } + + rtsThreshold <<= MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; + MXC_SETFIELD (uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH, rtsThreshold); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_SetClockSource (mxc_uart_reva_regs_t* uart, int usePCLK) +{ + int baudRate; + + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + baudRate = MXC_UART_GetFrequency ((mxc_uart_regs_t*) uart); + if(baudRate < 0) { // return error code + return baudRate; + } + + if (usePCLK) { + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 0 << MXC_F_UART_REVA_CTRL_CLKSEL_POS); + } + else { + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_CLKSEL, 1 << MXC_F_UART_REVA_CTRL_CLKSEL_POS); + } + + return MXC_UART_SetFrequency ((mxc_uart_regs_t*) uart, baudRate); +} + +int MXC_UART_RevA_SetNullModem (mxc_uart_reva_regs_t* uart, int nullModem) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + nullModem = (nullModem > 0) << MXC_F_UART_REVA_CTRL_NULL_MODEM_POS; + + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_NULL_MODEM, nullModem); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_SendBreak (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + MXC_SETFIELD (uart->ctrl, MXC_F_UART_REVA_CTRL_BREAK, 1 << MXC_F_UART_REVA_CTRL_BREAK_POS); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_GetActive (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (uart->status & (MXC_F_UART_REVA_STATUS_TX_BUSY | MXC_F_UART_REVA_STATUS_RX_BUSY)) { + return E_BUSY; + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AbortTransmission (mxc_uart_reva_regs_t* uart) +{ + MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*) uart); + return E_NO_ERROR; +} + +int MXC_UART_RevA_ReadCharacterRaw (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (uart->status & MXC_F_UART_REVA_STATUS_RX_EMPTY) { + return E_UNDERFLOW; + } + + return uart->fifo; +} + +int MXC_UART_RevA_WriteCharacterRaw (mxc_uart_reva_regs_t* uart, uint8_t character) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + // Return error if the FIFO is full + if (uart->status & MXC_F_UART_REVA_STATUS_TX_FULL) { + return E_OVERFLOW; + } + + uart->fifo = character; + + return E_NO_ERROR; +} + +int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len) +{ + int read = 0; + int retVal; + + for (; read < *len; read++) { + retVal = MXC_UART_ReadCharacter ((mxc_uart_regs_t*) uart); + + if (retVal < 0) { + *len = read; + return retVal; + } + else { + buffer[read] = retVal; + } + } + + *len = read; + return E_NO_ERROR; +} + +int MXC_UART_RevA_Write (mxc_uart_reva_regs_t* uart, uint8_t* byte, int* len) +{ + int written = 0; + int retVal; + + for (; written < *len; written++) { + retVal = MXC_UART_WriteCharacter ((mxc_uart_regs_t*) uart, byte[written]); + + if (retVal != E_NO_ERROR) { + *len = written; + return retVal; + } + } + + *len = written; + return E_NO_ERROR; +} + +unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, unsigned int len) +{ + unsigned int read = 0; + + for (; read < len; read++) { + if (uart->status & MXC_F_UART_REVA_STATUS_RX_EMPTY) { + break; + } + + bytes[read] = uart->fifo; + } + + return read; +} + +int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) +{ + uint8_t channel; + mxc_dma_srcdst_t srcdst; + + int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); + + if (uart_num < 0) { + return E_BAD_PARAM; + } + + if (bytes == NULL) { + return E_NULL_PTR; + } + + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.ch = channel; + + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + + config.srcinc_en = 0; + config.dstinc_en = 1; + + srcdst.ch = channel; + srcdst.dest = bytes; + srcdst.len = len; + + + states[uart_num].channelRx = channel; + MXC_DMA_ConfigChannel (config,srcdst); + MXC_DMA_SetCallback (channel, MXC_UART_DMACallback); + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + MXC_DMA_SetChannelInterruptEn(channel, 0, 1); + uart->dma |= MXC_F_UART_REVA_DMA_RXDMA_EN; + + return E_NO_ERROR; +} + +unsigned int MXC_UART_RevA_GetRXFIFOAvailable (mxc_uart_reva_regs_t* uart) +{ + return (uart->status & MXC_F_UART_REVA_STATUS_RX_FIFO_CNT) >> MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS; +} + +unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, unsigned int len) +{ + unsigned int written = 0; + + for (; written < len; written++) { + if (uart->status & MXC_F_UART_REVA_STATUS_TX_FULL) { + break; + } + + uart->fifo = bytes[written]; + } + + return written; +} + +unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) +{ + uint8_t channel; + mxc_dma_srcdst_t srcdst; + + int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); + + if (uart_num < 0) { + return E_BAD_PARAM; + } + + if (bytes == NULL) { + return E_NULL_PTR; + } + + #if TARGET_NUM == 32665 + channel = MXC_DMA_AcquireChannel(dma); + #else + channel = MXC_DMA_AcquireChannel(); + #endif + + config.ch = channel; + + config.srcwd = MXC_DMA_WIDTH_BYTE; + config.dstwd = MXC_DMA_WIDTH_BYTE; + + config.srcinc_en = 1; + config.dstinc_en = 0; + + srcdst.ch = channel; + srcdst.source = bytes; + srcdst.len = len; + + + states[uart_num].channelTx = channel; + MXC_DMA_ConfigChannel (config,srcdst); + MXC_DMA_SetCallback (channel, MXC_UART_DMACallback); + MXC_DMA_EnableInt (channel); + MXC_DMA_Start (channel); + //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; + MXC_DMA_SetChannelInterruptEn(channel, 0, 1); + + uart->dma |= MXC_F_UART_REVA_DMA_TXDMA_EN; + + return E_NO_ERROR; +} + +unsigned int MXC_UART_RevA_GetTXFIFOAvailable (mxc_uart_reva_regs_t* uart) +{ + int txCnt = (uart->status & MXC_F_UART_REVA_STATUS_TX_FIFO_CNT) >> MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS; + return MXC_UART_FIFO_DEPTH - txCnt; +} + +int MXC_UART_RevA_ClearRXFIFO (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + uart->ctrl |= MXC_F_UART_REVA_CTRL_RX_FLUSH; + + while (uart->ctrl & MXC_F_UART_REVA_CTRL_RX_FLUSH); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_ClearTXFIFO (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + uart->ctrl |= MXC_F_UART_REVA_CTRL_TX_FLUSH; + + while (uart->ctrl & MXC_F_UART_REVA_CTRL_TX_FLUSH); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_SetRXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (numBytes < 1 || numBytes > MXC_UART_FIFO_DEPTH) { + return E_BAD_PARAM; + } + + numBytes <<= MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; + MXC_SETFIELD (uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH, numBytes); + + return E_NO_ERROR; +} + +unsigned int MXC_UART_RevA_GetRXThreshold (mxc_uart_reva_regs_t* uart) +{ + return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH) >> MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS; +} + +int MXC_UART_RevA_SetTXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + if (numBytes < 1 || numBytes > MXC_UART_FIFO_DEPTH) { + return E_BAD_PARAM; + } + + numBytes <<= MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS; + MXC_SETFIELD (uart->thresh_ctrl, MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH, numBytes); + + return E_NO_ERROR; +} + +unsigned int MXC_UART_RevA_GetTXThreshold (mxc_uart_reva_regs_t* uart) +{ + return (uart->thresh_ctrl & MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH) >> MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS; +} + +unsigned int MXC_UART_RevA_GetFlags (mxc_uart_reva_regs_t* uart) +{ + return uart->int_fl; +} + +int MXC_UART_RevA_ClearFlags (mxc_uart_reva_regs_t* uart, unsigned int flags) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + uart->int_fl = flags; + + return E_NO_ERROR; +} + +int MXC_UART_RevA_EnableInt (mxc_uart_reva_regs_t* uart, unsigned int intEn) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + uart->int_en |= intEn; + + return E_NO_ERROR; +} + +int MXC_UART_RevA_DisableInt (mxc_uart_reva_regs_t* uart, unsigned int intDis) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + uart->int_en &= ~intDis; + + return E_NO_ERROR; +} + +unsigned int MXC_UART_RevA_GetStatus (mxc_uart_reva_regs_t* uart) +{ + return uart->status; +} + +int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t* uart) +{ + int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t*) uart); // Holds the current index of tx_states + MXC_ASSERT(uart_num >= 0); + if ((uart->status & MXC_F_UART_REVA_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_REVA_STATUS_RX_BUSY)) { + return E_BUSY; + } + // Check to see if there are any ongoing transactions and the UART has room in its FIFO + if ((states[uart_num].req == NULL) && + !(uart->status & MXC_F_UART_REVA_STATUS_TX_FULL)) { + + return E_NO_ERROR; + } + + return E_BUSY; +} + +int MXC_UART_RevA_Transaction (mxc_uart_reva_req_t* req) +{ + unsigned int numToWrite, numToRead; + + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart)) < 0) { + return E_BAD_PARAM; + } + + MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + + MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart)); + MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); + + req->txCnt = 0; + req->rxCnt = 0; + + if (req->rxLen) { + if (req->rxData == NULL) { + return E_BAD_PARAM; + } + } + + if (req->txLen) { + if (req->txData == NULL) { + return E_BAD_PARAM; + } + + numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); + + while (req->txCnt < req->txLen) { + while ( !(MXC_UART_GetFlags ((mxc_uart_regs_t*)(req->uart)) & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH)); + + numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH); + } + } + + if (req->rxLen) { + numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); + + while (req->rxCnt < req->rxLen) { + while ( !(MXC_UART_GetFlags ((mxc_uart_regs_t*)(req->uart)) & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH)); + + numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); + } + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_TransactionAsync (mxc_uart_reva_req_t* req) +{ + unsigned int numToWrite, numToRead; + + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart)) < 0) { + return E_BAD_PARAM; + } + + MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + + MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart)); + MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); + + req->txCnt = 0; + req->rxCnt = 0; + + if (req->txLen) { + if (req->txData == NULL) { + return E_BAD_PARAM; + } + + MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH); + numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); + } + + if (req->rxLen) { + // All error interrupts are related to RX + MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_UART_REVA_ERRINT_EN); + + if (req->rxData == NULL) { + MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); + return E_BAD_PARAM; + } + + MXC_UART_EnableInt ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH); + numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); + } + + AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart))] = (void *) req; + return E_NO_ERROR; +} + +int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma) +{ + int uart_num = MXC_UART_GET_IDX ((mxc_uart_regs_t*)(req->uart)); + + if (uart_num < 0) { + return E_BAD_PARAM; + } + + if (req->txLen) { + if (req->txData == NULL) { + return E_BAD_PARAM; + } + } + + if (req->rxLen) { + if (req->rxData == NULL) { + return E_BAD_PARAM; + } + } + + MXC_UART_DisableInt ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), 0xFFFFFFFF); + + MXC_UART_ClearRXFIFO ((mxc_uart_regs_t*)(req->uart)); + MXC_UART_ClearTXFIFO ((mxc_uart_regs_t*)(req->uart)); + + (req->uart)->dma |= (1 << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS); // Set RX DMA threshold to 1 byte + (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes + + #if TARGET_NUM == 32665 + MXC_DMA_Init(dma); + #else + MXC_DMA_Init(); + #endif + + //tx + if ( (req->txData != NULL) && (req->txLen)) { + #if TARGET_NUM == 32665 + if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { + return E_BAD_PARAM; + } + #else + if (MXC_UART_WriteTXFIFODMA ((mxc_uart_regs_t*)(req->uart), req->txData, req->txLen, NULL) != E_NO_ERROR) { + return E_BAD_PARAM; + } + #endif + } + + if ( (req->rxData != NULL) && (req->rxLen)) { + #if TARGET_NUM == 32665 + if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { + return E_BAD_PARAM; + } + #else + if (MXC_UART_ReadRXFIFODMA ((mxc_uart_regs_t*)(req->uart), req->rxData, req->rxLen, NULL) != E_NO_ERROR) { + return E_BAD_PARAM; + } + #endif + } + + return E_NO_ERROR; +} + +void MXC_UART_RevA_DMACallback (int ch, int error) +{ + mxc_uart_reva_req_t * temp_req; + + for (int i = 0; i < MXC_UART_INSTANCES; i ++) { + if (states[i].channelTx == ch) { + //save the request + temp_req = states[i].req; + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback((mxc_uart_req_t*)temp_req, E_NO_ERROR); + } + break; + } + + else if (states[i].channelRx == ch) { + //save the request + temp_req = states[i].req; + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback((mxc_uart_req_t*)temp_req, E_NO_ERROR); + } + break; + } + } +} + +int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + mxc_uart_reva_req_t* req = (mxc_uart_reva_req_t*) AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)]; + + if (req->callback != NULL) { + req->callback ((mxc_uart_req_t*) req, retVal); + } + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AsyncStop (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + MXC_UART_DisableInt ((mxc_uart_regs_t*) uart, 0xFFFFFFFF); + AsyncRequests[MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart)] = NULL; + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AbortAsync (mxc_uart_reva_regs_t* uart) +{ + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_ABORT); + MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart); + + return E_NO_ERROR; +} + +int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart) +{ + int uartNum = MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart); + unsigned int flags, numToWrite, numToRead; + mxc_uart_reva_req_t* req; + + if (MXC_UART_GET_IDX ((mxc_uart_regs_t*) uart) < 0) { + return E_BAD_PARAM; + } + + req = (mxc_uart_reva_req_t*) AsyncRequests[uartNum]; + + flags = MXC_UART_GetFlags ((mxc_uart_regs_t*) uart); + + if (flags & MXC_UART_REVA_ERRINT_FL & uart->int_en) { + MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_COMM_ERR); + MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart); + return E_INVALID; + } + + if ( (flags & MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH) && (req->txLen)) { + numToWrite = MXC_UART_GetTXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToWrite = numToWrite > (req->txLen-req->txCnt) ? req->txLen-req->txCnt : numToWrite; + req->txCnt += MXC_UART_WriteTXFIFO ((mxc_uart_regs_t*)(req->uart), &req->txData[req->txCnt], numToWrite); + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH); + } + + if ( (flags & MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH) && (req->rxLen)) { + numToRead = MXC_UART_GetRXFIFOAvailable ((mxc_uart_regs_t*)(req->uart)); + numToRead = numToRead > (req->rxLen-req->rxCnt) ? req->rxLen-req->rxCnt : numToRead; + req->rxCnt += MXC_UART_ReadRXFIFO ((mxc_uart_regs_t*)(req->uart), &req->rxData[req->rxCnt], numToRead); + + if ( (req->rxLen - req->rxCnt) < MXC_UART_GetRXThreshold ((mxc_uart_regs_t*)(req->uart))) { + MXC_UART_SetRXThreshold ((mxc_uart_regs_t*)(req->uart), req->rxLen - req->rxCnt); + } + + MXC_UART_ClearFlags ((mxc_uart_regs_t*)(req->uart), MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH); + } + + if ( (req->rxCnt == req->rxLen) && (req->txCnt == req->txLen)) { + MXC_UART_AsyncCallback ((mxc_uart_regs_t*) uart, E_NO_ERROR); + MXC_UART_AsyncStop ((mxc_uart_regs_t*) uart); + } + + return E_NO_ERROR; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h new file mode 100644 index 00000000000..f563d36492a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva.h @@ -0,0 +1,100 @@ +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + *************************************************************************** */ + +#include "mxc_device.h" +#include "mxc_assert.h" +#include "dma.h" +#include "uart_reva_regs.h" +#include "uart_regs.h" + +typedef struct _mxc_uart_reva_req_t mxc_uart_reva_req_t; + +struct _mxc_uart_reva_req_t { + mxc_uart_reva_regs_t* uart; + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; + uint32_t rxLen; + uint32_t txCnt; + uint32_t rxCnt; + mxc_uart_complete_cb_t callback; +}; + +int MXC_UART_RevA_Init (mxc_uart_reva_regs_t* uart, unsigned int baud); +int MXC_UART_RevA_Shutdown (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_ReadyForSleep (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_SetFrequency (mxc_uart_reva_regs_t* uart, unsigned int baud); +int MXC_UART_RevA_GetFrequency (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_SetDataSize (mxc_uart_reva_regs_t* uart, int dataSize); +int MXC_UART_RevA_SetStopBits (mxc_uart_reva_regs_t* uart, mxc_uart_stop_t stopBits); +int MXC_UART_RevA_SetParity (mxc_uart_reva_regs_t* uart, mxc_uart_parity_t parity); +int MXC_UART_RevA_SetFlowCtrl (mxc_uart_reva_regs_t* uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); +int MXC_UART_RevA_SetClockSource (mxc_uart_reva_regs_t* uart, int usePCLK); +int MXC_UART_RevA_SetNullModem (mxc_uart_reva_regs_t* uart, int nullModem); +int MXC_UART_RevA_SendBreak (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_GetActive (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_AbortTransmission (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_ReadCharacterRaw (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_WriteCharacterRaw (mxc_uart_reva_regs_t* uart, uint8_t character); +int MXC_UART_RevA_Read (mxc_uart_reva_regs_t* uart, uint8_t* buffer, int* len); +int MXC_UART_RevA_Write (mxc_uart_reva_regs_t* uart, uint8_t* byte, int* len); +unsigned int MXC_UART_RevA_ReadRXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, + unsigned int len); +int MXC_UART_RevA_ReadRXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); +unsigned int MXC_UART_RevA_GetRXFIFOAvailable (mxc_uart_reva_regs_t* uart); +unsigned int MXC_UART_RevA_WriteTXFIFO (mxc_uart_reva_regs_t* uart, unsigned char* bytes, + unsigned int len); +unsigned int MXC_UART_RevA_WriteTXFIFODMA (mxc_uart_reva_regs_t* uart, mxc_dma_regs_t* dma, unsigned char* bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); +unsigned int MXC_UART_RevA_GetTXFIFOAvailable (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_ClearRXFIFO (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_ClearTXFIFO (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_SetRXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes); +unsigned int MXC_UART_RevA_GetRXThreshold (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_SetTXThreshold (mxc_uart_reva_regs_t* uart, unsigned int numBytes); +unsigned int MXC_UART_RevA_GetTXThreshold (mxc_uart_reva_regs_t* uart); +unsigned int MXC_UART_RevA_GetFlags (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_ClearFlags (mxc_uart_reva_regs_t* uart, unsigned int flags); +int MXC_UART_RevA_EnableInt (mxc_uart_reva_regs_t* uart, unsigned int mask); +int MXC_UART_RevA_DisableInt (mxc_uart_reva_regs_t* uart, unsigned int mask); +unsigned int MXC_UART_RevA_GetStatus (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_Busy(mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_Transaction (mxc_uart_reva_req_t* req); +int MXC_UART_RevA_TransactionAsync (mxc_uart_reva_req_t* req); +int MXC_UART_RevA_TransactionDMA (mxc_uart_reva_req_t* req, mxc_dma_regs_t* dma); +int MXC_UART_RevA_AbortAsync (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_AsyncHandler (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_AsyncStop (mxc_uart_reva_regs_t* uart); +int MXC_UART_RevA_AsyncCallback (mxc_uart_reva_regs_t* uart, int retVal); +void MXC_UART_RevA_DMACallback (int ch, int error); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h new file mode 100644 index 00000000000..bc1acb7f532 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/UART/uart_reva_regs.h @@ -0,0 +1,405 @@ +/** + * @file uart_regs.h + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _UART_REVA_REGS_H_ +#define _UART_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup uart + * @defgroup uart_registers UART_Registers + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @details UART + */ + +/** + * @ingroup uart_registers + * Structure type to access the UART Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: UART CTRL Register */ + __IO uint32_t thresh_ctrl; /**< \b 0x04: UART THRESH_CTRL Register */ + __I uint32_t status; /**< \b 0x08: UART STATUS Register */ + __IO uint32_t int_en; /**< \b 0x0C: UART INT_EN Register */ + __IO uint32_t int_fl; /**< \b 0x10: UART INT_FL Register */ + __IO uint32_t baud0; /**< \b 0x14: UART BAUD0 Register */ + __IO uint32_t baud1; /**< \b 0x18: UART BAUD1 Register */ + __IO uint32_t fifo; /**< \b 0x1C: UART FIFO Register */ + __IO uint32_t dma; /**< \b 0x20: UART DMA Register */ + __IO uint32_t tx_fifo; /**< \b 0x24: UART TX_FIFO Register */ +} mxc_uart_reva_regs_t; + +/* Register offsets for module UART */ +/** + * @ingroup uart_registers + * @defgroup UART_Register_Offsets Register Offsets + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @{ + */ + #define MXC_R_UART_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ + #define MXC_R_UART_REVA_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ + #define MXC_R_UART_REVA_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ + #define MXC_R_UART_REVA_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ + #define MXC_R_UART_REVA_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ + #define MXC_R_UART_REVA_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ + #define MXC_R_UART_REVA_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ + #define MXC_R_UART_REVA_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ + #define MXC_R_UART_REVA_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ + #define MXC_R_UART_REVA_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: 0x0024 */ +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL UART_CTRL + * @brief Control Register. + * @{ + */ + #define MXC_F_UART_REVA_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ + #define MXC_F_UART_REVA_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ + + #define MXC_F_UART_REVA_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ + #define MXC_F_UART_REVA_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ + + #define MXC_F_UART_REVA_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ + #define MXC_F_UART_REVA_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_REVA_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ + #define MXC_V_UART_REVA_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ + #define MXC_S_UART_REVA_CTRL_PARITY_EVEN (MXC_V_UART_REVA_CTRL_PARITY_EVEN << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ + #define MXC_V_UART_REVA_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ + #define MXC_S_UART_REVA_CTRL_PARITY_ODD (MXC_V_UART_REVA_CTRL_PARITY_ODD << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ + #define MXC_V_UART_REVA_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ + #define MXC_S_UART_REVA_CTRL_PARITY_MARK (MXC_V_UART_REVA_CTRL_PARITY_MARK << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ + #define MXC_V_UART_REVA_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ + #define MXC_S_UART_REVA_CTRL_PARITY_SPACE (MXC_V_UART_REVA_CTRL_PARITY_SPACE << MXC_F_UART_REVA_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ + + #define MXC_F_UART_REVA_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ + #define MXC_F_UART_REVA_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ + + #define MXC_F_UART_REVA_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ + #define MXC_F_UART_REVA_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ + + #define MXC_F_UART_REVA_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ + #define MXC_F_UART_REVA_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ + + #define MXC_F_UART_REVA_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ + #define MXC_F_UART_REVA_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ + + #define MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ + #define MXC_F_UART_REVA_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ + #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ + #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_5 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_5 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ + #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ + #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_6 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_6 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ + #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ + #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_7 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_7 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ + #define MXC_V_UART_REVA_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ + #define MXC_S_UART_REVA_CTRL_CHAR_SIZE_8 (MXC_V_UART_REVA_CTRL_CHAR_SIZE_8 << MXC_F_UART_REVA_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ + + #define MXC_F_UART_REVA_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ + #define MXC_F_UART_REVA_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ + + #define MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ + #define MXC_F_UART_REVA_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ + + #define MXC_F_UART_REVA_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ + #define MXC_F_UART_REVA_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ + + #define MXC_F_UART_REVA_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ + #define MXC_F_UART_REVA_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */ + + #define MXC_F_UART_REVA_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ + #define MXC_F_UART_REVA_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */ + + #define MXC_F_UART_REVA_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ + #define MXC_F_UART_REVA_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_REVA_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ + + #define MXC_F_UART_REVA_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ + #define MXC_F_UART_REVA_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_REVA_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ + +/**@} end of group UART_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_THRESH_CTRL UART_THRESH_CTRL + * @brief Threshold Control register. + * @{ + */ + #define MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_REVA_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_REVA_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_REVA_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */ + +/**@} end of group UART_THRESH_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_STATUS UART_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_UART_REVA_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ + #define MXC_F_UART_REVA_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ + + #define MXC_F_UART_REVA_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ + #define MXC_F_UART_REVA_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ + + #define MXC_F_UART_REVA_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ + #define MXC_F_UART_REVA_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ + + #define MXC_F_UART_REVA_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ + #define MXC_F_UART_REVA_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ + + #define MXC_F_UART_REVA_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ + #define MXC_F_UART_REVA_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ + + #define MXC_F_UART_REVA_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ + #define MXC_F_UART_REVA_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + + #define MXC_F_UART_REVA_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ + #define MXC_F_UART_REVA_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ + + #define MXC_F_UART_REVA_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ + #define MXC_F_UART_REVA_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVA_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + + #define MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */ + #define MXC_F_UART_REVA_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_REVA_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */ + + #define MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */ + #define MXC_F_UART_REVA_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_REVA_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */ + +/**@} end of group UART_STATUS_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_EN UART_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ + #define MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ + #define MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_REVA_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ + #define MXC_F_UART_REVA_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */ + + #define MXC_F_UART_REVA_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ + #define MXC_F_UART_REVA_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ + + #define MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_REVA_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ + #define MXC_F_UART_REVA_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */ + + #define MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_REVA_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ + #define MXC_F_UART_REVA_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ + + #define MXC_F_UART_REVA_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ + #define MXC_F_UART_REVA_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */ + + #define MXC_F_UART_REVA_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ + #define MXC_F_UART_REVA_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ + +/**@} end of group UART_INT_EN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_FL UART_INT_FL + * @brief Interrupt Status Flags. + * @{ + */ + #define MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */ + #define MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */ + #define MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_REVA_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ + #define MXC_F_UART_REVA_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */ + + #define MXC_F_UART_REVA_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ + #define MXC_F_UART_REVA_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */ + + #define MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_REVA_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ + #define MXC_F_UART_REVA_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */ + + #define MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */ + #define MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_REVA_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ + #define MXC_F_UART_REVA_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ + + #define MXC_F_UART_REVA_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ + #define MXC_F_UART_REVA_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */ + + #define MXC_F_UART_REVA_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ + #define MXC_F_UART_REVA_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_REVA_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ + +/**@} end of group UART_INT_FL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD0 UART_BAUD0 + * @brief Baud rate register. Integer portion. + * @{ + */ + #define MXC_F_UART_REVA_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ + #define MXC_F_UART_REVA_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_REVA_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ + + #define MXC_F_UART_REVA_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ + #define MXC_F_UART_REVA_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_REVA_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ + #define MXC_V_UART_REVA_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ + #define MXC_S_UART_REVA_BAUD0_FACTOR_128 (MXC_V_UART_REVA_BAUD0_FACTOR_128 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ + #define MXC_V_UART_REVA_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ + #define MXC_S_UART_REVA_BAUD0_FACTOR_64 (MXC_V_UART_REVA_BAUD0_FACTOR_64 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ + #define MXC_V_UART_REVA_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ + #define MXC_S_UART_REVA_BAUD0_FACTOR_32 (MXC_V_UART_REVA_BAUD0_FACTOR_32 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ + #define MXC_V_UART_REVA_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ + #define MXC_S_UART_REVA_BAUD0_FACTOR_16 (MXC_V_UART_REVA_BAUD0_FACTOR_16 << MXC_F_UART_REVA_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ + +/**@} end of group UART_BAUD0_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD1 UART_BAUD1 + * @brief Baud rate register. Decimal Setting. + * @{ + */ + #define MXC_F_UART_REVA_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ + #define MXC_F_UART_REVA_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_REVA_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ + +/**@} end of group UART_BAUD1_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_FIFO UART_FIFO + * @brief FIFO Data buffer. + * @{ + */ + #define MXC_F_UART_REVA_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ + #define MXC_F_UART_REVA_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_REVA_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ + +/**@} end of group UART_FIFO_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_DMA UART_DMA + * @brief DMA Configuration. + * @{ + */ + #define MXC_F_UART_REVA_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */ + #define MXC_F_UART_REVA_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */ + + #define MXC_F_UART_REVA_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ + #define MXC_F_UART_REVA_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ + + #define MXC_F_UART_REVA_DMA_RXDMA_START_POS 3 /**< DMA_RXDMA_START Position */ + #define MXC_F_UART_REVA_DMA_RXDMA_START ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_RXDMA_START_POS)) /**< DMA_RXDMA_START Mask */ + + #define MXC_F_UART_REVA_DMA_RXDMA_AUTO_TO_POS 5 /**< DMA_RXDMA_AUTO_TO Position */ + #define MXC_F_UART_REVA_DMA_RXDMA_AUTO_TO ((uint32_t)(0x1UL << MXC_F_UART_REVA_DMA_RXDMA_AUTO_TO_POS)) /**< DMA_RXDMA_AUTO_TO Mask */ + + #define MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ + #define MXC_F_UART_REVA_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */ + + #define MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ + #define MXC_F_UART_REVA_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_REVA_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */ + +/**@} end of group UART_DMA_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_TX_FIFO UART_TX_FIFO + * @brief Transmit FIFO Status register. + * @{ + */ + #define MXC_F_UART_REVA_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ + #define MXC_F_UART_REVA_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_REVA_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ + +/**@} end of group UART_TX_FIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _UART_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c new file mode 100644 index 00000000000..2b6f245b588 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_common.c @@ -0,0 +1,39 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c new file mode 100644 index 00000000000..15a05eca5f3 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_me11.c @@ -0,0 +1,131 @@ +/* ***************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" +#include "wdt_reva.h" +#include "gcr_regs.h" + +/* **** Functions **** */ + +int MXC_WDT_Init (mxc_wdt_regs_t* wdt) +{ + if (wdt == MXC_WDT0) { + return E_NO_ERROR; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_WDT_Shutdown (mxc_wdt_regs_t* wdt) +{ + if (wdt == MXC_WDT0) { + return E_NO_ERROR; + } + else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} +void MXC_WDT_SetIntPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period) +{ + MXC_WDT_RevA_SetIntPeriod ((mxc_wdt_reva_regs_t*) wdt,period); +} + +void MXC_WDT_SetResetPeriod (mxc_wdt_regs_t* wdt, mxc_wdt_period_t period) +{ + MXC_WDT_RevA_SetResetPeriod ((mxc_wdt_reva_regs_t*) wdt,period); +} + +void MXC_WDT_Enable (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_Enable ((mxc_wdt_reva_regs_t*) wdt); +} + +void MXC_WDT_Disable (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_Disable ((mxc_wdt_reva_regs_t*) wdt); +} + +void MXC_WDT_EnableInt (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_EnableInt ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_ENABLE); +} + +void MXC_WDT_EnableReset (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_EnableReset ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_ENABLE); +} + +void MXC_WDT_DisableInt (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_EnableInt ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_DISABLE); +} + +void MXC_WDT_DisableReset (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_EnableReset ((mxc_wdt_reva_regs_t*) wdt, MXC_WDT_REVA_DISABLE); +} + +void MXC_WDT_ResetTimer (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_ResetTimer ((mxc_wdt_reva_regs_t*) wdt); +} + +int MXC_WDT_GetResetFlag (mxc_wdt_regs_t* wdt) +{ + return MXC_WDT_RevA_GetResetFlag ((mxc_wdt_reva_regs_t*) wdt); +} + +void MXC_WDT_ClearResetFlag (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_ClearResetFlag ((mxc_wdt_reva_regs_t*) wdt); +} + +int MXC_WDT_GetIntFlag (mxc_wdt_regs_t* wdt) +{ + return MXC_WDT_RevA_GetIntFlag ((mxc_wdt_reva_regs_t*) wdt); +} + +void MXC_WDT_ClearIntFlag (mxc_wdt_regs_t* wdt) +{ + MXC_WDT_RevA_ClearIntFlag ((mxc_wdt_reva_regs_t*) wdt); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c new file mode 100644 index 00000000000..7a623e768d8 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.c @@ -0,0 +1,109 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" +#include "wdt_reva.h" + +/* **** Functions **** */ + +void MXC_WDT_RevA_SetIntPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period) +{ + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_INT_PERIOD, period); +} + +void MXC_WDT_RevA_SetResetPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period) +{ + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_REVA_CTRL_RST_PERIOD, (period << (MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS - MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS))); +} + +void MXC_WDT_RevA_Enable(mxc_wdt_reva_regs_t* wdt) +{ + wdt->ctrl |= MXC_F_WDT_REVA_CTRL_WDT_EN; +} + +void MXC_WDT_RevA_Disable(mxc_wdt_reva_regs_t* wdt) +{ + wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_WDT_EN); + +} + +void MXC_WDT_RevA_EnableInt(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable) +{ + if(enable) { + wdt->ctrl |= MXC_F_WDT_REVA_CTRL_INT_EN; + } + else { + wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_INT_EN); + } +} + +void MXC_WDT_RevA_EnableReset(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable) +{ + if(enable) { + wdt->ctrl |= MXC_F_WDT_REVA_CTRL_RST_EN; + } + else { + wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_RST_EN); + } +} + +void MXC_WDT_RevA_ResetTimer(mxc_wdt_reva_regs_t* wdt) +{ + wdt->rst = 0x00A5; + wdt->rst = 0x005A; +} + +int MXC_WDT_RevA_GetResetFlag(mxc_wdt_reva_regs_t* wdt) +{ + return !!(wdt->ctrl & MXC_F_WDT_REVA_CTRL_RST_FLAG); +} + +void MXC_WDT_RevA_ClearResetFlag(mxc_wdt_reva_regs_t* wdt) +{ + wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_RST_FLAG); +} + +int MXC_WDT_RevA_GetIntFlag(mxc_wdt_reva_regs_t* wdt) +{ + return !!(wdt->ctrl & MXC_F_WDT_REVA_CTRL_INT_FLAG); +} + +void MXC_WDT_RevA_ClearIntFlag(mxc_wdt_reva_regs_t* wdt) +{ + wdt->ctrl &= ~(MXC_F_WDT_REVA_CTRL_INT_FLAG); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h new file mode 100644 index 00000000000..6185d35a4ce --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva.h @@ -0,0 +1,59 @@ +/* ***************************************************************************** + * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files(the "Software");, + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" +#include "wdt_reva_regs.h" + +/* **** Definitions **** */ +typedef enum { + MXC_WDT_REVA_DISABLE = 0, + MXC_WDT_REVA_ENABLE = 1, +} mxc_wdt_reva_en_t; + +/* **** Functions **** */ +void MXC_WDT_RevA_SetIntPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period); +void MXC_WDT_RevA_SetResetPeriod(mxc_wdt_reva_regs_t* wdt, mxc_wdt_period_t period); +void MXC_WDT_RevA_Enable(mxc_wdt_reva_regs_t* wdt); +void MXC_WDT_RevA_Disable(mxc_wdt_reva_regs_t* wdt); +void MXC_WDT_RevA_EnableInt(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable); +void MXC_WDT_RevA_EnableReset(mxc_wdt_reva_regs_t* wdt, mxc_wdt_reva_en_t enable); +void MXC_WDT_RevA_ResetTimer(mxc_wdt_reva_regs_t* wdt); +int MXC_WDT_RevA_GetResetFlag(mxc_wdt_reva_regs_t* wdt); +void MXC_WDT_RevA_ClearResetFlag(mxc_wdt_reva_regs_t* wdt); +int MXC_WDT_RevA_GetIntFlag(mxc_wdt_reva_regs_t* wdt); +void MXC_WDT_RevA_ClearIntFlag(mxc_wdt_reva_regs_t* wdt); diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h new file mode 100644 index 00000000000..eba132af176 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/WDT/wdt_reva_regs.h @@ -0,0 +1,216 @@ +/** + * @file wdt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _WDT_REVA_REGS_H_ +#define _WDT_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wdt + * @defgroup wdt_registers WDT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @details Watchdog Timer 0 + */ + +/** + * @ingroup wdt_registers + * Structure type to access the WDT Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: WDT CTRL Register */ + __O uint32_t rst; /**< \b 0x04: WDT RST Register */ +} mxc_wdt_reva_regs_t; + +/* Register offsets for module WDT */ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @{ + */ + #define MXC_R_WDT_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ + #define MXC_R_WDT_REVA_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +/**@} end of group wdt_registers */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL WDT_CTRL + * @brief Watchdog Timer Control Register. + * @{ + */ + #define MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ + #define MXC_F_WDT_REVA_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_REVA_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_REVA_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_REVA_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ + #define MXC_F_WDT_REVA_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_REVA_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_REVA_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_REVA_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_REVA_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ + #define MXC_F_WDT_REVA_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ + + #define MXC_F_WDT_REVA_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ + #define MXC_F_WDT_REVA_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ + + #define MXC_F_WDT_REVA_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ + #define MXC_F_WDT_REVA_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ + + #define MXC_F_WDT_REVA_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ + #define MXC_F_WDT_REVA_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ + + #define MXC_F_WDT_REVA_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ + #define MXC_F_WDT_REVA_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_REVA_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ + +/**@} end of group WDT_CTRL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_RST WDT_RST + * @brief Watchdog Timer Reset Register. + * @{ + */ + #define MXC_F_WDT_REVA_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ + #define MXC_F_WDT_REVA_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_REVA_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ + #define MXC_V_WDT_REVA_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ + #define MXC_S_WDT_REVA_RST_WDT_RST_SEQ0 (MXC_V_WDT_REVA_RST_WDT_RST_SEQ0 << MXC_F_WDT_REVA_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ + #define MXC_V_WDT_REVA_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ + #define MXC_S_WDT_REVA_RST_WDT_RST_SEQ1 (MXC_V_WDT_REVA_RST_WDT_RST_SEQ1 << MXC_F_WDT_REVA_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ + +/**@} end of group WDT_RST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_REVA_REGS_H_ */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/PeripheralPins.c b/targets/TARGET_Maxim/TARGET_MAX32660/PeripheralPins.c new file mode 100644 index 00000000000..83486a044fe --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/PeripheralPins.c @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "device.h" +#include "PeripheralPins.h" + +/* + * To select a peripheral function on Maxim microcontrollers, multiple + * configurations must be made. The mbed PinMap structure only includes one + * data member to hold this information. To extend the configuration storage, + * the "function" data member is used as a pointer to a pin_function_t + * structure. This structure is defined in objects.h. The definitions below + * include the creation of the pin_function_t structures and the assignment of + * the pointers to the "function" data members. + */ + + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + { P0_9, I2C_0, 1 }, + { P0_3, I2C_1, 1 }, + { NC, NC, 0 } +}; + +const PinMap PinMap_I2C_SCL[] = { + { P0_8, I2C_0, 1 }, + { P0_2, I2C_1, 1 }, + { NC, NC, 0 } +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_4, UART_0, 2}, + {P0_10, UART_1, 2}, + {P0_0, UART_1, 3}, + {P0_6, UART_1, 3}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_5, UART_0, 2}, + {P0_11, UART_1, 2}, + {P0_1, UART_1, 3}, + {P0_7, UART_1, 3}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {P0_6, UART_0, 2}, + {P0_12, UART_1, 2}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {P0_7, UART_0, 2}, + {P0_13, UART_1, 2}, + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + { P0_6, SPI_0, 1 }, + { P0_12, SPI_1, 1 }, + { P0_2, SPI_1, 2 }, + { NC, NC, 0 } +}; + +const PinMap PinMap_SPI_MOSI[] = { + { P0_5, SPI_0, 1 }, + { P0_11, SPI_1, 1 }, + { P0_1, SPI_1, 2 }, + { NC, NC, 0 } +}; + +const PinMap PinMap_SPI_MISO[] = { + { P0_4, SPI_0, 1 }, + { P0_10, SPI_1, 1 }, + { P0_0, SPI_1, 2 }, + { NC, NC, 0 } +}; + +const PinMap PinMap_SPI_SSEL[] = { + { P0_7, SPI_0, 1 }, + { P0_13, SPI_1, 1 }, + { P0_3, SPI_1, 2 }, + { NC, NC, 0 } +}; + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/PeripheralPins.h b/targets/TARGET_Maxim/TARGET_MAX32660/PeripheralPins.h new file mode 100644 index 00000000000..a7df48b08ce --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/PeripheralPins.h @@ -0,0 +1,55 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" + +//************I2C*************** +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//************UART*************** +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +//************SPI*************** +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/PortNames.h b/targets/TARGET_Maxim/TARGET_MAX32660/PortNames.h new file mode 100644 index 00000000000..c87eb5bb185 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/PortNames.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/CMakeLists.txt b/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/CMakeLists.txt new file mode 100644 index 00000000000..7fbe9653bba --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-max32660evsys INTERFACE) + +target_include_directories(mbed-max32660evsys + INTERFACE + . +) + +target_link_libraries(mbed-max32660evsys + INTERFACE + mbed-max32660 +) diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/PeripheralNames.h b/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/PeripheralNames.h new file mode 100644 index 00000000000..57dcb772b9e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/PeripheralNames.h @@ -0,0 +1,68 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = MXC_BASE_UART0, + UART_1 = MXC_BASE_UART1, +#if defined(MBED_CONF_TARGET_STDIO_UART) + STDIO_UART = MBED_CONF_TARGET_STDIO_UART, +#else + STDIO_UART = UART_1, +#endif +} UARTName; + +typedef enum { + I2C_0 = MXC_BASE_I2C0, + I2C_1 = MXC_BASE_I2C1, +} I2CName; + +typedef enum { + SPI_0 = MXC_BASE_SPI, + SPI_1 = MXC_BASE_SPIMSS, +} SPIName; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/PinNames.h new file mode 100644 index 00000000000..3417f5cf285 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/TARGET_MAX32660EVSYS/PinNames.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +/* MBED TARGET LIST: MAX32660EVSYS */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT = 1 +} PinDirection; + +#define PORT_SHIFT 12 + +#define PINNAME_TO_PORT(name) ((unsigned int)(name) >> PORT_SHIFT) +#define PINNAME_TO_PIN(name) ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT)) +#define NOT_CONNECTED (int)0xFFFFFFFF + +typedef enum { + P0_0 = (0 << PORT_SHIFT), P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, + + // USB bridge connected UART pins +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = P0_10, +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = P0_11, +#endif + STDIO_UART_TX = CONSOLE_TX, + STDIO_UART_RX = CONSOLE_RX, + + // I2C pins + I2C0_SCL = P0_8, + I2C0_SDA = P0_9, + + I2C1_SCL = P0_2, + I2C1_SDA = P0_3, + + // SPI pins + SPI0_SCK = P0_6, + SPI0_MOSI = P0_5, + SPI0_MISO = P0_4, + SPI0_SS = P0_7, + + SPI1A_SCK = P0_12, + SPI1A_MOSI = P0_11, + SPI1A_MISO = P0_10, + SPI1A_SS = P0_13, + + SPI1B_SCK = P0_2, + SPI1B_MOSI = P0_1, + SPI1B_MISO = P0_0, + SPI1B_SS = P0_3, + + // UART pins + UART0_RX = P0_5, + UART0_TX = P0_4, + UART0_CTS = P0_6, + UART0_RTS = P0_7, + + UART1A_RX = P0_11, + UART1A_TX = P0_10, + UART1A_CTS = P0_12, + UART1A_RTS = P0_13, + + UART1B_RX = P0_1, + UART1B_TX = P0_0, + + UART1C_RX = P0_7, + UART1C_TX = P0_6, + + // Not connected + NC = NOT_CONNECTED +} PinName; + +typedef enum { + PullNone = 0, + PullUp = 1, + PullDown = 2, + PullDefault = PullUp +} PinMode; + +typedef enum { + LED_ON = 0, + LED_OFF = 1 +} LedStates; + + +// Standardized LED and button names +#define LED1 P0_13 // RED Led +//#define LED2 P0_12 // for greentea ticker testing! +// +#define LED_RED LED1 // +//#define LED_GREEN LED2 // + +// +#define BUTTON1 P0_12 // B1 PushButton + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device.h b/targets/TARGET_Maxim/TARGET_MAX32660/device.h new file mode 100644 index 00000000000..f503c54ab81 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_ARM_STD/MAX32660.sct b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_ARM_STD/MAX32660.sct new file mode 100644 index 00000000000..227d2db57e0 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_ARM_STD/MAX32660.sct @@ -0,0 +1,41 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; MAX32660 +; 256K FLASH (0x200000) @ 0x000000000 +; 96KB RAM (0x18000) @ 0x20000000 +; - 16KB RAM_0 (0x4000) @ 0x20000000 +; - 16KB RAM_1 (0x4000) @ 0x20004000 +; - 32KB RAM_2 (0x8000) @ 0x20008000 +; - 32KB RAM_3 (0x8000) @ 0x20010000 + +#include "../nvic_table.h" + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +; Round up to 8 bytes +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND 0xFFFFFFF8) + + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY - MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack region growing down + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_ARM_STD/startup_max32660.S b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_ARM_STD/startup_max32660.S new file mode 100644 index 00000000000..a1797666461 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_ARM_STD/startup_max32660.S @@ -0,0 +1,305 @@ +;******************************************************************************* +; Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. +; +; Permission is hereby granted, free of charge, to any person obtaining a +; copy of this software and associated documentation files (the "Software"), +; to deal in the Software without restriction, including without limitation +; the rights to use, copy, modify, merge, publish, distribute, sublicense, +; and/or sell copies of the Software, and to permit persons to whom the +; Software is furnished to do so, subject to the following conditions: +; +; The above copyright notice and this permission notice shall be included +; in all copies or substantial portions of the Software. +; +; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +; OTHER DEALINGS IN THE SOFTWARE. +; +; Except as contained in this notice, the name of Maxim Integrated +; Products, Inc. shall not be used except as stated in the Maxim Integrated +; Products, Inc. Branding Policy. +; +; The mere transfer of this software does not imply any licenses +; of trade secrets, proprietary technology, copyrights, patents, +; trademarks, maskwork rights, or any other form of intellectual +; property whatsoever. Maxim Integrated Products, Inc. retains all +; ownership rights. +;******************************************************************************* + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Device-specific Interrupts + DCD PF_IRQHandler ; 0x10 0x0040 16: Power Fail + DCD WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0 + DCD RSV00_IRQHandler ; 0x12 0x0048 18: RSV00 + DCD RTC_IRQHandler ; 0x13 0x004C 19: RTC + DCD RSV01_IRQHandler ; 0x14 0x0050 20: RSV1 + DCD TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0 + DCD TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1 + DCD TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2 + DCD RSV02_IRQHandler ; 0x18 0x0060 24: RSV02 + DCD RSV03_IRQHandler ; 0x19 0x0064 25: RSV03 + DCD RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04 + DCD RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05 + DCD RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06 + DCD I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0 + DCD UART0_IRQHandler ; 0x1E 0x0078 30: UART 0 + DCD UART1_IRQHandler ; 0x1F 0x007C 31: UART 1 + DCD SPI0_IRQHandler ; 0x20 0x0080 32: SPIY17 + DCD SPI1_IRQHandler ; 0x21 0x0084 33: SPIMSS + DCD RSV07_IRQHandler ; 0x22 0x0088 34: RSV07 + DCD RSV08_IRQHandler ; 0x23 0x008C 35: RSV08 + DCD RSV09_IRQHandler ; 0x24 0x0090 36: RSV09 + DCD RSV10_IRQHandler ; 0x25 0x0094 37: RSV10 + DCD RSV11_IRQHandler ; 0x26 0x0098 38: RSV11 + DCD FLC_IRQHandler ; 0x27 0x009C 39: FLC + DCD GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0 + DCD RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12 + DCD RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13 + DCD RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14 + DCD DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0 + DCD DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1 + DCD DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2 + DCD DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3 + DCD RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15 + DCD RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16 + DCD RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17 + DCD RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18 + DCD I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1 + DCD RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19 + DCD RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20 + DCD RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21 + DCD RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22 + DCD RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23 + DCD RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24 + DCD RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25 + DCD RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26 + DCD RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27 + DCD RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28 + DCD RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29 + DCD RSV30_IRQHandler ; 0x40 0x0100 64: RSV30 + DCD RSV31_IRQHandler ; 0x41 0x0104 65: RSV31 + DCD RSV32_IRQHandler ; 0x42 0x0108 66: RSV32 + DCD RSV33_IRQHandler ; 0x43 0x010C 67: RSV33 + DCD RSV34_IRQHandler ; 0x44 0x0110 68: RSV34 + DCD RSV35_IRQHandler ; 0x45 0x0114 69: RSV35 + DCD GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + IMPORT PreInit + LDR R0, =PreInit + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 +__SPIN + WFI + BL __SPIN + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + ; MAX32660 interrupts + EXPORT PF_IRQHandler [WEAK] ; 0x10 0x0040 16: Power Fail + EXPORT WDT0_IRQHandler [WEAK] ; 0x11 0x0044 17: Watchdog 0 + EXPORT RSV00_IRQHandler [WEAK] ; 0x12 0x0048 18: RSV00 + EXPORT RTC_IRQHandler [WEAK] ; 0x13 0x004C 19: RTC + EXPORT RSV01_IRQHandler [WEAK] ; 0x14 0x0050 20: RSV01 + EXPORT TMR0_IRQHandler [WEAK] ; 0x15 0x0054 21: Timer 0 + EXPORT TMR1_IRQHandler [WEAK] ; 0x16 0x0058 22: Timer 1 + EXPORT TMR2_IRQHandler [WEAK] ; 0x17 0x005C 23: Timer 2 + EXPORT RSV02_IRQHandler [WEAK] ; 0x18 0x0060 24: RSV02 + EXPORT RSV03_IRQHandler [WEAK] ; 0x19 0x0064 25: RSV03 + EXPORT RSV04_IRQHandler [WEAK] ; 0x1A 0x0068 26: RSV04 + EXPORT RSV05_IRQHandler [WEAK] ; 0x1B 0x006C 27: RSV05 + EXPORT RSV06_IRQHandler [WEAK] ; 0x1C 0x0070 28: RSV06 + EXPORT I2C0_IRQHandler [WEAK] ; 0x1D 0x0074 29: I2C0 + EXPORT UART0_IRQHandler [WEAK] ; 0x1E 0x0078 30: UART 0 + EXPORT UART1_IRQHandler [WEAK] ; 0x1F 0x007C 31: UART 1 + EXPORT SPI0_IRQHandler [WEAK] ; 0x20 0x0080 32: SPIY17 + EXPORT SPI1_IRQHandler [WEAK] ; 0x21 0x0084 33: SPIMSS + EXPORT RSV07_IRQHandler [WEAK] ; 0x22 0x0088 34: RSV07 + EXPORT RSV08_IRQHandler [WEAK] ; 0x23 0x008C 35: RSV08 + EXPORT RSV09_IRQHandler [WEAK] ; 0x24 0x0090 36: RSV09 + EXPORT RSV10_IRQHandler [WEAK] ; 0x25 0x0094 37: RSV10 + EXPORT RSV11_IRQHandler [WEAK] ; 0x26 0x0098 38: RSV11 + EXPORT FLC_IRQHandler [WEAK] ; 0x27 0x009C 39: FLC + EXPORT GPIO0_IRQHandler [WEAK] ; 0x28 0x00A0 40: GPIO0 + EXPORT RSV12_IRQHandler [WEAK] ; 0x29 0x00A4 41: RSV12 + EXPORT RSV13_IRQHandler [WEAK] ; 0x2A 0x00A8 42: RSV13 + EXPORT RSV14_IRQHandler [WEAK] ; 0x2B 0x00AC 43: RSV14 + EXPORT DMA0_IRQHandler [WEAK] ; 0x2C 0x00B0 44: DMA0 + EXPORT DMA1_IRQHandler [WEAK] ; 0x2D 0x00B4 45: DMA1 + EXPORT DMA2_IRQHandler [WEAK] ; 0x2E 0x00B8 46: DMA2 + EXPORT DMA3_IRQHandler [WEAK] ; 0x2F 0x00BC 47: DMA3 + EXPORT RSV15_IRQHandler [WEAK] ; 0x30 0x00C0 48: RSV15 + EXPORT RSV16_IRQHandler [WEAK] ; 0x31 0x00C4 49: RSV16 + EXPORT RSV17_IRQHandler [WEAK] ; 0x32 0x00C8 50: RSV17 + EXPORT RSV18_IRQHandler [WEAK] ; 0x33 0x00CC 51: RSV18 + EXPORT I2C1_IRQHandler [WEAK] ; 0x34 0x00D0 52: I2C1 + EXPORT RSV19_IRQHandler [WEAK] ; 0x35 0x00D4 53: RSV19 + EXPORT RSV20_IRQHandler [WEAK] ; 0x36 0x00D8 54: RSV20 + EXPORT RSV21_IRQHandler [WEAK] ; 0x37 0x00DC 55: RSV21 + EXPORT RSV22_IRQHandler [WEAK] ; 0x38 0x00E0 56: RSV22 + EXPORT RSV23_IRQHandler [WEAK] ; 0x39 0x00E4 57: RSV23 + EXPORT RSV24_IRQHandler [WEAK] ; 0x3A 0x00E8 58: RSV24 + EXPORT RSV25_IRQHandler [WEAK] ; 0x3B 0x00EC 59: RSV25 + EXPORT RSV26_IRQHandler [WEAK] ; 0x3C 0x00F0 60: RSV26 + EXPORT RSV27_IRQHandler [WEAK] ; 0x3D 0x00F4 61: RSV27 + EXPORT RSV28_IRQHandler [WEAK] ; 0x3E 0x00F8 62: RSV28 + EXPORT RSV29_IRQHandler [WEAK] ; 0x3F 0x00FC 63: RSV29 + EXPORT RSV30_IRQHandler [WEAK] ; 0x40 0x0100 64: RSV30 + EXPORT RSV31_IRQHandler [WEAK] ; 0x41 0x0104 65: RSV31 + EXPORT RSV32_IRQHandler [WEAK] ; 0x42 0x0108 66: RSV32 + EXPORT RSV33_IRQHandler [WEAK] ; 0x43 0x010C 67: RSV33 + EXPORT RSV34_IRQHandler [WEAK] ; 0x44 0x0110 68: RSV34 + EXPORT RSV35_IRQHandler [WEAK] ; 0x45 0x0114 69: RSV35 + EXPORT GPIOWAKE_IRQHandler [WEAK] ; 0x46 0x0118 70: GPIO Wakeup + +PF_IRQHandler ; 0x10 0x0040 16: Power Fail +WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0 +RSV00_IRQHandler ; 0x12 0x0048 18: RSV00 +RTC_IRQHandler ; 0x13 0x004C 19: RTC +RSV01_IRQHandler ; 0x14 0x0050 20: RSV01 +TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0 +TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1 +TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2 +RSV02_IRQHandler ; 0x18 0x0060 24: RSV02 +RSV03_IRQHandler ; 0x19 0x0064 25: RSV03 +RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04 +RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05 +RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06 +I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0 +UART0_IRQHandler ; 0x1E 0x0078 30: UART 0 +UART1_IRQHandler ; 0x1F 0x007C 31: UART 1 +SPI0_IRQHandler ; 0x20 0x0080 32: SPI0 +SPI1_IRQHandler ; 0x21 0x0084 33: SPI1 +RSV07_IRQHandler ; 0x22 0x0088 34: RSV07 +RSV08_IRQHandler ; 0x23 0x008C 35: RSV08 +RSV09_IRQHandler ; 0x24 0x0090 36: RSV09 +RSV10_IRQHandler ; 0x25 0x0094 37: RSV10 +RSV11_IRQHandler ; 0x26 0x0098 38: RSV11 +FLC_IRQHandler ; 0x27 0x009C 39: FLC +GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0 +RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12 +RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13 +RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14 +DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0 +DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1 +DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2 +DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3 +RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15 +RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16 +RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17 +RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18 +I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1 +RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19 +RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20 +RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21 +RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22 +RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23 +RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24 +RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25 +RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26 +RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27 +RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28 +RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29 +RSV30_IRQHandler ; 0x40 0x0100 64: RSV30 +RSV31_IRQHandler ; 0x41 0x0104 65: RSV31 +RSV32_IRQHandler ; 0x42 0x0108 66: RSV32 +RSV33_IRQHandler ; 0x43 0x010C 67: RSV33 +RSV34_IRQHandler ; 0x44 0x0110 68: RSV34 +RSV35_IRQHandler ; 0x45 0x0114 69: RSV35 +GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup + + + B . + ENDP + ALIGN + END diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_GCC_ARM/max32660.ld b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_GCC_ARM/max32660.ld new file mode 100644 index 00000000000..1e2fcd7f868 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_GCC_ARM/max32660.ld @@ -0,0 +1,192 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "../nvic_table.h" + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = (MBED_RAM_START + VECTORS_SIZE), LENGTH = MBED_RAM_SIZE - VECTORS_SIZE + RAM_0 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 + RAM_1 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x4000 + RAM_2 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x8000 + RAM_3 (rwx) : ORIGIN = 0x20010000, LENGTH = 0x8000 +} + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_GCC_ARM/startup_max32660.S b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_GCC_ARM/startup_max32660.S new file mode 100644 index 00000000000..fa0cb6192fa --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device/TOOLCHAIN_GCC_ARM/startup_max32660.S @@ -0,0 +1,312 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + ******************************************************************************/ + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xC00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0xC00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Device-specific Interrupts */ + .long PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ + .long WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ + .long RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */ + .long RTC_IRQHandler /* 0x13 0x004C 19: RTC */ + .long RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */ + .long TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ + .long TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ + .long TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ + .long RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */ + .long RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */ + .long RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */ + .long RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */ + .long RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */ + .long I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ + .long UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ + .long UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ + .long SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */ + .long SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */ + .long RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */ + .long RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */ + .long RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */ + .long RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */ + .long RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */ + .long FLC_IRQHandler /* 0x27 0x009C 39: FLC */ + .long GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ + .long RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */ + .long RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */ + .long RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */ + .long DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ + .long DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ + .long DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ + .long DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ + .long RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */ + .long RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */ + .long RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */ + .long RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */ + .long I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ + .long RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */ + .long RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */ + .long RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */ + .long RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */ + .long RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */ + .long RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */ + .long RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */ + .long RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */ + .long RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */ + .long RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */ + .long RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */ + .long RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */ + .long RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */ + .long RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */ + .long RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */ + .long RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */ + .long RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */ + .long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =__StackTop + mov sp, r0 + + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ + ldr r0, =PreInit + blx r0 + cbnz r0, .SKIPRAMINIT + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __load_data: Where data sections are saved. + * _data /_edata: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 0 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +/* + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * _bss : start of BSS section. Must align to 4 + * _ebss : end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 + +.SKIPRAMINIT: + + /* Perform system initialization after RAM initialization */ + ldr r0, =SystemInit + blx r0 + + /* This must be called to walk the constructor array for static C++ objects */ + /* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */ + /* where X is {preinit, init, fini} */ + + /* Transfer control to users main program */ + ldr r0, =_start + blx r0 + +.SPIN: + /* Enter LP2 if main() ever returns. */ + wfi + bl .SPIN + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + /* SysTick_Handler is defined in mxc_delay.c */ + def_irq_handler Default_Handler + + /* Device-specific Interrupts */ + def_irq_handler PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ + def_irq_handler WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ + def_irq_handler RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */ + def_irq_handler RTC_IRQHandler /* 0x13 0x004C 19: RTC */ + def_irq_handler RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */ + def_irq_handler TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ + def_irq_handler TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ + def_irq_handler TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ + def_irq_handler RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */ + def_irq_handler RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */ + def_irq_handler RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */ + def_irq_handler RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */ + def_irq_handler RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */ + def_irq_handler I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ + def_irq_handler UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ + def_irq_handler UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ + def_irq_handler SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */ + def_irq_handler SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */ + def_irq_handler RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */ + def_irq_handler RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */ + def_irq_handler RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */ + def_irq_handler RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */ + def_irq_handler RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */ + def_irq_handler FLC_IRQHandler /* 0x27 0x009C 39: FLC */ + def_irq_handler GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ + def_irq_handler RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */ + def_irq_handler RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */ + def_irq_handler RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */ + def_irq_handler DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ + def_irq_handler DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ + def_irq_handler DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ + def_irq_handler DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ + def_irq_handler RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */ + def_irq_handler RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */ + def_irq_handler RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */ + def_irq_handler RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */ + def_irq_handler I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ + def_irq_handler RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */ + def_irq_handler RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */ + def_irq_handler RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */ + def_irq_handler RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */ + def_irq_handler RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */ + def_irq_handler RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */ + def_irq_handler RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */ + def_irq_handler RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */ + def_irq_handler RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */ + def_irq_handler RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */ + def_irq_handler RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */ + def_irq_handler RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */ + def_irq_handler RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */ + def_irq_handler RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */ + def_irq_handler RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */ + def_irq_handler RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */ + def_irq_handler RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */ + def_irq_handler GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ + + .end diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device/cmsis.h b/targets/TARGET_Maxim/TARGET_MAX32660/device/cmsis.h new file mode 100644 index 00000000000..35470a67cdf --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device/cmsis.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "max32660.h" +#include "nvic_table.h" + +#endif + diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/device/nvic_table.h b/targets/TARGET_Maxim/TARGET_MAX32660/device/nvic_table.h new file mode 100644 index 00000000000..ce84217db4e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/device/nvic_table.h @@ -0,0 +1,63 @@ +/** + * @file + * @brief NVIC utility function and type declarations. + */ + +/* **************************************************************************** + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _NVIC_TABLE_H +#define _NVIC_TABLE_H + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 // 256 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x18000 // 96 KB +#endif + +#define NVIC_NUM_VECTORS (16 + 55) // MXC_IRQ_COUNT +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START // Vectors positioned at start of RAM + +#endif /* _NVIC_TABLE_H */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/flash_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/flash_api.c new file mode 100644 index 00000000000..7db4781d706 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/flash_api.c @@ -0,0 +1,161 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#if DEVICE_FLASH +#include "flash_api.h" +#include "mbed_critical.h" +#include "cmsis.h" +#include "flc.h" + + +/** Initialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_init(flash_t *obj) +{ + return MXC_FLC_Init(); +} + +/** Uninitialize the flash peripheral and the flash_t object + * + * @param obj The flash object + * @return 0 for success, -1 for error + */ +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +/** Erase one sector starting at defined address + * + * The address should be at sector boundary. This function does not do any check for address alignments + * @param obj The flash object + * @param address The sector starting address + * @return 0 for success, -1 for error + */ +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + if(MXC_FLC_PageErase(address) != 0) { + return -1; + } else { + return 0; + } +} + +/** Program pages starting at defined address + * + * The pages should not cross multiple sectors. + * This function does not do any check for address alignments or if size is aligned to a page size. + * @param obj The flash object + * @param address The sector starting address + * @param data The data buffer to be programmed + * @param size The number of bytes to program + * @return 0 for success, -1 for error + */ +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int32_t status = E_BUSY; + + while ( status == E_BUSY ) { + status = MXC_FLC_Write(address, size, (uint32_t *)data); + } + + if (status != 0) { + return -1; + } else { + return 0; + } +} + +/** Get sector size + * + * @param obj The flash object + * @param address The sector starting address + * @return The size of a sector + */ +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + /* 1 sector = 1 page */ + if (address >= (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return MBED_FLASH_INVALID_SIZE; + } else { + return MXC_FLASH_PAGE_SIZE; + } +} + +/** Get page size + * + * The page size defines the writable page size + * @param obj The flash object + * @return The size of a page + */ +uint32_t flash_get_page_size(const flash_t *obj) +{ + return MXC_FLASH_PAGE_SIZE; +} + +/** Get start address for the flash region + * + * @param obj The flash object + * @return The start address for the flash region + */ +uint32_t flash_get_start_address(const flash_t *obj) +{ + return MXC_FLASH_MEM_BASE; +} + +/** Get the flash region size + * + * @param obj The flash object + * @return The flash region size + */ +uint32_t flash_get_size(const flash_t *obj) +{ + return MXC_FLASH_MEM_SIZE; +} + +/** Get the flash erase value + * + * @param obj The flash object + * @return The flash erase value + */ +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/gpio_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/gpio_api.c new file mode 100644 index 00000000000..b85b1c44aff --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/gpio_api.c @@ -0,0 +1,99 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_regs.h" + +uint32_t gpio_set(PinName name) +{ + MBED_ASSERT(name != (PinName)NC); + // Set function as GPIO_INPUT (Default) + pin_function(name, 0); + return 1 << PINNAME_TO_PIN(name); +} + +void gpio_init(gpio_t *obj, PinName name) +{ + obj->name = name; + if (name == (PinName)NC) { + return; + } + // Obtain pin number + unsigned int pin = PINNAME_TO_PIN(name); + + // Set register pointers + obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO0->out, pin); + obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO0->in, pin); + obj->mode = PullNone; + + // Ensure that the GPIO clock is enabled + MXC_GCR->pclk_dis0 &= ~MXC_F_GCR_PCLK_DIS0_GPIO0D; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + pin_mode(obj->name, mode); +} + +void pin_dir_mode(PinName name, PinDirection direction, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + switch (direction){ + case PIN_INPUT: + pin_function(name, 0); + + unsigned int pin = PINNAME_TO_PIN(name); + + if (mode == PullUp) { + MXC_GPIO0->out |= 1 << pin; + } else if (mode == PullDown) { + MXC_GPIO0->out &= ~(1 << pin); + } else { // PullNone + MXC_GPIO0->out &= ~(1 << pin); + } + break; + case PIN_OUTPUT: + pin_function(name, 1); + break; + default: + break; + } + pin_mode(name, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + pin_dir_mode(obj->name, direction, obj->mode); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/gpio_irq_api.c new file mode 100644 index 00000000000..10c4315ec2e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/gpio_irq_api.c @@ -0,0 +1,157 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "mbed_error.h" + +static gpio_irq_t *objs[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT] = {{0}}; +static gpio_irq_handler irq_handler; + +void gpio_irq_0(void) +{ + uint32_t intfl, in_val; + uint32_t mask; + unsigned int pin; + + /* Get GPIO Register Structure */ + mxc_gpio_regs_t *gpio = MXC_GPIO0; //MXC_GPIO_GET_GPIO(port); + + /* Read pin state */ + in_val = gpio->in; + + /* Read interrupts */ + intfl = gpio->int_stat & gpio->int_en; + + mask = 1; + + /* Determine related routine*/ + for (pin = 0; pin < MXC_CFG_GPIO_PINS_PORT; pin++) { + if (intfl & mask) { + gpio->int_clr |= mask;/* clear interrupt */ + gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL; + gpio_irq_t *obj = objs[0][pin]; + if (obj && obj->id) { + if ((event == IRQ_RISE) && obj->rise_en) { + irq_handler(obj->id, IRQ_RISE); + } else if ((event == IRQ_FALL) && obj->fall_en) { + irq_handler(obj->id, IRQ_FALL); + } + } + } + mask <<= 1; + } +} + +int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uintptr_t context) +{ + if (name == NC) { + return -1; + } + + uint8_t port = PINNAME_TO_PORT(name); + uint8_t pin = PINNAME_TO_PIN(name); + + if ((port > MXC_CFG_GPIO_INSTANCES) || (pin > MXC_CFG_GPIO_PINS_PORT)) { + return 1; + } + + obj->port = port; + obj->pin = pin; + obj->id = context; + objs[port][pin] = obj; + + /* register handlers */ + irq_handler = handler; + NVIC_SetVector(GPIO0_IRQn, (uint32_t)gpio_irq_0); + + /* disable the interrupt locally */ + MXC_GPIO0->int_en &= ~(1 << pin); + + /* clear a pending request */ + MXC_GPIO0->int_stat |= (1 << pin); + + NVIC_EnableIRQ(GPIO0_IRQn); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + MXC_GPIO0->int_en &= ~(1 << obj->pin); + objs[obj->port][obj->pin] = NULL; + +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + /* Note that MAX32660 supports only one edge interrupt at a time */ + if (event == IRQ_FALL) { + obj->fall_en = enable; + MXC_GPIO0->int_mod |= (1 << obj->pin); + MXC_GPIO0->int_pol &= ~(1 << obj->pin); + MXC_GPIO0->int_en |= (1 << obj->pin); + } else if (event == IRQ_RISE) { + obj->rise_en = enable; + MXC_GPIO0->int_mod |= (1 << obj->pin); + MXC_GPIO0->int_pol |= (1 << obj->pin); + MXC_GPIO0->int_en |= (1 << obj->pin); + } +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + MXC_GPIO0->int_en |= (1 << obj->pin); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + MXC_GPIO0->int_en &= ~(1 << obj->pin); +} + +gpio_irq_t *gpio_irq_get_obj(PinName name) +{ + if (name == NC) { + return NULL; + } + + unsigned int port = PINNAME_TO_PORT(name); + unsigned int pin = PINNAME_TO_PIN(name); + + if ((port > MXC_CFG_GPIO_INSTANCES) || (pin > MXC_CFG_GPIO_PINS_PORT)) { + return NULL; + } + + return objs[port][pin]; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/gpio_object.h b/targets/TARGET_Maxim/TARGET_MAX32660/gpio_object.h new file mode 100644 index 00000000000..8cce1bc4d5e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/gpio_object.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName name; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PinMode mode; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->name != (PinName)NC); + *obj->reg_out = !!value; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->name != (PinName)NC); + return *obj->reg_in; +} + +void pin_dir_mode(PinName name, PinDirection direction, PinMode mode); + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->name != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/i2c_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/i2c_api.c new file mode 100644 index 00000000000..310a321bfa2 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/i2c_api.c @@ -0,0 +1,246 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "i2c_regs.h" +#include "mxc_i2c.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#ifndef MXC_I2CM_RX_TIMEOUT +#define MXC_I2CM_RX_TIMEOUT 0x5000 +#endif + +#ifndef I2C_ERROR +#define I2C_ERROR (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | MXC_F_I2C_INT_FL0_ADDR_NACK_ER | \ + MXC_F_I2C_INT_FL0_DATA_ER | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \ + MXC_F_I2C_INT_FL0_STOP_ER) +#endif + +#define MBED_NAK 0 +#define MBED_ACK 1 +#define MBED_TIMEOUT 2 + +//****************************************************************************** +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + // SDA and SCL must map to same peripheral instance + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + mxc_i2c_regs_t *i2c = (mxc_i2c_regs_t*)pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)i2c != NC); + + obj->i2c = i2c; + obj->start_pending = 0; + + MXC_I2C_Shutdown(obj->i2c); + MXC_I2C_Init(obj->i2c, 1, 0);// configure as master +} + +//****************************************************************************** +void i2c_frequency(i2c_t *obj, int hz) +{ + MXC_I2C_SetFrequency(obj->i2c, hz); +} + +//****************************************************************************** +int i2c_start(i2c_t *obj) +{ + int ret; + ret = MXC_I2C_Start(obj->i2c); + if (ret != 0) { + //... + } + return ret; +} + +//****************************************************************************** +int i2c_stop(i2c_t *obj) +{ + int ret; + ret = MXC_I2C_Stop(obj->i2c); + if (ret != 0) { + //... + } + return ret; +} + +//****************************************************************************** +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int ret = 0; + mxc_i2c_req_t reqMaster; + + reqMaster.i2c = obj->i2c; + reqMaster.addr = address; + reqMaster.tx_buf = NULL; + reqMaster.tx_len = 0; + reqMaster.rx_buf = (unsigned char *)data; + reqMaster.rx_len = length; + reqMaster.restart = !stop; + reqMaster.callback = NULL; + + ret = MXC_I2C_MasterTransaction(&reqMaster); + if (ret == 0) { + ret = length; + } + + return ret; +} + +//****************************************************************************** +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int ret = 0; + mxc_i2c_req_t reqMaster; + + reqMaster.i2c = obj->i2c; + reqMaster.addr = address; + reqMaster.tx_buf = (unsigned char *)data; + reqMaster.tx_len = length; + reqMaster.rx_buf = NULL; + reqMaster.rx_len = 0; + reqMaster.restart = !stop; + reqMaster.callback = NULL; + + ret = MXC_I2C_MasterTransaction(&reqMaster); + if (ret == 0) { + ret = length; + } + + return ret; +} + +//****************************************************************************** +void i2c_reset(i2c_t *obj) +{ + MXC_I2C_Recover(obj->i2c, 5); +} + +//****************************************************************************** +int i2c_byte_read(i2c_t *obj, int ack) +{ + unsigned char byt = 0; + + MXC_I2C_ReadByte(obj->i2c, &byt, ack); + + return byt; +} + +//****************************************************************************** +int i2c_byte_write(i2c_t *obj, int data) +{ + int ret; + + ret = MXC_I2C_WriteByte(obj->i2c, (unsigned char)data); + + /* + Functions returns: + =0 if byte is acknowledged, + =1 if not acknowledged, + <0 if error + */ + // Convert return value + if (ret == 0) { + ret = MBED_ACK; // ACK Receviced + } else if (ret == 1) { + ret = MBED_NAK; // NAK Received + } else { + //... Error + } + + return ret; +} + +//****************************************************************************** +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +//****************************************************************************** +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +//****************************************************************************** +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +//****************************************************************************** +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if 0 // DEVICE_I2CSLAVE +//****************************************************************************** +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + +} +//****************************************************************************** +int i2c_slave_receive(i2c_t *obj) +{ + + +} + +//****************************************************************************** +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + +} + +//****************************************************************************** +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + +} + +//****************************************************************************** +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + +} + +#endif + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c new file mode 100644 index 00000000000..315352b172c --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/lp_ticker.c @@ -0,0 +1,236 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#if DEVICE_LPTICKER + +#include +#include +#include "rtc_api.h" +#include "lp_ticker_api.h" +#include "rtc.h" +#include "lp.h" +#include "mxc_sys.h" + +#if 0 + +#define LP_TIMER_RATE_HZ 4096 +#define LP_TIMER_WIDTH 32 + +/* Converts a time in milleseconds to the equivalent RSSA register value. */ +#define MSEC_TO_RSSA(x) (0 - ((x * 4096) / 1000)) + +static uint32_t g_nb_irq_tick = 0; + +//****************************************************************************** +void lp_ticker_init(void) +{ + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; + + while(MXC_RTC_DisableInt(MXC_RTC_INT_EN_SHORT) == E_BUSY) { + ; + } + + NVIC_SetVector(RTC_IRQn, (uint32_t)lp_ticker_irq_handler); + NVIC_EnableIRQ(RTC_IRQn); + + while(MXC_RTC_Start() == E_BUSY) { + ; + } + + MXC_LP_EnableRTCAlarmWakeup(); + + MXC_RTC->rssa = 0; +} + +//****************************************************************************** +void lp_ticker_free(void) +{ + while(MXC_RTC_DisableInt(MXC_RTC_INT_EN_SHORT) == E_BUSY) { + ; + } +} + +//****************************************************************************** +uint32_t lp_ticker_read(void) +{ + uint32_t tick; + + tick = g_nb_irq_tick + g_nb_irq_tick - (0-MXC_RTC->rssa); + + return tick; +} + +//****************************************************************************** +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + while(MXC_RTC_DisableInt(MXC_RTC_INT_EN_SHORT) == E_BUSY) { + ; + } + + g_nb_irq_tick = timestamp ? timestamp : 1; + + while(MXC_RTC_SetSubsecondAlarm(0-g_nb_irq_tick) == E_BUSY) { + ; + } + + while(MXC_RTC_EnableInt(MXC_RTC_INT_EN_SHORT) == E_BUSY) { + ; + } + + while(MXC_RTC_Start() == E_BUSY) { + ; + } +} + +//****************************************************************************** +void lp_ticker_disable_interrupt(void) +{ + while(MXC_RTC_DisableInt(MXC_RTC_INT_EN_SHORT) == E_BUSY) { + ; + } + NVIC_DisableIRQ(RTC_IRQn); +} + +//****************************************************************************** +void lp_ticker_clear_interrupt(void) +{ + MXC_RTC->ctrl &= ~(MXC_F_RTC_CTRL_ALSF); + MXC_RTC->ctrl &= ~(MXC_F_RTC_CTRL_ALDF); +} + +//****************************************************************************** +void lp_ticker_fire_interrupt(void) +{ + MXC_RTC->ctrl |= MXC_F_RTC_CTRL_ALSF; + NVIC_SetPendingIRQ(RTC_IRQn); +} + +//****************************************************************************** +const ticker_info_t *lp_ticker_get_info(void) +{ + static const ticker_info_t info = { + LP_TIMER_RATE_HZ, + LP_TIMER_WIDTH + }; + + return &info; +} +#else + +#include "tmr.h" + +#define LP_TIMER MXC_TMR2 +#define LP_TIMER_IRQn TMR2_IRQn +#define LP_TIMER_PRESCALE TMR_PRES_1024 +#define LP_TIMER_FREQ ((HIRC96_FREQ/2) >> (MXC_V_TMR_CN_PRES_DIV_BY_1024+1)) +#define LP_TIMER_WIDTH 32 + +//****************************************************************************** +void lp_ticker_init(void) +{ + mxc_tmr_cfg_t cfg; + unsigned int count; + + cfg.pres = LP_TIMER_PRESCALE; + cfg.mode = TMR_MODE_COMPARE; + cfg.bitMode = TMR_BIT_MODE_32; + cfg.clock = MXC_TMR_HFIO_CLK; + cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(LP_TIMER); + cfg.pol = 0; + + // Disable and deconfigure + MXC_TMR_Shutdown(LP_TIMER); + MXC_TMR_ClearFlags(LP_TIMER); + + count = MXC_TMR_GetCount(LP_TIMER); + + // Configure and enable + MXC_TMR_Init(LP_TIMER, &cfg); + MXC_TMR_SetCount(LP_TIMER, count); + MXC_TMR_Start(LP_TIMER); + + // Enable interrupts + NVIC_SetVector(LP_TIMER_IRQn, (uint32_t)lp_ticker_irq_handler); + NVIC_EnableIRQ(LP_TIMER_IRQn); +} + +//****************************************************************************** +void lp_ticker_free(void) +{ + MXC_TMR_Shutdown(LP_TIMER); +} + +//****************************************************************************** +uint32_t lp_ticker_read(void) +{ + return LP_TIMER->cnt; +} + +//****************************************************************************** +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + MXC_TMR_SetCompare(LP_TIMER, (timestamp) ? timestamp : 1); +} + +//****************************************************************************** +void lp_ticker_disable_interrupt(void) +{ + NVIC_DisableIRQ(LP_TIMER_IRQn); +} + +//****************************************************************************** +void lp_ticker_clear_interrupt(void) +{ + MXC_TMR_ClearFlags(LP_TIMER); +} + +//****************************************************************************** +void lp_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(LP_TIMER_IRQn); +} + +//****************************************************************************** +const ticker_info_t *lp_ticker_get_info(void) +{ + static const ticker_info_t info = { + LP_TIMER_FREQ, + LP_TIMER_WIDTH + }; + + return &info; +} + +#endif + +#endif // DEVICE_LPTICKER \ No newline at end of file diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/objects.h b/targets/TARGET_Maxim/TARGET_MAX32660/objects.h new file mode 100644 index 00000000000..00277d84fc6 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/objects.h @@ -0,0 +1,95 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "gpio_regs.h" +#include "uart.h" +#include "i2c_regs.h" +#include "spi_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct flash_s { + uint8_t notused; +}; + +struct port_s { + PortName port; + uint32_t mask; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PinMode mode; +}; + +struct gpio_irq_s { + uint8_t port; + uint8_t pin; + uint8_t rise_en; + uint8_t fall_en; + uint32_t id; +}; + +struct serial_s { + int index; + mxc_uart_regs_t *uart; + uint32_t id; + sys_map_t map; + PinName tx; + PinName rx; +}; + +struct i2c_s { + mxc_i2c_regs_t *i2c; + int start_pending; + //sys_cfg_i2c_t sys_cfg; +}; + +struct spi_s { + int index; + void *spi; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/pinmap.c b/targets/TARGET_Maxim/TARGET_MAX32660/pinmap.c new file mode 100644 index 00000000000..c897bcc4759 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/pinmap.c @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "objects.h" +#include "gpio_regs.h" + +void pin_function(PinName name, int function) +{ + MBED_ASSERT(name != (PinName)NC); + + if ((function >= 0) && (function <= 0xF)) { + + // Set GPIO Function + unsigned int pin_val = (1 << PINNAME_TO_PIN(name)); + switch (function) { + case 0: // GPIO_FUNC_IN + MXC_GPIO0->en0 |= pin_val; + MXC_GPIO0->en1 &= ~pin_val; + break; + case 1: // GPIO_FUNC_OUT + MXC_GPIO0->en0 |= pin_val; + MXC_GPIO0->en1 &= ~pin_val; + MXC_GPIO0->out_en |= pin_val; + break; + case 2: // GPIO_FUNC_ALT1 + MXC_GPIO0->en0 &= ~pin_val; + MXC_GPIO0->en1 &= ~pin_val; + break; + case 3: // GPIO_FUNC_ALT2 + MXC_GPIO0->en0 &= ~pin_val; + MXC_GPIO0->en1 |= pin_val; + break; + case 4: // GPIO_FUNC_ALT3 + MXC_GPIO0->en0 |= pin_val; + MXC_GPIO0->en1 |= pin_val; + break; + default: + break; + } + } +} + +void pin_mode(PinName name, PinMode mode) +{ + MBED_ASSERT(name != (PinName)NC); + + unsigned int pin_val = (1 << PINNAME_TO_PIN(name)); + switch (mode) { + case PullUp: + MXC_GPIO0->pad_cfg1 |= pin_val; + MXC_GPIO0->ps |= pin_val; + break; + case PullDown: + MXC_GPIO0->pad_cfg1 |= pin_val; + MXC_GPIO0->ps &= ~pin_val; + break; + case PullNone: + MXC_GPIO0->pad_cfg1 &= ~pin_val; + MXC_GPIO0->ps &= ~pin_val; + break; + default: + break; + } +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/port_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/port_api.c new file mode 100644 index 00000000000..67dd71487eb --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/port_api.c @@ -0,0 +1,111 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_regs.h" + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName)((port << PORT_SHIFT) | pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection direction) +{ + uint32_t pin_per_port; + mxc_gpio_regs_t *gpio = MXC_GPIO0; //MXC_GPIO_GET_GPIO(port); + obj->port = port; + obj->mask = mask; + obj->reg_out = &gpio->out; + obj->reg_in = &gpio->in; + obj->mode = PullDefault; + + // Ensure that the GPIO clock is enabled + if (port == Port0) { + MXC_GCR->pclk_dis0 &= ~MXC_F_GCR_PCLK_DIS0_GPIO0D; + } + + // Obtain pin number of the port + pin_per_port = (port == Port0) ? MXC_CFG_GPIO_PINS_PORT : (MXC_CFG_GPIO_PINS_PORT)/2; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i = 0; i < pin_per_port; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(obj->port, i)); + pin_dir_mode(port_pin(obj->port, i), direction, obj->mode); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i, pin_per_port; + obj->mode = mode; + + // Obtain pin number of the port + pin_per_port = (PINNAME_TO_PORT(obj->port) == Port0) ? MXC_CFG_GPIO_PINS_PORT : (MXC_CFG_GPIO_PINS_PORT)/2; + + // The mode is set per pin: reuse pinmap logic + for (i = 0; i < pin_per_port; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection direction) +{ + uint32_t i, pin_per_port; + + // Obtain pin number of the port + pin_per_port = (PINNAME_TO_PORT(obj->port) == Port0) ? MXC_CFG_GPIO_PINS_PORT : (MXC_CFG_GPIO_PINS_PORT)/2; + + // The mode is set per pin: reuse gpio logic + for (i = 0; i < pin_per_port; i++) { + if (obj->mask & (1 << i)) { + pin_dir_mode(port_pin(obj->port, i), direction, obj->mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) +{ + return (*obj->reg_in & obj->mask); +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/rtc_api.c new file mode 100644 index 00000000000..c17c676696e --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/rtc_api.c @@ -0,0 +1,90 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#if DEVICE_RTC + +#include +#include +#include "rtc_api.h" +#include "rtc.h" +#include "mxc_sys.h" + + +//****************************************************************************** +void rtc_init(void) +{ + // Enable clock + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; + + while(MXC_RTC_Start() == E_BUSY) { + ; + } +} + +//****************************************************************************** +void rtc_free(void) +{ + +} + +//****************************************************************************** +int rtc_isenabled(void) +{ + return ((MXC_RTC->ctrl & MXC_F_RTC_CTRL_RTCE) >> MXC_F_RTC_CTRL_RTCE_POS); +} + +//****************************************************************************** +void rtc_write(time_t t) +{ + MXC_RTC_Stop(); + MXC_RTC_Init(t, 0); + + while(MXC_RTC_Start() == E_BUSY) { + ; + } +} + +//****************************************************************************** +time_t rtc_read(void) +{ + uint32_t sec = 0; + uint32_t subsec = 0; + + while (MXC_RTC_GetTime (&sec, &subsec) != 0) { + ; + } + + return sec; +} + +#endif // DEVICE_RTC diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c new file mode 100644 index 00000000000..4c0b22854cd --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/serial_api.c @@ -0,0 +1,357 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include +#include "mbed_assert.h" +#include "cmsis.h" +#include "serial_api.h" +#include "gpio_api.h" +#include "uart.h" +#include "uart_regs.h" +#include "uart_reva_regs.h" +#include "PeripheralPins.h" + +#define DEFAULT_BAUD 9600 + +// Variables for managing the stdio UART +int stdio_uart_inited = 0; +serial_t stdio_uart = {0}; + +// Variables for interrupt driven +static uart_irq_handler irq_handler = NULL; +static serial_t *objs[MXC_UART_INSTANCES]; + + +#define UART_ER_IE (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | \ + MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ + MXC_F_UART_REVA_INT_EN_RX_OVERRUN) + +#define UART_RX_IE (MXC_F_UART_INT_EN_RX_FIFO_LVL) + +#define UART_TX_IE (MXC_F_UART_INT_EN_TX_FIFO_AE | \ + MXC_F_UART_INT_EN_TX_FIFO_LVL) + +#define MXC_F_UART_THRESH_CTRL_TX_FIFO_DEFAULT_THRESH_VAL (1 << MXC_F_UART_CTRL1_TX_FIFO_LVL_POS) +#define MXC_F_UART_THRESH_CTRL_RX_FIFO_DEFAULT_THRESH_VAL (1 << MXC_F_UART_CTRL1_RX_FIFO_LVL_POS) + +static void usurp_pin(PinName, int); + +//****************************************************************************** +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // Determine which uart is associated with each pin + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); + + // Make sure that both pins are pointing to the same uart + MBED_ASSERT(uart != (UARTName)NC); + + // Set the obj pointer to the proper uart + obj->uart = (mxc_uart_regs_t*)uart; + + // Set the uart index + obj->index = MXC_UART_GET_IDX(obj->uart); + + // Record the pins requested + obj->tx = tx; + obj->rx = rx; + + obj->map = MAP_A; + + if (uart == UART_1) { + if ( (tx == UART1B_TX) && (rx == UART1B_RX) ) { + obj->map = MAP_B; + } else if ( (tx == UART1C_TX) && (rx == UART1C_RX) ) { + obj->map = MAP_C; + } + } + + // Manage stdio UART + if (uart == STDIO_UART) { + stdio_uart_inited = 1; + stdio_uart = *obj; + } + + MXC_UART_Init (obj->uart, DEFAULT_BAUD, obj->map); + //MBED_ASSERT(retval == E_NO_ERROR); +} + +void serial_free(serial_t *obj) +{ + MXC_UART_Shutdown(obj->uart); + objs[obj->index] = 0; + obj->index = 0xff; +} + +//****************************************************************************** +void serial_baud(serial_t *obj, int baudrate) +{ + MXC_UART_SetFrequency(obj->uart, baudrate); + //MBED_ASSERT(retval == E_NO_ERROR); +} + +//****************************************************************************** +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + + MXC_UART_SetDataSize(obj->uart, data_bits); + + switch (parity) { + case ParityNone: + MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_DISABLE); + break; + case ParityOdd : + MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_ODD); + break; + case ParityEven: + MXC_UART_SetParity (obj->uart, MXC_UART_PARITY_EVEN); + break; + case ParityForced1: + case ParityForced0: + default: + MBED_ASSERT(0); + break; + } + + switch (stop_bits) { + case 1: + MXC_UART_SetStopBits (obj->uart, MXC_UART_STOP_1); + break; + case 2: + MXC_UART_SetStopBits (obj->uart, MXC_UART_STOP_2); + break; + default: + MBED_ASSERT(0); + break; + } +} + +//****************************************************************************** +void uart_handler(serial_t *obj) +{ + // clear interrupts + volatile uint32_t flags = obj->uart->int_fl; + + if (flags & UART_ER_IE) { + // clear error flags + obj->uart->int_fl = UART_ER_IE; + } + + if (flags & UART_RX_IE) { + obj->uart->int_fl = UART_RX_IE; + if (obj && irq_handler) { + irq_handler(obj->id, RxIrq); + } + } + + if (flags & UART_TX_IE) { + obj->uart->int_fl = UART_TX_IE; + if (obj && irq_handler) { + irq_handler(obj->id, TxIrq); + } + } +} + +void uart0_handler(void) { uart_handler(objs[0]); } +void uart1_handler(void) { uart_handler(objs[1]); } + +//****************************************************************************** +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) +{ + irq_handler = handler; + obj->id = context; +} + +//****************************************************************************** +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj->index < MXC_UART_INSTANCES); + objs[obj->index] = obj; + + switch (obj->index) { + case 0: + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); + NVIC_EnableIRQ(UART0_IRQn); + break; + case 1: + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); + NVIC_EnableIRQ(UART1_IRQn); + break; + default: + MBED_ASSERT(0); + } + + // Clear pending interrupts + obj->uart->int_fl = obj->uart->int_fl; + + // Set TX Almost Empty level to interrupt when empty + obj->uart->ctrl1 = (MXC_F_UART_THRESH_CTRL_RX_FIFO_DEFAULT_THRESH_VAL | MXC_F_UART_THRESH_CTRL_TX_FIFO_DEFAULT_THRESH_VAL); + + if (irq == RxIrq) { + // Enable RX FIFO Threshold Interrupt + if (enable) { + obj->uart->int_en |= UART_RX_IE | UART_ER_IE; + } else { + obj->uart->int_en &= ~(UART_RX_IE | UART_ER_IE); + } + } else if (irq == TxIrq) { + // Enable TX Almost Empty Interrupt + if (enable) { + //obj->uart->int_en |= MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; + obj->uart->int_en |= UART_TX_IE | UART_ER_IE; + } else { + //obj->uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; + obj->uart->int_en &= ~(UART_TX_IE | UART_ER_IE); + } + } else { + MBED_ASSERT(0); + } +} + +//****************************************************************************** +int serial_getc(serial_t *obj) +{ + int c = -1; + + if (obj->rx != NC) { + // Wait for data to be available + while( (obj->uart->stat & MXC_F_UART_STAT_RX_NUM) == 0); + c = obj->uart->fifo; + } + + return c; +} + +//****************************************************************************** +void serial_putc(serial_t *obj, int c) +{ + if (obj->tx != NC) { + // Wait for room in the FIFO without blocking interrupts. + while (MXC_UART_GetTXFIFOAvailable(obj->uart) == 0); + + //obj->uart->int_fl |= MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY; + obj->uart->fifo = (uint8_t)c; + } +} + +//****************************************************************************** +int serial_readable(serial_t *obj) +{ + unsigned int ret; + ret = MXC_UART_GetRXFIFOAvailable(obj->uart); + return ret; +} + +//****************************************************************************** +int serial_writable(serial_t *obj) +{ + return MXC_UART_GetTXFIFOAvailable(obj->uart); +} + +//****************************************************************************** +void serial_clear(serial_t *obj) +{ + // Clear the RX and TX FIFOs + MXC_UART_ClearRXFIFO(obj->uart); + MXC_UART_ClearTXFIFO(obj->uart); +} + +//****************************************************************************** +void serial_break_set(serial_t *obj) +{ + // Make sure that nothing is being sent + while ( (obj->uart->stat & MXC_F_UART_REVA_STATUS_TX_BUSY) ); + + // Configure TX to output 0 + usurp_pin(obj->tx, 0); +} + +//****************************************************************************** +void serial_break_clear(serial_t *obj) +{ + // Configure TX to output 1 + usurp_pin(obj->tx, 1); + // Return TX to UART control + serial_pinout_tx(obj->tx); +} + +//****************************************************************************** +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +//****************************************************************************** +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + + if ((FlowControlCTS == type) || (FlowControlRTSCTS == type) || (FlowControlRTS == type) || (FlowControlRTSCTS == type)) { + UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); + UARTName uart = (UARTName)pinmap_merge(uart_cts, (UARTName)obj->uart); + // Assert pin is usable with existing uart + MBED_ASSERT(uart != (UARTName)NC); + } + + MXC_UART_SetFlowCtrl (obj->uart, MXC_UART_FLOW_EN_LOW, 1); + //MBED_ASSERT(retval == E_NO_ERROR); +} + +//****************************************************************************** +static void usurp_pin(PinName pin, int state) +{ + gpio_t gpio; + gpio_init_out(&gpio, pin); + gpio_write(&gpio, state); +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32660/sleep.c new file mode 100644 index 00000000000..37dfe6eb0fc --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/sleep.c @@ -0,0 +1,86 @@ +/******************************************************************************* + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "sleep_api.h" +#include "lp.h" +#include "uart.h" + +#if 0 +static void prep_for_sleep(void) +{ + while(MXC_UART_ReadyForSleep(MXC_UART1) != E_NO_ERROR) { + ; + } + while(MXC_UART_ReadyForSleep(MXC_UART0) != E_NO_ERROR) { + ; + } +} +#else +#define prep_for_sleep() +#endif + +//****************************************************************************** +void hal_sleep(void) +{ + prep_for_sleep(); + + /* Call MXC_LP_DisableBlockDetect function if the system runs from + a single supply only and VCORE is not connected to an external supply. + Bypassing the hardware detection of an external supply on VCORE + enables a faster wakeup time. + */ + MXC_LP_DisableBlockDetect(); + + /* Switch to sleep mode */ + MXC_LP_EnterSleepMode(); +} + +void hal_deepsleep(void) +{ +#if 0 + prep_for_sleep(); + + //MXC_LP_DisableBandGap(); + //MXC_LP_DisableVCorePORSignal(); + //MXC_LP_EnableRamRetReg(); + + MXC_LP_EnableFastWk(); + MXC_LP_ClearWakeStatus(); + + MXC_LP_DisableBlockDetect(); + MXC_LP_EnterDeepSleepMode(); +#else + hal_sleep(); +#endif +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/spi_api.c new file mode 100644 index 00000000000..8894314a665 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/spi_api.c @@ -0,0 +1,339 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "mbed_assert.h" +#include "mbed_critical.h" +#include "spi_api.h" // mbed HAL + +#include "mxc_sys.h" +#include "spi_regs.h" +#include "spimss_regs.h" +#include "spimss.h" +#include "mxc_spi.h" + +#include "pinmap.h" +#include "PeripheralPins.h" + + +#define SPI_NUM_0 0 // SPI17Y +#define SPI_NUM_1A 1 // SPIMSS MAPA +#define SPI_NUM_1B 2 // SPIMSS MAPB +#define SPI_NUM_MAX 3 // + +static unsigned int spi_speed = 1000000; +static unsigned int spi_mode = 0; +static unsigned int g_drv_ssel = 1; + +static int master_send(int spi_num, void *req) +{ + int error = E_NO_ERROR; + + if (spi_num == SPI_NUM_0) { + error = MXC_SPI_MasterTransaction((mxc_spi_req_t *)req); + } else if (spi_num < SPI_NUM_MAX) { + mxc_spimss_req_t spimss_req; + mxc_spi_req_t *req_tmp = (mxc_spi_req_t *)req; + + spimss_req.ssel = req_tmp->ssIdx; /**< Not Used*/ + spimss_req.deass = req_tmp->ssDeassert; /**< Not Used*/ + spimss_req.tx_data = req_tmp->txData; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + spimss_req.rx_data = req_tmp->rxData; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + spimss_req.width = DUMMY_1; /**< Not Used */ + /**< Number of transfer units to send from the \p tx_data buffer. */ + spimss_req.len = (req_tmp->txLen > req_tmp->rxLen)? req_tmp->txLen: req_tmp->rxLen; + spimss_req.bits = 8; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + spimss_req.rx_num = req_tmp->rxCnt; /**< Number of bytes actually read into the \p rx_data buffer. */ + spimss_req.tx_num = req_tmp->txCnt; /**< Number of bytes actually sent from the \p tx_data buffer */ + spimss_req.callback = NULL; /**< Callback function if desired, NULL otherwise */ + + error = MXC_SPIMSS_MasterTrans(MXC_SPIMSS, &spimss_req); + } else { + return E_BAD_PARAM; + } + + return error; +} + +//****************************************************************************** +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Make sure pins are pointing to the same SPI instance + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + + SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + SPIName spi_cntl; + + // Control is SCK and optionaly SS + if ((SPIName)spi_ssel != (SPIName)NC) { + g_drv_ssel = 1; // Driver will drive SSEL pin + spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + } else { + g_drv_ssel = 0; // Driver will NOT drive SSEL pin + spi_cntl = spi_sclk; + } + + SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((SPIName)spi != (SPIName)NC); + + if (spi == SPI_0) { + obj->spi = MXC_SPI0; + obj->index = SPI_NUM_0; + + MXC_SPI_Init(obj->spi, 1, 0, 1, 0, spi_speed, g_drv_ssel); + MXC_SPI_SetDataSize(obj->spi, 8); + MXC_SPI_SetWidth(obj->spi, SPI_WIDTH_STANDARD); + } + else if(spi == SPI_1) { + obj->spi = (void *)MXC_SPIMSS; + + if (pinmap_function(mosi, PinMap_SPI_MOSI) == 1) { + obj->index = SPI_NUM_1A; + MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_A, g_drv_ssel); + } else { + obj->index = SPI_NUM_1B; + MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_B, g_drv_ssel); + } + } + + // Configure Slave Slect Pin if defined + if ((SPIName)spi_ssel != (SPIName)NC) { + uint32_t function = pinmap_function(ssel, PinMap_SPI_SSEL); + if (function != (uint32_t)NC) { + pin_function(ssel, function+1);// index start from 1; + pin_mode(ssel, PullNone); + } + } +} + +//****************************************************************************** +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + // Only supports master mode + MBED_ASSERT(!slave); + + spi_mode = mode; + + if (obj->index == SPI_NUM_0) { + MXC_SPI_SetDataSize(obj->spi, bits); + MXC_SPI_SetMode(obj->spi, (mxc_spi_mode_t)mode); + } + else if (obj->index < SPI_NUM_MAX) { + MXC_SPIMSS_Shutdown(obj->spi); + if (obj->index == SPI_NUM_1A) { + MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_A, g_drv_ssel); + } else { + MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_B, g_drv_ssel); + } + } +} + +////****************************************************************************** +void spi_frequency(spi_t *obj, int hz) +{ + // Maximum frequency is the PeripheralClock + MBED_ASSERT((unsigned int)hz <= PeripheralClock); + + if (obj->index == SPI_NUM_0) { + spi_speed = hz; + MXC_SPI_SetFrequency(obj->spi, spi_speed); + } + else if (obj->index < SPI_NUM_MAX) { + spi_speed = hz; + MXC_SPIMSS_Shutdown(obj->spi); + if (obj->index == SPI_NUM_1A) { + MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_A, g_drv_ssel); + } else { + MXC_SPIMSS_Init(obj->spi, spi_mode, spi_speed, MAP_B, g_drv_ssel); + } + } +} + +////****************************************************************************** +int spi_master_write(spi_t *obj, int value) +{ + mxc_spi_req_t req; + uint8_t out, in; + + // Prepare req structure for transfer + out = value; + //SPI Request + req.spi = obj->spi; + req.txData = &out; + req.rxData = ∈ + req.txLen = 1; + req.rxLen = 1; + req.ssIdx = 0; + req.ssDeassert = 1; + req.txCnt = 0; + req.rxCnt = 0; + req.completeCB = NULL; + + // Start transfer + master_send(obj->index, &req); + + return in; +} + +////****************************************************************************** +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + mxc_spi_req_t req; + + if (!(tx_length | rx_length) || + (tx_length < 0) || + (rx_length < 0)) { + return 0; + } + + req.spi = obj->spi; + req.ssIdx = 0; + req.ssDeassert = 1; + req.txCnt = 0; + req.rxCnt = 0; + req.completeCB = NULL; + + if (obj->index == SPI_NUM_0) { + MXC_SPI_SetDefaultTXData(obj->spi, write_fill); + } else { + MXC_SPIMSS_SetDefaultTXData(obj->spi, write_fill); + } + + core_util_critical_section_enter(); + if (tx_length == rx_length) { + req.txData = (uint8_t *)tx_buffer; + req.txLen = tx_length; + req.rxData = (uint8_t *)rx_buffer; + req.rxLen = rx_length; + + master_send(obj->index, &req); + } else if (tx_length < rx_length) { + if (tx_length == 0) { + req.txData = NULL; + req.txLen = 0; + req.rxData = (uint8_t *)rx_buffer; + req.rxLen = rx_length; + + master_send(obj->index, &req); + } else { + req.txData = (uint8_t *)tx_buffer; + req.txLen = tx_length; + req.rxData = (uint8_t *)rx_buffer; + req.rxLen = tx_length; + + master_send(obj->index, &req); + + req.txData = NULL; + req.txLen = 0; + req.rxData = (uint8_t *)&rx_buffer[tx_length]; + req.rxLen = rx_length-tx_length; + req.txCnt = 0; + req.rxCnt = 0; + + master_send(obj->index, &req); + } + } else { + if (rx_length == 0) { + req.txData = (uint8_t *)tx_buffer; + req.txLen = tx_length; + req.rxData = NULL; + req.rxLen = 0; + + master_send(obj->index, &req); + } else { + req.txData = (uint8_t *)tx_buffer; + req.txLen = rx_length; + req.rxData = (uint8_t *)rx_buffer; + req.rxLen = rx_length; + + master_send(obj->index, &req); + + req.txData = (uint8_t *)&tx_buffer[rx_length]; + req.txLen = tx_length-rx_length; + req.rxData = NULL; + req.rxLen = 0; + req.txCnt = 0; + req.rxCnt = 0; + + master_send(obj->index, &req); + } + } + core_util_critical_section_exit(); + + return tx_length > rx_length ? tx_length : rx_length; +} + +//****************************************************************************** +int spi_busy(spi_t *obj) +{ + if (obj->index == SPI_NUM_0) { + return (((mxc_spi_regs_t *)obj->spi)->stat & MXC_F_SPI_STAT_BUSY); + } + else if (obj->index < SPI_NUM_MAX) { + unsigned int reg = ((mxc_spimss_regs_t *)obj->spi)->int_fl; + return (reg & MXC_F_SPIMSS_INT_FL_TXST) >> MXC_F_SPIMSS_INT_FL_TXST_POS; + } + + return 1; +} + +//****************************************************************************** +uint8_t spi_get_module(spi_t *obj) +{ + return obj->index; +} + +//****************************************************************************** +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c new file mode 100644 index 00000000000..539751c609a --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/us_ticker.c @@ -0,0 +1,119 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ + +#include +#include "us_ticker_api.h" +#include "tmr.h" + +#define US_TIMER MXC_TMR1 +#define US_TIMER_IRQn TMR1_IRQn +#define US_TIMER_PRESCALE TMR_PRES_32 +#define US_TIMER_FREQ ((HIRC96_FREQ/2) >> MXC_V_TMR_CN_PRES_DIV_BY_32) +#define US_TIMER_WIDTH 32 + + +//****************************************************************************** +void us_ticker_init(void) +{ + mxc_tmr_cfg_t cfg; + unsigned int count; + + cfg.pres = US_TIMER_PRESCALE; + cfg.mode = TMR_MODE_COMPARE; + cfg.bitMode = TMR_BIT_MODE_32; + cfg.clock = MXC_TMR_HFIO_CLK; + cfg.cmp_cnt = 0;//MXC_TMR_GetCompare(US_TIMER); + cfg.pol = 0; + + // Disable and deconfigure + MXC_TMR_Shutdown(US_TIMER); + MXC_TMR_ClearFlags(US_TIMER); + + count = MXC_TMR_GetCount(US_TIMER); + + // Configure and enable + MXC_TMR_Init(US_TIMER, &cfg); + MXC_TMR_SetCount(US_TIMER, count); + MXC_TMR_Start(US_TIMER); + + // Enable interrupts + NVIC_SetVector(US_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(US_TIMER_IRQn); +} + +//****************************************************************************** +void us_ticker_free(void) +{ + MXC_TMR_Shutdown(US_TIMER); +} + +//****************************************************************************** +uint32_t us_ticker_read(void) +{ + return US_TIMER->cnt; +} + +//****************************************************************************** +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + MXC_TMR_SetCompare(US_TIMER, (timestamp) ? timestamp : 1); +} + +//****************************************************************************** +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(US_TIMER_IRQn); +} + +//****************************************************************************** +void us_ticker_disable_interrupt(void) +{ + NVIC_DisableIRQ(US_TIMER_IRQn); +} + +//****************************************************************************** +void us_ticker_clear_interrupt(void) +{ + MXC_TMR_ClearFlags(US_TIMER); +} + +//****************************************************************************** +const ticker_info_t* us_ticker_get_info(void) +{ + static const ticker_info_t info = { + US_TIMER_FREQ, + US_TIMER_WIDTH + }; + + return &info; +} diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/watchdog_api.c b/targets/TARGET_Maxim/TARGET_MAX32660/watchdog_api.c new file mode 100644 index 00000000000..d94b117a8e4 --- /dev/null +++ b/targets/TARGET_Maxim/TARGET_MAX32660/watchdog_api.c @@ -0,0 +1,117 @@ +/******************************************************************************* + * Copyright (c) Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + ******************************************************************************* + */ +#ifdef DEVICE_WATCHDOG + +#include "watchdog_api.h" +#include "mbed_error.h" + +#include "mxc_sys.h" +#include "wdt_regs.h" +#include "wdt.h" +#include "system_max32660.h" + + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + int i; + + // WDT Disable + MXC_WDT_Disable(MXC_WDT0); + + uint32_t number_of_tick = ( (float)config->timeout_ms * (float)PeripheralClock) /1000; + + // Find top bit index + for (i=31; i >= 16; i--) { + if ( number_of_tick & (1< 31) { + i = 31; // max + } else if (i < 16) { + i = 16; // min + } + + MXC_WDT_SetResetPeriod(MXC_WDT0, (mxc_wdt_period_t)(31-i) ); + + hal_watchdog_kick(); + + // WDT Enable RESET + MXC_WDT_EnableReset(MXC_WDT0); + + // WDT Enable + MXC_WDT_Enable(MXC_WDT0); + + return WATCHDOG_STATUS_OK; +} + +void hal_watchdog_kick(void) +{ + MXC_WDT0->rst = 0x00A5; + MXC_WDT0->rst = 0x005A; +} + +watchdog_status_t hal_watchdog_stop(void) +{ + MXC_WDT_Disable(MXC_WDT0); + + return WATCHDOG_STATUS_OK; +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + uint32_t rst_period = (MXC_WDT0->ctrl & MXC_F_WDT_CTRL_RST_PERIOD) >> MXC_F_WDT_CTRL_RST_PERIOD_POS; + uint32_t val = (1<<(31-rst_period)); + + return ( (float)val / (float)PeripheralClock) * 1000; +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + uint32_t max_wdt_val = 1<<31; // max val + watchdog_features_t features; + + features.max_timeout = ((float)max_wdt_val / (float)PeripheralClock)*1000; + features.update_config = true; + features.disable_watchdog = true; + features.clock_typical_frequency = PeripheralClock; + features.clock_max_frequency = PeripheralClock; + + return features; +} + +#endif // DEVICE_WATCHDOG diff --git a/targets/TARGET_Maxim/mbed_rtx.h b/targets/TARGET_Maxim/mbed_rtx.h index e0d1114f904..927ea3a7242 100644 --- a/targets/TARGET_Maxim/mbed_rtx.h +++ b/targets/TARGET_Maxim/mbed_rtx.h @@ -48,6 +48,12 @@ #define INITIAL_SP (0x20080000UL) #endif +#elif defined(TARGET_MAX32660) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20018000UL) +#endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/gpio_api.c index f357cfb0de0..a5d4216c83f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/gpio_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/gpio_api.c @@ -56,7 +56,7 @@ static gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT]; ***********/ static gpio_irq_handler m_irq_handler; -static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0}; +static uintptr_t m_channel_contexts[GPIO_PIN_COUNT] = {0}; static gpio_mask_t m_gpio_irq_enabled; @@ -68,7 +68,7 @@ static void gpiote_irq_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t acti if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) { if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise) || ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall)) { - m_irq_handler(m_channel_ids[pin], event); + m_irq_handler(m_channel_contexts[pin], event); } } } @@ -114,6 +114,7 @@ static void gpiote_pin_uninit(uint8_t pin) static void gpio_apply_config(uint8_t pin) { if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq) { + nrfx_err_t err_code = NRFX_SUCCESS; if ((m_gpio_cfg[pin].direction == PIN_INPUT) || (m_gpio_cfg[pin].used_as_irq)) { //Configure as input. @@ -135,7 +136,7 @@ static void gpio_apply_config(uint8_t pin) break; } if (m_gpio_cfg[pin].used_as_irq) { - nrfx_gpiote_in_init(pin, &cfg, gpiote_irq_handler); + err_code = nrfx_gpiote_in_init(pin, &cfg, gpiote_irq_handler); if ((m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) && (m_gpio_cfg[pin].irq_rise || m_gpio_cfg[pin].irq_fall)) { nrfx_gpiote_in_event_enable(pin, true); @@ -146,8 +147,9 @@ static void gpio_apply_config(uint8_t pin) } else { // Configure as output. nrfx_gpiote_out_config_t cfg = NRFX_GPIOTE_CONFIG_OUT_SIMPLE(nrf_gpio_pin_out_read(pin)); - nrfx_gpiote_out_init(pin, &cfg); + err_code = nrfx_gpiote_out_init(pin, &cfg); } + MBED_ASSERT(err_code != NRFX_ERROR_NO_MEM); m_gpio_initialized |= ((gpio_mask_t)1UL << pin); } else { m_gpio_initialized &= ~((gpio_mask_t)1UL << pin); @@ -193,7 +195,7 @@ void gpio_dir(gpio_t *obj, PinDirection direction) GPIO IRQ ***********/ -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -205,10 +207,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 m_gpio_cfg[pin].used_as_irq = true; m_gpio_cfg[pin].pull = PullNone; - m_channel_ids[pin] = id; + m_channel_contexts[pin] = context; obj->ch = pin; m_irq_handler = handler; - m_channel_ids[pin] = id; gpio_apply_config(pin); return 0; @@ -219,7 +220,7 @@ void gpio_irq_free(gpio_irq_t *obj) { nrfx_gpiote_in_uninit(obj->ch); m_gpio_cfg[obj->ch].used_as_irq = false; - m_channel_ids[obj->ch] = 0; + m_channel_contexts[obj->ch] = 0; gpio_apply_config(obj->ch); } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c index 7db9639f519..4f965183c6a 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c @@ -1231,9 +1231,9 @@ void serial_pinout_tx(PinName tx) * * Param obj The serial object * Param handler The interrupt handler which will be invoked when the interrupt fires - * Param id The SerialBase object + * Param context The SerialBase object */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { MBED_ASSERT(obj); @@ -1245,7 +1245,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) /* Store handler and ID in serial object. */ uart_object->handler = (uint32_t) handler; - uart_object->context = id; + uart_object->context = context; } /** Configure serial interrupt. This function is used for word-approach diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin index 3fdad3bd316..80dfd6813b0 100644 Binary files a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin and b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h index a0d2aaff606..97561f51a97 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h @@ -31,13 +31,13 @@ * 0x0010_0000 Secondary image area (2KB): * 0x0010_0000 Secure image secondary (320KB) (Dummy) * 0x0015_0000 Non-secure image secondary (576KB) (Dummy) - * 0x001E_0000 Scratch area (4KB) (Dummy) + * 0x001E_0000 Scratch area (16KB) (Dummy) * * SDH Flash: * 0x0000_0000 Secondary image area (896KB) * 0x0000_0000 Secure image secondary (320KB) * 0x0005_0000 Non-secure image secondary (576KB) - * 0x0020_0000 Scratch area (4 KB) + * 0x0020_0000 Scratch area (16 KB) * * Flash layout on M2354 with BL2 (multiple image boot): * @@ -50,12 +50,12 @@ * 0x0007_0000 Non-secure image primary slot (576KB) * 0x0010_0000 Secure image secondary slot (320KB) (Dummy) * 0x0015_0000 Non-secure image secondary slot (576KB) (Dummy) - * 0x001E_0000 Scratch area (4KB) (Dummy) + * 0x001E_0000 Scratch area (16KB) (Dummy) * * SDH Flash: * 0x0000_0000 Secure image secondary slot (320KB) * 0x0010_0000 Non-secure image secondary slot (576KB) - * 0x0020_0000 Scratch area (2 KB) + * 0x0020_0000 Scratch area (16 KB) */ /* This header file is included from linker scatter file as well, where only a @@ -123,13 +123,13 @@ #if NU_UPDATE_STAGE_SDH #define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) #define FLASH_AREA_SCRATCH_OFFSET (0x200000) -#define FLASH_AREA_SCRATCH_SIZE (0x1000) +#define FLASH_AREA_SCRATCH_SIZE (0x4000) #define FLASH_DEVICE_ID_SCRATCH SDH_FLASH_DEVICE_ID #define FLASH_DEV_NAME_SCRATCH SDH_FLASH_DEV_NAME #else #define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) #define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (0x1000) +#define FLASH_AREA_SCRATCH_SIZE (0x4000) #endif /* The maximum number of status entries supported by the bootloader. */ @@ -181,13 +181,13 @@ #if NU_UPDATE_STAGE_SDH #define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) #define FLASH_AREA_SCRATCH_OFFSET (0x200000) -#define FLASH_AREA_SCRATCH_SIZE (0x1000) +#define FLASH_AREA_SCRATCH_SIZE (0x4000) #define FLASH_DEVICE_ID_SCRATCH SDH_FLASH_DEVICE_ID #define FLASH_DEV_NAME_SCRATCH SDH_FLASH_DEV_NAME #else #define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1) #define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE) -#define FLASH_AREA_SCRATCH_SIZE (0x1000) +#define FLASH_AREA_SCRATCH_SIZE (0x4000) #endif /* The maximum number of status entries supported by the bootloader. */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf index 4c8e693f1cc..0bf99824b42 100644 Binary files a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf and b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.axf differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin index a5f9ae7f5ba..e8f3b9bf7af 100644 Binary files a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin and b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c index e0a67966885..768110a4bf0 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c @@ -79,7 +79,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -94,7 +94,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; GPIO_T *gpio_base = NU_PORT_BASE(port_index); // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c index 42ad209ad2a..9793321650a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c @@ -448,7 +448,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); @@ -458,7 +458,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c index d471893f4ae..68cebd27206 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c @@ -75,7 +75,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -90,7 +90,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; GPIO_T *gpio_base = NU_PORT_BASE(port_index); // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. diff --git a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c index aefd9673197..c194b884f41 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c @@ -388,7 +388,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); @@ -398,7 +398,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/can_api.c b/targets/TARGET_NUVOTON/TARGET_M261/can_api.c new file mode 100644 index 00000000000..fa04232ee46 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M261/can_api.c @@ -0,0 +1,344 @@ +/* mbed Microcontroller Library + * Copyright (c) 2015-2022 Nuvoton + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "can_api.h" + #include "m261_gpio.h" + #include "m261_can.h" + + #if DEVICE_CAN + #include + #include "cmsis.h" + #include "pinmap.h" + #include "PeripheralPins.h" + #include "nu_modutil.h" + #include "nu_miscutil.h" + #include "nu_bitutil.h" + #include "mbed_critical.h" + + #define NU_CAN_DEBUG 0 + #define CAN_NUM 1 + + static uintptr_t can_irq_contexts[CAN_NUM] = {0}; + static can_irq_handler can0_irq_handler; + + + static const struct nu_modinit_s can_modinit_tab[] = { + {CAN_0, CAN0_MODULE, 0, 0, CAN0_RST, CAN0_IRQn, NULL}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + + +void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) +{ + uint32_t can_td = (CANName)pinmap_peripheral(td, PinMap_CAN_TD); + uint32_t can_rd = (CANName)pinmap_peripheral(rd, PinMap_CAN_RD); + obj->can = (CANName)pinmap_merge(can_td, can_rd); + MBED_ASSERT((int)obj->can != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int)obj->can); + + obj->pin_rd = rd; + obj->pin_td = td; + + pinmap_pinout(td, PinMap_CAN_TD); + pinmap_pinout(rd, PinMap_CAN_RD); + + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + // Disable IRQ + NVIC_DisableIRQ(CAN0_IRQn); + + obj->index = 0; + + /* For M263 mbed Board Transmitter Setting (RS Pin) */ + GPIO_SetMode(PG, BIT2| BIT3, GPIO_MODE_OUTPUT); + PG2 = 0x00; + PG3 = 0x00; + + CAN_Open((CAN_T *)NU_MODBASE(obj->can), hz, CAN_NORMAL_MODE); + + can_filter(obj, 0, 0, CANStandard, 0); +} + + +void can_init(can_t *obj, PinName rd, PinName td) +{ + can_init_freq(obj, rd, td, 500000); +} + + +void can_free(can_t *obj) +{ + + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int)obj->can); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + CLK_DisableModuleClock(modinit->clkidx); + + /* Free up pins */ + gpio_set(obj->pin_rd); + gpio_set(obj->pin_td); + obj->pin_rd = NC; + obj->pin_td = NC; +} + +int can_frequency(can_t *obj, int hz) +{ + CAN_SetBaudRate((CAN_T *)NU_MODBASE(obj->can), hz); + + return CAN_GetCANBitRate((CAN_T *)NU_MODBASE(obj->can)); +} + +static void can_irq(CANName name, int id) +{ + + CAN_T *can = (CAN_T *)NU_MODBASE(name); + uint32_t u8IIDRstatus; + + u8IIDRstatus = can->IIDR; + + if(u8IIDRstatus == 0x00008000) { /* Check Status Interrupt Flag (Error status Int and Status change Int) */ + /**************************/ + /* Status Change interrupt*/ + /**************************/ + if(can->STATUS & CAN_STATUS_RXOK_Msk) { + can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/ + can0_irq_handler(can_irq_contexts[id], IRQ_RX); + } + + if(can->STATUS & CAN_STATUS_TXOK_Msk) { + can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/ + can0_irq_handler(can_irq_contexts[id], IRQ_TX); + } + + /**************************/ + /* Error Status interrupt */ + /**************************/ + if(can->STATUS & CAN_STATUS_EWARN_Msk) { + can0_irq_handler(can_irq_contexts[id], IRQ_ERROR); + } + + if(can->STATUS & CAN_STATUS_BOFF_Msk) { + can0_irq_handler(can_irq_contexts[id], IRQ_BUS); + } + } else if (u8IIDRstatus!=0) { + + can0_irq_handler(can_irq_contexts[id], IRQ_OVERRUN); + + CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1)); /* Clear Interrupt Pending */ + + } else if(can->WU_STATUS == 1) { + + can->WU_STATUS = 0; /* Write '0' to clear */ + can0_irq_handler(can_irq_contexts[id], IRQ_WAKEUP); + } +} + +void CAN0_IRQHandler(void) +{ + can_irq(CAN_0, 0); +} + +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) +{ + can0_irq_handler = handler; + can_irq_contexts[obj->index] = context; +} + +void can_irq_free(can_t *obj) +{ + CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); + + can_irq_contexts[obj->index] = 0; + + NVIC_DisableIRQ(CAN0_IRQn); +} + +void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable) +{ + CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can); + + CAN_EnterInitMode(can_base, ((enable != 0 )? CAN_CON_IE_Msk :0) ); + + + switch (irq) + { + case IRQ_ERROR: + case IRQ_BUS: + case IRQ_PASSIVE: + can_base->CON = can_base->CON |CAN_CON_EIE_Msk; + can_base->CON = can_base->CON |CAN_CON_SIE_Msk; + break; + + case IRQ_RX: + case IRQ_TX: + case IRQ_OVERRUN: + case IRQ_WAKEUP: + can_base->CON = can_base->CON |CAN_CON_SIE_Msk; + break; + + default: + break; + + } + + CAN_LeaveInitMode(can_base); + + NVIC_SetVector(CAN0_IRQn, (uint32_t)&CAN0_IRQHandler); + NVIC_EnableIRQ(CAN0_IRQn); + +} + +int can_write(can_t *obj, CAN_Message msg, int cc) +{ + STR_CANMSG_T CMsg; + + CMsg.IdType = (uint32_t)msg.format; + CMsg.FrameType = (uint32_t)!msg.type; + CMsg.Id = msg.id; + CMsg.DLC = msg.len; + memcpy((void *)&CMsg.Data[0],(const void *)&msg.data[0], (unsigned int)8); + + return CAN_Transmit((CAN_T *)NU_MODBASE(obj->can), cc, &CMsg); +} + +int can_read(can_t *obj, CAN_Message *msg, int handle) +{ + STR_CANMSG_T CMsg; + + if(!CAN_Receive((CAN_T *)NU_MODBASE(obj->can), handle, &CMsg)) + return 0; + + msg->format = (CANFormat)CMsg.IdType; + msg->type = (CANType)!CMsg.FrameType; + msg->id = CMsg.Id; + msg->len = CMsg.DLC; + memcpy(&msg->data[0], &CMsg.Data[0], 8); + + return 1; +} + +int can_mode(can_t *obj, CanMode mode) +{ + CAN_T *can_base = (CAN_T *) NU_MODBASE(obj->can); + + int success = 0; + switch (mode) + { + case MODE_RESET: + CAN_LeaveTestMode(can_base); + success = 1; + break; + + case MODE_NORMAL: + CAN_EnterTestMode(can_base, CAN_TEST_BASIC_Msk); + success = 1; + break; + + case MODE_SILENT: + CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk); + success = 1; + break; + + case MODE_TEST_LOCAL: + case MODE_TEST_GLOBAL: + CAN_EnterTestMode(can_base, CAN_TEST_LBACK_Msk); + success = 1; + break; + + case MODE_TEST_SILENT: + CAN_EnterTestMode(can_base, CAN_TEST_SILENT_Msk | CAN_TEST_LBACK_Msk); + success = 1; + break; + + default: + success = 0; + break; + + } + + + return success; +} + +int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) +{ + uint32_t numask = mask; + if( numask == 0x0000 ) + { + return CAN_SetRxMsg((CAN_T *)NU_MODBASE(obj->can), handle, (uint32_t)format, id); + } + if( format == CANStandard ) + { + numask = (mask << 18); + } + numask = (numask | CAN_IF_MASK2_MDIR_Msk | CAN_IF_MASK2_MXTD_Msk); + return CAN_SetRxMsgAndMsk((CAN_T *)NU_MODBASE(obj->can), handle, (uint32_t)format, id, numask); +} + + +void can_reset(can_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab); + + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->can); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + +} + +unsigned char can_rderror(can_t *obj) +{ + CAN_T *can = (CAN_T *)NU_MODBASE(obj->can); + return ((can->ERR>>8)&0xFF); +} + +unsigned char can_tderror(can_t *obj) +{ + CAN_T *can = (CAN_T *)NU_MODBASE(obj->can); + return ((can->ERR)&0xFF); +} + +void can_monitor(can_t *obj, int silent) +{ + CAN_EnterTestMode((CAN_T *)NU_MODBASE(obj->can), CAN_TEST_SILENT_Msk); +} + +const PinMap *can_rd_pinmap() +{ + return PinMap_CAN_TD; +} + +const PinMap *can_td_pinmap() +{ + return PinMap_CAN_RD; +} + +#endif // DEVICE_CAN diff --git a/targets/TARGET_NUVOTON/TARGET_M261/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M261/gpio_irq_api.c index b36d4ff50cf..bcb1dc2fa76 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/gpio_irq_api.c @@ -76,7 +76,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -91,7 +91,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; GPIO_T *gpio_base = NU_PORT_BASE(port_index); // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. diff --git a/targets/TARGET_NUVOTON/TARGET_M261/objects.h b/targets/TARGET_NUVOTON/TARGET_M261/objects.h index 9064b89f2be..3f65bee80ed 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M261/objects.h @@ -130,6 +130,13 @@ struct trng_s { uint8_t dummy; }; +struct can_s { + CANName can; + PinName pin_rd; + PinName pin_td; + int index; +}; + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c index a57c20204d4..524c2ef38aa 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c @@ -433,7 +433,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); @@ -443,7 +443,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/can_api.c b/targets/TARGET_NUVOTON/TARGET_M451/can_api.c index 775f98f8b07..fa2e7c2e21e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/can_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/can_api.c @@ -31,7 +31,7 @@ #define NU_CAN_DEBUG 0 #define CAN_NUM 1 - static uint32_t can_irq_ids[CAN_NUM] = {0}; + static uintptr_t can_irq_contexts[CAN_NUM] = {0}; static can_irq_handler can0_irq_handler; @@ -125,34 +125,34 @@ static void can_irq(CANName name, int id) /**************************/ if(can->STATUS & CAN_STATUS_RXOK_Msk) { can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/ - can0_irq_handler(can_irq_ids[id], IRQ_RX); + can0_irq_handler(can_irq_contexts[id], IRQ_RX); } if(can->STATUS & CAN_STATUS_TXOK_Msk) { can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/ - can0_irq_handler(can_irq_ids[id], IRQ_TX); + can0_irq_handler(can_irq_contexts[id], IRQ_TX); } /**************************/ /* Error Status interrupt */ /**************************/ if(can->STATUS & CAN_STATUS_EWARN_Msk) { - can0_irq_handler(can_irq_ids[id], IRQ_ERROR); + can0_irq_handler(can_irq_contexts[id], IRQ_ERROR); } if(can->STATUS & CAN_STATUS_BOFF_Msk) { - can0_irq_handler(can_irq_ids[id], IRQ_BUS); + can0_irq_handler(can_irq_contexts[id], IRQ_BUS); } } else if (u8IIDRstatus!=0) { - can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN); + can0_irq_handler(can_irq_contexts[id], IRQ_OVERRUN); CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1)); /* Clear Interrupt Pending */ } else if(can->WU_STATUS == 1) { can->WU_STATUS = 0; /* Write '0' to clear */ - can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP); + can0_irq_handler(can_irq_contexts[id], IRQ_WAKEUP); } } @@ -161,17 +161,17 @@ void CAN0_IRQHandler(void) can_irq(CAN_0, 0); } -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { can0_irq_handler = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } void can_irq_free(can_t *obj) { CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; NVIC_DisableIRQ(CAN0_IRQn); } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c index b6ac940dd47..5eea6a4ada2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/gpio_irq_api.c @@ -72,7 +72,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -87,7 +87,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; GPIO_T *gpio_base = NU_PORT_BASE(port_index); // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c index 7d7bce7e7a9..eed9f41f07b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c @@ -387,7 +387,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); @@ -397,7 +397,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h index 19911b9357e..9bf6d76141b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/PeripheralNames.h @@ -101,8 +101,8 @@ typedef enum { UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0), UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0), - UART_6 = (int) NU_MODNAME(UART5_BASE, 6, 0), - UART_7 = (int) NU_MODNAME(UART5_BASE, 7, 0), + UART_6 = (int) NU_MODNAME(UART6_BASE, 6, 0), + UART_7 = (int) NU_MODNAME(UART7_BASE, 7, 0), // NOTE: board-specific #if defined(MBED_CONF_TARGET_USB_UART) USB_UART = MBED_CONF_TARGET_USB_UART, diff --git a/targets/TARGET_NUVOTON/TARGET_M480/can_api.c b/targets/TARGET_NUVOTON/TARGET_M480/can_api.c index f532454ece0..771cb6d9ff8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/can_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/can_api.c @@ -34,7 +34,7 @@ #define NU_CAN_DEBUG 0 #define CAN_NUM 2 -static uint32_t can_irq_ids[CAN_NUM] = {0}; +static uintptr_t can_irq_contexts[CAN_NUM] = {0}; static can_irq_handler can0_irq_handler; static can_irq_handler can1_irq_handler; @@ -140,17 +140,17 @@ static void can_irq(CANName name, int id) if(can->STATUS & CAN_STATUS_RXOK_Msk) { can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/ if(id) - can1_irq_handler(can_irq_ids[id], IRQ_RX); + can1_irq_handler(can_irq_contexts[id], IRQ_RX); else - can0_irq_handler(can_irq_ids[id], IRQ_RX); + can0_irq_handler(can_irq_contexts[id], IRQ_RX); } if(can->STATUS & CAN_STATUS_TXOK_Msk) { can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/ if(id) - can1_irq_handler(can_irq_ids[id], IRQ_TX); + can1_irq_handler(can_irq_contexts[id], IRQ_TX); else - can0_irq_handler(can_irq_ids[id], IRQ_TX); + can0_irq_handler(can_irq_contexts[id], IRQ_TX); } @@ -159,23 +159,23 @@ static void can_irq(CANName name, int id) /**************************/ if(can->STATUS & CAN_STATUS_EWARN_Msk) { if(id) - can1_irq_handler(can_irq_ids[id], IRQ_ERROR); + can1_irq_handler(can_irq_contexts[id], IRQ_ERROR); else - can0_irq_handler(can_irq_ids[id], IRQ_ERROR); + can0_irq_handler(can_irq_contexts[id], IRQ_ERROR); } if(can->STATUS & CAN_STATUS_BOFF_Msk) { if(id) - can1_irq_handler(can_irq_ids[id], IRQ_BUS); + can1_irq_handler(can_irq_contexts[id], IRQ_BUS); else - can0_irq_handler(can_irq_ids[id], IRQ_BUS); + can0_irq_handler(can_irq_contexts[id], IRQ_BUS); } } else if (u8IIDRstatus!=0) { if(id) - can1_irq_handler(can_irq_ids[id], IRQ_OVERRUN); + can1_irq_handler(can_irq_contexts[id], IRQ_OVERRUN); else - can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN); + can0_irq_handler(can_irq_contexts[id], IRQ_OVERRUN); CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1)); /* Clear Interrupt Pending */ @@ -183,9 +183,9 @@ static void can_irq(CANName name, int id) can->WU_STATUS = 0; /* Write '0' to clear */ if(id) - can1_irq_handler(can_irq_ids[id], IRQ_WAKEUP); + can1_irq_handler(can_irq_contexts[id], IRQ_WAKEUP); else - can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP); + can0_irq_handler(can_irq_contexts[id], IRQ_WAKEUP); } } @@ -199,13 +199,13 @@ void CAN1_IRQHandler(void) can_irq(CAN_1, 1); } -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { if(obj->index) can1_irq_handler = handler; else can0_irq_handler = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } @@ -213,7 +213,7 @@ void can_irq_free(can_t *obj) { CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; if(!obj->index) NVIC_DisableIRQ(CAN0_IRQn); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c index ee05cae9cfe..0ee012f2b3b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c @@ -79,7 +79,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -94,7 +94,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; GPIO_T *gpio_base = NU_PORT_BASE(port_index); // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. diff --git a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c index fdf825a4b46..effcf4cb815 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c @@ -465,7 +465,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); @@ -475,7 +475,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c index faf8b045525..031e3b6a361 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c @@ -69,7 +69,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -84,7 +84,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; obj->next = NULL; GPIO_T *gpio_base = NU_PORT_BASE(port_index); diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c index 2da2c9d3606..e31c79cb33a 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c @@ -350,7 +350,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); @@ -360,7 +360,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.async_en = 0; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c index f4d57e4d820..7ea08e771eb 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/can_api.c @@ -31,7 +31,7 @@ #define NU_CAN_DEBUG 0 #define CAN_NUM 2 - static uint32_t can_irq_ids[CAN_NUM] = {0}; + static uintptr_t can_irq_contexts[CAN_NUM] = {0}; static can_irq_handler can0_irq_handler; static can_irq_handler can1_irq_handler; @@ -134,17 +134,17 @@ static void can_irq(CANName name, int id) if(can->STATUS & CAN_STATUS_RXOK_Msk) { can->STATUS &= ~CAN_STATUS_RXOK_Msk; /* Clear Rx Ok status*/ if(id) - can1_irq_handler(can_irq_ids[id] , IRQ_RX); + can1_irq_handler(can_irq_contexts[id] , IRQ_RX); else - can0_irq_handler(can_irq_ids[id], IRQ_RX); + can0_irq_handler(can_irq_contexts[id], IRQ_RX); } if(can->STATUS & CAN_STATUS_TXOK_Msk) { can->STATUS &= ~CAN_STATUS_TXOK_Msk; /* Clear Tx Ok status*/ if(id) - can1_irq_handler(can_irq_ids[id] , IRQ_TX); + can1_irq_handler(can_irq_contexts[id] , IRQ_TX); else - can0_irq_handler(can_irq_ids[id], IRQ_TX); + can0_irq_handler(can_irq_contexts[id], IRQ_TX); } @@ -153,23 +153,23 @@ static void can_irq(CANName name, int id) /**************************/ if(can->STATUS & CAN_STATUS_EWARN_Msk) { if(id) - can1_irq_handler(can_irq_ids[id] , IRQ_ERROR); + can1_irq_handler(can_irq_contexts[id] , IRQ_ERROR); else - can0_irq_handler(can_irq_ids[id], IRQ_ERROR); + can0_irq_handler(can_irq_contexts[id], IRQ_ERROR); } if(can->STATUS & CAN_STATUS_BOFF_Msk) { if(id) - can1_irq_handler(can_irq_ids[id] , IRQ_BUS); + can1_irq_handler(can_irq_contexts[id] , IRQ_BUS); else - can0_irq_handler(can_irq_ids[id], IRQ_BUS); + can0_irq_handler(can_irq_contexts[id], IRQ_BUS); } } else if (u8IIDRstatus!=0) { if(id) - can1_irq_handler(can_irq_ids[id] , IRQ_OVERRUN); + can1_irq_handler(can_irq_contexts[id] , IRQ_OVERRUN); else - can0_irq_handler(can_irq_ids[id], IRQ_OVERRUN); + can0_irq_handler(can_irq_contexts[id], IRQ_OVERRUN); CAN_CLR_INT_PENDING_BIT(can, ((can->IIDR) -1)); /* Clear Interrupt Pending */ @@ -177,9 +177,9 @@ static void can_irq(CANName name, int id) can->WU_STATUS = 0; /* Write '0' to clear */ if(id) - can1_irq_handler(can_irq_ids[id] , IRQ_WAKEUP); + can1_irq_handler(can_irq_contexts[id] , IRQ_WAKEUP); else - can0_irq_handler(can_irq_ids[id], IRQ_WAKEUP); + can0_irq_handler(can_irq_contexts[id], IRQ_WAKEUP); } } @@ -193,13 +193,13 @@ void CAN1_IRQHandler(void) can_irq(CAN_1, 1); } -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { if(obj->index) can1_irq_handler = handler; else can0_irq_handler = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } @@ -207,7 +207,7 @@ void can_irq_free(can_t *obj) { CAN_DisableInt((CAN_T *)NU_MODBASE(obj->can), (CAN_CON_IE_Msk|CAN_CON_SIE_Msk|CAN_CON_EIE_Msk)); - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; if(!obj->index) NVIC_DisableIRQ(CAN0_IRQn); diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c index fd5a8806073..05380708d60 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/gpio_irq_api.c @@ -78,7 +78,7 @@ static PinName gpio_irq_debounce_arr[] = { #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 #endif -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -93,7 +93,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin = pin; obj->irq_types = 0; obj->irq_handler = (uint32_t) handler; - obj->irq_id = id; + obj->irq_id = context; GPIO_T *gpio_base = NU_PORT_BASE(port_index); // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c index 6c1f8889b0c..dadb7c309b0 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c @@ -427,7 +427,7 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi #endif //DEVICE_SERIAL_FC -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { // Flush Tx FIFO. Otherwise, output data may get lost on this change. while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)))); @@ -437,7 +437,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; - obj->serial.irq_id = id; + obj->serial.irq_id = context; // Restore sync-mode vector obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; diff --git a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c index 38a8e5b81ad..2c377a16bee 100644 --- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c @@ -24,7 +24,7 @@ // PIO0_0..PIO0_11, PIO1_0..PIO1_11, PIO2_0..PIO2_11, PIO3_0..PIO3_5 #define CHANNEL_NUM 42 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; static inline int numofbits(uint32_t bits) @@ -53,15 +53,15 @@ static inline void handle_interrupt_in(uint32_t port) { if (port_reg->MIS & port_reg->IBE) { // both edge, read the level of pin if ((port_reg->DATA & port_reg->MIS) != 0) - irq_handler(channel_ids[channel], IRQ_RISE); + irq_handler(channel_contexts[channel], IRQ_RISE); else - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_contexts[channel], IRQ_FALL); } else if (port_reg->MIS & port_reg->IEV) { - irq_handler(channel_ids[channel], IRQ_RISE); + irq_handler(channel_contexts[channel], IRQ_RISE); } else { - irq_handler(channel_ids[channel], IRQ_FALL); + irq_handler(channel_contexts[channel], IRQ_FALL); } // Clear the interrupt... @@ -73,7 +73,7 @@ void gpio_irq1(void) {handle_interrupt_in(1);} void gpio_irq2(void) {handle_interrupt_in(2);} void gpio_irq3(void) {handle_interrupt_in(3);} -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { int channel; uint32_t port_num; @@ -116,14 +116,14 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // PIO3_0 - PIO3_5 : 36..41 channel = (port_num * 12) + ((pin & 0x0F00) >> PIN_SHIFT); - channel_ids[channel] = id; + channel_contexts[channel] = context; obj->ch = channel; return 0; } void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { diff --git a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c index c993f1d3f85..38be06298f9 100644 --- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/serial_api.c @@ -45,7 +45,7 @@ static const PinMap PinMap_UART_RX[] = { {NC , NC , 0x00} }; -static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; static uart_irq_handler irq_handler; int stdio_uart_inited = 0; @@ -103,7 +103,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } // serial_baud @@ -223,15 +223,15 @@ static inline void uart_irq(uint32_t iir, uint32_t index) { default: return; } - if (serial_irq_ids[index] != 0) - irq_handler(serial_irq_ids[index], irq_type); + if (serial_irq_contexts[index] != 0) + irq_handler(serial_irq_contexts[index], irq_type); } void uart0_irq() {uart_irq((LPC_UART->IIR >> 1) & 0x7, 0);} -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { diff --git a/targets/TARGET_NXP/TARGET_LPC176X/can_api.c b/targets/TARGET_NXP/TARGET_LPC176X/can_api.c index 07a7aa07b78..dde466a794a 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/can_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/can_api.c @@ -64,7 +64,7 @@ struct CANMsg { }; typedef struct CANMsg CANMsg; -static uint32_t can_irq_ids[CAN_NUM] = {0}; +static uintptr_t can_irq_contexts[CAN_NUM] = {0}; static can_irq_handler irq_handler; static uint32_t can_disable(can_t *obj) { @@ -130,18 +130,18 @@ static inline void can_irq(uint32_t icr, uint32_t index) { for(i = 0; i < 8; i++) { - if((can_irq_ids[index] != 0) && (icr & (1 << i))) + if((can_irq_contexts[index] != 0) && (icr & (1 << i))) { switch (i) { - case 0: irq_handler(can_irq_ids[index], IRQ_RX); break; - case 1: irq_handler(can_irq_ids[index], IRQ_TX); break; - case 2: irq_handler(can_irq_ids[index], IRQ_ERROR); break; - case 3: irq_handler(can_irq_ids[index], IRQ_OVERRUN); break; - case 4: irq_handler(can_irq_ids[index], IRQ_WAKEUP); break; - case 5: irq_handler(can_irq_ids[index], IRQ_PASSIVE); break; - case 6: irq_handler(can_irq_ids[index], IRQ_ARB); break; - case 7: irq_handler(can_irq_ids[index], IRQ_BUS); break; - case 8: irq_handler(can_irq_ids[index], IRQ_READY); break; + case 0: irq_handler(can_irq_contexts[index], IRQ_RX); break; + case 1: irq_handler(can_irq_contexts[index], IRQ_TX); break; + case 2: irq_handler(can_irq_contexts[index], IRQ_ERROR); break; + case 3: irq_handler(can_irq_contexts[index], IRQ_OVERRUN); break; + case 4: irq_handler(can_irq_contexts[index], IRQ_WAKEUP); break; + case 5: irq_handler(can_irq_contexts[index], IRQ_PASSIVE); break; + case 6: irq_handler(can_irq_contexts[index], IRQ_ARB); break; + case 7: irq_handler(can_irq_contexts[index], IRQ_BUS); break; + case 8: irq_handler(can_irq_contexts[index], IRQ_READY); break; } } } @@ -164,17 +164,17 @@ void can_irq_n() { } // Register CAN object's irq handler -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_handler = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } // Unregister CAN object's irq handler void can_irq_free(can_t *obj) { obj->dev->IER &= ~(1); - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; - if ((can_irq_ids[0] == 0) && (can_irq_ids[1] == 0)) { + if ((can_irq_contexts[0] == 0) && (can_irq_contexts[1] == 0)) { NVIC_DisableIRQ(CAN_IRQn); } } diff --git a/targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c index 74f7ce91920..cf7f21e6fdf 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/gpio_irq_api.c @@ -22,7 +22,7 @@ #define CHANNEL_NUM 48 -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; static void handle_interrupt_in(void) { @@ -36,8 +36,8 @@ static void handle_interrupt_in(void) { while(rise0 > 0) { //Continue as long as there are interrupts pending bitloc = 31 - __CLZ(rise0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt - if (channel_ids[bitloc] != 0) - irq_handler(channel_ids[bitloc], IRQ_RISE); //Run that interrupt + if (channel_contexts[bitloc] != 0) + irq_handler(channel_contexts[bitloc], IRQ_RISE); //Run that interrupt //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register LPC_GPIOINT->IO0IntClr = 1 << bitloc; @@ -46,8 +46,8 @@ static void handle_interrupt_in(void) { while(fall0 > 0) { //Continue as long as there are interrupts pending bitloc = 31 - __CLZ(fall0); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt - if (channel_ids[bitloc] != 0) - irq_handler(channel_ids[bitloc], IRQ_FALL); //Run that interrupt + if (channel_contexts[bitloc] != 0) + irq_handler(channel_contexts[bitloc], IRQ_FALL); //Run that interrupt //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register LPC_GPIOINT->IO0IntClr = 1 << bitloc; @@ -59,8 +59,8 @@ static void handle_interrupt_in(void) { bitloc = 31 - __CLZ(rise2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt if (bitloc < 16) //Not sure if this is actually needed - if (channel_ids[bitloc+32] != 0) - irq_handler(channel_ids[bitloc+32], IRQ_RISE); //Run that interrupt + if (channel_contexts[bitloc+32] != 0) + irq_handler(channel_contexts[bitloc+32], IRQ_RISE); //Run that interrupt //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register LPC_GPIOINT->IO2IntClr = 1 << bitloc; @@ -71,8 +71,8 @@ static void handle_interrupt_in(void) { bitloc = 31 - __CLZ(fall2); //CLZ returns number of leading zeros, 31 minus that is location of first pending interrupt if (bitloc < 16) //Not sure if this is actually needed - if (channel_ids[bitloc+32] != 0) - irq_handler(channel_ids[bitloc+32], IRQ_FALL); //Run that interrupt + if (channel_contexts[bitloc+32] != 0) + irq_handler(channel_contexts[bitloc+32], IRQ_FALL); //Run that interrupt //Both clear the interrupt with clear register, and remove it from our local copy of the interrupt pending register LPC_GPIOINT->IO2IntClr = 1 << bitloc; @@ -80,7 +80,7 @@ static void handle_interrupt_in(void) { } } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) return -1; irq_handler = handler; @@ -95,7 +95,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // put us in the interrupt table int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32; - channel_ids[index] = id; + channel_contexts[index] = context; obj->ch = index; NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in); @@ -104,7 +104,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 } void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { diff --git a/targets/TARGET_NXP/TARGET_LPC176X/serial_api.c b/targets/TARGET_NXP/TARGET_LPC176X/serial_api.c index 15358039f6c..bf5c3f2142a 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/serial_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/serial_api.c @@ -76,7 +76,7 @@ int stdio_uart_inited = 0; serial_t stdio_uart; struct serial_global_data_s { - uint32_t serial_irq_id; + uintptr_t serial_irq_context; gpio_t sw_rts, sw_cts; uint8_t count, rx_irq_set_flow, rx_irq_set_api; }; @@ -147,7 +147,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { - uart_data[obj->index].serial_irq_id = 0; + uart_data[obj->index].serial_irq_context = 0; } // serial_baud @@ -291,9 +291,9 @@ static inline void uart_irq(uint32_t iir, uint32_t index, LPC_UART_TypeDef *puar if (!uart_data[index].rx_irq_set_api) puart->IER &= ~(1 << RxIrq); } - if (uart_data[index].serial_irq_id != 0) + if (uart_data[index].serial_irq_context != 0) if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) - irq_handler(uart_data[index].serial_irq_id, irq_type); + irq_handler(uart_data[index].serial_irq_context, irq_type); } void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0, (LPC_UART_TypeDef*)LPC_UART0);} @@ -301,9 +301,9 @@ void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LP void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);} void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);} -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - uart_data[obj->index].serial_irq_id = id; + uart_data[obj->index].serial_irq_context = context; } static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c index 4b8b51f6705..bfa3f48ba44 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/gpio_irq_api.c @@ -32,7 +32,7 @@ #define IRQ_FALLING_EDGE (3) #define IRQ_EITHER_EDGE (4) -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler irq_handler; @@ -52,7 +52,7 @@ static void handle_interrupt_in(PortName port, int ch_base) for (i = 0; i < 32; i++) { if (interrupt_flags & (1 << i)) { - uint32_t id = channel_ids[ch_base + i]; + uint32_t id = channel_contexts[ch_base + i]; if (id == 0) { continue; } @@ -117,7 +117,7 @@ void gpio5_irq(void) handle_interrupt_in(Gpio5, 128); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -165,14 +165,14 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 } obj->ch = ch_base + obj->pin; - channel_ids[obj->ch] = id; + channel_contexts[obj->ch] = context; return 0; } void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c index 2b8c102d81c..cebc2ffbe19 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c @@ -28,7 +28,7 @@ #define INTERRUPT_PORTS 2 -static uint32_t channel_ids[NUMBER_OF_GPIO_INTS] = {0}; +static uintptr_t channel_contexts[NUMBER_OF_GPIO_INTS] = {0}; static gpio_irq_handler irq_handler; /* Array of PORT IRQ number. */ static const IRQn_Type pint_irqs[] = PINT_IRQS; @@ -42,24 +42,24 @@ void pint_intr_callback(pint_pin_int_t pintr, uint32_t pmatch_status) // * There is no user handler // * It is a level interrupt, not an edge interrupt if (((PINT->IST & ch_bit) == 0) || - (channel_ids[pintr] == 0) || + (channel_contexts[pintr] == 0) || (PINT->ISEL & ch_bit)) { return; } if ((PINT->IENR & ch_bit) && (PINT->RISE & ch_bit)){ - irq_handler(channel_ids[pintr], IRQ_RISE); + irq_handler(channel_contexts[pintr], IRQ_RISE); PINT->RISE = ch_bit; } if ((PINT->IENF & ch_bit) && (PINT->FALL & ch_bit)) { - irq_handler(channel_ids[pintr], IRQ_FALL); + irq_handler(channel_contexts[pintr], IRQ_FALL); PINT->FALL = ch_bit; } PINT_PinInterruptClrStatus(PINT, pintr); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { int found_free_channel = 0; int i = 0; @@ -78,8 +78,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 irq_handler = handler; for (i = 0; i < NUMBER_OF_GPIO_INTS; i++) { - if (channel_ids[i] == 0) { - channel_ids[i] = id; + if (channel_contexts[i] == 0) { + channel_contexts[i] = context; obj->ch = i; found_free_channel = 1; break; @@ -108,7 +108,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; + channel_contexts[obj->ch] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c index 4e7bfe62b00..89fb990b98e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/serial_api.c @@ -31,7 +31,7 @@ #include "clock_config.h" #include "gpio_api.h" -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_USART_COUNT] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_USART_COUNT] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static USART_Type *const uart_addrs[] = USART_BASE_PTRS; @@ -140,7 +140,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { USART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -189,12 +189,12 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b ******************************************************************************/ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_not_empty, uint32_t index) { - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty && (uart_addrs[index]->FIFOINTENSET & kUSART_TxLevelInterruptEnable)) - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); if (receive_not_empty && (uart_addrs[index]->FIFOINTENSET & kUSART_RxLevelInterruptEnable)) - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } @@ -262,10 +262,10 @@ void uart9_irq() } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c index 0af83e98d30..a1cfa603e18 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c @@ -31,7 +31,7 @@ #include "fsl_clock_config.h" /* LPUART starts from index 1 */ -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; @@ -80,7 +80,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { LPUART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -129,13 +129,13 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty) { - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); } if (receive_full) { - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } } @@ -164,10 +164,10 @@ void uart4_irq() uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/serial_api.c index c479ade934e..e4aad5cab8a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/serial_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/serial_api.c @@ -31,7 +31,7 @@ #include "clock_config.h" /* LPUART starts from index 1 */ -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; +static uintptr_t serial_irq_contexts[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; static uart_irq_handler irq_handler; /* Array of UART peripheral base address. */ static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; @@ -80,7 +80,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) void serial_free(serial_t *obj) { LPUART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + serial_irq_contexts[obj->index] = 0; } void serial_baud(serial_t *obj, int baudrate) @@ -129,13 +129,13 @@ static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); } - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { if (transmit_empty) { - irq_handler(serial_irq_ids[index], TxIrq); + irq_handler(serial_irq_contexts[index], TxIrq); } if (receive_full) { - irq_handler(serial_irq_ids[index], RxIrq); + irq_handler(serial_irq_contexts[index], RxIrq); } } } @@ -164,10 +164,10 @@ void uart4_irq() uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c index 6015146ec16..8909c5a873e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c @@ -104,7 +104,7 @@ typedef struct { } can_info_int_t; static can_irq_handler irq_handler; -static uint32_t can_irq_id[CAN_NUM]; +static uintptr_t can_irq_contexts[CAN_NUM]; static int can_initialized[CAN_NUM] = {0}; @@ -310,13 +310,13 @@ static __IO uint32_t *dmy_gaflm = &RSCAN0GAFLM0; static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00; static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10; -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_handler = handler; - can_irq_id[obj->ch] = id; + can_irq_contexts[obj->ch] = context; } void can_irq_free(can_t *obj) { - can_irq_id[obj->ch] = 0; + can_irq_contexts[obj->ch] = 0; } void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { @@ -358,7 +358,7 @@ static void can_rec_irq(uint32_t ch) { dmy_cfsts = CFSTS_TBL[ch][CAN_RECV]; *dmy_cfsts &= 0xFFFFFFF7; // Clear CFRXIF - irq_handler(can_irq_id[ch], IRQ_RX); + irq_handler(can_irq_contexts[ch], IRQ_RX); } static void can_trx_irq(uint32_t ch) { @@ -367,7 +367,7 @@ static void can_trx_irq(uint32_t ch) { dmy_cfsts = CFSTS_TBL[ch][CAN_SEND]; *dmy_cfsts &= 0xFFFFFFEF; // Clear CFTXIF - irq_handler(can_irq_id[ch], IRQ_TX); + irq_handler(can_irq_contexts[ch], IRQ_TX); } static void can_err_irq(uint32_t ch, CanIrqType type) { @@ -400,7 +400,7 @@ static void can_err_irq(uint32_t ch, CanIrqType type) { break; } if (val == 1) { - irq_handler(can_irq_id[ch], type); + irq_handler(can_irq_contexts[ch], type); } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c index 78f1893b163..37a85c21074 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c @@ -112,13 +112,13 @@ static void gpio_irq7(void) { handle_interrupt_in(7); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { int shift; if (pin == NC) return -1; obj->ch = pinmap_peripheral(pin, PinMap_IRQ); obj->pin = (int)pin ; - obj->port = (int)id ; + obj->port = (int)context ; shift = obj->ch*2; channel_obj[obj->ch] = obj; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c index ace09575e81..fdbd0cd8562 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c @@ -78,7 +78,7 @@ int stdio_uart_inited = 0; serial_t stdio_uart; struct serial_global_data_s { - uint32_t serial_irq_id; + uintptr_t serial_irq_context; gpio_t sw_rts, sw_cts; serial_t *tranferring_obj, *receiving_obj; uint32_t async_tx_callback, async_rx_callback; @@ -218,7 +218,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } void serial_free(serial_t *obj) { - uart_data[obj->serial.index].serial_irq_id = 0; + uart_data[obj->serial.index].serial_irq_context = 0; } // serial_baud @@ -344,7 +344,7 @@ static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) { } } - irq_handler(uart_data[index].serial_irq_id, TxIrq); + irq_handler(uart_data[index].serial_irq_context, TxIrq); } static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { @@ -408,7 +408,7 @@ static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) { } } - irq_handler(uart_data[index].serial_irq_id, RxIrq); + irq_handler(uart_data[index].serial_irq_context, RxIrq); } static void uart_err_irq(IRQn_Type irq_num, uint32_t index) { @@ -522,9 +522,9 @@ static void uart7_er_irq(void) { } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - uart_data[obj->serial.index].serial_irq_id = id; + uart_data[obj->serial.index].serial_irq_context = context; } static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/can_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/can_api.c index 74c70e29fe4..5dc733395dd 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/can_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/can_api.c @@ -382,17 +382,17 @@ volatile int g_normal_bitrate[CHANNEL_MAX]; volatile int g_data_bitrate[CHANNEL_MAX] = {D_CH0_BITRATE, D_CH1_BITRATE}; uint32_t rx_buf[RX_BUFFER_MAX]; static can_irq_handler irq_handler[CHANNEL_MAX] = {NULL}; -static uint32_t can_irq_id[CHANNEL_MAX] = {0}; +static uintptr_t can_irq_contexts[CHANNEL_MAX] = {0}; -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_handler[obj->ch] = handler; - can_irq_id[obj->ch] = id; + can_irq_contexts[obj->ch] = context; } void can_irq_free(can_t *obj) { - can_irq_id[obj->ch] = 0; + can_irq_contexts[obj->ch] = 0; *g_regtbl_cfcc[obj->ch][CAN_RX] &= ~CFCC_CFRXIE; *g_regtbl_cfcc[obj->ch][CAN_TX] &= ~CFCC_CFTXIE; *g_regtbl_ctr[obj->ch] &= ~(CTR_EWIE | CTR_OLIE | CTR_EPIE | CTR_ALIE | CTR_BEIE); @@ -454,13 +454,13 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) static void can_rec_irq(uint32_t ch) { *g_regtbl_cfsts[ch][CAN_RX] &= ~CFSTS_CFRXIF; - irq_handler[ch](can_irq_id[ch], IRQ_RX); + irq_handler[ch](can_irq_contexts[ch], IRQ_RX); } static void can_trx_irq(uint32_t ch) { *g_regtbl_cfsts[ch][CAN_TX] &= ~CFSTS_CFTXIF; - irq_handler[ch](can_irq_id[ch], IRQ_TX); + irq_handler[ch](can_irq_contexts[ch], IRQ_TX); } static void can_err_irq(uint32_t ch) @@ -468,32 +468,32 @@ static void can_err_irq(uint32_t ch) /* error warning */ if (*g_regtbl_erfl[ch] & ERFL_EWF) { *g_regtbl_erfl[ch] &= ~ERFL_EWF; - irq_handler[ch](can_irq_id[ch], IRQ_ERROR); + irq_handler[ch](can_irq_contexts[ch], IRQ_ERROR); } /* over load */ if (*g_regtbl_erfl[ch] & ERFL_OVLF) { *g_regtbl_erfl[ch] &= ~ERFL_OVLF; - irq_handler[ch](can_irq_id[ch], IRQ_OVERRUN); + irq_handler[ch](can_irq_contexts[ch], IRQ_OVERRUN); } /* error passive */ if (*g_regtbl_erfl[ch] & ERFL_EPF) { *g_regtbl_erfl[ch] &= ~ERFL_EPF; - irq_handler[ch](can_irq_id[ch], IRQ_PASSIVE); + irq_handler[ch](can_irq_contexts[ch], IRQ_PASSIVE); } /* arbitration lost */ if (*g_regtbl_erfl[ch] & ERFL_ALF) { *g_regtbl_erfl[ch] &= ~ERFL_ALF; - irq_handler[ch](can_irq_id[ch], IRQ_ARB); + irq_handler[ch](can_irq_contexts[ch], IRQ_ARB); } /* bus error */ if (*g_regtbl_erfl[ch] & ERFL_ALLERR) { *g_regtbl_erfl[ch] &= ~ERFL_ALLERR; *g_regtbl_erfl[ch] &= ~ERFL_BEF; - irq_handler[ch](can_irq_id[ch], IRQ_BUS); + irq_handler[ch](can_irq_contexts[ch], IRQ_BUS); } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c index d57bddbb419..cd06aadafb3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c @@ -120,7 +120,7 @@ static void gpio_irq7(void) handle_interrupt_in(7); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { int shift; if (pin == NC) { @@ -129,7 +129,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->ch = pinmap_peripheral(pin, PinMap_IRQ); obj->pin = (int)pin ; - obj->port = (int)id ; + obj->port = (int)context ; shift = obj->ch * 2; channel_obj[obj->ch] = obj; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c index fc8513c1adc..edfaf822333 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c @@ -67,7 +67,7 @@ serial_t stdio_uart; static uart_irq_handler irq_handler; struct serial_global_data_s { - uint32_t serial_irq_id; + uintptr_t serial_irq_context; gpio_t sw_rts, sw_cts; serial_t *tranferring_obj, *receiving_obj; uint32_t async_tx_callback, async_rx_callback; @@ -355,7 +355,7 @@ static void uart_tx_irq(uint32_t ch) } } - irq_handler(uart_data[ch].serial_irq_id, TxIrq); + irq_handler(uart_data[ch].serial_irq_context, TxIrq); } static void uart_rx_irq(uint32_t ch) @@ -411,7 +411,7 @@ static void uart_rx_irq(uint32_t ch) } } - irq_handler(uart_data[ch].serial_irq_id, RxIrq); + irq_handler(uart_data[ch].serial_irq_context, RxIrq); } static void uart_err_irq(uint32_t ch) @@ -506,10 +506,10 @@ static void uart4_er_irq(void) uart_err_irq(4); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - uart_data[obj->serial.ch].serial_irq_id = id; + uart_data[obj->serial.ch].serial_irq_context = context; } static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable) diff --git a/targets/TARGET_STM/PeripheralPins.h b/targets/TARGET_STM/PeripheralPins.h index fe4954068ad..56303f8bab6 100644 --- a/targets/TARGET_STM/PeripheralPins.h +++ b/targets/TARGET_STM/PeripheralPins.h @@ -34,6 +34,27 @@ #include "pinmap.h" #include "PeripheralNames.h" +#if TARGET_STM32F1 +#define AFIO_NONE 0 +#define AFIO_REMAP_SPI1_ENABLE 1 +#define AFIO_REMAP_I2C1_ENABLE 2 +#define AFIO_REMAP_USART1_ENABLE 3 +#define AFIO_REMAP_USART2_ENABLE 4 +#define AFIO_REMAP_USART3_PARTIAL 5 +#define AFIO_REMAP_TIM1_PARTIAL 6 +#define AFIO_REMAP_TIM3_PARTIAL 7 +#define AFIO_REMAP_TIM2_ENABLE 8 +#define AFIO_REMAP_TIM3_ENABLE 9 +#define AFIO_REMAP_CAN1_2 10 +#define AFIO_REMAP_TIM1_ENABLE 11 +#define AFIO_REMAP_USART3_ENABLE 12 +#define AFIO_REMAP_CAN1_3 13 +#define AFIO_REMAP_TIM2_PARTIAL_1 14 +#define AFIO_REMAP_TIM2_PARTIAL_2 15 +#define AFIO_REMAP_TIM4_ENABLE 16 +#endif + + //*** GPIO *** #if GPIO_PINMAP_READY /* If this macro is defined, then PinMap_GPIO is present in PeripheralPins.c */ diff --git a/targets/TARGET_STM/README.md b/targets/TARGET_STM/README.md index 2b6d4c56e14..11c63ad37b7 100644 --- a/targets/TARGET_STM/README.md +++ b/targets/TARGET_STM/README.md @@ -109,7 +109,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br | F3 | 1.11.2 | https://github.com/STMicroelectronics/STM32CubeF3 | | F4 | 1.26.1 | https://github.com/STMicroelectronics/STM32CubeF4 | | F7 | 1.16.1 | https://github.com/STMicroelectronics/STM32CubeF7 | -| G0 | 1.4.1 | https://github.com/STMicroelectronics/STM32CubeG0 | +| G0 | 1.5.0 | https://github.com/STMicroelectronics/STM32CubeG0 | | G4 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeG4 | | H7 | 1.9.0 | https://github.com/STMicroelectronics/STM32CubeH7 | | L0 | 1.12.0 | https://github.com/STMicroelectronics/STM32CubeL0 | @@ -118,7 +118,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br | L5 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeL5 | | U5 | 1.0.0 | https://github.com/STMicroelectronics/STM32CubeU5 | | WB | 1.11.1 | https://github.com/STMicroelectronics/STM32CubeWB | -| WL | 1.0.0 | https://github.com/STMicroelectronics/STM32CubeWL | +| WL | 1.1.0 | https://github.com/STMicroelectronics/STM32CubeWL | In Mbed OS repository, we try to minimize the difference between "official" and copied files. @@ -181,8 +181,8 @@ But also each STM32 Part Number with different FLASH size : STM32F401xC / STM32F Mbed OS porting layer specific for this family are placed here. Example in TARGET_STM32G0: -- TARGET_STM32G031xx -- TARGET_STM32G071xx +- TARGET_STM32G031x8 +- TARGET_STM32G071xB - ... Each STM32 sub-family contains: @@ -474,6 +474,14 @@ Detailed sleep Mbed OS description : https://os.mbed.com/docs/mbed-os/latest/api - debug profile is disabling deepsleep - deepsleep can also be disabled by application or drivers using sleep_manager_lock_deep_sleep() - deep-sleep-latency value is configured to 4 by default for STM32 +- trace with MBED_SLEEP_TRACING_ENABLED macro is set by default with low verbosity +``` + "target_overrides": { + "*": { + "platform.deepsleep-stats-enabled": true, + "platform.deepsleep-stats-verbose": false + }, +``` ### WiFi configuration @@ -578,6 +586,7 @@ the CAN interface. While using RxInterrupt with the CAN object the receive ISR callback registered should defer read to thread context. A simple example is as shown below: +``` #include "mbed.h" Ticker ticker; @@ -621,6 +630,7 @@ int main() { while(1) { } } +``` ## Mbed OS Wiki pages diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x6.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x6.h index c1e69f41192..7780daa3cf7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x8.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x8.h index 57d81519238..b8339f640d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x8.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030x8.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030xc.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030xc.h index 39cd541b05d..6bc5d648a3c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030xc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f030xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f031x6.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f031x6.h index 7e5310d0eaf..84b58151a75 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f031x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f031x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f038xx.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f038xx.h index ff2aa0f56b5..88f59dc7e1a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f038xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f038xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f042x6.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f042x6.h index ec1ce27287e..4458034b0d3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f042x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f042x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f048xx.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f048xx.h index 50ddb1acc74..f05ecd4f8f7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f048xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f048xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f051x8.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f051x8.h index 7b3b898d53a..fb9374a164d 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f051x8.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f051x8.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f058xx.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f058xx.h index a598585c5ae..b634fe81059 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f058xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f058xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070x6.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070x6.h index 9b132211239..8c54407fe61 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070x6.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070xb.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070xb.h index 04fdb7eb75a..18a15badf3a 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f070xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f071xb.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f071xb.h index 057c175430c..0600936c8f7 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f071xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f071xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f072xb.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f072xb.h index 64e0a42e3da..3337fdcde75 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f072xb.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f072xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f078xx.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f078xx.h index bd73ff93100..4e7ef5df591 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f078xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f078xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f091xc.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f091xc.h index 704ecf432b5..9bf4a5e6724 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f091xc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f091xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f098xx.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f098xx.h index 05f11ac43bc..d70caea9ebf 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f098xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f098xx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f0xx.h b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f0xx.h index 3361e7655b4..5a92473891f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f0xx.h +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/CMSIS/stm32f0xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F0xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * @@ -59,8 +59,8 @@ * - IRQ channel definition * - Peripheral memory mapping and physical registers address definition * - Peripheral pointer declaration and driver header file inclusion - * - Product miscellaneous configuration: assert macros - * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-familys superset. + * - Product miscellaneous configuration: assert macros, ... + * Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-family's superset. */ #if !defined (STM32F030x6) && !defined (STM32F030x8) && \ diff --git a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/STM32F0xx_HAL_Driver/stm32f0xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/STM32F0xx_HAL_Driver/stm32f0xx_hal_wwdg.c index 4eb13d7a11f..a3481d20fb3 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/STM32F0xx_HAL_Driver/stm32f0xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F0/STM32Cube_FW/STM32F0xx_HAL_Driver/stm32f0xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 48MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 85.3s + max timeout before reset: approximately 85.3us (++) Counter max (T[5;0] = 0x3F) at 48MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 43.7ms diff --git a/targets/TARGET_STM/TARGET_STM32F0/objects.h b/targets/TARGET_STM/TARGET_STM32F0/objects.h index 140b06048e8..dbdadf96263 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F0/objects.h @@ -100,8 +100,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 8bdb2d285e6..6f7d38b2038 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -27,7 +27,7 @@ #define UART_NUM (8) // max value (TARGET_STM32F091RC) #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -45,15 +45,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -128,12 +128,12 @@ static void uart3_8_irq(void) #endif } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xb.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xb.h index ab7898074d4..73fe39fbebb 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xe.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xe.h index 334c4dcca44..3c31948f34f 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xe.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f100xe.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101x6.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101x6.h index 250962dbaa4..d57f6a5dd6c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101x6.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xb.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xb.h index aa524a99030..21f7e9b62c2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xe.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xe.h index bde6d7a9fad..1af271d7121 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xe.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xe.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xg.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xg.h index 35a142d0e19..f243214f9fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xg.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f101xg.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102x6.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102x6.h index 9917ec36c4f..a7a26330702 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102x6.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102xb.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102xb.h index f5d00422680..e5d46a7f435 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f102xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103x6.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103x6.h index a48464523ca..143993b2b2c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103x6.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103x6.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xb.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xb.h index 4bd7e5d0d5a..e8f5decbd6b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xe.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xe.h index 1001fd800f3..fd60371aa1a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xe.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xe.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xg.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xg.h index f74befff761..11545c996c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xg.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f103xg.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f105xc.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f105xc.h index 74215930fd0..0dcbc4fb258 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f105xc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f105xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f107xc.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f107xc.h index 5c40b46e880..8abdaeed23e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f107xc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f107xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f1xx.h b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f1xx.h index e34cc488f76..1310e2d6068 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f1xx.h +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/CMSIS/stm32f1xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F1xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_wwdg.c index 730775bce45..ed9d08414cf 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F1/STM32Cube_FW/STM32F1xx_HAL_Driver/stm32f1xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 910s + max timeout before reset: approximately 910us (++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 58.25ms diff --git a/targets/TARGET_STM/TARGET_STM32F1/objects.h b/targets/TARGET_STM/TARGET_STM32F1/objects.h index c3610186e13..491cdd2e092 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/objects.h @@ -124,8 +124,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h index e4319321808..660403eb5c3 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/pin_device.h +++ b/targets/TARGET_STM/TARGET_STM32F1/pin_device.h @@ -32,6 +32,7 @@ #include "cmsis.h" #include "stm32f1xx_ll_gpio.h" +#include "PeripheralPins.h" extern const uint32_t ll_pin_defines[16]; @@ -58,38 +59,56 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af if (afnum > 0) { switch (afnum) { - case 1: // Remap SPI1 + case AFIO_REMAP_SPI1_ENABLE: __HAL_AFIO_REMAP_SPI1_ENABLE(); break; - case 2: // Remap I2C1 + case AFIO_REMAP_I2C1_ENABLE: __HAL_AFIO_REMAP_I2C1_ENABLE(); break; - case 3: // Remap USART1 + case AFIO_REMAP_USART1_ENABLE: __HAL_AFIO_REMAP_USART1_ENABLE(); break; - case 4: // Remap USART2 + case AFIO_REMAP_USART2_ENABLE: __HAL_AFIO_REMAP_USART2_ENABLE(); break; - case 5: // Partial Remap USART3 + case AFIO_REMAP_USART3_PARTIAL: __HAL_AFIO_REMAP_USART3_PARTIAL(); break; - case 6: // Partial Remap TIM1 + case AFIO_REMAP_TIM1_PARTIAL: __HAL_AFIO_REMAP_TIM1_PARTIAL(); break; - case 7: // Partial Remap TIM3 + case AFIO_REMAP_TIM3_PARTIAL: __HAL_AFIO_REMAP_TIM3_PARTIAL(); break; - case 8: // Full Remap TIM2 + case AFIO_REMAP_TIM2_ENABLE: __HAL_AFIO_REMAP_TIM2_ENABLE(); break; - case 9: // Full Remap TIM3 + case AFIO_REMAP_TIM3_ENABLE: __HAL_AFIO_REMAP_TIM3_ENABLE(); break; #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) - case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9 + case AFIO_REMAP_CAN1_2: __HAL_AFIO_REMAP_CAN1_2(); break; #endif + case AFIO_REMAP_TIM1_ENABLE: + __HAL_AFIO_REMAP_TIM1_ENABLE(); + break; + case AFIO_REMAP_USART3_ENABLE: + __HAL_AFIO_REMAP_USART3_ENABLE(); + break; + case AFIO_REMAP_CAN1_3: + __HAL_AFIO_REMAP_CAN1_3(); + break; + case AFIO_REMAP_TIM2_PARTIAL_1: + __HAL_AFIO_REMAP_TIM2_PARTIAL_1(); + break; + case AFIO_REMAP_TIM2_PARTIAL_2: + __HAL_AFIO_REMAP_TIM2_PARTIAL_2(); + break; + case AFIO_REMAP_TIM4_ENABLE: + __HAL_AFIO_REMAP_TIM4_ENABLE(); + break; default: break; } diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c index 6902da9672c..5027bd7e069 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c @@ -38,7 +38,7 @@ #define UART_NUM (3) #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -56,15 +56,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -112,12 +112,12 @@ static void uart5_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f205xx.h b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f205xx.h index d86312ed098..c315ffd322d 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f205xx.h +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f205xx.h @@ -7,7 +7,7 @@ * This file contains : * - Data structures and the address mapping for all peripherals * - Peripherals registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f207xx.h b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f207xx.h index b6eb4dc63df..9182ea9b56d 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f207xx.h +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f207xx.h @@ -7,7 +7,7 @@ * This file contains : * - Data structures and the address mapping for all peripherals * - Peripherals registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f215xx.h b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f215xx.h index 6c33ec98221..fa440202f00 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f215xx.h +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f215xx.h @@ -7,7 +7,7 @@ * This file contains : * - Data structures and the address mapping for all peripherals * - Peripherals registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f217xx.h b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f217xx.h index 78dc95465af..7164bb71ca4 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f217xx.h +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f217xx.h @@ -7,7 +7,7 @@ * This file contains : * - Data structures and the address mapping for all peripherals * - Peripherals registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f2xx.h b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f2xx.h index 4c26e626084..5d643dcfd9d 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f2xx.h +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/CMSIS/stm32f2xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F2xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_cryp.c index d0f654acc5c..db592056321 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_cryp.c @@ -299,7 +299,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is "don't care" in the DES or TDES modes) data type and Algorithm */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /* Reset Error Code field */ @@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeySize = pConf->KeySize; hcryp->Init.pInitVect = pConf->pInitVect; - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is "don't care" in the DES or TDES modes) data type, AlgoMode and operating mode*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE|CRYP_CR_KEYSIZE|CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); /* Process Unlocked */ diff --git a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_wwdg.c index 6850ad2535c..39846d93a54 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F2/STM32Cube_FW/STM32F2xx_HAL_Driver/stm32f2xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 30MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 136.53s + max timeout before reset: approximately 136.53us (++) Counter max (T[5;0] = 0x3F) at 30MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 69.91ms diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h index 2bbc6f5729c..e30629a09b0 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -129,8 +129,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index 04a160a9d2a..a113382510a 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -34,7 +34,7 @@ #define UART_NUM (6) -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -52,15 +52,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -129,12 +129,12 @@ static void uart8_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h index feef6ece821..69ee952c9b7 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F3xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_wwdg.c index 2180536ced1..60841890c96 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 113.78s + max timeout before reset: approximately 113.78us (++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 58.25ms diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h index 07ea93ef1df..20aed170d08 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h @@ -134,6 +134,14 @@ typedef enum { // Standardized LED and button names #define LED1 PB_3 +#define I2C_SDA D4 +#define I2C_SCL D5 + +#define SPI_SCK D10 +#define SPI_MOSI D11 +#define SPI_MISO D12 +#define SPI_CS D13 + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/CMakeLists.txt index 1c8c36a155e..d66d9eb9218 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/CMakeLists.txt @@ -23,4 +23,4 @@ target_include_directories(mbed-stm32f303xc mbed_set_linker_script(mbed-stm32f303xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32f303xc INTERFACE STM32F3) +target_link_libraries(mbed-stm32f303xc INTERFACE mbed-stm32f3) diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h index d1c76fab8f8..caaad197767 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h @@ -355,6 +355,9 @@ typedef enum { #define LED3 PB_14 // LD3 [Red] #define BUTTON1 PC_13 // USER_Btn [B1] +// USB +#define USB_PULLUP_CONTROL PG_6 // USB_Disconnect in the schematics + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c index 05873573cbe..863fb9c281a 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c @@ -93,7 +93,6 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; /* Enable HSE oscillator and activate PLL with HSE as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; @@ -120,11 +119,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } +#if DEVICE_USBDEVICE + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* Output clock on MCO1 pin(PA8) for debugging purpose */ //if (bypass == 0) @@ -144,7 +146,6 @@ uint8_t SetSysClock_PLL_HSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; /* Enable HSI oscillator and activate PLL with HSI as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; @@ -169,11 +170,14 @@ uint8_t SetSysClock_PLL_HSI(void) return 0; // FAIL } +#if DEVICE_USBDEVICE + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { return 0; // FAIL } +#endif /* Output clock on MCO1 pin(PA8) for debugging purpose */ //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz diff --git a/targets/TARGET_STM/TARGET_STM32F3/objects.h b/targets/TARGET_STM/TARGET_STM32F3/objects.h index 01d77e9aab9..d69e9e7b6fc 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F3/objects.h @@ -115,8 +115,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c index 53f66301b33..a597f6b989f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c @@ -38,7 +38,7 @@ #define UART_NUM (5) // max value #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -56,15 +56,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -112,12 +112,12 @@ static void uart5_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32F4/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/PeripheralNames.h index a7786020d8e..50e86a20e5c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/PeripheralNames.h @@ -139,7 +139,7 @@ typedef enum { #endif } PWMName; -#if DEVICE_CAN +#if CAN1_BASE typedef enum { CAN_1 = (int)CAN1_BASE, #if defined CAN2_BASE diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h index d3beea922e9..ffedae725aa 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F4xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c index efb64e596a6..23fb46ed0a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, @@ -589,7 +589,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c index 43b238a13bd..b3af317f02e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c @@ -177,7 +177,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - /*ALGODIR bit must be set to 0.*/ + /*ALGODIR bit must be set to '0'.*/ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; /* Enable the CRYP peripheral */ @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /* Select final phase & ALGODIR bit must be set to 0. */ + /* Select final phase & ALGODIR bit must be set to '0'. */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c index d1e2fa071e8..e853ba2d113 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 42MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 97.52s + max timeout before reset: approximately 97.52us (++) Counter max (T[5;0] = 0x3F) at 42MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 49.93ms diff --git a/targets/TARGET_STM/TARGET_STM32F4/objects.h b/targets/TARGET_STM/TARGET_STM32F4/objects.h index 507ca3be7a4..a71b3030b90 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F4/objects.h @@ -113,8 +113,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index a95c005262f..53b753280ab 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -29,7 +29,7 @@ #define UART_NUM (10) // max value // TARGET_STM32F413xH #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -47,15 +47,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -138,12 +138,12 @@ static void uart10_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt index 9cada3e83c6..fc81e3bd8d7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt @@ -1,6 +1,7 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_STM32F722xE EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32F746xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32F756xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32F767xI EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f722xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f722xx.h index 095ec93c68b..c19278cbb47 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f722xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f722xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f723xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f723xx.h index 68f8f34c7f8..3e3a67669eb 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f723xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f723xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f730xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f730xx.h index a97b5685d2f..ed437c8324c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f730xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f730xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f732xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f732xx.h index 946a5b9a163..408e693d1d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f732xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f732xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f733xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f733xx.h index e160c62777a..0fa6e370027 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f733xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f733xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h index 25039936b6c..1a53a6ecc9f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h index 3da6583903e..9ef24783b36 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h index 4a0cee60201..e866d160bd9 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h index 0c889c71791..70e88e09836 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h index 0dd0b24746b..c2c0a9955b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h index e89cc7d19fa..02cd114e552 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h index e11eb75b16c..1c66731ecdd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h index 4e4b2db115c..fde73de8360 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h index 2af746576ac..27f1ab9bb83 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h index 5bc217f80cb..2974b1b12c4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F7xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c index 6b9424412c5..42e52b47cfa 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, @@ -589,7 +589,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c index 5bcce352234..da73ad5dd64 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c @@ -177,7 +177,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - /*ALGODIR bit must be set to 0.*/ + /*ALGODIR bit must be set to '0'.*/ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; /* Enable the CRYP peripheral */ @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /* Select final phase & ALGODIR bit must be set to 0. */ + /* Select final phase & ALGODIR bit must be set to '0'. */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c index 4f3a9855d55..b7b0f6d504a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 54MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 75.85s + max timeout before reset: approximately 75.85us (++) Counter max (T[5;0] = 0x3F) at 54MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 38.83ms diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/CMakeLists.txt new file mode 100644 index 00000000000..45be6c9108b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/CMakeLists.txt @@ -0,0 +1,28 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TARGET_NUCLEO_F722ZE EXCLUDE_FROM_ALL) + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32f722xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32f722xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32f722xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32f722xe.sct) +endif() + +add_library(mbed-stm32f722xe INTERFACE) + +target_sources(mbed-stm32f722xe + INTERFACE + ${STARTUP_FILE} +) + +target_include_directories(mbed-stm32f722xe + INTERFACE + . +) + +mbed_set_linker_script(mbed-stm32f722xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32f722xe INTERFACE mbed-stm32f7) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/CMakeLists.txt new file mode 100644 index 00000000000..fe1a3cb6775 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-nucleo-f722ze INTERFACE) + +target_sources(mbed-nucleo-f722ze + INTERFACE + PeripheralPins.c + system_clock.c +) + +target_include_directories(mbed-nucleo-f722ze + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-f722ze INTERFACE mbed-stm32f722xe) diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PeripheralNames.h new file mode 100644 index 00000000000..a866b844553 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PeripheralNames.h @@ -0,0 +1,107 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE +} UARTName; + +#define DEVICE_SPI_COUNT 6 +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE +} CANName; + +typedef enum { + QSPI_1 = (int)QSPI_R_BASE, +} QSPIName; + +typedef enum { + USB_FS = (int)USB_OTG_FS_PERIPH_BASE, + USB_HS = (int)USB_OTG_HS_PERIPH_BASE +} USBName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PeripheralPins.c new file mode 100644 index 00000000000..f4944ad9bf2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PeripheralPins.c @@ -0,0 +1,433 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32F722Z(C-E)Tx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 + {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1 [Green] + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to LD1 [Green] + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {NC, NC, 0} +}; + +// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { +// {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, +// {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, +// {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue] + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1] + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1] + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1 [Green] + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1 [Green] + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1 [Green] + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue] + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red] + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red] + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red] + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue] + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red] + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD1 [Green] + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red] + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_VBUS + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF // Connected to USB_SOF [TP1] + {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to USB_VBUS + {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID // Connected to USB_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM // Connected to USB_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP // Connected to USB_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM // Connected to LD3 [Red] + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 // Connected to LD1 [Green] + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PinNames.h new file mode 100644 index 00000000000..b9e3e44639f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/PinNames.h @@ -0,0 +1,371 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32F746ZGTx.xml + */ + +/* MBED TARGET LIST: NUCLEO_F746ZG */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0 | ALT0, // same pin used for alternate HW + PA_0_ALT1 = PA_0 | ALT1, // same pin used for alternate HW + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_1_ALT1 = PA_1 | ALT1, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_2_ALT1 = PA_2 | ALT1, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_3_ALT1 = PA_3 | ALT1, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_2 = 0x22, + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_3 = 0x23, + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno (Rev3) pins + ARDUINO_UNO_A0 = PA_3, + ARDUINO_UNO_A1 = PC_0, + ARDUINO_UNO_A2 = PC_3, + ARDUINO_UNO_A3 = PF_3, + ARDUINO_UNO_A4 = PF_5, + ARDUINO_UNO_A5 = PF_10, + + ARDUINO_UNO_D0 = PG_9, + ARDUINO_UNO_D1 = PG_14, + ARDUINO_UNO_D2 = PF_15, + ARDUINO_UNO_D3 = PE_13, + ARDUINO_UNO_D4 = PF_14, + ARDUINO_UNO_D5 = PE_11, + ARDUINO_UNO_D6 = PE_9, + ARDUINO_UNO_D7 = PF_13, + ARDUINO_UNO_D8 = PF_12, + ARDUINO_UNO_D9 = PD_15, + ARDUINO_UNO_D10 = PD_14, + ARDUINO_UNO_D11 = PA_7, + ARDUINO_UNO_D12 = PA_6, + ARDUINO_UNO_D13 = PA_5, + ARDUINO_UNO_D14 = PB_9, + ARDUINO_UNO_D15 = PB_8, +#endif + + // Arduino extension pins + A6 = PB_1, + A7 = PC_2, + A8 = PF_4, + + D16 = PC_6, + D17 = PB_15, + D18 = PB_13, + D19 = PB_12, + D20 = PA_15, + D21 = PC_7, + D22 = PB_5, + D23 = PB_3, + D24 = PA_4, + D25 = PB_4, + D26 = PB_6, + D27 = PB_2, + D28 = PD_13, + D29 = PD_12, + D30 = PD_11, + D31 = PE_2, + D32 = PA_0, + D33 = PB_0, + D34 = PE_0, + D35 = PB_11, + D36 = PB_10, + D37 = PE_15, + D38 = PE_14, + D39 = PE_12, + D40 = PE_10, + D41 = PE_7, + D42 = PE_8, + D43 = PC_8, + D44 = PC_9, + D45 = PC_10, + D46 = PC_11, + D47 = PC_12, + D48 = PD_2, + D49 = PG_2, + D50 = PG_3, + D51 = PD_7, + D52 = PD_6, + D53 = PD_5, + D54 = PD_4, + D55 = PD_3, + D56 = PE_2, + D57 = PE_4, + D58 = PE_5, + D59 = PE_6, + D60 = PE_3, + D61 = PF_8, + D62 = PF_7, + D63 = PF_9, + D64 = PG_1, + D65 = PG_0, + D66 = PD_1, + D67 = PD_0, + D68 = PF_0, + D69 = PF_1, + D70 = PF_2, + D71 = PA_7, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PD_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PD_9, +#endif + + /**** USB FS pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + + /**** USB HS pins ****/ + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED0_ALT0 = PC_1, + SYS_TRACED0_ALT1 = PG_13, + SYS_TRACED1 = PE_4, + SYS_TRACED1_ALT0 = PC_8, + SYS_TRACED1_ALT1 = PG_14, + SYS_TRACED2 = PE_5, + SYS_TRACED2_ALT0 = PD_2, + SYS_TRACED3 = PE_6, + SYS_TRACED3_ALT0 = PC_12, + SYS_WKUP1 = PA_0, + SYS_WKUP2 = PA_2, + SYS_WKUP3 = PC_1, + SYS_WKUP4 = PC_13, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 PB_0 // LD1 [Green] +#define LED2 PB_7 // LD2 [Blue] +#define LED3 PB_14 // LD3 [Red] +#define BUTTON1 PC_13 // USER_Btn [B1] + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/system_clock.c new file mode 100644 index 00000000000..3e0f97d89f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TARGET_NUCLEO_F722ZE/system_clock.c @@ -0,0 +1,211 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2019 ARM Limited +* +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 216 + * AHBCLK (MHz) | 216 + * APB1CLK (MHz) | 54 + * APB2CLK (MHz) | 108 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32f7xx.h" +#include "mbed_error.h" + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } + + // Output clock on MCO2 pin(PC9) for debugging purpose + // Can be visualized on CN8 connector pin 4 + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct; + + // Enable power clock + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + // Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */ + } + // Warning: this configuration is for a 8 MHz xtal clock only + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Activate the OverDrive to reach the 216 MHz Frequency + if (HAL_PWREx_EnableOverDrive() != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInitStruct; + + // Enable power clock + __PWR_CLK_ENABLE(); + + // Select HSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 216; // VCO output clock = 432 MHz (2 MHz * 216) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2) + RCC_OscInitStruct.PLL.PLLQ = 9; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Activate the OverDrive to reach the 216 MHz Frequency + if (HAL_PWREx_EnableOverDrive() != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + RCC_PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_ARM/startup_stm32f722xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_ARM/startup_stm32f722xx.S new file mode 100644 index 00000000000..e48e79f3acd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_ARM/startup_stm32f722xx.S @@ -0,0 +1,403 @@ +;******************************************************************************* +;* File Name : startup_stm32f722xx.s +;* Author : MCD Application Team +;* Description : STM32F722xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2016 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +SDMMC2_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_ARM/stm32f722xe.sct b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_ARM/stm32f722xe.sct new file mode 100644 index 00000000000..a4a135d5714 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_ARM/stm32f722xe.sct @@ -0,0 +1,68 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE + +#define MBED_VECTTABLE_RAM_START (NVIC_RAM_VECTOR_ADDRESS) +#define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +#define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_CRASH_REPORT_RAM_SIZE 0x100 + +#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE + MBED_RAM1_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data + } + + RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM0_START + MBED_RAM0_SIZE - Stack_Size - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_GCC_ARM/startup_stm32f722xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_GCC_ARM/startup_stm32f722xx.S new file mode 100644 index 00000000000..962883bc696 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_GCC_ARM/startup_stm32f722xx.S @@ -0,0 +1,538 @@ +/** + ****************************************************************************** + * @file startup_stm32f722xx.s + * @author MCD Application Team + * @brief STM32F722xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_GCC_ARM/stm32f722xe.ld b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_GCC_ARM/stm32f722xe.ld new file mode 100644 index 00000000000..c9765e58f56 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_GCC_ARM/stm32f722xe.ld @@ -0,0 +1,219 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +M_CRASH_DATA_RAM_SIZE = 0x100; + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +#define MBED_VECTTABLE_RAM_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +#define MBED_RAM0_START (MBED_RAM1_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE + MBED_RAM1_SIZE - MBED_VECTTABLE_RAM_SIZE) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM0_START, LENGTH = MBED_RAM0_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .crash_data_ram : + { + . = ALIGN(8); + __CRASH_DATA_RAM__ = .; + __CRASH_DATA_RAM_START__ = .; /* Create a global symbol at data start */ + KEEP(*(.keep.crash_data_ram)) + *(.m_crash_data_ram) /* This is a user defined section */ + . += M_CRASH_DATA_RAM_SIZE; + . = ALIGN(8); + __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ + } > RAM + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_IAR/startup_stm32f722xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_IAR/startup_stm32f722xx.S new file mode 100644 index 00000000000..b0a5a61d2c2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_IAR/startup_stm32f722xx.S @@ -0,0 +1,653 @@ +;******************************************************************************** +;* File Name : startup_stm32f722xx.s +;* Author : MCD Application Team +;* Description : STM32F722xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;*

© Copyright (c) 2016 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_IAR/stm32f722xe.icf b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_IAR/stm32f722xe.icf new file mode 100644 index 00000000000..86f3039fae2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/TOOLCHAIN_IAR/stm32f722xe.icf @@ -0,0 +1,69 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = MBED_ROM_START; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = MBED_ROM_SIZE; } + +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; + +define symbol NVIC_NUM_VECTORS = 120; /* This value must match NVIC_NUM_VECTORS in ../cmsis_nvic.h */ +define symbol MBED_VECTTABLE_RAM_SIZE = ((NVIC_NUM_VECTORS * 4) + 7) & ~7; +define symbol M_CRASH_DATA_RAM_SIZE = 0x100; + +define symbol __NVIC_start__ = MBED_RAM1_START; +define symbol __region_CRASH_DATA_RAM_start__ = MBED_RAM1_START + MBED_VECTTABLE_RAM_SIZE; +define symbol __NVIC_end__ = __region_CRASH_DATA_RAM_start__ - 1; +define symbol __region_RAM_start__ = __region_CRASH_DATA_RAM_start__ + M_CRASH_DATA_RAM_SIZE; +define symbol __region_CRASH_DATA_RAM_end__ = __region_RAM_start__ - 1; +define symbol __region_RAM_end__ = MBED_RAM1_START + MBED_RAM_SIZE + MBED_RAM1_SIZE - 1; + +define symbol __region_ITCMRAM_start__ = 0x00000000; +define symbol __region_ITCMRAM_end__ = 0x00003FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define region ITCMRAM_region = mem:[from __region_ITCMRAM_start__ to __region_ITCMRAM_end__]; + +/* Define Crash Data Symbols */ +define exported symbol __CRASH_DATA_RAM_START__ = __region_CRASH_DATA_RAM_start__; +define exported symbol __CRASH_DATA_RAM_END__ = __region_CRASH_DATA_RAM_end__; + +/* Stack and Heap */ +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} +define symbol __size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; +define symbol __size_heap__ = 0x13000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/cmsis_nvic.h new file mode 100644 index 00000000000..31c3c8c1124 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/cmsis_nvic.h @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20010000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x30000 // 192 KB +#endif + +#if !defined(MBED_RAM1_START) +#define MBED_RAM1_START 0x20000000 +#endif + +#if !defined(MBED_RAM1_SIZE) +#define MBED_RAM1_SIZE 0x10000 // 64 KB +#endif + +#define NVIC_NUM_VECTORS 120 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM1_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/flash_data.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/flash_data.h new file mode 100644 index 00000000000..8a7d60d73f2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F722xE/flash_data.h @@ -0,0 +1,50 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +// #include "device.h" +// #include + +#if DEVICE_FLASH + +#define FLASH_SIZE 0x80000 + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c index 48d661bf10c..71948f34ef7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/PeripheralPins.c @@ -523,8 +523,8 @@ MBED_WEAK const PinMap PinMap_USB_HS[] = { {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 // Connected to ULPI_D5 [USB3320C-EZK_D5] {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 // Connected to ULPI_D6 [USB3320C-EZK_D6] {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP // Connected to ULPI_STP [USB3320C-EZK_STP] - {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR // Connected to ARD_A2 - {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT +// {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR // Connected to ARD_A2 +// {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT // Connected to ULPI_NXT [USB3320C-EZK_NXT] {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR // Connected to ULPI_DIR [USB3320C-EZK_DIR] #endif /* MBED_CONF_TARGET_USB_SPEED */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c index e21b042779a..e7da2142f4f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c @@ -188,8 +188,9 @@ uint32_t flash_get_size(const flash_t *obj) static uint32_t GetSector(uint32_t address) { uint32_t sector = 0; - uint32_t tmp = address - ADDR_FLASH_SECTOR_0; + #if (MBED_CONF_TARGET_FLASH_DUAL_BANK) && defined(FLASH_OPTCR_nDBANK) + uint32_t tmp = address - ADDR_FLASH_SECTOR_0; if (address < ADDR_FLASH_SECTOR_4) { // Sectors 0 to 3 sector += tmp >> 14; } else if (address < ADDR_FLASH_SECTOR_5) { // Sector 4 @@ -206,13 +207,37 @@ static uint32_t GetSector(uint32_t address) sector += 16 + (tmp >> 17); } #else // SINGLE BANK - if (address < ADDR_FLASH_SECTOR_4) { // Sectors 0 to 3 - sector += tmp >> 15; - } else if (address < ADDR_FLASH_SECTOR_5) { // Sector 4 - sector += FLASH_SECTOR_4; - } else { // Sectors 5 to 11 - sector += 4 + (tmp >> 18); + if (address < ADDR_FLASH_SECTOR_1) { + sector = 0; + } else if (address < ADDR_FLASH_SECTOR_2) { + sector = 1; + } else if (address < ADDR_FLASH_SECTOR_3) { + sector = 2; + } else if (address < ADDR_FLASH_SECTOR_4) { + sector = 3; + } else if (address < ADDR_FLASH_SECTOR_5) { + sector = 4; + } else if (address < ADDR_FLASH_SECTOR_6) { + sector = 5; + } else if (address < ADDR_FLASH_SECTOR_7) { + sector = 6; +#if defined (ADDR_FLASH_SECTOR_8) + } else if (address < ADDR_FLASH_SECTOR_8) { + sector = 7; + } else if (address < ADDR_FLASH_SECTOR_9) { + sector = 8; + } else if (address < ADDR_FLASH_SECTOR_10) { + sector = 9; + } else if (address < ADDR_FLASH_SECTOR_11) { + sector = 10; + } else { + sector = 11; + } +#else + } else { + sector = 7; } +#endif #endif return sector; } @@ -239,11 +264,11 @@ static uint32_t GetSectorSize(uint32_t Sector) #else // SINGLE BANK if ((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || \ (Sector == FLASH_SECTOR_2) || (Sector == FLASH_SECTOR_3)) { - sectorsize = 32 * 1024; + sectorsize = ADDR_FLASH_SECTOR_1 - ADDR_FLASH_SECTOR_0; } else if (Sector == FLASH_SECTOR_4) { - sectorsize = 128 * 1024; + sectorsize = ADDR_FLASH_SECTOR_5 - ADDR_FLASH_SECTOR_4; } else { - sectorsize = 256 * 1024; + sectorsize = ADDR_FLASH_SECTOR_7 - ADDR_FLASH_SECTOR_6; } #endif return sectorsize; diff --git a/targets/TARGET_STM/TARGET_STM32F7/objects.h b/targets/TARGET_STM/TARGET_STM32F7/objects.h index d49ab8c1c62..ef8dc2919e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F7/objects.h @@ -131,8 +131,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c index 45e40dff385..002a861c9ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c @@ -33,7 +33,7 @@ #include "serial_api_hal.h" #define UART_NUM (8) -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -51,15 +51,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -128,12 +128,12 @@ static void uart8_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32F7/spi_api.c b/targets/TARGET_STM/TARGET_STM32F7/spi_api.c index f7c8cdbc2cb..dd636b2ba73 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/spi_api.c @@ -58,7 +58,9 @@ int spi_get_clock_freq(spi_t *obj) case SPI_1: case SPI_4: case SPI_5: + #if defined SPI6_BASE case SPI_6: + #endif // defined SPI6_BASE /* SPI_1, SPI_4, SPI_5 and SPI_6. Source CLK is PCKL2 */ spi_hz = HAL_RCC_GetPCLK2Freq(); break; diff --git a/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt index 6fabba85b54..5b92d4b8a9e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt @@ -1,16 +1,29 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(TARGET_STM32G030xx EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_STM32G031xx EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_STM32G041xx EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_STM32G070xx EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_STM32G071xx EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_STM32G081xx EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G030x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G031x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G041x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G050x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G051x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G061x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G070xB EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G071xB EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G081xB EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G0B0xE EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G0B1xE EXCLUDE_FROM_ALL) + +add_subdirectory(TARGET_STM32G0C1xE EXCLUDE_FROM_ALL) + add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL) add_library(mbed-stm32g0 INTERFACE) +target_include_directories(mbed-stm32g0 + INTERFACE + . +) + target_sources(mbed-stm32g0 INTERFACE analogin_device.c @@ -23,9 +36,4 @@ target_sources(mbed-stm32g0 spi_api.c ) -target_include_directories(mbed-stm32g0 - INTERFACE - . -) - target_link_libraries(mbed-stm32g0 INTERFACE mbed-stm mbed-stm32g0cube-fw) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32G0/PeripheralNames.h similarity index 57% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32G0/PeripheralNames.h index bc233aebf18..4757de2f417 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32G0/PeripheralNames.h @@ -22,42 +22,87 @@ extern "C" { #endif typedef enum { - ADC_1 = (int)ADC1_BASE + ADC_1 = (int)ADC1_BASE, } ADCName; +#if defined DAC_BASE typedef enum { - DAC_1 = (int)DAC_BASE + DAC_1 = (int)DAC_BASE, } DACName; +#endif typedef enum { UART_1 = (int)USART1_BASE, UART_2 = (int)USART2_BASE, +#if defined USART3_BASE UART_3 = (int)USART3_BASE, +#endif +#if defined USART4_BASE UART_4 = (int)USART4_BASE, - LPUART_1 = (int)LPUART1_BASE +#endif +#if defined USART5_BASE + UART_5 = (int)USART5_BASE, +#endif +#if defined USART6_BASE + UART_6 = (int)USART6_BASE, +#endif +#if defined LPUART1_BASE + LPUART_1 = (int)LPUART1_BASE, +#endif +#if defined LPUART2_BASE + LPUART_2 = (int)LPUART2_BASE, +#endif } UARTName; #define DEVICE_SPI_COUNT 2 typedef enum { SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE + SPI_2 = (int)SPI2_BASE, +#if defined SPI3_BASE + SPI_3 = (int)SPI3_BASE, +#endif } SPIName; typedef enum { I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE + I2C_2 = (int)I2C2_BASE, +#if defined I2C3_BASE + I2C_3 = (int)I2C3_BASE, +#endif } I2CName; typedef enum { PWM_1 = (int)TIM1_BASE, +#if defined TIM2_BASE PWM_2 = (int)TIM2_BASE, +#endif PWM_3 = (int)TIM3_BASE, +#if defined TIM4_BASE + PWM_4 = (int)TIM4_BASE, +#endif PWM_14 = (int)TIM14_BASE, +#if defined TIM15_BASE PWM_15 = (int)TIM15_BASE, +#endif PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE + PWM_17 = (int)TIM17_BASE, } PWMName; +#if defined FDCAN1_BASE +typedef enum { + CAN_1 = (int)FDCAN1_BASE, +#if defined FDCAN2_BASE + CAN_2 = (int)FDCAN2_BASE, +#endif +} CANName; +#endif + +#if defined USB_BASE +typedef enum { + USB_FS = (int)USB_BASE +} USBName; +#endif + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/LICENSE.txt b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..872e82b4670 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g030xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g030xx.h index eeb9463a15b..0ec6489d986 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g030xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g030xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -521,6 +519,7 @@ typedef struct #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ #define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) + /*!< Peripheral memory map */ #define APBPERIPH_BASE (PERIPH_BASE) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) @@ -661,6 +660,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -784,7 +792,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1591,7 +1599,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ @@ -2287,92 +2294,92 @@ typedef struct /******************* Bits definition for FLASH_CR register ******************/ #define FLASH_CR_PG_Pos (0U) -#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ #define FLASH_CR_PG FLASH_CR_PG_Msk #define FLASH_CR_PER_Pos (1U) -#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ #define FLASH_CR_PER FLASH_CR_PER_Msk #define FLASH_CR_MER1_Pos (2U) -#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ #define FLASH_CR_MER1 FLASH_CR_MER1_Msk #define FLASH_CR_PNB_Pos (3U) -#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */ +#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */ #define FLASH_CR_PNB FLASH_CR_PNB_Msk #define FLASH_CR_STRT_Pos (16U) -#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ #define FLASH_CR_STRT FLASH_CR_STRT_Msk #define FLASH_CR_OPTSTRT_Pos (17U) -#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk #define FLASH_CR_FSTPG_Pos (18U) -#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk #define FLASH_CR_EOPIE_Pos (24U) -#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk #define FLASH_CR_ERRIE_Pos (25U) -#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_OBL_LAUNCH_Pos (27U) #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk #define FLASH_CR_OPTLOCK_Pos (30U) -#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk #define FLASH_CR_LOCK_Pos (31U) -#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /******************* Bits definition for FLASH_ECCR register ****************/ #define FLASH_ECCR_ADDR_ECC_Pos (0U) -#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk #define FLASH_ECCR_SYSF_ECC_Pos (20U) -#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk #define FLASH_ECCR_ECCCIE_Pos (24U) -#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ #define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk #define FLASH_ECCR_ECCC_Pos (30U) -#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk #define FLASH_ECCR_ECCD_Pos (31U) -#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /******************* Bits definition for FLASH_OPTR register ****************/ #define FLASH_OPTR_RDP_Pos (0U) -#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk #define FLASH_OPTR_nRST_STOP_Pos (13U) -#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk #define FLASH_OPTR_nRST_STDBY_Pos (14U) -#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk #define FLASH_OPTR_IWDG_SW_Pos (16U) -#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk #define FLASH_OPTR_IWDG_STOP_Pos (17U) -#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk #define FLASH_OPTR_IWDG_STDBY_Pos (18U) -#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk #define FLASH_OPTR_WWDG_SW_Pos (19U) -#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk #define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) #define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ #define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk #define FLASH_OPTR_nBOOT_SEL_Pos (24U) -#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ #define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk #define FLASH_OPTR_nBOOT1_Pos (25U) -#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk #define FLASH_OPTR_nBOOT0_Pos (26U) -#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /****************** Bits definition for FLASH_WRP1AR register ***************/ @@ -3942,7 +3949,6 @@ typedef struct #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */ #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */ - /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (8U) #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */ @@ -5566,9 +5572,9 @@ typedef struct #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) -#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ @@ -6429,7 +6435,7 @@ typedef struct /******************* Bit definition for TIM_TISEL register *********************/ #define TIM_TISEL_TI1SEL_Pos (0U) #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ -#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!
© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -150,6 +148,8 @@ typedef struct } ADC_Common_TypeDef; + + /** * @brief CRC calculation unit */ @@ -552,6 +552,7 @@ typedef struct #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ #define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) + /*!< Peripheral memory map */ #define APBPERIPH_BASE (PERIPH_BASE) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) @@ -702,6 +703,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -825,7 +835,7 @@ typedef struct #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ @@ -1632,7 +1642,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ @@ -2422,88 +2431,88 @@ typedef struct #define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk #define FLASH_ECCR_SYSF_ECC_Pos (20U) -#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk #define FLASH_ECCR_ECCCIE_Pos (24U) -#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ #define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk #define FLASH_ECCR_ECCC_Pos (30U) -#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk #define FLASH_ECCR_ECCD_Pos (31U) -#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /******************* Bits definition for FLASH_OPTR register ****************/ #define FLASH_OPTR_RDP_Pos (0U) -#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk #define FLASH_OPTR_BOR_EN_Pos (8U) -#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ #define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk #define FLASH_OPTR_BORR_LEV_Pos (9U) -#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ #define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk -#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ -#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ #define FLASH_OPTR_BORF_LEV_Pos (11U) -#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ #define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk -#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ -#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ #define FLASH_OPTR_nRST_STOP_Pos (13U) -#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk #define FLASH_OPTR_nRST_STDBY_Pos (14U) -#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk #define FLASH_OPTR_nRST_SHDW_Pos (15U) -#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */ #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk #define FLASH_OPTR_IWDG_SW_Pos (16U) -#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk #define FLASH_OPTR_IWDG_STOP_Pos (17U) -#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk #define FLASH_OPTR_IWDG_STDBY_Pos (18U) -#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk #define FLASH_OPTR_WWDG_SW_Pos (19U) -#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk #define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) #define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ #define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk #define FLASH_OPTR_nBOOT_SEL_Pos (24U) -#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ #define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk #define FLASH_OPTR_nBOOT1_Pos (25U) -#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk #define FLASH_OPTR_nBOOT0_Pos (26U) -#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk #define FLASH_OPTR_NRST_MODE_Pos (27U) -#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ +#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */ #define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk -#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ -#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */ #define FLASH_OPTR_IRHEN_Pos (29U) -#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */ #define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk /****************** Bits definition for FLASH_PCROP1ASR register ************/ #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) -#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ #define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /****************** Bits definition for FLASH_PCROP1AER register ************/ #define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) -#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ #define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk #define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) -#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ +#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ #define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /****************** Bits definition for FLASH_WRP1AR register ***************/ @@ -2524,12 +2533,12 @@ typedef struct /****************** Bits definition for FLASH_PCROP1BSR register ************/ #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) -#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ #define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /****************** Bits definition for FLASH_PCROP1BER register ************/ #define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) -#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ #define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk @@ -5815,8 +5824,8 @@ typedef struct #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) -#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ @@ -6703,7 +6712,7 @@ typedef struct /******************* Bit definition for TIM_TISEL register *********************/ #define TIM_TISEL_TI1SEL_Pos (0U) #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */ -#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!
© Copyright (c) 2021 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -596,6 +594,7 @@ typedef struct #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */ #define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U) + /*!< Peripheral memory map */ #define APBPERIPH_BASE (PERIPH_BASE) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) @@ -751,6 +750,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -1870,7 +1878,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g050xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g050xx.h index c39b1b9d01e..73e63a16956 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g050xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g050xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -681,6 +679,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -1611,7 +1618,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g051xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g051xx.h index 063f5c72cb9..ed85d2ba4db 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g051xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g051xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -768,6 +766,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -1929,7 +1936,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g061xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g061xx.h index dc0a900ea45..d252527987e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g061xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g061xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -815,6 +813,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2165,7 +2172,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g070xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g070xx.h index 22ee5dfd752..882e210122c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g070xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g070xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -684,6 +682,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -1614,7 +1621,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g071xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g071xx.h index 0e6540d8920..e50300d3a72 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g071xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g071xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -821,6 +819,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2119,7 +2126,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g081xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g081xx.h index 1e617738329..3282955f776 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g081xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g081xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -868,6 +866,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2355,7 +2362,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b0xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b0xx.h index b488366a6c0..3f1b831c0f1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b0xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b0xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -770,6 +768,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -1700,12 +1707,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ -#define DMAMUX_CxCR_DMAREQ_ID_8 (0x100UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000100 */ -#define DMAMUX_CxCR_DMAREQ_ID_9 (0x200UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000200 */ -#define DMAMUX_CxCR_DMAREQ_ID_10 (0x400UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000400 */ -#define DMAMUX_CxCR_DMAREQ_ID_11 (0x800UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000800 */ -#define DMAMUX_CxCR_DMAREQ_ID_12 (0x1000UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00001000 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b1xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b1xx.h index dd1981c0d2d..48d15716eec 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b1xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0b1xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -992,6 +990,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2388,12 +2395,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ -#define DMAMUX_CxCR_DMAREQ_ID_8 (0x100UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000100 */ -#define DMAMUX_CxCR_DMAREQ_ID_9 (0x200UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000200 */ -#define DMAMUX_CxCR_DMAREQ_ID_10 (0x400UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000400 */ -#define DMAMUX_CxCR_DMAREQ_ID_11 (0x800UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000800 */ -#define DMAMUX_CxCR_DMAREQ_ID_12 (0x1000UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00001000 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0c1xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0c1xx.h index 7c7fbb47196..b3ffee04a52 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0c1xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0c1xx.h @@ -14,17 +14,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS_Device * @{ */ @@ -1039,6 +1037,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2624,12 +2631,6 @@ typedef struct #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ -#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ -#define DMAMUX_CxCR_DMAREQ_ID_8 (0x100UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000100 */ -#define DMAMUX_CxCR_DMAREQ_ID_9 (0x200UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000200 */ -#define DMAMUX_CxCR_DMAREQ_ID_10 (0x400UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000400 */ -#define DMAMUX_CxCR_DMAREQ_ID_11 (0x800UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000800 */ -#define DMAMUX_CxCR_DMAREQ_ID_12 (0x1000UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00001000 */ #define DMAMUX_CxCR_SOIE_Pos (8U) #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0xx.h index 6235a0f493e..bd1302d336d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/stm32g0xx.h @@ -16,17 +16,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -92,7 +90,7 @@ */ #define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ @@ -183,6 +181,46 @@ typedef enum #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) +/* Use of interrupt control for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + SET_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + CLEAR_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \ + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + /*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/system_stm32g0xx.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/system_stm32g0xx.h index 78bacc40a28..0d2dad6917b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/system_stm32g0xx.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMSIS/system_stm32g0xx.h @@ -6,17 +6,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMakeLists.txt index 54e97666794..651b4eb03f2 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/CMakeLists.txt @@ -43,6 +43,7 @@ target_sources(mbed-stm32g0cube-fw STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.c STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.c STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.c + STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.c STM32G0xx_HAL_Driver/stm32g0xx_hal_spi.c STM32G0xx_HAL_Driver/stm32g0xx_hal_spi_ex.c STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.c diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/License.md b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/License.md new file mode 100644 index 00000000000..d2ca26da6d8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/License.md @@ -0,0 +1,3 @@ +# Copyright (c) 2018 STMicroelectronics + +This software component is licensed by STMicroelectronics under the **BSD 3-Clause** license. You may not use this file except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/Legacy/stm32_hal_legacy.h index cf0b41f1e3b..5057a2d47e3 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -23,7 +23,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,6 +38,14 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ /** * @} */ @@ -210,6 +218,18 @@ * @} */ +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif +/** + * @} + */ + /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ @@ -235,7 +255,7 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -382,7 +402,6 @@ #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ - /** * @} */ @@ -470,15 +489,24 @@ #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ /** * @} @@ -521,6 +549,7 @@ #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -595,24 +624,24 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 @@ -773,49 +802,6 @@ #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U @@ -895,7 +881,11 @@ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#endif /* STM32U5 */ /** * @} */ @@ -968,6 +958,11 @@ #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -979,15 +974,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -1022,7 +1017,7 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ @@ -1122,16 +1117,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1417,6 +1412,20 @@ */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1435,6 +1444,16 @@ * @} */ +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -1494,7 +1513,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1502,7 +1522,8 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode @@ -1525,9 +1546,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1537,7 +1558,8 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT @@ -1562,9 +1584,9 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ @@ -1619,9 +1641,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1870,15 +1892,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -2089,8 +2111,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -2146,7 +2168,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2283,7 +2305,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3251,7 +3274,7 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3363,7 +3386,20 @@ #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#endif /** * @} */ @@ -3380,7 +3416,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3400,19 +3436,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3437,13 +3473,17 @@ * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3596,6 +3636,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal.c index eb3ab8f9461..e2208fa34d1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal.c @@ -57,7 +57,7 @@ */ #define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ -#define __STM32G0xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32G0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ #define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.c index b732a5447cb..a4c205312a0 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.c @@ -19,6 +19,18 @@ * Other functions (extended functions) are available in file * "stm32g0xx_hal_adc_ex.c". * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** @verbatim ============================================================================== ##### ADC peripheral features ##### @@ -275,17 +287,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -415,7 +416,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - + if (hadc->Init.OversamplingMode == ENABLE) + { + assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); + } assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) @@ -475,7 +481,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -530,7 +536,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* function on the fly (update of a parameter of ADC_InitTypeDef */ /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ - /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* - internal measurement paths (VrefInt, ...) */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ @@ -539,15 +545,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) hadc->Init.Resolution); tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode | hadc->Init.TriggerFrequencyMode ); if (hadc->Init.OversamplingMode == ENABLE) { - SET_BIT(tmpCFGR2, ADC_CFGR2_OVSE); + tmpCFGR2 |= (ADC_CFGR2_OVSE | + (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode + ); } MODIFY_REG(hadc->Instance->CFGR2, @@ -747,7 +755,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_ERROR; } - /* Return function status */ return tmp_hal_status; } @@ -763,9 +770,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) * bypassed without error reporting: it can be the intended behavior in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. - * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents - * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ @@ -857,12 +861,10 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ /* forced to a similar state after device power-on. */ - /* If needed, copy-paste and uncomment the following reset code into */ - /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ - /* */ - /* __HAL_RCC_ADC1_FORCE_RESET() */ - /* __HAL_RCC_ADC1_RELEASE_RESET() */ - + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { @@ -885,10 +887,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1191,7 +1191,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ @@ -1229,7 +1228,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } } @@ -1238,7 +1236,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1258,7 +1255,6 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC group regular */ @@ -1280,10 +1276,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1308,7 +1302,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; - uint32_t tmp_Flag_End; + uint32_t tmp_flag_end; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1316,7 +1310,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { - tmp_Flag_End = ADC_FLAG_EOS; + tmp_flag_end = ADC_FLAG_EOS; } /* If end of conversion selected to end of unitary conversion */ else /* ADC_EOC_SINGLE_CONV */ @@ -1336,7 +1330,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti } else { - tmp_Flag_End = (ADC_FLAG_EOC); + tmp_flag_end = (ADC_FLAG_EOC); } } @@ -1344,20 +1338,23 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1451,13 +1448,16 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1569,7 +1569,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ @@ -1632,7 +1631,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } @@ -1642,7 +1640,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1660,7 +1657,6 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC group regular */ @@ -1686,10 +1682,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1713,7 +1707,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - /* Process locked */ __HAL_LOCK(hadc); /* Specific case for first call occurrence of this function (DMA transfer */ @@ -1790,7 +1783,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1808,7 +1800,6 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential ADC group regular conversion on going */ @@ -1859,10 +1850,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2099,7 +2088,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* ========== Check channel configuration ready flag ========== */ if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY)) { - /* Level out of window 1 callback */ + /* Channel configuration ready callback */ HAL_ADCEx_ChannelConfigReadyCallback(hadc); /* Clear ADC analog watchdog flag */ @@ -2207,10 +2196,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". * @param hadc ADC handle - * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_config_internal_channel; @@ -2218,22 +2207,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime)); + assert_param(IS_ADC_CHANNEL(pConfig->Channel)); + assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime)); if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) { - assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank)); + assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank)); } else { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); } - /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ @@ -2251,7 +2239,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Otherwise (sequencer set to fully configurable or to to not fully */ /* configurable with channel rank to be set), configure the selected */ /* channel. */ - if (sConfig->Rank != ADC_RANK_NONE) + if (pConfig->Rank != ADC_RANK_NONE) { /* Regular sequence configuration */ /* Note: ADC channel configuration requires few ADC clock cycles */ @@ -2264,7 +2252,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* Sequencer set to not fully configurable: */ /* Set the channel by enabling the corresponding bitfield. */ - LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel); + LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel); } else { @@ -2273,21 +2261,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Memorize the channel set into variable in HAL ADC handle */ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, - ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL), - __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL)); + ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL), + __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL)); /* If the selected rank is below ADC group regular sequencer length, */ /* apply the configuration in ADC register. */ /* Note: Otherwise, configuration is not applied. */ /* To apply it, parameter'NbrOfConversion' must be increased. */ - if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) + if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) { - LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); } } /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths enable: If internal channel selected, */ @@ -2295,13 +2283,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), @@ -2312,18 +2300,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } - else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } - else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && + else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), @@ -2347,27 +2335,27 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* Sequencer set to not fully configurable: */ /* Reset the channel by disabling the corresponding bitfield. */ - LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel); + LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); } - else if (sConfig->Channel == ADC_CHANNEL_VBAT) + else if (pConfig->Channel == ADC_CHANNEL_VBAT) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel); } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + else if (pConfig->Channel == ADC_CHANNEL_VREFINT) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); @@ -2391,10 +2379,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2417,24 +2403,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; + uint32_t tmp_awd_high_threshold_shifted; + uint32_t tmp_awd_low_threshold_shifted; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); - if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) + if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel)); } /* Verify thresholds range */ @@ -2443,17 +2429,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of oversampling enabled: depending on ratio and shift configuration, analog watchdog thresholds can be higher than ADC resolution. Verify if thresholds are within maximum thresholds range. */ - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold)); } else { /* Verify if thresholds are within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); } - /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ @@ -2463,16 +2448,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Analog watchdog configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels. */ - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, - __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_ALL_REG: @@ -2494,7 +2479,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD1(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -2506,31 +2491,31 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel))); } break; case ADC_ANALOGWATCHDOG_ALL_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); break; default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); @@ -2542,7 +2527,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD2(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -2551,7 +2536,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_DisableIT_AWD2(hadc->Instance); } } - /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Update state, clear previous result related to AWD3 */ @@ -2564,7 +2549,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD3(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -2578,13 +2563,13 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG } /* Analog watchdog thresholds configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); } /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ else @@ -2592,18 +2577,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* No need to shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ - tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold; - tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold; + tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold; + tmp_awd_low_threshold_shifted = pAnalogWDGConfig->LowThreshold; } /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, - tmpAWDLowThresholdShifted); + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted, + tmp_awd_low_threshold_shifted); - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2707,13 +2690,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } @@ -2763,7 +2750,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2794,13 +2781,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -2855,13 +2846,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.h index 1e06740bae5..d58433f6430 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc.h @@ -132,8 +132,7 @@ typedef struct FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). - This parameter can be set to ENABLE or DISABLE. - Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ + This parameter can be set to ENABLE or DISABLE. */ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). @@ -473,7 +472,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} @@ -516,17 +515,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #if defined(TIM2) #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM2 */ #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #if defined(TIM4) #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM4 */ #if defined(TIM6) #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM6 */ #if defined(TIM15) #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM15 */ #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} @@ -941,7 +940,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ ((REGTRIG) == ADC_SOFTWARE_START) ) -#endif +#endif /* TIM15 && TIM6 && TIM2 */ #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) @@ -1707,8 +1706,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc_ex.c index d39e5937a40..b26cfd61e81 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_adc_ex.c @@ -12,12 +12,6 @@ * Other functions (generic functions) are available in file * "stm32g0xx_hal_adc.c". * - @verbatim - [..] - (@) Sections "ADC peripheral features" and "How to use this driver" are - available in file of generic functions "stm32g0xx_hal_adc.c". - [..] - @endverbatim ****************************************************************************** * @attention * @@ -30,6 +24,12 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32g0xx_hal_adc.c". + [..] + @endverbatim */ /* Includes ------------------------------------------------------------------*/ @@ -110,7 +110,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* Calibration prerequisite: ADC must be disabled. */ @@ -149,7 +148,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -172,10 +170,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) /* to state "HAL_ERROR" by function disabling the ADC. */ } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -209,7 +205,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); - /* Process locked */ __HAL_LOCK(hadc); /* Verification of hardware constraints before modifying the calibration */ @@ -234,10 +229,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cec.c index bdb35b6003b..74e672835f2 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cec.c @@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* CEC TX byte request interrupt ------------------------------------------------*/ if ((reg & CEC_FLAG_TXBR) != 0U) { + --hcec->TxXferCount; if (hcec->TxXferCount == 0U) { /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ __HAL_CEC_LAST_BYTE_TX_SET(hcec); - hcec->Instance->TXDR = *hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - } - else - { - hcec->Instance->TXDR = *hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - hcec->TxXferCount--; } + /* In all cases transmit the byte */ + hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.c index 63f14193ce0..84b73f5a62d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.c @@ -240,7 +240,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) #if defined(COMP3) __IO uint32_t * comp_common_odd; __IO uint32_t * comp_common_even; -#endif +#endif /* COMP3 */ /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) @@ -425,7 +425,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); break; } -#endif +#endif /* COMP3 */ /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is required and not already enabled */ @@ -436,7 +436,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; @@ -811,7 +811,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; @@ -907,7 +907,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2); -#endif +#endif /* COMP3 */ /* Check COMP EXTI flag */ if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.h index e6e8d8b0ff9..f8e995cf381 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_comp.h @@ -103,7 +103,7 @@ typedef enum typedef struct __COMP_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ { COMP_TypeDef *Instance; /*!< Register base address */ COMP_InitTypeDef Init; /*!< COMP required parameters */ @@ -173,7 +173,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ #if defined(COMP3) #define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ -#endif +#endif /* COMP3 */ #define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ /** * @} @@ -307,7 +307,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer } while(0) #else #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) -#endif +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ /** * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). @@ -674,7 +674,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */ #if defined(COMP3) #define COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20) /*!< EXTI line 20 connected to COMP3 output */ -#endif +#endif /* COMP3 */ /** * @} */ @@ -714,7 +714,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #else #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ : COMP_EXTI_LINE_COMP2) -#endif +#endif /* COMP3 */ /** * @} */ @@ -738,7 +738,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) -#endif +#endif /* COMP3 */ #define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \ ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.c index b8f8094379c..6d18f20a38e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.c @@ -62,8 +62,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup CRC_Private_Functions CRC Private Functions - * @{ - */ + * @{ + */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); /** @@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 */ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * + * @brief management functions. + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ /** @addtogroup CRC_Private_Functions - * @{ - */ + * @{ + */ /** * @brief Enter 8-bit input data to the CRC calculator. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.h index ebdf8dd4c3b..164ca102525 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_crc.h @@ -60,19 +60,22 @@ typedef struct { uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. In that case, there is no need to set GeneratingPolynomial field. - If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. - If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal representation, - e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. - No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of @@ -87,14 +90,18 @@ typedef struct uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. Can be either one of the following values @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion - @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 - @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ } CRC_InitTypeDef; /** @@ -112,12 +119,16 @@ typedef struct uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. Can be either - @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) - - Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error - must occur if InputBufferFormat is not one of the three values listed above */ + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ } CRC_HandleTypeDef; /** * @} @@ -199,15 +210,6 @@ typedef struct * @} */ -/** @defgroup CRC_Aliases CRC API aliases - * @{ - */ -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ -/** - * @} - */ - /** * @} */ @@ -267,7 +269,6 @@ typedef struct #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.c index 0d9f954cdb9..0a12d936256 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.c @@ -587,15 +587,17 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD __HAL_LOCK(hcryp); /* Set CRYP parameters */ - hcryp->Init.DataType = pConf->DataType; - hcryp->Init.pKey = pConf->pKey; - hcryp->Init.Algorithm = pConf->Algorithm; - hcryp->Init.KeySize = pConf->KeySize; - hcryp->Init.pInitVect = pConf->pInitVect; - hcryp->Init.Header = pConf->Header; - hcryp->Init.HeaderSize = pConf->HeaderSize; - hcryp->Init.B0 = pConf->B0; - hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); @@ -661,7 +663,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->Header = hcryp->Init.Header ; pConf->HeaderSize = hcryp->Init.HeaderSize; pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -693,8 +697,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ } @@ -709,8 +713,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ } @@ -1205,7 +1209,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1305,7 +1309,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1404,7 +1408,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1514,7 +1518,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1624,7 +1628,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1750,7 +1754,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* Check input buffer size */ assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); -#endif +#endif /* USE_FULL_ASSERT */ if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1929,8 +1933,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } @@ -1945,8 +1949,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -1961,8 +1965,8 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file */ } /** @@ -2570,15 +2574,31 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /* Initiate payload DMA IN and processed data DMA OUT transfers */ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); } + else + { + uint32_t algo; + /* ECB, CBC or CTR end of input data feeding + or + end of GCM/CCM payload data feeding through DMA */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; - /* Call input data transfer complete callback */ + /* Don't call input data transfer complete callback only if + it remains some input data to write to the peripheral. + This case can only occur for GCM and CCM with a payload length + not a multiple of 16 bytes */ + if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ + (((hcryp->Size) % 16U) != 0U))) + { + /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */ } /** @@ -2642,6 +2662,14 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) hcryp->Instance->DINR = 0x0U; count++; } + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /*Wait on CCF flag*/ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); @@ -3380,7 +3408,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3431,6 +3459,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } /* Enter header data */ @@ -3470,15 +3506,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; } } - - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { @@ -3528,7 +3555,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3579,6 +3606,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3904,6 +3939,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t npblb; uint32_t mode; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3993,7 +4033,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (headersize_in_bytes == 0U) /* Header phase is skipped */ { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4077,26 +4126,63 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ + /* Enter header data */ + /* Check first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + hcryp->CrypHeaderCount++; + loopcounter++; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; } + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4105,9 +4191,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - } - - } /* end of if (DoKeyIVConfig == 1U) */ + }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ + } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, header has already been processed; only process here message payload */ @@ -4182,6 +4267,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4387,9 +4480,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); @@ -4435,6 +4528,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4509,6 +4610,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr hcryp->Instance->DINR = 0U; index++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Wait for CCF flag to be raised */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do @@ -4550,6 +4659,15 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /* Process unlocked */ __HAL_UNLOCK(hcryp); + + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } return HAL_OK; @@ -4947,6 +5065,14 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) @@ -5398,9 +5524,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.h index 29ec80926d0..d55e1e04eff 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_cryp.h @@ -107,7 +107,7 @@ typedef enum typedef struct __CRYP_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ { AES_TypeDef *Instance; /*!< AES Register base address */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dac.h index 98961f4eace..e377ab0a661 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dac.h @@ -64,7 +64,7 @@ typedef enum typedef struct __DAC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ { DAC_TypeDef *Instance; /*!< Register base address */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_def.h index 8d1ecf0500a..dd1f37cc184 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_def.h @@ -110,10 +110,10 @@ typedef enum #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #ifndef __weak #define __weak __attribute__((weak)) - #endif + #endif /* __weak */ #ifndef __packed #define __packed __attribute__((packed)) - #endif + #endif /* __packed */ #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) @@ -129,10 +129,10 @@ typedef enum #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN - #endif + #endif /* __ALIGN_BEGIN */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) - #endif + #endif /* __ALIGN_END */ #elif defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4U))) @@ -185,7 +185,7 @@ typedef enum */ #define __RAM_FUNC __attribute__((section(".RamFunc"))) -#endif +#endif /* __CC_ARM || __ARMCC_VERSION */ /** * @brief __NOINLINE definition @@ -202,7 +202,7 @@ typedef enum */ #define __NOINLINE _Pragma("optimize = no_inline") -#endif +#endif /* __CC_ARM || __ARMCC_VERSION */ #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.c index 0c39128773d..230decf9d7d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.c @@ -26,7 +26,6 @@ Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX thanks to: (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(); - (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. @@ -185,7 +184,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) } #else hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; -#endif +#endif /* DMA2 */ /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -286,7 +285,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) } #else hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; -#endif +#endif /* DMA2 */ /* Reset DMA Channel control register */ hdma->Instance->CCR = 0U; @@ -296,7 +295,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ @@ -537,7 +536,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; @@ -595,7 +594,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; @@ -710,7 +709,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level return HAL_ERROR; } -#endif +#endif /* DMA2 */ /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -764,7 +763,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* Process unlocked */ __HAL_UNLOCK(hdma); @@ -780,7 +779,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ } return HAL_OK; @@ -798,7 +797,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) uint32_t flag_it = hdma->DmaBaseAddress->ISR; #else uint32_t flag_it = DMA1->ISR; -#endif +#endif /* DMA2 */ uint32_t source_it = hdma->Instance->CCR; /* Half Transfer Complete Interrupt management ******************************/ @@ -815,7 +814,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ @@ -864,7 +863,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; @@ -1082,7 +1081,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); #else __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); -#endif +#endif /* DMA2 */ /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; @@ -1143,7 +1142,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; -#endif +#endif /* DMA2 */ /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.h index d1acb78acd7..7fc66095abc 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma.h @@ -136,7 +136,7 @@ typedef struct __DMA_HandleTypeDef #if defined(DMA2) DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ -#endif +#endif /* DMA2 */ uint32_t ChannelIndex; /*!< DMA Channel Index */ DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ @@ -190,11 +190,11 @@ typedef struct __DMA_HandleTypeDef #if defined(AES) #define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ #define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ -#endif +#endif /* AES */ #if defined(DAC1) #define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */ #define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */ -#endif +#endif /* DAC1 */ #define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ #define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ #define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ @@ -202,7 +202,7 @@ typedef struct __DMA_HandleTypeDef #if defined(LPUART1) #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ -#endif +#endif /* LPUART1 */ #define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ #define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ #define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ @@ -220,7 +220,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ #define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */ #define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ -#endif +#endif /* TIM2 */ #define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */ #define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */ #define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */ @@ -229,16 +229,16 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */ #if defined(TIM6) #define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */ -#endif +#endif /* TIM6 */ #if defined(TIM7) #define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */ -#endif +#endif /* TIM7 */ #if defined(TIM15) #define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */ #define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */ #define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */ #define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */ -#endif +#endif /* TIM15 */ #define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ #define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */ #define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ @@ -252,34 +252,34 @@ typedef struct __DMA_HandleTypeDef #if defined(USART3) #define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */ #define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */ -#endif +#endif /* USART3 */ #if defined(USART4) #define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */ #define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */ -#endif +#endif /* USART4 */ #if defined(UCPD1) #define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */ #define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */ -#endif +#endif/* UCPD1 */ #if defined(UCPD2) #define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */ #define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */ -#endif +#endif /* UCPD2 */ #if defined(I2C3) #define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ #define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ -#endif +#endif /* I2C3 */ #if defined(LPUART2) #define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */ #define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */ -#endif +#endif /* LPUART2 */ #if defined(SPI3) #define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ #define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ -#endif +#endif /* SPI3 */ #if defined(TIM4) #define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */ @@ -288,17 +288,17 @@ typedef struct __DMA_HandleTypeDef #define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */ #define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */ #define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */ -#endif +#endif /* TIM4 */ #if defined(USART5) #define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */ #define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */ -#endif +#endif /* USART5 */ #if defined(USART6) #define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */ #define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */ -#endif +#endif /* USART6 */ #define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ @@ -391,36 +391,36 @@ typedef struct __DMA_HandleTypeDef #define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ #define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ -#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ -#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ #define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ #define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ -#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ -#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ #define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ #define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ -#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ -#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ #define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ #define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ -#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ -#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ #define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ #define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ -#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ -#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ #if defined(DMA1_Channel6) #define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ #define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ -#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ -#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ -#endif +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) #define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ #define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ -#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ -#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ -#endif +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ +#endif /* DMA1_Channel7 */ /** * @} */ @@ -490,7 +490,7 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ DMA_FLAG_TC5) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** @@ -529,7 +529,7 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ DMA_FLAG_HT5) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** @@ -568,7 +568,7 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ DMA_FLAG_TE5) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** @@ -607,7 +607,7 @@ typedef struct __DMA_HandleTypeDef ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ DMA_FLAG_GI5) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma_ex.h index ac387b84fe7..c737f3d64a5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_dma_ex.h @@ -116,10 +116,10 @@ typedef struct #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3 /*!< Synchronization signal from DMAMUX channel3 Event */ #if defined(LPTIM1) #define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */ -#endif +#endif /* LPTIM1 */ #if defined(LPTIM2) #define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */ -#endif +#endif /* LPTIM2 */ #define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC /*!< Synchronization signal from TIM14 OC */ #define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC @@ -164,10 +164,10 @@ typedef struct #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3 /*!< Request signal generation from DMAMUX channel3 Event */ #if defined(LPTIM1) #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */ -#endif +#endif /* LPTIM1 */ #if defined(LPTIM2) #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */ -#endif +#endif /* LPTIM2 */ #define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC /*!< Request signal generation from TIM14 OC */ #define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.c index 02371b7393d..76986d2cbf1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.c @@ -312,6 +312,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { @@ -323,10 +327,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); @@ -346,15 +346,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = EXTI->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.h index 6caa18df763..96c6904d9d0 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_exti.h @@ -109,80 +109,80 @@ typedef struct #define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) #else #define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) -#endif +#endif /* COMP1 */ #if defined(COMP2) #define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u) #else #define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u) -#endif +#endif /* COMP2 */ #define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u) #if defined(COMP3) #define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) #else #define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) -#endif +#endif /* COMP3 */ #define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u) #if defined(RCC_CCIPR_I2C2SEL) #define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) #else #define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u) -#endif +#endif /* RCC_CCIPR_I2C2SEL */ #define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) #if defined(RCC_CCIPR_USART3SEL) #define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) #else #define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u) -#endif +#endif /* RCC_CCIPR_USART3SEL */ #define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) #if defined(RCC_CCIPR_USART2SEL) #define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) #else #define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au) -#endif +#endif /* RCC_CCIPR_USART2SEL */ #if defined(CEC) #define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) #else #define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu) -#endif +#endif /* CEC */ #if defined(LPUART1) #define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) #else #define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) -#endif +#endif /* LPUART1 */ #if defined(LPTIM1) #define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) #else #define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) -#endif +#endif /* LPTIM1 */ #if defined(LPTIM2) #define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) #else #define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) -#endif +#endif /* LPTIM2 */ #define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu) #if defined(UCPD1) #define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u) #else #define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u) -#endif +#endif /* UCPD1 */ #if defined(UCPD2) #define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u) #else #define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u) -#endif +#endif /* UCPD2 */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) #define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u) #else #define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ #if defined(LPUART2) #define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) #else #define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) -#endif +#endif /* LPUART2 */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) #define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) -#endif +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @} */ @@ -218,7 +218,7 @@ typedef struct #define EXTI_GPIOD 0x00000003u #if defined(GPIOE) #define EXTI_GPIOE 0x00000004u -#endif +#endif /* GPIOE */ #define EXTI_GPIOF 0x00000005u /** * @} @@ -285,7 +285,7 @@ typedef struct #define EXTI_LINE_NB 32uL #else #define EXTI_LINE_NB 32uL -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @} @@ -325,7 +325,7 @@ typedef struct ((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOF)) -#endif +#endif /* GPIOE */ #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.c index 177de10b9c6..5426e3975ea 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.c @@ -103,8 +103,8 @@ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ + * @{ + */ /** * @brief Variable used for Program/Erase sectors under interruption */ @@ -122,8 +122,8 @@ FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ + * @{ + */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); /** @@ -136,8 +136,8 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); */ /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * + * @brief Programming operation functions + * @verbatim =============================================================================== ##### Programming operation functions ##### @@ -157,7 +157,9 @@ static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); * @param Address Specifies the address to be programmed. * @param Data Specifies the data to be programmed * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program. + * are stored the data for the row fast program depending on the TypeProgram: + * TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) + * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). * * @retval HAL_StatusTypeDef HAL Status */ @@ -217,7 +219,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint * @param Address Specifies the address to be programmed. * @param Data Specifies the data to be programmed * This parameter is the data for the double word program and the address where - * are stored the data for the row fast program. + * are stored the data for the row fast program depending on the TypeProgram: + * TypeProgram = FLASH_TYPEPROGRAM_DOUBLEWORD (64-bit) + * TypeProgram = FLASH_TYPEPROGRAM_FAST (32-bit). * * @retval HAL Status */ @@ -410,8 +414,8 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions - * + * @brief Management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -531,8 +535,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) */ /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * + * @brief Peripheral Errors functions + * @verbatim =============================================================================== ##### Peripheral Errors functions ##### @@ -598,7 +602,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) error = (FLASH_SR_BSY1 | FLASH_SR_BSY2); #else error = FLASH_SR_BSY1; -#endif +#endif /* FLASH_DBANK_SUPPORT */ while ((FLASH->SR & error) != 0x00U) { @@ -694,7 +698,7 @@ static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U) #else while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) -#endif +#endif /* FLASH_DBANK_SUPPORT */ { } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.h index 456bb4e8647..1d2554ce800 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash.h @@ -117,8 +117,8 @@ typedef struct to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ uint32_t PCROP2BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) uint32_t BootEntryPoint; /*!< Allow to force a unique boot entry point to Flash or system Flash */ uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting from Flash base address. @@ -128,13 +128,13 @@ typedef struct uint32_t SecSize2; /*!< This parameter defines securable memory area width in number of pages starting from 2nd Bank start address. This parameter must be a value between [0] and [FLASH_PAGE_NB], [0] meaning no secure area defined, [1] meaning first page only protected, etc... */ -#endif -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ +#endif /* FLASH_DBANK_SUPPORT */ } FLASH_OBProgramInitTypeDef; /** -* @brief FLASH handle Structure definition -*/ + * @brief FLASH handle Structure definition + */ typedef struct { HAL_LockTypeDef Lock; /* FLASH locking object */ @@ -196,18 +196,18 @@ typedef struct #define FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos) /*!< FLASH Operation Busy flag for Bank 1 */ #if defined(FLASH_DBANK_SUPPORT) #define FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos) /*!< FLASH Operation Busy flag for Bank 2 */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_BSY FLASH_FLAG_BSY1 /*!< FLASH Operation Busy flag - legacy name for single bank */ #define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos) /*!< FLASH Configuration Busy flag */ #if defined(FLASH_DBANK_SUPPORT) #define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos) /*!< FLASH Programming/erase operation suspended */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos) /*!< FLASH ECC correction on bank 1 */ #define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos) /*!< FLASH ECC detection on bank 1 */ #if defined(FLASH_DBANK_SUPPORT) #define FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos) /*!< FLASH ECC correction on bank 2 */ #define FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos) /*!< FLASH ECC detection on bank 2 */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_FLAG_ECCC FLASH_FLAG_ECCC1 /*!< FLASH ECC correction - legacy name for single bank */ #define FLASH_FLAG_ECCD FLASH_FLAG_ECCD1 /*!< FLASH ECC detection - legacy name for single bank */ /** @@ -222,11 +222,11 @@ typedef struct #define FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos) /*!< Error Interrupt source */ #if defined(FLASH_PCROP_SUPPORT) #define FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos) /*!< PCROP Read Error Interrupt source*/ -#endif +#endif /* FLASH_PCROP_SUPPORT */ #define FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction on Bank 1 Interrupt source */ #if defined(FLASH_DBANK_SUPPORT) #define FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos) /*!< ECC Correction on Bank 2 Interrupt source */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ #define FLASH_IT_ECCC FLASH_IT_ECCC1 /*!< ECC Correction - legacy name for single bank */ /** * @} @@ -246,7 +246,7 @@ typedef struct #define HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR #if defined(FLASH_PCROP_SUPPORT) #define HAL_FLASH_ERROR_RD FLASH_SR_RDERR -#endif +#endif /* FLASH_PCROP_SUPPORT */ #define HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR #define HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD /** @@ -268,7 +268,7 @@ typedef struct #define FLASH_BANK_1 FLASH_CR_MER1 /*!< Bank 1 */ #if defined(FLASH_DBANK_SUPPORT) #define FLASH_BANK_2 FLASH_CR_MER2 /*!< Bank 2 */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -291,17 +291,17 @@ typedef struct #define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ #if defined(FLASH_PCROP_SUPPORT) #define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ -#endif +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) #define OPTIONBYTE_SEC 0x00000010U /*!< SEC option byte configuration */ -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ #if defined(FLASH_PCROP_SUPPORT) && defined(FLASH_SECURABLE_MEMORY_SUPPORT) #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ OPTIONBYTE_PCROP | OPTIONBYTE_SEC) /*!< All option byte configuration */ #else #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte configuration */ -#endif +#endif /* FLASH_PCROP_SUPPORT && FLASH_SECURABLE_MEMORY_SUPPORT */ /** * @} */ @@ -314,7 +314,7 @@ typedef struct #if defined(FLASH_DBANK_SUPPORT) #define OB_WRPAREA_ZONE2_A 0x00000004U /*!< Flash Bank 2 Zone A */ #define OB_WRPAREA_ZONE2_B 0x00000008U /*!< Flash Bank 2 Zone B */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -336,12 +336,12 @@ typedef struct #if defined(PWR_BOR_SUPPORT) #define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /*!< BOR reset enable */ #define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */ -#endif +#endif /* PWR_BOR_SUPPORT */ #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ #if defined(PWR_SHDW_SUPPORT) #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ -#endif +#endif /* PWR_SHDW_SUPPORT */ #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ @@ -349,17 +349,17 @@ typedef struct #if defined(FLASH_DBANK_SUPPORT) #define OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK /*!< Swap bank memory addresses */ #define OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK /*!< Select single or dual bank (depending of device memory size) */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ #define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity check control */ #define OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL /*!< Boot Selection */ #define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< nBoot1 configuration */ #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBoot0 configuration */ #if defined(GPIO_NRST_CONFIG_SUPPORT) #define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE /*!< Reset pin configuration */ -#endif +#endif /* GPIO_NRST_CONFIG_SUPPORT */ #if defined(FLASH_OPTR_IRHEN) #define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ -#endif +#endif /* FLASH_OPTR_IRHEN */ #if defined(FLASH_DBANK_SUPPORT) #if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT) @@ -371,12 +371,12 @@ typedef struct OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ #else #define OB_USER_ALL ( OB_USER_nRST_STOP | \ - OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ - OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ - OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \ - OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ - OB_USER_nBOOT0) /*!< all option bits */ -#endif + OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0) /*!< all option bits */ +#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */ #else #if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT) #define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \ @@ -386,12 +386,12 @@ typedef struct OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ #else #define OB_USER_ALL ( OB_USER_nRST_STOP | \ - OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ - OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ - OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ - OB_USER_nBOOT0) /*!< all option bits */ -#endif -#endif + OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0) /*!< all option bits */ +#endif /* PWR_BOR_SUPPORT && PWR_SHDW_SUPPORT && GPIO_NRST_CONFIG_SUPPORT */ +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -420,7 +420,7 @@ typedef struct /** * @} */ -#endif +#endif /* PWR_BOR_SUPPORT */ /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop * @{ @@ -449,7 +449,7 @@ typedef struct /** * @} */ -#endif +#endif /* PWR_SHDW_SUPPORT */ /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type * @{ @@ -505,7 +505,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity * @{ @@ -553,7 +553,7 @@ typedef struct /** * @} */ -#endif +#endif /* GPIO_NRST_CONFIG_SUPPORT */ #if defined(FLASH_OPTR_IRHEN) /** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit @@ -564,7 +564,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_OPTR_IRHEN */ #if defined(FLASH_PCROP_SUPPORT) /** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE @@ -575,7 +575,7 @@ typedef struct #if defined(FLASH_DBANK_SUPPORT) #define OB_PCROP_ZONE2_A 0x00000004U /*!< PCROP Bank 2 Zone A */ #define OB_PCROP_ZONE2_B 0x00000008U /*!< PCROP Bank 2 Zone B */ -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -591,7 +591,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) /** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock @@ -602,7 +602,7 @@ typedef struct /** * @} */ -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ /** * @} @@ -672,9 +672,9 @@ typedef struct */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros - * @brief macros to handle FLASH interrupts - * @{ - */ + * @brief macros to handle FLASH interrupts + * @{ + */ /** * @brief Enable the specified FLASH interrupt. @@ -698,7 +698,7 @@ typedef struct #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ } while(0U) -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** * @brief Disable the specified FLASH interrupt. @@ -722,7 +722,7 @@ typedef struct #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ } while(0U) -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** * @brief Check whether the specified FLASH flag is set or not. @@ -754,15 +754,15 @@ typedef struct */ #if defined(FLASH_DBANK_SUPPORT) #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ - (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ - ((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ - (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ - (READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))) + (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + ((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + (READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))) #else #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ - (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ - (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)) -#endif + (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)) +#endif /* FLASH_DBANK_SUPPORT */ /** * @brief Clear the FLASH pending flags. @@ -797,7 +797,7 @@ typedef struct #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ } while(0U) -#endif +#endif /* FLASH_DBANK_SUPPORT */ /** * @} */ @@ -883,7 +883,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos) /*!< 0x02000000 */ #define FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE)) #define OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK)) -#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U) || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U) +#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U)\ + || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U) #define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /*!< FLASH Bank Size. Divided by 2 if 2 Banks */ #else /* FLASH_DBANK_SUPPORT */ #define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */ @@ -896,21 +897,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #if defined(FLASH_PCROP_SUPPORT) #define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \ - FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ - FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | \ - FLASH_SR_OPTVERR) /*!< All SR error flags */ + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ + FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | \ + FLASH_SR_OPTVERR) /*!< All SR error flags */ #else #define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \ - FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ - FLASH_SR_MISERR | FLASH_SR_FASTERR | \ - FLASH_SR_OPTVERR) /*!< All SR error flags */ -#endif + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ + FLASH_SR_MISERR | FLASH_SR_FASTERR | \ + FLASH_SR_OPTVERR) /*!< All SR error flags */ +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_DBANK_SUPPORT) #define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD) #else #define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP) -#endif +#endif /* FLASH_DBANK_SUPPORT */ /* Internal defines for HAL macro usage */ #define FLASH_FLAG_REG_POS 16u @@ -925,35 +926,42 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ -#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) -#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL))) +#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL))) #if defined(FLASH_DBANK_SUPPORT) -#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) -#endif +#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) +#endif /* FLASH_DBANK_SUPPORT */ -#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL))) +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL))) -#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U) && ((__ADDRESS__) <= (0x1FFF7400U - 8UL))) +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U)\ + && ((__ADDRESS__) <= (0x1FFF7400U - 8UL))) -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)) || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__))) +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__))\ + || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__))) -#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL))) +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE))\ + && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL))) #define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB) #if defined(FLASH_DBANK_SUPPORT) #define IS_FLASH_BANK(__BANK__) \ - ((FLASH_BANK_NB == 2U) ? \ - (((__BANK__) == FLASH_BANK_1) || \ - ((__BANK__) == FLASH_BANK_2) || \ - ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \ - ((__BANK__) == FLASH_BANK_1)) + ((FLASH_BANK_NB == 2U) ? \ + (((__BANK__) == FLASH_BANK_1) || \ + ((__BANK__) == FLASH_BANK_2) || \ + ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \ + ((__BANK__) == FLASH_BANK_1)) #else #define IS_FLASH_BANK(__BANK__) ((__BANK__) == FLASH_BANK_1) -#endif +#endif /* FLASH_DBANK_SUPPORT */ #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ ((__VALUE__) == FLASH_TYPEERASE_MASS)) @@ -962,17 +970,18 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) #define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \ - (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U)) + (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U)) #if defined(FLASH_DBANK_SUPPORT) #define IS_OB_WRPAREA(__VALUE__) \ - ((FLASH_BANK_NB == 2U) ? \ - (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \ - ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \ - (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B))) + ((FLASH_BANK_NB == 2U) ? \ + (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \ + ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \ + (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B))) #else -#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)) -#endif +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A)\ + || ((__VALUE__) == OB_WRPAREA_ZONE_B)) +#endif /* FLASH_DBANK_SUPPORT */ #define IS_OB_RDP_LEVEL(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ @@ -986,20 +995,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #if defined(FLASH_PCROP_SUPPORT) #if defined(FLASH_DBANK_SUPPORT) #define IS_OB_PCROP_CONFIG(__CONFIG__) \ - ((FLASH_BANK_NB == 2U) ? \ - (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \ - OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \ - (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)) + ((FLASH_BANK_NB == 2U) ? \ + (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \ + OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \ + (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)) #else -#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U) -#endif -#endif +#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__)\ + & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U) +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) -#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE) || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH)) +#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE)\ + || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH)) #define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U)) -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ ((__LATENCY__) == FLASH_LATENCY_1) || \ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.c index e7c31dcf0be..637fe06b88b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.c @@ -89,8 +89,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ + * @{ + */ static void FLASH_MassErase(uint32_t Banks); void FLASH_FlushCaches(void); static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); @@ -99,17 +99,19 @@ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserCo static uint32_t FLASH_OB_GetRDP(void); static uint32_t FLASH_OB_GetUser(void); #if defined(FLASH_PCROP_SUPPORT) -static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr); +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, + uint32_t PCROP1AEndAddr); static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); -static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr); +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, + uint32_t *PCROP1AEndAddr); static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); #if defined(FLASH_DBANK_SUPPORT) static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr); static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr); static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr); static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr); -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) #if defined(FLASH_DBANK_SUPPORT) static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2); @@ -117,8 +119,8 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecS #else static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize); static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize); -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ /** * @} */ @@ -129,8 +131,8 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecS */ /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * + * @brief Extended IO operation functions + * @verbatim =============================================================================== ##### Extended programming operation functions ##### @@ -173,7 +175,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t #if !defined(FLASH_DBANK_SUPPORT) /* For single bank product force Banks to Bank 1 */ pEraseInit->Banks = FLASH_BANK_1; -#endif +#endif /* FLASH_DBANK_SUPPORT */ if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) { @@ -252,7 +254,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) #if !defined(FLASH_DBANK_SUPPORT) /* For single bank product force Banks to Bank 1 */ pEraseInit->Banks = FLASH_BANK_1; -#endif +#endif /* FLASH_DBANK_SUPPORT */ /* Store Bank number */ pFlash.Banks = pEraseInit->Banks; @@ -368,9 +370,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /* Configure the 2B Proprietary code readout protection */ FLASH_OB_PCROP2BConfig(pOBInit->PCROP2BStartAddr, pOBInit->PCROP2BEndAddr); } -#endif +#endif /* FLASH_DBANK_SUPPORT */ } -#endif +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) /* Securable Memory Area Configuration */ @@ -382,9 +384,9 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) #else /* Configure the securable memory area protection */ FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize); -#endif +#endif /* FLASH_DBANK_SUPPORT */ } -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); @@ -441,8 +443,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) FLASH_OB_GetPCROP2A(&(pOBInit->PCROP2AStartAddr), &(pOBInit->PCROP2AEndAddr)); FLASH_OB_GetPCROP2B(&(pOBInit->PCROP2BStartAddr), &(pOBInit->PCROP2BEndAddr)); pOBInit->PCROPConfig |= (OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B); -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) #if defined(FLASH_DBANK_SUPPORT) @@ -451,8 +453,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) #else /* Get the Securable Memory Area protection */ FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize)); -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ } #if defined(FLASH_ACR_DBG_SWEN) @@ -537,12 +539,12 @@ void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks) else #else UNUSED(Banks); -#endif +#endif /* FLASH_DBANK_SUPPORT */ { FLASH->CR |= FLASH_CR_SEC_PROT; } } -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ /** * @} */ @@ -598,7 +600,7 @@ void FLASH_PageErase(uint32_t Banks, uint32_t Page) #if defined(FLASH_DBANK_SUPPORT) /* Check if page has to be erased in bank 1 or 2 */ - if(Banks != FLASH_BANK_1) + if (Banks != FLASH_BANK_1) { tmp |= FLASH_CR_BKER; } @@ -606,7 +608,7 @@ void FLASH_PageErase(uint32_t Banks, uint32_t Page) { tmp &= ~FLASH_CR_BKER; } -#endif +#endif /* FLASH_DBANK_SUPPORT */ /* Set page number, Page Erase bit & Start bit */ FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); @@ -674,7 +676,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32 { FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset); } -#endif +#endif /* FLASH_DBANK_SUPPORT */ else { FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); @@ -718,8 +720,8 @@ static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos); } -#endif -else +#endif /* FLASH_DBANK_SUPPORT */ + else { *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); @@ -862,7 +864,7 @@ static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAd ropbase = (FLASH_BASE + FLASH_BANK_SIZE); } else -#endif +#endif /* FLASH_DBANK_SUPPORT */ { /* Check the parameters */ assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AStartAddr)); @@ -931,7 +933,7 @@ static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEn ropbase = (FLASH_BASE + FLASH_BANK_SIZE); } else -#endif +#endif /* FLASH_DBANK_SUPPORT */ { /* Check the parameters */ assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BStartAddr)); @@ -973,7 +975,7 @@ static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAdd ropbase = (FLASH_BASE + FLASH_BANK_SIZE); } else -#endif +#endif /* FLASH_DBANK_SUPPORT */ { /* No Bank swap, bank 1 read only protection is on first half of Flash */ ropbase = FLASH_BASE; @@ -1012,7 +1014,7 @@ static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEnd ropbase = (FLASH_BASE + FLASH_BANK_SIZE); } else -#endif +#endif /* FLASH_DBANK_SUPPORT */ { /* No Bank swap, bank 1 read only protection is on first half of Flash */ ropbase = FLASH_BASE; @@ -1193,8 +1195,8 @@ static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEnd *PCROP2BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); *PCROP2BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); } -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_PCROP_SUPPORT */ #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) #if defined(FLASH_DBANK_SUPPORT) @@ -1284,8 +1286,8 @@ static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize) *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); *SecSize = (secmem & FLASH_SECR_SEC_SIZE); } -#endif -#endif +#endif /* FLASH_DBANK_SUPPORT */ +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.h index 753f47b1dc4..93f979f891e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_flash_ex.h @@ -71,7 +71,7 @@ uint32_t HAL_FLASHEx_FlashEmptyCheck(void); void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); #if defined(FLASH_SECURABLE_MEMORY_SUPPORT) void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks); -#endif +#endif /* FLASH_SECURABLE_MEMORY_SUPPORT */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.c index f12e8e7a511..0f023190708 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.c @@ -123,17 +123,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants +/** @addtogroup GPIO_Private_Constants * @{ */ -#define GPIO_MODE (0x00000003u) -#define EXTI_MODE (0x10000000u) -#define GPIO_MODE_IT (0x00010000u) -#define GPIO_MODE_EVT (0x00020000u) -#define RISING_EDGE (0x00100000u) -#define FALLING_EDGE (0x00200000u) -#define GPIO_OUTPUT_TYPE (0x00000010u) - #define GPIO_NUMBER (16u) /** * @} @@ -177,7 +169,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00u) @@ -189,11 +180,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); @@ -203,18 +194,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); - temp |= ((GPIO_Init->Pull) << (position * 2u)); - GPIOx->PUPDR = temp; + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); + GPIOx->PUPDR = temp; + } /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); @@ -235,7 +232,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) { temp = EXTI->EXTICR[position >> 2u]; temp &= ~(0x0FuL << (8u * (position & 0x03u))); @@ -245,7 +242,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear EXTI line configuration */ temp = EXTI->IMR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) { temp |= iocurrent; } @@ -253,7 +250,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->EMR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) { temp |= iocurrent; } @@ -262,7 +259,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) { temp |= iocurrent; } @@ -270,7 +267,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) { temp |= iocurrent; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.h index fd89eb32c78..dcae93472fe 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio.h @@ -107,26 +107,25 @@ typedef enum /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ */ -#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -135,10 +134,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< High speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< Very high speed */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ /** * @} */ @@ -147,9 +146,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ -#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ /** * @} */ @@ -246,6 +245,31 @@ typedef enum */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +/** + * @} + */ + /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio_ex.h index 74d34677045..97225c5bbe2 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_gpio_ex.h @@ -186,7 +186,7 @@ extern "C" { #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0A) -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ #if defined (STM32G0B0xx) /*------------------------- STM32G0B0xx ------------------------*/ @@ -297,7 +297,7 @@ extern "C" { #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x09) -#endif +#endif /* STM32G0B0xx */ #if defined (STM32G081xx) || defined (STM32G071xx) @@ -810,7 +810,7 @@ extern "C" { ((__GPIOx__) == (GPIOB))? 1uL :\ ((__GPIOx__) == (GPIOC))? 2uL :\ ((__GPIOx__) == (GPIOD))? 3uL : 5uL) -#endif +#endif /* GPIOE */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.c index 9196f3e78c8..55aee180f3d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.c @@ -39,7 +39,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -57,10 +57,9 @@ * @{ */ -//#ifdef HAL_HCD_MODULE_ENABLED //-> ERREUR DE COMPILATION +#ifdef HAL_HCD_MODULE_ENABLED #if defined (USB_DRD_FS) - /** @defgroup HCD HCD * @brief HCD HAL module driver * @{ @@ -191,9 +190,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to 255 * @param speed Current device speed. * This parameter can be one of these values: - * HCD_SPEED_HIGH High speed mode, - * HCD_SPEED_FULL Full speed mode, - * HCD_SPEED_LOW Low speed mode + * HCD_DEVICE_SPEED_HIGH High speed mode, + * HCD_DEVICE_SPEED_FULL Full speed mode, + * HCD_DEVICE_SPEED_LOW Low speed mode * @param ep_type Endpoint Type. * This parameter can be one of these values: * USBH_EP_CONTROL Control type, @@ -602,6 +601,12 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) uint8_t chnum; uint32_t epch_reg; + /* check if this is an USB pending IT */ + if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U) + { + return; + } + /* Port Change Detected (Connection/Disconnection) */ if (__HAL_HCD_GET_FLAG(hhcd, USB_ISTR_DCON)) { @@ -1354,7 +1359,10 @@ uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) /** * @brief Return the Host enumeration speed. * @param hhcd HCD handle - * @retval Enumeration speed + * @retval speed : Device speed after Host enumeration + * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode */ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) { @@ -2492,8 +2500,8 @@ static HAL_StatusTypeDef HAL_HCD_PMAFree(HCD_HandleTypeDef *hhcd, uint32_t pma_ /** * @} */ -#endif /* USB_DRD_FS */ -//#endif /* HAL_HCD_MODULE_ENABLED */ +#endif /* defined (USB_DRD_FS) */ +#endif /* HAL_HCD_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.h index b956885793a..d849cde9fcf 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_hcd.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -29,7 +29,6 @@ extern "C" { #include "stm32g0xx_ll_usb.h" #if defined (USB_DRD_FS) - /** @addtogroup STM32G0xx_HAL_Driver * @{ */ @@ -55,8 +54,7 @@ typedef enum HAL_HCD_STATE_TIMEOUT = 0x04 } HCD_StateTypeDef; - -typedef USB_DRD_TypeDef HCD_TypeDef; +typedef USB_DRD_TypeDef HCD_TypeDef; typedef USB_DRD_CfgTypeDef HCD_InitTypeDef; typedef USB_DRD_HCTypeDef HCD_HCTypeDef; typedef USB_DRD_URBStateTypeDef HCD_URBStateTypeDef; @@ -131,7 +129,16 @@ typedef struct */ #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U /** * @} */ @@ -169,7 +176,8 @@ typedef struct #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -449,14 +457,35 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); */ #define HCD_SET_CH_TX_CNT USB_DRD_SET_CHEP_TX_CNT #define HCD_SET_CH_RX_CNT USB_DRD_SET_CHEP_RX_CNT + /** * @brief gets counter of the tx buffer. * @param USBx USB peripheral instance register address. - * @param bChNum Endpoint Number. + * @param bChNum channel Number. * @retval Counter value */ #define HCD_GET_CH_TX_CNT USB_DRD_GET_CHEP_TX_CNT -#define HCD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_RX_CNT(HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bChNum)); +} + /** * @brief Gets buffer 0/1 address of a double buffer endpoint. * @param USBx USB peripheral instance register address. @@ -470,27 +499,59 @@ HAL_StatusTypeDef HAL_HCD_PMAReset(HCD_HandleTypeDef *hhcd); #define HCD_SET_CH_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT #define HCD_SET_CH_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT + /** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx USB peripheral instance register address. - * @param bChNum Endpoint Number. - * @retval None + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF0_CNT(HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bChNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bChNum channel Number. + * @retval Counter value */ -#define HCD_GET_CH_DBUF0_CNT USB_DRD_GET_CHEP_DBUF0_CNT -#define HCD_GET_CH_DBUF1_CNT USB_DRD_GET_CHEP_DBUF1_CNT +__STATIC_INLINE uint16_t HCD_GET_CH_DBUF1_CNT(HCD_TypeDef *Instance, uint16_t bChNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bChNum)); +} + /** * @} */ /* Private functions prototypes ----------------------------------------------*/ - /** +/** * @} */ - /** +/** * @} */ - -#endif +#endif /* defined (USB_DRD_FS) */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.c index 51771aef836..c9b56a42d30 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.c @@ -28,7 +28,8 @@ (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx channel @@ -65,22 +66,22 @@ =================================== [..] (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -93,62 +94,79 @@ [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and with a final stop condition in both cases - (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential - interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. - (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential interface. - Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). - Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() - or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() - or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Master_Seq_Receive_IT() or using @ref HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() + (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() + @ref HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Slave_Seq_Transmit_IT() or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() + (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + @ref HAL_I2C_Slave_Seq_Receive_IT() or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -157,39 +175,39 @@ [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -198,14 +216,14 @@ [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -336,28 +354,48 @@ #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ - -#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ -#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ -#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -390,21 +428,34 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); @@ -417,7 +468,8 @@ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); /* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); @@ -432,8 +484,8 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -555,7 +607,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ @@ -672,7 +725,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -977,8 +1031,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -1060,7 +1114,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1091,12 +1146,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -1126,12 +1183,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1174,7 +1233,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1205,12 +1265,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -1241,12 +1303,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1287,7 +1351,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1424,7 +1489,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1550,7 +1616,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1598,7 +1665,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -1619,7 +1687,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1667,7 +1736,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -1716,7 +1786,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1765,7 +1836,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1786,7 +1858,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1837,7 +1910,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -1897,7 +1971,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1907,7 +1982,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -1929,7 +2005,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1980,7 +2057,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2040,7 +2118,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2050,7 +2129,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -2108,7 +2188,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2211,7 +2292,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2280,7 +2362,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2363,17 +2446,18 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2415,7 +2499,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2463,12 +2548,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } do @@ -2499,16 +2586,17 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2548,7 +2636,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2597,7 +2686,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2616,7 +2706,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -2639,7 +2730,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2707,7 +2799,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -2729,7 +2822,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2779,7 +2873,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2800,7 +2895,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2873,7 +2969,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param Size Amount of data to be read * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2943,7 +3040,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3014,7 +3112,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3124,8 +3223,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Increment Trials */ I2C_Trials++; - } - while (I2C_Trials < Trials); + } while (I2C_Trials < Trials); /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; @@ -3156,7 +3254,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3191,9 +3290,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3240,7 +3341,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3276,9 +3378,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3309,7 +3413,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3368,7 +3473,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3378,7 +3484,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3402,7 +3509,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3437,9 +3545,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3486,7 +3596,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3522,9 +3633,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3555,7 +3668,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3614,7 +3728,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3624,7 +3739,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3646,7 +3762,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3741,7 +3858,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -3843,7 +3961,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3920,7 +4039,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4015,7 +4135,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -4117,7 +4238,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); } else { @@ -4300,8 +4422,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA */ /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -4335,7 +4457,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -4344,7 +4467,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -4353,7 +4477,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -4539,8 +4664,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * + * @brief Peripheral State, Mode and Error functions + * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### @@ -4577,11 +4702,11 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) } /** -* @brief Return the I2C error code. + * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ + * @retval I2C Error Code + */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; @@ -4607,7 +4732,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4615,7 +4741,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4628,7 +4755,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; @@ -4642,7 +4770,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; @@ -4653,7 +4782,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { @@ -4669,11 +4799,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -4693,7 +4825,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4724,7 +4857,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); @@ -4744,7 +4878,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4753,13 +4888,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4767,7 +4904,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4806,7 +4945,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { @@ -4827,15 +4967,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint I2C_ITSlaveSeqCplt(hi2c); } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, tmpITFlags); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all data have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -4877,7 +5019,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -4885,7 +5028,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4901,7 +5045,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -4962,7 +5107,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4988,7 +5134,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -5012,7 +5159,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5022,13 +5170,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5063,7 +5213,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5124,7 +5276,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } @@ -5151,7 +5304,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5204,7 +5359,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5272,7 +5429,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; @@ -5868,7 +6025,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; - if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { @@ -5897,7 +6055,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } } /* Abort DMA RX transfer if any */ - else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { @@ -5997,7 +6156,8 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -6025,7 +6185,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -6045,7 +6206,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) @@ -6072,7 +6234,8 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -6100,7 +6263,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -6120,7 +6284,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ @@ -6147,7 +6312,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -6164,7 +6330,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) @@ -6189,7 +6356,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { @@ -6219,7 +6387,8 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { @@ -6256,7 +6425,8 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { @@ -6290,7 +6460,8 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { @@ -6357,6 +6528,12 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { + /* In case of Soft End condition, generate the STOP condition */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) @@ -6421,7 +6598,8 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -6429,8 +6607,13 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.h index e05d5fad838..70394b79375 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c.h @@ -48,29 +48,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ + This parameter calculated by referring to I2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ } I2C_InitTypeDef; @@ -200,7 +201,8 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -217,20 +219,32 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ - - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ - - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; @@ -259,8 +273,11 @@ typedef enum /** * @brief HAL I2C Callback pointer definition */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @@ -440,14 +457,14 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -#endif +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. @@ -495,7 +512,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. @@ -521,7 +539,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval The new state of __FLAG__ (SET or RESET). */ #define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. @@ -540,26 +559,27 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ @@ -583,7 +603,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); @@ -598,49 +619,72 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); /** * @} */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -732,10 +776,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) @@ -743,13 +792,20 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.c index 88b8a2e85bc..f7c0bdb53cb 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.c @@ -71,17 +71,15 @@ * @{ */ -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters - (+) Configure Wake Up Feature - (+) Configure Fast Mode Plus @endverbatim * @{ @@ -182,6 +180,23 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ /** * @brief Enable I2C wakeup from Stop mode(s). @@ -260,6 +275,23 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ /** * @brief Enable the I2C fast mode plus driving capability. @@ -314,7 +346,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); } - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.h index 41b555411f4..00f970e4b0d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2c_ex.h @@ -38,7 +38,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -68,7 +67,7 @@ extern "C" { #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ #else #define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ -#endif +#endif /* SYSCFG_CFGR1_I2C3_FMP */ /** * @} */ @@ -78,24 +77,50 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -111,7 +136,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) @@ -125,9 +150,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))) - - - /** * @} */ @@ -149,14 +171,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2s.c index 9560e2c1225..f6bc39f109f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_i2s.c @@ -356,7 +356,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) #else /* Get the source clock value: based on System Clock value */ i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S1); -#endif +#endif /* RCC_PERIPHCLK_I2S2 */ /* Compute the Real divider depending on the MCLK output state, with a floating point */ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) { @@ -755,7 +755,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -872,7 +872,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -973,7 +973,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1037,7 +1037,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization @@ -1103,7 +1103,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1194,7 +1194,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.c index c25606b1249..3a7d8171a5f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.c @@ -40,7 +40,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), the normal or low power mode and the clock prescaler in the hirda handle Init structure. @@ -612,43 +613,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD switch (CallbackID) { case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -771,13 +774,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -1482,7 +1488,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -1680,7 +1687,8 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised @@ -2338,7 +2346,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) uint32_t tmpreg; IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the communication parameters */ @@ -2475,7 +2483,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.h index 4329445c0b4..cdc75ef6d1f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda.h @@ -78,7 +78,8 @@ typedef struct /** * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -89,7 +90,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -106,7 +107,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -247,7 +248,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -259,15 +261,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -570,9 +572,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -586,10 +593,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -605,8 +616,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -620,9 +631,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda_ex.h index e67542b2c5e..9ce590d6abe 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_irda_ex.h @@ -220,7 +220,7 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.c index d7b305ac7d4..49c8d711758 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.c @@ -65,13 +65,13 @@ (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) Wait for status flags to be reset. (++) Depending on window parameter: (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. (+++) Else modify Window register. This will automatically reload watchdog counter. + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -121,11 +121,14 @@ /* Status register needs up to 5 LSI clock periods divided by the clock prescaler to be updated. The number of LSI clock periods is upper-rounded to 6 for the timeout value calculation. - The timeout value is also calculated using the highest prescaler (256) and + The timeout value is calculated using the highest prescaler (256) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} */ @@ -196,11 +199,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != 0x00u) + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { - return HAL_TIMEOUT; + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } } } @@ -223,6 +229,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ @@ -242,7 +249,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ - /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains @@ -258,6 +264,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.h index 23b3953ed46..0650bf121c4 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_iwdg.h @@ -87,7 +87,6 @@ typedef struct #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ - /** * @} */ @@ -100,7 +99,6 @@ typedef struct * @} */ - /** * @} */ @@ -138,7 +136,7 @@ typedef struct * @{ */ /* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ @@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.c index 34749053a65..b6b51baeb95 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.c @@ -188,10 +188,10 @@ */ #if defined(LPTIM2) #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \ - (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()) + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()) #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \ - (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()) + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()) #else #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() @@ -215,8 +215,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t */ /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -253,19 +253,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); @@ -299,21 +297,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ @@ -332,19 +327,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UltraLowPowerClock.SampleTime); } - /* Configure the active edge or edges used by the counter only if LPTIM is - * clocked by an external clock source - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); } + /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ @@ -458,8 +455,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * + * @brief Start-Stop operation functions. + * @verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### @@ -563,7 +560,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -699,7 +696,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -786,7 +783,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -922,7 +919,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1009,7 +1006,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1145,7 +1142,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1584,7 +1581,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1665,7 +1663,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1756,8 +1755,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * + * @brief Read operation functions. + * @verbatim ============================================================================== ##### LPTIM Read operation functions ##### @@ -1814,8 +1813,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks - * @brief LPTIM IRQ handler. - * + * @brief LPTIM IRQ handler. + * @verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### @@ -2205,39 +2204,48 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; break; case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; break; case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; break; case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; break; case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; break; case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; break; case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; break; default : @@ -2251,11 +2259,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; default : @@ -2282,8 +2292,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti */ /** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -2330,13 +2340,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) { /* Reset the LPTIM callback to the legacy weak callbacks */ - lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ - lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ - lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ - lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ - lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ - lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2358,8 +2368,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { result = HAL_TIMEOUT; } - } - while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); return result; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.h index bf6ef2055ba..8faa4addc10 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_lptim.h @@ -98,30 +98,30 @@ typedef struct */ typedef struct { - LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ - LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - uint32_t OutputPolarity; /*!< Specifies the Output polarity. - This parameter can be a value of @ref LPTIM_Output_Polarity */ + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ - uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare - values is done immediately or after the end of current period. - This parameter can be a value of @ref LPTIM_Updating_Mode */ + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ - uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event - or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ - uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). - This parameter can be a value of @ref LPTIM_Input1_Source */ + uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). + This parameter can be a value of @ref LPTIM_Input1_Source */ - uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). - Note: This parameter is used only for encoder feature so is used only - for LPTIM1 instance. - This parameter can be a value of @ref LPTIM_Input2_Source */ + uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). + Note: This parameter is used only for encoder feature so is used only + for LPTIM1 instance. + This parameter can be a value of @ref LPTIM_Input2_Source */ } LPTIM_InitTypeDef; /** @@ -378,10 +378,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -531,7 +531,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Enable the LPTIM1 EXTI line in interrupt mode. @@ -543,7 +544,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM1 EXTI line in interrupt mode. * @retval None */ -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1)) +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) /** @@ -556,7 +558,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM1 EXTI line in event mode. * @retval None */ -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1)) +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) /** * @brief Enable the LPTIM2 EXTI line in interrupt mode. @@ -568,7 +571,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM2 EXTI line in interrupt mode. * @retval None */ -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2)) +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) /** @@ -581,7 +585,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM2 EXTI line in event mode. * @retval None */ -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2)) +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) /** * @} @@ -593,9 +598,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ /** @addtogroup LPTIM_Exported_Functions_Group1 - * @brief Initialization and Configuration functions. - * @{ - */ + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -608,9 +613,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group2 - * @brief Start-Stop operation functions. - * @{ - */ + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -664,9 +669,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group3 - * @brief Read operation functions. - * @{ - */ + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); @@ -676,9 +681,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group4 - * @brief LPTIM IRQ handler and callback functions. - * @{ - */ + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -693,7 +698,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** @@ -701,9 +707,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ */ /** @addtogroup LPTIM_Group5 - * @brief Peripheral State functions. - * @{ - */ + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @@ -807,20 +813,20 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ - || \ - (((__INSTANCE__) == LPTIM2) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))) + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ - (((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.c index b5ec4fd3ded..7e21083ca42 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.c @@ -42,7 +42,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; - + /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { @@ -695,7 +695,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -769,7 +770,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -1003,6 +1005,12 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { + /* check if this is an USB pending IT */ + if ((SYSCFG->IT_LINE_SR[8] & (0x1U << 2)) == 0U) + { + return; + } + if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR)) { /* servicing of the endpoint correct transfer interrupt */ @@ -1759,8 +1767,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U) + { + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1847,9 +1858,9 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - /* Manage all non bulk transaction or Bulk Single Buffer Transaction */ - if ((ep->type != EP_TYPE_BULK) || - ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))) + /* Manage all non bulk/isoc transaction Bulk Single Buffer Transaction */ + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_CTRL) || + ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))) { /* multi-packet on the NON control IN endpoint */ TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); @@ -1881,7 +1892,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) (void)USB_EPStartXfer(hpcd->Instance, ep); } } - /* bulk in double buffer enable in case of transferLen> Ep_Mps */ + /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); @@ -1927,7 +1938,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /* Check if Buffer1 is in blocked state which requires to toggle */ + /* Check if Buffer1 is in blocked sate which requires to toggle */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) { PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); @@ -2005,6 +2016,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */ if (ep->xfer_len == 0U) { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2075,6 +2089,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */ if (ep->xfer_len == 0U) { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2082,7 +2099,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, HAL_PCD_DataInStageCallback(hpcd, ep->num); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - /*need to Free USB Buff*/ + /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.h index 8e7aa567129..5f3e29450bf 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -190,8 +190,11 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ + &= (uint16_t)(~(__INTERRUPT__))) #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR2 |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR2 &= ~(USB_WAKEUP_EXTI_LINE) @@ -528,7 +531,26 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval Counter value */ #define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT -#define PCD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT + +/** + * @brief gets counter of the rx buffer. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum)); +} /** * @brief Sets addresses in a double buffer endpoint. @@ -554,13 +576,44 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT /** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None + * @brief gets counter of the rx buffer0. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value */ -#define PCD_GET_EP_DBUF0_CNT USB_DRD_GET_CHEP_DBUF0_CNT -#define PCD_GET_EP_DBUF1_CNT USB_DRD_GET_CHEP_DBUF1_CNT +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum)); +} + +/** + * @brief gets counter of the rx buffer1. + * @param Instance USB peripheral instance register address. + * @param bEpNum channel Number. + * @retval Counter value + */ +__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(PCD_TypeDef *Instance, uint16_t bEpNum) +{ + UNUSED(Instance); + __IO uint32_t count = 10U; + + /* WA: few cycles for RX PMA descriptor to update */ + while (count > 0U) + { + count--; + } + + return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); +} /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.c index 828a6170802..c88c44e3f1b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.c @@ -10,7 +10,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.h index ef465469082..952abbca139 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pcd_ex.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.c index 702bb276ab4..1c9a956fb85 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.c @@ -11,11 +11,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -246,7 +246,7 @@ void HAL_PWR_DisableBkUpAccess(void) * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. * This parameter can be one of the following legacy values which set * the default polarity i.e. detection on high level (rising edge): - * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 * or one of the following value where the user can explicitly specify * the enabled pin and the chosen polarity: @@ -323,11 +323,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Set Regulator parameter */ - if(Regulator != PWR_MAINREGULATOR_ON) + if (Regulator != PWR_MAINREGULATOR_ON) { /* If in run mode, first move to low-power run mode. The system clock frequency must be below 2 MHz at this point. */ - if((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u) + if ((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u) { HAL_PWREx_EnableLowPowerRunMode(); } @@ -335,7 +335,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) else { /* If in low-power run mode at this point, exit it */ - if((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u) + if ((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u) { if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) { @@ -348,7 +348,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); @@ -417,7 +417,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) + if (STOPEntry == PWR_STOPENTRY_WFI) { /* Request Wait For Interrupt */ __WFI(); @@ -459,10 +459,10 @@ void HAL_PWR_EnterSTANDBYMode(void) /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -/* This option is used to ensure that store operations are completed */ + /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); -#endif +#endif /* __CC_ARM */ /* Request Wait For Interrupt */ __WFI(); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.h index f9fd1848481..66ffb3e2d72 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -22,7 +22,7 @@ #define STM32G0xx_HAL_PWR_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -58,31 +58,31 @@ #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ #if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ -#endif +#endif /* PWR_CR3_EWUP3 */ #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ #if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ -#endif +#endif /* PWR_CR3_EWUP5 */ #define PWR_WAKEUP_PIN6 PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ #if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ -#endif +#endif /* PWR_CR3_EWUP3 */ #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ #if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ -#endif +#endif /* PWR_CR3_EWUP5*/ #define PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */ #define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */ #if defined(PWR_CR3_EWUP3) #define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */ -#endif +#endif /* PWR_CR3_EWUP3 */ #define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */ #if defined(PWR_CR3_EWUP5) #define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */ -#endif +#endif /* PWR_CR3_EWUP5 */ #define PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */ /** * @} @@ -96,7 +96,7 @@ #define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ #if defined(PWR_SHDW_SUPPORT) #define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */ -#endif +#endif /* PWR_SHDW_SUPPORT */ /** * @} */ @@ -142,11 +142,11 @@ #define PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2) /*!< Wakeup event on wakeup pin 2 */ #if defined(PWR_CR3_EWUP3) #define PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3) /*!< Wakeup event on wakeup pin 3 */ -#endif +#endif /* PWR_CR3_EWUP3 */ #define PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4) /*!< Wakeup event on wakeup pin 4 */ #if defined(PWR_CR3_EWUP5) #define PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5) /*!< Wakeup event on wakeup pin 5 */ -#endif +#endif /* PWR_CR3_EWUP5 */ #define PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6) /*!< Wakeup event on wakeup pin 6 */ #define PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF) /*!< Wakeup event on all wakeup pin */ #define PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF) /*!< Standby flag */ @@ -156,15 +156,15 @@ #define PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF) /*!< Regulator Low Power flag */ #if defined(PWR_PVD_SUPPORT) #define PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO) /*!< Power Voltage Detector output */ -#endif +#endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) #define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB) /*!< Power Voltage Monitoring output */ -#endif +#endif /* PWR_PVM_SUPPORT */ /** * @} */ - + /** * @} */ @@ -206,8 +206,8 @@ * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_PWR_GET_FLAG(__FLAG__) (((__FLAG__) & 0x00010000u) ?\ - ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\ - ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u))) + ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\ + ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u))) /** @brief Clear a specific PWR flag. * @param __FLAG__ specifies the flag to clear. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.c index 84439418162..2fae93f9cff 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.c @@ -11,11 +11,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -56,7 +56,7 @@ /** * @} */ -#endif +#endif /* PWR_PVD_SUPPORT */ /** @defgroup PWREx_TimeOut_Value PWREx Flag Setting Time Out Value * @{ @@ -171,7 +171,7 @@ void HAL_PWREx_DisablePORMonitorSampling(void) { PWR->CR3 &= ~PWR_CR3_ENB_ULP; } -#endif +#endif /* PWR_CR3_ENB_ULP */ #if defined(PWR_PVD_SUPPORT) /** @@ -201,24 +201,24 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } @@ -245,7 +245,7 @@ void HAL_PWREx_DisablePVD(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); } -#endif +#endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) /** @@ -266,7 +266,7 @@ void HAL_PWREx_DisableVddUSB(void) { CLEAR_BIT(PWR->CR2, PWR_CR2_USV); } -#endif +#endif /* PWR_PVM_SUPPORT */ #if defined(PWR_CR2_IOSV) /** @@ -308,7 +308,7 @@ void HAL_PWREx_DisablePVMUSB(void) { CLEAR_BIT(PWR->CR2, PWR_PVM_USB); } -#endif +#endif /* PWR_PVM_SUPPORT */ #if defined(PWR_PVM_SUPPORT) /** @@ -344,24 +344,24 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); /* Configure interrupt mode */ - if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) { __HAL_PWR_PVM_EXTI_ENABLE_IT(); } /* Configure event mode */ - if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + if ((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) { __HAL_PWR_PVM_EXTI_ENABLE_EVENT(); } /* Configure the edge */ - if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) { __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); } - if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) { __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); } @@ -374,7 +374,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) return status; } -#endif +#endif /* PWR_PVM_SUPPORT */ /** * @brief Enable Internal Wake-up Line. * @retval None @@ -422,35 +422,35 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) switch (GPIO) { case PWR_GPIO_A: - SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); - CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); - break; + SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + break; case PWR_GPIO_B: - SET_BIT(PWR->PUCRB, GPIONumber); - CLEAR_BIT(PWR->PDCRB, GPIONumber); - break; + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; case PWR_GPIO_C: - SET_BIT(PWR->PUCRC, GPIONumber); - CLEAR_BIT(PWR->PDCRC, GPIONumber); - break; + SET_BIT(PWR->PUCRC, GPIONumber); + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; case PWR_GPIO_D: - SET_BIT(PWR->PUCRD, GPIONumber); - CLEAR_BIT(PWR->PDCRD, GPIONumber); - break; + SET_BIT(PWR->PUCRD, GPIONumber); + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; #if defined(GPI0E) case PWR_GPIO_E: - SET_BIT(PWR->PUCRE, GPIONumber); - CLEAR_BIT(PWR->PDCRE, GPIONumber); - break; -#endif + SET_BIT(PWR->PUCRE, GPIONumber); + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; +#endif /* GPI0E */ case PWR_GPIO_F: - SET_BIT(PWR->PUCRF, GPIONumber); - CLEAR_BIT(PWR->PDCRF, GPIONumber); - break; + SET_BIT(PWR->PUCRF, GPIONumber); + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; default: status = HAL_ERROR; @@ -503,14 +503,14 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber case PWR_GPIO_E: CLEAR_BIT(PWR->PUCRE, GPIONumber); break; -#endif +#endif /* GPI0E */ case PWR_GPIO_F: CLEAR_BIT(PWR->PUCRF, GPIONumber); break; default: - status = HAL_ERROR; - break; + status = HAL_ERROR; + break; } return status; @@ -546,35 +546,35 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe switch (GPIO) { case PWR_GPIO_A: - SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); - CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); - break; + SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + break; case PWR_GPIO_B: - SET_BIT(PWR->PDCRB, GPIONumber); - CLEAR_BIT(PWR->PUCRB, GPIONumber); - break; + SET_BIT(PWR->PDCRB, GPIONumber); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; case PWR_GPIO_C: - SET_BIT(PWR->PDCRC, GPIONumber); - CLEAR_BIT(PWR->PUCRC, GPIONumber); - break; + SET_BIT(PWR->PDCRC, GPIONumber); + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; case PWR_GPIO_D: - SET_BIT(PWR->PDCRD, GPIONumber); - CLEAR_BIT(PWR->PUCRD, GPIONumber); - break; + SET_BIT(PWR->PDCRD, GPIONumber); + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; #if defined(GPIOE) case PWR_GPIO_E: - SET_BIT(PWR->PDCRE, GPIONumber); - CLEAR_BIT(PWR->PUCRE, GPIONumber); - break; -#endif + SET_BIT(PWR->PDCRE, GPIONumber); + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; +#endif /* GPI0E */ case PWR_GPIO_F: - SET_BIT(PWR->PDCRF, GPIONumber); - CLEAR_BIT(PWR->PUCRF, GPIONumber); - break; + SET_BIT(PWR->PDCRF, GPIONumber); + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; default: status = HAL_ERROR; @@ -627,7 +627,7 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb case PWR_GPIO_E: CLEAR_BIT(PWR->PDCRE, GPIONumber); break; -#endif +#endif /* GPI0E */ case PWR_GPIO_F: CLEAR_BIT(PWR->PDCRF, GPIONumber); break; @@ -690,7 +690,7 @@ void HAL_PWREx_DisableSRAMRetention(void) { CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); } -#endif +#endif /* PWR_CR3_RRS */ /** * @brief Enable Flash Power Down. @@ -770,15 +770,15 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ - if(VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) { /* Set timeout value */ - wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock ) / 1000000U) + 1U; + wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; /* Wait until VOSF is reset */ - while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) { - if(wait_loop_index != 0U) + if (wait_loop_index != 0U) { wait_loop_index--; } @@ -818,15 +818,15 @@ void HAL_PWREx_EnableLowPowerRunMode(void) */ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { - uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock ) / 1000000U) + 1U; + uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock) / 1000000U) + 1U; /* Clear LPR bit */ CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); /* Wait until REGLPF is reset */ - while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) + while (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) { - if(wait_loop_index != 0U) + if (wait_loop_index != 0U) { wait_loop_index--; } @@ -869,12 +869,12 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); -#endif +#endif /* __CC_ARM */ /* Request Wait For Interrupt */ __WFI(); } -#endif +#endif /* PWR_SHDW_SUPPORT */ #if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) /** @@ -885,7 +885,7 @@ void HAL_PWREx_EnterSHUTDOWNMode(void) void HAL_PWREx_PVD_PVM_IRQHandler(void) { /* Check PWR PVD exti Rising flag */ - if(__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) { /* Clear PVD exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); @@ -895,7 +895,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void) } /* Check PWR exti fallling flag */ - if(__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) { /* Clear PVD exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); @@ -903,9 +903,9 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void) /* PWR PVD interrupt falling user callback */ HAL_PWREx_PVD_PVM_Falling_Callback(); } - + /* Check PWR PVM exti Rising flag */ - if(__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U) + if (__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U) { /* Clear PVM exti pending bit */ __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG(); @@ -915,7 +915,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void) } /* Check PWR PVM exti fallling flag */ - if(__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U) + if (__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U) { /* Clear PVM exti pending bit */ __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG(); @@ -955,7 +955,7 @@ __weak void HAL_PWREx_PVD_PVM_Falling_Callback(void) void HAL_PWREx_PVD_IRQHandler(void) { /* Check PWR exti Rising flag */ - if(__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + if (__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) { /* Clear PVD exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); @@ -965,7 +965,7 @@ void HAL_PWREx_PVD_IRQHandler(void) } /* Check PWR exti fallling flag */ - if(__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + if (__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) { /* Clear PVD exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); @@ -997,7 +997,7 @@ __weak void HAL_PWREx_PVD_Falling_Callback(void) */ } -#endif +#endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.h index 68b8b2ee343..d0f1225ae98 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_pwr_ex.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -22,7 +22,7 @@ #define STM32G0xx_HAL_PWR_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -54,8 +54,8 @@ typedef struct uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWREx_PVM_Mode. */ -}PWR_PVMTypeDef; -#endif +} PWR_PVMTypeDef; +#endif /* PWR_PVM_SUPPORT */ #if defined(PWR_PVD_SUPPORT) /** @@ -69,8 +69,8 @@ typedef struct uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. This parameter can be a value of @ref PWR_PVD_Mode. */ -}PWR_PVDTypeDef; -#endif +} PWR_PVDTypeDef; +#endif /* PWR_PVD_SUPPORT */ /** * @} @@ -139,7 +139,7 @@ typedef struct /** * @} */ -#endif +#endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type @@ -177,7 +177,7 @@ typedef struct /** * @} */ -#endif +#endif /* PWR_PVM_SUPPORT */ /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection * @{ @@ -221,7 +221,7 @@ typedef struct #define PWR_GPIO_D (0x00000003u) /*!< GPIO port D */ #if defined (GPIOE) #define PWR_GPIO_E (0x00000004u) /*!< GPIO port E */ -#endif +#endif /* GPIOE */ #define PWR_GPIO_F (0x00000005u) /*!< GPIO port F */ /** * @} @@ -258,7 +258,7 @@ typedef struct */ #if defined(PWR_PVM_SUPPORT) #define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB) /*!< USB Peripheral Voltage Monitoring output */ -#endif +#endif /* PWR_PVM_SUPPORT */ /** * @} */ @@ -369,7 +369,7 @@ typedef struct * @retval None */ #define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD) -#endif +#endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) /** @@ -469,7 +469,7 @@ typedef struct * @retval None */ #define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM) -#endif +#endif /* PWR_PVM_SUPPORT */ /** * @} */ @@ -516,7 +516,7 @@ typedef struct ((__GPIO__) == PWR_GPIO_C) || \ ((__GPIO__) == PWR_GPIO_D) || \ ((__GPIO__) == PWR_GPIO_F)) -#endif +#endif /* GPIOE */ #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \ (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u)) @@ -534,7 +534,7 @@ typedef struct ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || \ ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) -#endif +#endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) #define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB) @@ -546,7 +546,7 @@ typedef struct ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) -#endif +#endif /* PWR_PVM_SUPPORT */ /** * @} */ @@ -566,7 +566,7 @@ void HAL_PWREx_DisableBatteryCharging(void); #if defined(PWR_CR3_ENB_ULP) void HAL_PWREx_EnablePORMonitorSampling(void); void HAL_PWREx_DisablePORMonitorSampling(void); -#endif +#endif /* PWR_CR3_ENB_ULP */ void HAL_PWREx_EnableInternalWakeUpLine(void); void HAL_PWREx_DisableInternalWakeUpLine(void); HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); @@ -578,7 +578,7 @@ void HAL_PWREx_DisablePullUpPullDownConfig(void); #if defined(PWR_CR3_RRS) void HAL_PWREx_EnableSRAMRetention(void); void HAL_PWREx_DisableSRAMRetention(void); -#endif +#endif /* PWR_CR3_RRS */ void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); uint32_t HAL_PWREx_GetVoltageRange(void); @@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWREx_EnablePVD(void); void HAL_PWREx_DisablePVD(void); -#endif +#endif /* PWR_PVD_SUPPORT */ #if defined(PWR_PVM_SUPPORT) /* Power voltage monitoring configuration functions ***************************/ void HAL_PWREx_EnableVddIO2(void); @@ -598,14 +598,14 @@ void HAL_PWREx_DisableVddUSB(void); void HAL_PWREx_EnablePVMUSB(void); void HAL_PWREx_DisablePVMUSB(void); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); -#endif +#endif /* PWR_PVM_SUPPORT */ /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); #if defined(PWR_SHDW_SUPPORT) void HAL_PWREx_EnterSHUTDOWNMode(void); -#endif +#endif /* PWR_SHDW_SUPPORT */ #if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) void HAL_PWREx_PVD_PVM_IRQHandler(void); @@ -615,7 +615,7 @@ void HAL_PWREx_PVD_PVM_Falling_Callback(void); void HAL_PWREx_PVD_IRQHandler(void); void HAL_PWREx_PVD_Rising_Callback(void); void HAL_PWREx_PVD_Falling_Callback(void); -#endif +#endif /* PWR_PVD_SUPPORT && PWR_PVM_SUPPORT */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.c index 8efc348a8f3..2f8d0f70764 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.c @@ -98,7 +98,7 @@ #endif /* RCC_MCO2_SUPPORT */ #define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) /** * @} */ @@ -334,7 +334,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) + || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) { if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { @@ -388,7 +389,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); - if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) + || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) { /* When HSI is used as system clock or as PLL input clock it can not be disabled */ if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) @@ -991,7 +993,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP clock selected as MCO1 source(*) * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ clock selected as MCO1 source(*) * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO1 source(*) - * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*) * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2(*) * @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source(*) * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48(*) @@ -1236,9 +1238,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); - RCC_OscInitStruct->HSIDiv = ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + RCC_OscInitStruct->HSIDiv = (RCC->CR & RCC_CR_HSIDIV); /* Get the LSE configuration -----------------------------------------------*/ if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) @@ -1417,6 +1418,25 @@ __weak void HAL_RCC_LSECSSCallback(void) */ } +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->CSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->CSR |= RCC_CSR_RMVF; + + return reset; +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.h index 0836275045d..aa6856a7c92 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc.h @@ -107,7 +107,10 @@ extern "C" { ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= RCC_PLLM_DIV8) +#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1) || ((__VALUE__) == RCC_PLLM_DIV2) || \ + ((__VALUE__) == RCC_PLLM_DIV3) || ((__VALUE__) == RCC_PLLM_DIV4) || \ + ((__VALUE__) == RCC_PLLM_DIV5) || ((__VALUE__) == RCC_PLLM_DIV6) || \ + ((__VALUE__) == RCC_PLLM_DIV7) || ((__VALUE__) == RCC_PLLM_DIV8)) #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) @@ -119,13 +122,14 @@ extern "C" { #define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) -#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\ + & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ @@ -148,7 +152,7 @@ extern "C" { #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) #endif /* RCC_MCO2_SUPPORT */ -#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ @@ -696,7 +700,7 @@ typedef struct #define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLLPCLK selection as MCO2 source */ #define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0) /*!< PLLQCLK selection as MCO2 source */ #define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1) /*!< RTCCLK selection as MCO2 source */ -#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */ +#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */ /** * @} */ @@ -751,6 +755,11 @@ typedef struct #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ +#if defined(RCC_HSI48_SUPPORT) +/* Flags in the CR register */ +#define RCC_FLAG_HSI48RDY ((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos) /*!< HSI48 Ready flag */ +#endif /* RCC_HSI48_SUPPORT */ + /* Flags in the BDCR register */ #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ @@ -765,11 +774,6 @@ typedef struct #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ -#if defined(RCC_HSI48_SUPPORT) -/* Flags in the CRRCR register */ -#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_RC48RDY_Pos) /*!< HSI48 Ready flag */ -#endif /* RCC_HSI48_SUPPORT */ - /** * @} */ @@ -785,6 +789,23 @@ typedef struct * @} */ +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + /** * @} */ @@ -804,59 +825,59 @@ typedef struct */ #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(DMA2) #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* DMA2 */ #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(RNG) #define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* RNG */ #if defined(AES) #define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* AES */ #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) @@ -884,54 +905,54 @@ typedef struct */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(GPIOE) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* GPIOE */ #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) @@ -955,275 +976,275 @@ typedef struct */ #if defined(TIM2) #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* TIM2 */ #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(TIM4) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* TIM4 */ #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(CRS) #define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* CRS */ #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(SPI3) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* SPI3 */ #define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_USART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(USART5) #define __HAL_RCC_USART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* USART5 */ #if defined(USART6) #define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* USART6 */ #if defined(LPUART1) #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* LPUART1 */ #if defined(LPUART2) #define __HAL_RCC_LPUART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* LPUART2 */ #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(I2C3) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* I2C3 */ #if defined(CEC) #define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* CEC */ #if defined(UCPD1) #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* UCPD1 */ #if defined(UCPD2) #define __HAL_RCC_UCPD2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* UCPD2 */ #if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) #define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ #if defined(FDCAN1) || defined(FDCAN2) #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* FDCAN1 || FDCAN2 */ #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(DAC1) #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* DAC1 */ #if defined(LPTIM2) #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* LPTIM2 */ #if defined(LPTIM1) #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* LPTIM1 */ /** @@ -1239,78 +1260,78 @@ typedef struct */ #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(TIM15) #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0U) #endif /* TIM15 */ #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0U) #define __HAL_RCC_ADC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ - UNUSED(tmpreg); \ - } while(0U) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + UNUSED(tmpreg); \ + } while(0U) #if defined(TIM2) #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) @@ -2585,7 +2606,7 @@ typedef struct CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ } while(0U) - + #if defined(RCC_HSI48_SUPPORT) /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. @@ -2734,18 +2755,18 @@ typedef struct MODIFY_REG(RCC->PLLCFGR, \ (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ - ((uint32_t) (__PLLSOURCE__) | \ - (uint32_t) (__PLLM__) | \ - (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - (uint32_t) (__PLLP__) | \ - (uint32_t) (__PLLQ__) | \ - (uint32_t) (__PLLR__))) + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLQ__) | \ + (uint32_t) (__PLLR__))) #else #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \ MODIFY_REG(RCC->PLLCFGR, \ (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR), \ - ((uint32_t) (__PLLSOURCE__) | \ + ((uint32_t) (__PLLSOURCE__) | \ (uint32_t) (__PLLM__) | \ (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ (uint32_t) (__PLLP__) | \ @@ -2866,7 +2887,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source @if STM32G0C1xx * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 @endif @@ -2878,8 +2899,13 @@ typedef struct * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 - * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 128 - * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 256 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 + @if STM32G0C1xx + * @arg @ref RCC_MCODIV_256 MCO clock source is divided by 256 + * @arg @ref RCC_MCODIV_512 MCO clock source is divided by 512 + * @arg @ref RCC_MCODIV_1024 MCO clock source is divided by 1024 + @endif */ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) @@ -3024,15 +3050,15 @@ typedef struct #if defined(RCC_HSI48_SUPPORT) #define __HAL_RCC_GET_FLAG(__FLAG__) \ (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ + ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #else #define __HAL_RCC_GET_FLAG(__FLAG__) \ (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) #endif /* RCC_HSI48_SUPPORT */ @@ -3080,6 +3106,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void); uint32_t HAL_RCC_GetPCLK1Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +uint32_t HAL_RCC_GetResetSource(void); /* LSE & HSE CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.c index aa2d968236e..fb65ec4dae5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.c @@ -419,7 +419,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /* RCC_CCIPR2_I2S2SEL */ -#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) /*-------------------------- USB clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { @@ -1528,8 +1528,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) /* frequency error counter reached a zero value */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } - } - while (RCC_CRS_NONE == crsstatus); + } while (RCC_CRS_NONE == crsstatus); return crsstatus; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.h index a7ace391976..e3ff99a6a2b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rcc_ex.h @@ -611,8 +611,8 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ + * @{ + */ /** @brief Macro to configure the I2C1 clock (I2C1CLK). @@ -623,7 +623,7 @@ typedef struct * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: @@ -641,7 +641,7 @@ typedef struct * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: @@ -662,10 +662,10 @@ typedef struct */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) #else #define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** @brief Macro to get the I2S1 clock source. * @retval The clock source can be one of the following values: @@ -691,7 +691,7 @@ typedef struct * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock */ #define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__)) /** @brief Macro to get the I2S2 clock source. * @retval The clock source can be one of the following values: @@ -713,7 +713,7 @@ typedef struct * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @@ -735,7 +735,7 @@ typedef struct * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: @@ -758,7 +758,7 @@ typedef struct * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: @@ -781,7 +781,7 @@ typedef struct * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: @@ -804,7 +804,7 @@ typedef struct * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock */ #define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__)) /** @brief Macro to get the LPUART2 clock source. * @retval The clock source can be one of the following values: @@ -827,7 +827,7 @@ typedef struct * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: @@ -850,7 +850,7 @@ typedef struct * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock */ #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) /** @brief Macro to get the LPTIM2 clock source. * @retval The clock source can be one of the following values: @@ -871,7 +871,7 @@ typedef struct * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock */ #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) /** @brief Macro to get the CEC clock source. * @retval The clock source can be one of the following values: @@ -893,7 +893,7 @@ typedef struct * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: @@ -915,7 +915,7 @@ typedef struct * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 */ #define __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__)) /** @brief Macro to get the RNG clock division factor. * @retval The division factor can be one of the following values: @@ -935,7 +935,7 @@ typedef struct * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: @@ -953,7 +953,7 @@ typedef struct * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock */ #define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__)) /** @brief Macro to get the TIM1 clock source. * @retval The clock source can be one of the following values: @@ -971,7 +971,7 @@ typedef struct * @arg RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock */ #define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__)) /** @brief Macro to get the TIM15 clock source. * @retval The clock source can be one of the following values: @@ -991,7 +991,7 @@ typedef struct * (*) Feature not available on all devices */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: @@ -1011,7 +1011,7 @@ typedef struct * @arg RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock */ #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) /** @brief Macro to get the FDCAN clock source. * @retval The clock source can be one of the following values: @@ -1074,15 +1074,15 @@ typedef struct #define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0) + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) /** * @brief Check whether the specified CRS flag is set or not. @@ -1118,15 +1118,15 @@ typedef struct #define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0) + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) #endif /* CRS */ @@ -1248,303 +1248,303 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #if defined(STM32G0C1xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) #elif defined(STM32G0B1xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) #elif defined(STM32G0B0xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) #elif defined(STM32G081xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) #elif defined(STM32G071xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) #elif defined(STM32G070xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G061xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) #elif defined(STM32G051xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) #elif defined(STM32G041xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) #elif defined(STM32G031xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) - -#elif defined(STM32G030xx) || defined(STM32G050xx) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) + +#elif defined(STM32G030xx) || defined(STM32G050xx) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #endif /* STM32G0C1xx */ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) #if defined(RCC_CCIPR_USART2SEL) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) #endif /* RCC_CCIPR_USART2SEL */ #if defined(RCC_CCIPR_USART3SEL) #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) #endif /* RCC_CCIPR_USART3SEL */ #if defined(LPUART1) #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) #endif /* LPUART1 */ #if defined(LPUART2) #define IS_RCC_LPUART2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI)) #endif /* LPUART2 */ #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) #if defined(RCC_CCIPR_I2C2SEL) #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) #endif /* RCC_CCIPR_I2C2SEL */ #define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) + (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) #if defined(RCC_CCIPR2_I2S2SEL) #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT)) + (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT)) #endif /* RCC_CCIPR2_I2S2SEL */ #if defined(RCC_CCIPR_LPTIM1SEL) #define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) #endif /* RCC_CCIPR_LPTIM1SEL */ #if defined(RCC_CCIPR_LPTIM2SEL) #define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) #endif /* RCC_CCIPR_LPTIM2SEL */ #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) + (((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) #if defined(RNG) #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) + (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) #define IS_RCC_RNGDIV(__DIV__) \ - (((__DIV__) == RCC_RNGCLK_DIV1) || \ - ((__DIV__) == RCC_RNGCLK_DIV2) || \ - ((__DIV__) == RCC_RNGCLK_DIV4) || \ - ((__DIV__) == RCC_RNGCLK_DIV8)) + (((__DIV__) == RCC_RNGCLK_DIV1) || \ + ((__DIV__) == RCC_RNGCLK_DIV2) || \ + ((__DIV__) == RCC_RNGCLK_DIV4) || \ + ((__DIV__) == RCC_RNGCLK_DIV8)) #endif /* RNG */ #if defined(CEC) #define IS_RCC_CECCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \ - ((__SOURCE__) == RCC_CECCLKSOURCE_LSE)) + (((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \ + ((__SOURCE__) == RCC_CECCLKSOURCE_LSE)) #endif /* CEC */ #if defined(FDCAN1) || defined(FDCAN2) #define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \ - ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \ - ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) #endif /* FDCAN1 */ #if defined(RCC_HSI48_SUPPORT) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \ - ((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) #else #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) + (((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) #endif /* RCC_HSI48_SUPPORT */ #if defined(RCC_CCIPR_TIM1SEL) #define IS_RCC_TIM1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1)) + (((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1)) #endif /* RCC_CCIPR_TIM1SEL */ #if defined(RCC_CCIPR_TIM15SEL) #define IS_RCC_TIM15CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1)) + (((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1)) #endif /* RCC_CCIPR_TIM15SEL */ #if defined(CRS) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.c index 481824cb3f2..734fe8c9874 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.c @@ -129,8 +129,8 @@ */ /** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and configuration functions - * + * @brief Initialization and configuration functions + * @verbatim =============================================================================== ##### Initialization and configuration functions ##### @@ -301,7 +301,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -318,44 +319,44 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call { switch (CallbackID) { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = pCallback; - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_RNG_STATE_RESET == hrng->State) { switch (CallbackID) { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -393,44 +394,44 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { switch (CallbackID) { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else if (HAL_RNG_STATE_RESET == hrng->State) { switch (CallbackID) { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -520,8 +521,8 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) */ /** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -538,11 +539,11 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) /** * @brief Generates a 32-bit random number. * @note This function checks value of RNG_FLAG_DRDY flag to know if valid - * random number is available in the DR register (RNG_FLAG_DRDY flag set + * random number is available in the DR register (RNG_FLAG_DRDY flag set * whenever a random number is available through the RNG_DR register). - * After transitioning from 0 to 1 (random number available), - * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading - * four words from the RNG_DR register, i.e. further function calls + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls * will immediately return a new u32 random number (additional words are * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). * @note When no more random number data is available in DR register, RNG_FLAG_DRDY @@ -575,11 +576,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -693,6 +698,8 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; } /* Check RNG data ready interrupt occurred */ @@ -738,7 +745,7 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) * @note When RNG_FLAG_DRDY flag value is set, first random number has been read * from DR register in IRQ Handler and is provided as callback parameter. * Depending on valid data available in the conditioning output buffer, - * additional words can be read by the application from DR register till + * additional words can be read by the application from DR register till * DRDY bit remains high. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. @@ -775,8 +782,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -804,7 +811,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @brief Return the RNG handle error code. * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code -*/ + */ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.h index d13c107c0ed..4d9a6f6110e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rng.h @@ -22,7 +22,7 @@ #define STM32G0xx_HAL_RNG_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -81,7 +81,7 @@ typedef enum typedef struct __RNG_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ { RNG_TypeDef *Instance; /*!< Register base address */ @@ -91,7 +91,7 @@ typedef struct __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - __IO uint32_t ErrorCode; /*!< RNG Error code */ + __IO uint32_t ErrorCode; /*!< RNG Error code */ uint32_t RandomNumber; /*!< Last Generated RNG Data */ @@ -171,14 +171,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t /** @defgroup RNG_Error_Definition RNG Error Definition * @{ */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ -#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */ @@ -204,7 +204,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t } while(0U) #else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) -#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enables the RNG peripheral. @@ -299,7 +299,8 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); @@ -346,8 +347,8 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); ((IT) == RNG_IT_SEI)) #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) /** * @brief Verify the RNG Clock Error Detection mode. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.c index 4dae3fb447d..e222b6e7636 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.c @@ -274,7 +274,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ #if defined(TAMP_CR1_TAMP3E) hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ -#endif +#endif /* TAMP_CR1_TAMP3E */ hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /*!< Legacy weak InternalTamper3EventCallback */ hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; /*!< Legacy weak InternalTamper4EventCallback */ hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; /*!< Legacy weak InternalTamper5EventCallback */ @@ -494,7 +494,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = pCallback; break; -#endif +#endif /* TAMP_CR1_TAMP3E */ case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : hrtc->InternalTamper3EventCallback = pCallback; @@ -616,7 +616,7 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca case HAL_RTC_TAMPER3_EVENT_CB_ID : hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ break; -#endif +#endif /* TAMP_CR1_TAMP3E */ case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; /* Legacy weak InternalTamper3EventCallback */ @@ -803,10 +803,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - /* Clear the bits to be configured */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); - /* Configure the RTC_CR register */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ @@ -1833,6 +1833,67 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); } +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +{ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Subtract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +{ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +{ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(hrtc->Instance->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +{ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +{ + return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP); +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.h index e994a19e0bb..818ba797684 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc.h @@ -112,12 +112,11 @@ typedef struct with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, + please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, + please use HAL_RTC_DST_xxx functions */ }RTC_TimeTypeDef; /** @@ -170,7 +169,7 @@ typedef struct typedef struct __RTC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ { RTC_TypeDef *Instance; /*!< Register base address */ @@ -197,7 +196,7 @@ typedef struct #if defined(TAMP_CR1_TAMP3E) void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */ -#endif +#endif /* TAMP_CR1_TAMP3E */ void (* InternalTamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Internal Tamper 3 Event callback */ @@ -230,7 +229,7 @@ typedef enum HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ #if defined(TAMP_CR1_TAMP3E) HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ -#endif +#endif /* TAMP_CR1_TAMP3E */ HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U, /*!< RTC Internal Tamper 3 Callback ID */ HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, /*!< RTC Internal Tamper 4 Callback ID */ HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU, /*!< RTC Internal Tamper 5 Callback ID */ @@ -566,6 +565,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** * @brief Add 1 hour (summer time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions * @param __HANDLE__ specifies the RTC handle. * @param __BKP__ Backup * This parameter can be: @@ -583,6 +584,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** * @brief Subtract 1 hour (winter time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions * @param __HANDLE__ specifies the RTC handle. * @param __BKP__ Backup * This parameter can be: @@ -759,6 +762,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.c index ccf1ff480d9..55dacc3300e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.c @@ -251,12 +251,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Enable IT timestamp */ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); - /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1712,7 +1712,7 @@ void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_Tamper3EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif +#endif /* TAMP_CR1_TAMP3E */ /* Check Internal Tamper3 status */ if((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) @@ -1811,7 +1811,7 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @brief Internal Tamper 3 callback. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.h index ba29c78a5c5..cb0e7505709 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_rtc_ex.h @@ -187,7 +187,7 @@ typedef struct #define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) #else #define RTC_TAMPER_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E) -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -316,7 +316,7 @@ typedef struct #define RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE) #else #define RTC_IT_TAMPALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE) -#endif +#endif /* TAMP_CR1_TAMP3E */ #define RTC_IT_INT_TAMP3 TAMP_IER_ITAMP3IE #define RTC_IT_INT_TAMP4 TAMP_IER_ITAMP4IE @@ -338,7 +338,7 @@ typedef struct #define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3) #else #define RTC_FLAG_TAMPALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2) -#endif +#endif /* TAMP_CR1_TAMP3E */ #define RTC_FLAG_INT_TAMP3 TAMP_SR_ITAMP3F #define RTC_FLAG_INT_TAMP4 TAMP_SR_ITAMP4F #define RTC_FLAG_INT_TAMP5 TAMP_SR_ITAMP5F @@ -985,7 +985,7 @@ void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); #if defined(TAMP_CR1_TAMP3E) void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif +#endif /* TAMP_CR1_TAMP3E */ void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.c index 763b9eabdb0..c437c5b60b1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.c @@ -35,7 +35,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -107,8 +108,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -123,9 +124,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -140,13 +141,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -155,8 +156,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -198,23 +199,24 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ @@ -483,7 +485,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -618,43 +621,45 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma switch (CallbackID) { case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ break; case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -725,62 +730,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (##) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() [..] (#) Non-Blocking mode transfers could be aborted using Abort API's : - (++) HAL_SMARTCARD_Abort() - (++) HAL_SMARTCARD_AbortTransmit() - (++) HAL_SMARTCARD_AbortReceive() - (++) HAL_SMARTCARD_Abort_IT() - (++) HAL_SMARTCARD_AbortTransmit_IT() - (++) HAL_SMARTCARD_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (++) HAL_SMARTCARD_AbortCpltCallback() - (++) HAL_SMARTCARD_AbortTransmitCpltCallback() - (++) HAL_SMARTCARD_AbortReceiveCpltCallback() + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -828,7 +838,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -855,8 +865,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, - Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -864,14 +874,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable the Peripheral first to update mode */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* In case of TX only mode, if NACK is enabled, receiver block has been enabled for Transmit phase. Disable this receiver block. */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); @@ -1001,7 +1011,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -1158,7 +1168,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -1311,7 +1321,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); @@ -1373,8 +1384,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1465,7 +1476,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1505,8 +1517,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1533,14 +1545,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t abortcplt = 1U; - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ /* DMA Tx Handle is valid */ if (hsmartcard->hdmatx != NULL) { @@ -1634,8 +1648,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1767,7 +1781,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1806,8 +1821,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1832,8 +1847,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2304,14 +2319,18 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) { /* Init the SMARTCARD Callback settings */ - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak + RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak + TxFifoEmptyCallback */ } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2327,7 +2346,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the parameters */ @@ -2352,8 +2371,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode; + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2401,17 +2420,21 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: - tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; default: ret = HAL_ERROR; @@ -2572,7 +2595,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -2766,8 +2790,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2815,8 +2839,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2877,8 +2901,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2984,14 +3008,14 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the Peripheral first to update mode */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* In case of TX only mode, if NACK is enabled, receiver block has been enabled for Transmit phase. Disable this receiver block. */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.h index 6040335885c..7b609b10404 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard.h @@ -52,7 +52,8 @@ typedef struct where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -76,13 +77,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -141,14 +143,16 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -159,7 +163,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -176,7 +180,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -215,7 +219,8 @@ typedef struct __SMARTCARD_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. - This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -227,12 +232,14 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -311,23 +318,26 @@ typedef enum /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -335,15 +345,15 @@ typedef enum /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -663,7 +673,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -676,9 +687,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -688,7 +706,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -701,9 +720,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -713,7 +739,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -726,8 +753,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -737,7 +766,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -750,9 +780,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -817,162 +854,6 @@ typedef enum * @{ */ -/** @brief Report the SMARTCARD clock source. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. - */ -#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) -#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) -#else -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) -#endif /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on G0 (64 MHz) @@ -1181,7 +1062,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.c index 0f36ec38162..6047900421b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.c @@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { @@ -472,8 +472,10 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \ + (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \ + (uint16_t)denominator[rx_fifo_threshold]; } } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.h index 8e68a6435bd..1ae3f9f8555 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smartcard_ex.h @@ -196,6 +196,162 @@ extern "C" { * @{ */ +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** @brief Set the Transmission Completion flag * @param __HANDLE__ specifies the SMARTCARD Handle. * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.c index a386ceb5d11..99a24da58eb 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.c @@ -44,35 +44,41 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode + using @ref HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode + using @ref HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() + (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode + using @ref HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode + using @ref HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using + @ref HAL_SMBUS_EnableAlert_IT() or @ref HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() to check the Alert Error Code using function @ref HAL_SMBUS_GetError() (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError() - (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() + (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() to check the Error Code using function @ref HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** @@ -203,7 +209,8 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); @@ -214,7 +221,8 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); /** * @} */ @@ -226,8 +234,8 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -362,15 +370,20 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ - hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ + (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ - hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ + hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ + hsmbus->Init.AnalogFilter); - /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and SMBUS Peripheral is set in Slave mode */ + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ + ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } @@ -579,7 +592,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -692,7 +707,8 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -787,7 +803,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_ * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -858,8 +875,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -911,7 +928,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -950,7 +968,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); } else { @@ -960,9 +980,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Store current volatile XferOptions, misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -971,7 +993,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ @@ -1010,7 +1034,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -1050,7 +1075,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_READ); } else { @@ -1060,9 +1087,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Store current volatile XferOptions, Misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1071,7 +1100,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_READ); } } @@ -1165,7 +1196,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1213,12 +1245,15 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1259,7 +1294,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1303,7 +1339,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } else { @@ -1417,7 +1454,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -1526,8 +1564,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Increment Trials */ SMBUS_Trials++; - } - while (SMBUS_Trials < Trials); + } while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1549,8 +1586,8 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief Handle SMBUS event interrupt request. @@ -1566,7 +1603,13 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1585,7 +1628,13 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1604,7 +1653,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { @@ -1695,7 +1749,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -1744,8 +1799,8 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1771,11 +1826,11 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) } /** -* @brief Return the SMBUS error code. + * @brief Return the SMBUS error code. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. -* @retval SMBUS Error Code -*/ + * @retval SMBUS Error Code + */ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; @@ -1790,7 +1845,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1941,13 +1996,16 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2155,7 +2213,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { @@ -2198,7 +2257,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -2210,13 +2271,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2461,7 +2525,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmperror; /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; @@ -2470,7 +2535,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; @@ -2479,7 +2545,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; @@ -2488,7 +2555,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; @@ -2497,7 +2565,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; @@ -2506,7 +2575,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; @@ -2554,7 +2624,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2674,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2611,8 +2683,13 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.h index ffda0fa1211..b987b8689e1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus.h @@ -48,42 +48,43 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref SMBUS_Analog_Filter */ + This parameter can be a value of @ref SMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. - This parameter can be a value of @ref SMBUS_addressing_mode */ + This parameter can be a value of @ref SMBUS_addressing_mode */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref SMBUS_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref SMBUS_nostretch_mode */ + This parameter can be a value of @ref SMBUS_nostretch_mode */ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref SMBUS_peripheral_mode */ + This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ } SMBUS_InitTypeDef; /** * @} @@ -102,7 +103,7 @@ typedef struct #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -121,7 +122,7 @@ typedef struct #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** @@ -159,17 +160,26 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ - - void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp DeInit callback */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } SMBUS_HandleTypeDef; @@ -195,8 +205,11 @@ typedef enum /** * @brief HAL SMBUS Callback pointer definition */ -typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ -typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); +/*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an SMBUS Address Match callback function */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -358,8 +371,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE #define SMBUS_IT_RXI I2C_CR1_RXIE #define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) -#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ + SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ + SMBUS_IT_RXI) #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) /** @@ -407,14 +422,14 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval None */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) -#endif +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__ specifies the SMBUS Handle. @@ -462,7 +477,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SMBUS flag is set or not. * @param __HANDLE__ specifies the SMBUS Handle. @@ -488,7 +504,9 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -539,15 +557,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ ((MASK) == SMBUS_OA2_MASK01) || \ @@ -565,47 +583,58 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ - ((PEC) == SMBUS_PEC_ENABLE)) + ((PEC) == SMBUS_PEC_ENABLE)) -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ + SMBUS_RELOAD_MODE ))) #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) - - -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) - -#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) + + +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ + I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ + (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) @@ -613,7 +642,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) @@ -623,14 +653,17 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @} */ +/* Include SMBUS HAL Extended module */ +#include "stm32g0xx_hal_smbus_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions * @{ */ /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); @@ -642,10 +675,14 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -653,28 +690,33 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling - * @{ - */ + * @{ + */ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /** * @} */ /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt - * @{ - */ + * @{ + */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); @@ -685,8 +727,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); @@ -703,8 +745,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ + * @{ + */ /* Peripheral State and Errors functions **************************************************/ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.c new file mode 100644 index 00000000000..96d6b4ede1f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.c @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32G0xx + devices contains the following additional features + + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_EnableFastModePlus() + (++) HAL_SMBUSEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using SMBUS_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.h new file mode 100644 index 00000000000..20317c18c71 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_smbus_ex.h @@ -0,0 +1,148 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_SMBUS_EX_H +#define STM32G0xx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define SMBUS_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */ +#define SMBUS_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */ +#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#if defined(SYSCFG_CFGR1_I2C3_FMP) +#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define SMBUS_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /* SYSCFG_CFGR1_I2C3_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions + * @{ + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA9)) == SMBUS_FASTMODEPLUS_PA9) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PA10)) == SMBUS_FASTMODEPLUS_PA10) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32g0xx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_SMBUS_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_spi.c index 6c1147a726c..04598650f08 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_spi.c @@ -987,6 +987,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1153,12 +1158,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { @@ -1170,7 +1181,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -1220,8 +1233,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; #if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; uint32_t spi_cr1; uint32_t spi_cr2; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ @@ -1422,12 +1438,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1439,7 +1461,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -2994,6 +3018,11 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3018,12 +3047,18 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -3033,7 +3068,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -3098,6 +3135,11 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3120,8 +3162,12 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - /* Read CRC to Flush DR and RXNE flag */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } else { @@ -3131,7 +3177,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } #endif /* USE_SPI_CRC */ @@ -3466,8 +3514,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); hspi->CRCSize--; @@ -3574,8 +3629,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3630,8 +3689,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); hspi->CRCSize--; @@ -3684,8 +3750,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3863,11 +3933,16 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); tmp_tickstart = HAL_GetTick(); + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); @@ -3875,8 +3950,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - /* Read 8bit CRC to flush Data Register */ - READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } if (Timeout != HAL_MAX_DELAY) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.c index 08a0f391e3e..cdde80feda5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.c @@ -569,7 +569,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1086,7 +1087,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1107,7 +1109,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1128,7 +1131,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1148,7 +1152,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1726,7 +1731,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1747,7 +1753,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1767,7 +1774,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1787,7 +1795,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2341,6 +2350,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + switch (Channel) { case TIM_CHANNEL_1: @@ -2353,7 +2379,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2373,7 +2400,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2393,7 +2421,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2413,7 +2442,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2427,23 +2457,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - /* Return function status */ return HAL_OK; } @@ -2698,11 +2711,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2734,7 +2748,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2754,11 +2768,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2770,7 +2785,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2796,11 +2811,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2832,7 +2848,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2858,11 +2874,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2880,7 +2897,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -3563,7 +3580,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3588,7 +3606,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3614,7 +3633,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3628,7 +3648,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -6105,115 +6126,143 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; break; case HAL_TIM_BREAK2_CB_ID : - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; break; default : @@ -6227,59 +6276,73 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : @@ -7687,20 +7750,20 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ - htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.h index 60564494718..87b606b2a30 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim.h @@ -65,8 +65,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -218,7 +220,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -268,32 +271,32 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. - This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ - uint32_t Break2State; /*!< TIM Break2 State - This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - uint32_t Break2Polarity; /*!< TIM Break2 input polarity - This parameter can be a value of @ref TIM_Break2_Polarity */ - uint32_t Break2Filter; /*!< TIM break2 input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. - This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + } TIM_BreakDeadTimeConfigTypeDef; /** @@ -671,10 +674,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -934,19 +935,18 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event - (if none of the break inputs BRK and BRK2 is active) */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ -/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 * @{ */ -#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ /** * @} */ @@ -1086,24 +1086,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -1238,7 +1238,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -1405,7 +1406,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. * @param __HANDLE__ TIM handle. * @retval None mode. @@ -1432,8 +1434,8 @@ mode. * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1447,7 +1449,8 @@ mode. /** * @brief Set the TIM Counter Register value on runtime. - * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. * @param __HANDLE__ TIM handle. * @param __COUNTER__ specifies the Counter register new value. @@ -1509,7 +1512,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -2117,12 +2121,18 @@ mode. ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ @@ -2138,10 +2148,14 @@ mode. ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ } while(0) /** @@ -2316,14 +2330,14 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_Sla HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.c index 11d52580920..917ade667e3 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.c @@ -56,10 +56,13 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** @@ -348,7 +351,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -380,7 +384,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -431,7 +436,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -463,7 +469,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -523,7 +530,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ @@ -570,7 +578,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -899,7 +908,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -919,7 +929,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -939,7 +950,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1356,7 +1368,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1376,7 +1389,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1396,7 +1410,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1521,8 +1536,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1531,22 +1548,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); @@ -1562,8 +1585,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1587,8 +1612,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1597,8 +1624,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1607,22 +1636,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -1644,8 +1679,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1675,8 +1712,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2443,15 +2482,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } @@ -2464,15 +2505,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.h index ee6e7f361d1..398151208a8 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_tim_ex.h @@ -71,8 +71,7 @@ typedef struct This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ uint32_t Polarity; /*!< Specifies the break input source polarity. This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ -} -TIMEx_BreakInputConfigTypeDef; +} TIMEx_BreakInputConfigTypeDef; /** * @} @@ -97,7 +96,7 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ #if defined(COMP3) #define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */ -#endif +#endif /* COMP3 */ #if defined(TIM2) #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ #define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ @@ -107,7 +106,7 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */ #define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */ #define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */ -#endif +#endif /* COMP3 */ #endif /* TIM2 */ #if defined(TIM3) #define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ @@ -136,8 +135,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input TIM Extended Break input * @{ */ -#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ -#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ /** * @} */ @@ -160,8 +159,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling * @{ */ -#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ /** * @} */ @@ -169,8 +168,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity * @{ */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ /** * @} */ @@ -262,17 +261,17 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */ #if defined(RCC_MCO2_SUPPORT) #define TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */ -#endif +#endif /* RCC_MCO2_SUPPORT */ #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */ #if defined(RCC_HSI48_SUPPORT) #define TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */ -#endif +#endif /* RCC_HSI48_SUPPORT */ #define TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */ #define TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */ #if defined(RCC_MCO2_SUPPORT) #define TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */ -#endif +#endif /* RCC_MCO2_SUPPORT */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.c index a3a8351dff6..60b366e9492 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.c @@ -177,27 +177,22 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ /* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -227,6 +222,16 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); * @} */ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -1073,7 +1078,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() - (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: (+) HAL_UARTEx_RxEventCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. @@ -1212,8 +1218,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required * to ensure proper alignment for pData. * @param huart UART handle. @@ -1371,7 +1377,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ - SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } else { @@ -1388,7 +1394,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } return HAL_OK; @@ -1405,8 +1411,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pData. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using u16 pointer cast). Depending on compilation chain, * use of specific alignment compilation directives or pragmas might be required * to ensure proper alignment for pData. * @param huart UART handle. @@ -1440,7 +1446,17 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - return(UART_Start_Receive_IT(huart, pData, Size)); + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1528,7 +1544,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1581,7 +1597,17 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - return(UART_Start_Receive_DMA(huart, pData, Size)); + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1605,17 +1631,17 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) (gstate == HAL_UART_STATE_BUSY_TX)) { /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1635,7 +1661,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if (huart->RxState == HAL_UART_STATE_BUSY_RX) { @@ -1643,11 +1669,11 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1676,7 +1702,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel */ if (huart->hdmatx != NULL) @@ -1700,7 +1726,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -1738,20 +1764,20 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | - USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1776,7 +1802,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1839,13 +1865,13 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1897,19 +1923,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1966,14 +1992,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) uint32_t abortcplt = 1U; /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | - USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -2011,7 +2037,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2034,7 +2060,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2116,13 +2142,13 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2206,19 +2232,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2399,7 +2425,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -2460,9 +2486,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check current reception Mode : If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - &&((isrflags & USART_ISR_IDLE) != 0U) - &&((cr1its & USART_ISR_IDLE) != 0U)) + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); @@ -2474,8 +2500,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ( (nb_remaining_rx_data > 0U) - &&(nb_remaining_rx_data < huart->RxXferSize)) + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; @@ -2484,18 +2510,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); @@ -2506,7 +2532,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; } @@ -2516,14 +2542,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ( (huart->RxXferCount > 0U) - &&(nb_rx_data > 0U) ) + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -2532,14 +2558,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; } @@ -2882,7 +2908,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2902,7 +2928,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2931,10 +2957,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); huart->gState = HAL_UART_STATE_READY; @@ -2954,10 +2980,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); huart->gState = HAL_UART_STATE_READY; @@ -3116,7 +3142,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - tmpreg |= (uint32_t)huart->FifoMode; MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -3429,8 +3454,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3449,8 +3475,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3492,7 +3519,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxState = HAL_UART_STATE_BUSY_RX; /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) @@ -3510,8 +3537,8 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else { @@ -3528,7 +3555,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); } return HAL_OK; } @@ -3574,8 +3601,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } @@ -3583,14 +3610,14 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -3604,8 +3631,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, TXFT interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3620,13 +3647,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } /* At end of Rx process, restore huart->RxState to Ready */ @@ -3654,10 +3681,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -3705,12 +3732,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) huart->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3718,7 +3745,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } } @@ -3762,10 +3789,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize/2U); + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -4030,10 +4057,10 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { @@ -4061,10 +4088,10 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { @@ -4095,10 +4122,10 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } @@ -4136,10 +4163,10 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } @@ -4167,7 +4194,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -4205,10 +4232,10 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4220,16 +4247,24 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4242,7 +4277,6 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -4277,10 +4311,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4292,16 +4326,24 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4314,7 +4356,6 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -4399,11 +4440,11 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4415,16 +4456,24 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4437,7 +4486,6 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4449,13 +4497,13 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else @@ -4542,11 +4590,11 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4558,16 +4606,24 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } else { @@ -4580,7 +4636,6 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4592,13 +4647,13 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.h index 48062eec5a5..1bb40276c4e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart.h @@ -46,54 +46,54 @@ extern "C" { */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ } UART_InitTypeDef; @@ -151,7 +151,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -168,7 +168,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -301,8 +301,9 @@ typedef enum /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -342,16 +343,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -1136,10 +1137,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) /** @brief Disable CTS flow control. @@ -1155,10 +1156,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) /** @brief Enable RTS flow control. @@ -1174,10 +1175,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) /** @brief Disable RTS flow control. @@ -1193,10 +1194,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) /** * @} @@ -1570,12 +1571,6 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart /* Include UART HAL Extended module */ #include "stm32g0xx_hal_uart_ex.h" - -/* Prescaler Table used in BRR computation macros. - Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ -extern const uint16_t UARTPrescTable[12]; - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1697,6 +1692,17 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.c index 1164ba827a8..4e17a68e541 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.c @@ -483,7 +483,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -502,7 +502,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -688,29 +688,33 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 } /** - * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. - * @note HAL_OK is returned if reception is completed (expected number of data has been received) - * or if reception is stopped after IDLE event (less than the expected number of data has been received) - * In this case, RxLen output parameter indicates number of data available in reception buffer. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper + * alignment for pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) { uint8_t *pdata8bits; uint16_t *pdata16bits; @@ -832,17 +836,19 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p } /** - * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating - * number of received data elements. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. @@ -884,7 +890,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -905,20 +911,22 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t } /** - * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to DMA services, transferring automatically received data elements in user reception buffer and - * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider - * reception phase as ended. In all cases, callback execution will indicate number of received data elements. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. * @param huart UART handle. * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. @@ -960,7 +968,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1022,8 +1030,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.h index 45b06a4c75d..1f022a88b34 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_uart_ex.h @@ -99,12 +99,12 @@ typedef struct * @brief UART TXFIFO threshold level * @{ */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ @@ -113,12 +113,12 @@ typedef struct * @brief UART RXFIFO threshold level * @{ */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ @@ -174,7 +174,8 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); @@ -654,7 +655,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.c index 37d9ef2fd90..5f2d5440ac8 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode (Receiver/Transmitter) in the husart handle Init structure. @@ -317,7 +318,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ husart->Instance->CR2 &= ~USART_CR2_LINEN; husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); @@ -532,7 +534,7 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US /** * @brief Unregister an USART Callback - * USART callback is redirected to the weak predefined callback + * USART callaback is redirected to the weak predefined callback * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -561,47 +563,47 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ switch (CallbackID) { case HAL_USART_TX_HALFCOMPLETE_CB_ID : - husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_USART_TX_COMPLETE_CB_ID : - husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_USART_RX_HALFCOMPLETE_CB_ID : - husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_USART_RX_COMPLETE_CB_ID : - husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_USART_TX_RX_COMPLETE_CB_ID : - husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ break; case HAL_USART_ERROR_CB_ID : - husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_USART_ABORT_COMPLETE_CB_ID : - husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_USART_RX_FIFO_FULL_CB_ID : - husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_USART_TX_FIFO_EMPTY_CB_ID : - husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -720,13 +722,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -740,7 +745,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pTxData. * @param husart USART handle. * @param pTxData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. @@ -1472,7 +1478,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData. + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pTxData. * @param husart USART handle. * @param pTxData pointer to data buffer (u8 or u16 data elements). * @param Size amount of data elements (u8 or u16) to be sent. @@ -1570,9 +1577,10 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData. + * address of user data buffer for storing data to be received, should be aligned on + * a half word frontier (16 bits) (as received data will be handled by DMA from halfword frontier). + * Depending on compilation chain, use of specific alignment compilation directives or pragmas + * might be required to ensure proper alignment for pRxData. * @param husart USART handle. * @param pRxData pointer to data buffer (u8 or u16 data elements). * @param Size amount of data elements (u8 or u16) to be received. @@ -1701,9 +1709,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits) - * (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData. + * address of user data buffers containing data to be sent/received, should be aligned on a half word frontier + * (16 bits) (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation + * chain, use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pTxData and pRxData. * @param husart USART handle. * @param pTxData pointer to TX data buffer (u8 or u16 data elements). * @param pRxData pointer to RX data buffer (u8 or u16 data elements). @@ -2226,7 +2235,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_UDR)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -2281,6 +2291,14 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->ErrorCode |= HAL_USART_ERROR_ORE; } + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + /* USART SPI slave underrun error interrupt occurred -------------------------*/ if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) { @@ -3032,7 +3050,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8((uint32_t)LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; default: ret = HAL_ERROR; @@ -3543,7 +3561,8 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Clear RxISR function pointer */ @@ -3677,7 +3696,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Clear RxISR function pointer */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.h index 56f9376a6a4..46252505d82 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart.h @@ -48,11 +48,15 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. - @note Oversampling by 8 is systematically applied to achieve high baud rates. */ + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -138,7 +142,7 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value @@ -215,16 +219,17 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @defgroup USART_Error_Definition USART Error Definition * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -260,15 +265,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -349,6 +345,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ #define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ #define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ #define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ @@ -403,6 +400,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -459,6 +457,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -479,6 +478,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -544,9 +544,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -566,10 +569,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) - +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -592,7 +597,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -614,10 +620,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) - +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the USART Handle. @@ -629,6 +638,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None @@ -703,189 +713,9 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKPRESCALER__ USART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief Report the USART clock source. - * @param __HANDLE__ specifies the USART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval the USART clocking source, written in __CLOCKSOURCE__. - */ -#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) -#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART4) \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - } \ - else if((__HANDLE__)->Instance == USART5) \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) -#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) -#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - } \ - else if((__HANDLE__)->Instance == USART4) \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) -#else -#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) -#endif +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. @@ -920,14 +750,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - /** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.c index 1026b317dab..cfba02b802a 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.c @@ -57,10 +57,10 @@ /** @defgroup USARTEx_Private_Constants USARTEx Private Constants * @{ */ -/* UART RX FIFO depth */ +/* USART RX FIFO depth */ #define RX_FIFO_DEPTH 8U -/* UART TX FIFO depth */ +/* USART TX FIFO depth */ #define TX_FIFO_DEPTH 8U /** * @} @@ -503,8 +503,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) { @@ -515,10 +515,14 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; - rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); - tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); - husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; } } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.h index 7f719d35cec..9dacba31b78 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_usart_ex.h @@ -45,9 +45,9 @@ extern "C" { /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ @@ -119,6 +119,186 @@ extern "C" { * @{ */ +/** @brief Report the USART clock source. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** @brief Compute the USART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. * @note If PCE = 1, the parity bit is not included in the data extracted @@ -169,7 +349,6 @@ extern "C" { } \ } while(0U) - /** * @brief Ensure that USART frame length is valid. * @param __LENGTH__ USART frame length. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_wwdg.c index 0e4afecb515..e644895ea60 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 64s + max timeout before reset: approximately 64us (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 524.28ms diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.c index 2de209f6bf2..3b61218f5aa 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -172,7 +172,7 @@ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ ) -#endif +#endif /* TIM15 && TIM6 && TIM2 */ #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ @@ -262,18 +262,18 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) * must be disabled. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()": */ @@ -286,7 +286,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - common to several ADC */ /* (all ADC instances belonging to the same ADC common instance) */ /* - Set ADC clock (conversion clock) */ - LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); + LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); } else { @@ -300,16 +300,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { - /* Set ADC_CommonInitStruct fields to default values */ + /* Set pADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ - ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; } @@ -533,22 +533,22 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); - assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock)); + assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -565,15 +565,15 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) | ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF , - ADC_InitStruct->Resolution - | ADC_InitStruct->DataAlignment - | ADC_InitStruct->LowPowerMode + pADC_InitStruct->Resolution + | pADC_InitStruct->DataAlignment + | pADC_InitStruct->LowPowerMode ); MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE , - ADC_InitStruct->Clock + pADC_InitStruct->Clock ); } else @@ -587,18 +587,18 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) { - /* Set ADC_InitStruct fields to default values */ + /* Set pADC_InitStruct fields to default values */ /* Set fields of ADC instance */ - ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; - ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; } @@ -637,37 +637,37 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); - assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun)); if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); } if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) - || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) ) { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ - assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) - || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } /* Note: Hardware constraint (refer to description of this function): */ @@ -686,7 +686,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) - || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) ) { /* Case of sequencer mode fixed @@ -701,11 +701,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR1_DMACFG | ADC_CFGR1_OVRMOD , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun + pADC_RegInitStruct->TriggerSource + | pADC_RegInitStruct->SequencerDiscont + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun ); } else @@ -722,18 +722,18 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR1_DMACFG | ADC_CFGR1_OVRMOD , - ADC_REG_InitStruct->TriggerSource + pADC_RegInitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun ); } /* Set ADC group regular sequencer length */ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) { - LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength); } } else @@ -746,22 +746,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { - /* Set ADC_REG_InitStruct fields to default values */ + /* Set pADC_RegInitStruct fields to default values */ /* Set fields of ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; - ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; - ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; + pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.h index a72e85518cb..c6eff2c546c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_adc.h @@ -54,14 +54,14 @@ extern "C" { /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ @@ -88,8 +88,8 @@ extern "C" { ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ @@ -101,8 +101,8 @@ extern "C" { /* GPIO pins) and internal channels (connected to internal paths) */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ @@ -211,31 +211,31 @@ extern "C" { /* ADC registers bits positions */ -#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */ -#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ -#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ -#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ -#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ -#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ -#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ -#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ -#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ -#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ -#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ -#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ -#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ -#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ -#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ -#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ -#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ -#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ -#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ -#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ -#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ -#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ -#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */ -#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */ -#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ +#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */ +#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */ +#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ /* ADC registers bits groups */ @@ -330,7 +330,6 @@ typedef struct ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). - This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). For more details, refer to description of this function. */ @@ -618,17 +617,17 @@ typedef struct #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ #if defined(TIM2) #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM2 */ #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ #if defined(TIM4) #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM4 */ #if defined(TIM6) #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM6 */ #if defined(TIM15) #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ -#endif +#endif /* TIM15 */ #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ /** * @} @@ -2368,17 +2367,17 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) + return ((trigger_source + & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN) ); } @@ -2625,21 +2624,21 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) { - __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); - uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; - uint32_t RankIndex; + __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; + uint32_t rank_index; /* Parse register for end of sequence identifier */ - for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U) + for (rank_index = 0UL; rank_index < (32U - 4U); rank_index += 4U) { - if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex)) + if ((channels_ranks & (ADC_CHSELR_SQ2 << rank_index)) == (ADC_CHSELR_SQ2 << rank_index)) { - SequencerLength = (ADC_CHSELR_SQ2 << RankIndex); + sequencer_length = (ADC_CHSELR_SQ2 << rank_index); break; } } - return SequencerLength; + return sequencer_length; } /** @@ -3244,29 +3243,29 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) { - uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); - - return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) + uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) + | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) + | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) + | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) + | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) + | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) + | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) + | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) #if defined(ADC_CCR_VBATEN) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18) -#endif + | (((channels_bitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18) +#endif /* ADC_CCR_VBATEN */ ); } @@ -3771,55 +3770,55 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if (AnalogWDMonitChannels != 0UL) + if (analog_wd_monit_channels != 0UL) { if (AWDy == LL_ADC_AWD1) { - if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL) + if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ((AnalogWDMonitChannels - | (ADC_AWD_CR23_CHANNEL_MASK) - ) - & (~(ADC_CFGR1_AWD1CH)) - ); + analog_wd_monit_channels = ((analog_wd_monit_channels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR1_AWD1CH)) + ); } else { /* AWD monitoring a single channel */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos)) - ); + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos)) + ); } } else { - if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK - | (ADC_CFGR1_AWD1EN) - ); + analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK + | (ADC_CFGR1_AWD1EN) + ); } else { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) - | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos) - ); + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos) + ); } } } - return AnalogWDMonitChannels; + return analog_wd_monit_channels; } /** @@ -4785,7 +4784,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) /** * @brief Enable interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY + * @rmtoll IER CCRDYIE LL_ADC_EnableIT_CCRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ @@ -4895,7 +4894,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) /** * @brief Disable interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY + * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ @@ -5006,7 +5005,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) /** * @brief Get state of interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY + * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ @@ -5122,19 +5121,19 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) /* Initialization of some features of ADC common parameters and multimode */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_bus.h index 2838a65ab58..8d817593a3d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_bus.h @@ -307,7 +307,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset -* @param Periphs This parameter can be a combination of the following values: + * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB1_GRP1_PERIPH_ALL * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.c index f43fd377232..f55461eae93 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.h index bd48912343e..cd027506a48 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_comp.h @@ -158,7 +158,7 @@ typedef struct #define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ #if defined(COMP3) #define LL_COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Available only on devices featuring COMP3 instance. */ -#endif +#endif /* COMP3 */ #define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ /** * @} @@ -328,7 +328,7 @@ typedef struct #else #define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ (COMP12_COMMON) -#endif +#endif /* COMP3 */ /** * @} @@ -379,7 +379,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM window_mode_tmp = LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON; } } -#endif +#endif /* COMP3 */ __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (window_mode_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); @@ -434,7 +434,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy #else const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); -#endif +#endif /* COMP3 */ return (uint32_t)(window_mode_comp_odd | window_mode_comp_even @@ -481,7 +481,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_C /* No modification of other parameters */ } } -#endif +#endif /* COMP3 */ __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, (window_output_tmp & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); @@ -538,7 +538,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(COMP_Common_TypeDef *COMP #else const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT); const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT); -#endif +#endif /* COMP3 */ /* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */ return (uint32_t)(window_output_comp_odd diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_crc.c index 0725c6249f8..d3e6f8eb867 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_crc.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dac.c index 135842ae3aa..035fa494ccf 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dac.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.c index 5499e0c5b86..0aaacba3a79 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -106,7 +106,7 @@ ((CHANNEL) == LL_DMA_CHANNEL_3) || \ ((CHANNEL) == LL_DMA_CHANNEL_4) || \ ((CHANNEL) == LL_DMA_CHANNEL_5)))) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** * @} @@ -165,7 +165,7 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Release reset of DMA clock */ LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); } -#endif +#endif /* DMA2 */ else { status = ERROR; @@ -226,14 +226,14 @@ ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) /* Reset interrupt pending bits for DMAx Channel6 */ LL_DMA_ClearFlag_GI6(DMAx); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) else if (Channel == LL_DMA_CHANNEL_7) { /* Reset interrupt pending bits for DMAx Channel7 */ LL_DMA_ClearFlag_GI7(DMAx); } -#endif +#endif /* DMA1_Channel7 */ else { status = ERROR; diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.h index cedd014b2ee..df9ef63e4cc 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dma.h @@ -54,10 +54,10 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), #if defined(DMA1_Channel6_BASE) (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), -#endif +#endif /* DMA1_Channel6_BASE */ #if defined(DMA1_Channel7_BASE) (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), -#endif +#endif /* DMA1_Channel7_BASE */ }; /** * @} @@ -191,13 +191,13 @@ typedef struct #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ -#endif +#endif /* DMA1_Channel7 */ /** * @} */ @@ -231,13 +231,13 @@ typedef struct #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ -#endif +#endif /* DMA1_Channel7 */ /** * @} */ @@ -263,10 +263,10 @@ typedef struct #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ #if defined(DMA1_Channel6) #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ -#endif +#endif /* DMA1_Channel7 */ #if defined(USE_FULL_LL_DRIVER) #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ #endif /*USE_FULL_LL_DRIVER*/ @@ -387,7 +387,7 @@ typedef struct (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) #else /* DMA1 */ #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) -#endif +#endif /* DMA2 */ /** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y @@ -425,7 +425,7 @@ typedef struct ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ LL_DMA_CHANNEL_5) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** @@ -465,7 +465,7 @@ typedef struct (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ DMA1_Channel5) -#endif +#endif /* DMA1_Channel8 */ #endif /* DMA2 */ /** @@ -1433,7 +1433,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Get Channel 7 global interrupt flag. @@ -1446,7 +1446,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Get Channel 1 transfer complete flag. * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 @@ -1514,7 +1514,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Get Channel 7 transfer complete flag. @@ -1527,7 +1527,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Get Channel 1 half transfer flag. * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 @@ -1595,7 +1595,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Get Channel 7 half transfer flag. @@ -1608,7 +1608,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Get Channel 1 transfer error flag. * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 @@ -1676,7 +1676,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Get Channel 7 transfer error flag. @@ -1689,7 +1689,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Clear Channel 1 global interrupt flag. * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. @@ -1781,7 +1781,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Clear Channel 7 global interrupt flag. @@ -1798,7 +1798,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Clear Channel 1 transfer complete flag. * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 @@ -1866,7 +1866,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Clear Channel 7 transfer complete flag. @@ -1879,7 +1879,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Clear Channel 1 half transfer flag. * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 @@ -1947,7 +1947,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Clear Channel 7 half transfer flag. @@ -1960,7 +1960,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); } -#endif +#endif /* DMA1_Channel7 */ /** * @brief Clear Channel 1 transfer error flag. * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 @@ -2028,7 +2028,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); } -#endif +#endif /* DMA1_Channel6 */ #if defined(DMA1_Channel7) /** * @brief Clear Channel 7 transfer error flag. @@ -2041,7 +2041,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); } -#endif +#endif /* DMA1_Channel7 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dmamux.h index 8a1e80ed7f9..47abaa612c9 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dmamux.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_dmamux.h @@ -70,10 +70,10 @@ extern "C" { #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ #if defined(DMAMUX1_Channel5) #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ -#endif +#endif /* DMAMUX1_Channel5 */ #if defined(DMAMUX1_Channel6) #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ -#endif +#endif /* DMAMUX1_Channel6 */ #if defined(DMA2) #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ @@ -100,10 +100,10 @@ extern "C" { #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ #if defined(DMAMUX1_Channel5) #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ -#endif +#endif /* DMAMUX1_Channel5 */ #if defined(DMAMUX1_Channel6) #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ -#endif +#endif /* DMAMUX1_Channel6 */ #if defined(DMA2) #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ @@ -141,11 +141,11 @@ extern "C" { #if defined(AES) #define LL_DMAMUX_REQ_AES_IN 0x00000006U /*!< DMAMUX AES_IN request */ #define LL_DMAMUX_REQ_AES_OUT 0x00000007U /*!< DMAMUX AES_OUT request */ -#endif +#endif /* AES */ #if defined(DAC1) #define LL_DMAMUX_REQ_DAC1_CH1 0x00000008U /*!< DMAMUX DAC_CH1 request */ #define LL_DMAMUX_REQ_DAC1_CH2 0x00000009U /*!< DMAMUX DAC_CH2 request */ -#endif +#endif /* DAC1 */ #define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */ #define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */ #define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU /*!< DMAMUX I2C2 RX request */ @@ -153,7 +153,7 @@ extern "C" { #if defined(LPUART1) #define LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU /*!< DMAMUX LPUART1 RX request */ #define LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU /*!< DMAMUX LPUART1 TX request */ -#endif +#endif /* LPUART1 */ #define LL_DMAMUX_REQ_SPI1_RX 0x00000010U /*!< DMAMUX SPI1 RX request */ #define LL_DMAMUX_REQ_SPI1_TX 0x00000011U /*!< DMAMUX SPI1 TX request */ #define LL_DMAMUX_REQ_SPI2_RX 0x00000012U /*!< DMAMUX SPI2 RX request */ @@ -171,7 +171,7 @@ extern "C" { #define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU /*!< DMAMUX TIM2 CH4 request */ #define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU /*!< DMAMUX TIM2 TRIG request */ #define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU /*!< DMAMUX TIM2 UP request */ -#endif +#endif /* TIM2 */ #define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U /*!< DMAMUX TIM3 CH1 request */ #define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U /*!< DMAMUX TIM3 CH2 request */ #define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U /*!< DMAMUX TIM3 CH3 request */ @@ -180,16 +180,16 @@ extern "C" { #define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */ #if defined(TIM6) #define LL_DMAMUX_REQ_TIM6_UP 0x00000026U /*!< DMAMUX TIM6 UP request */ -#endif +#endif /* TIM6 */ #if defined(TIM7) #define LL_DMAMUX_REQ_TIM7_UP 0x00000027U /*!< DMAMUX TIM7 UP request */ -#endif +#endif /* TIM7 */ #if defined(TIM15) #define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */ #define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */ #define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */ #define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */ -#endif +#endif /* TIM15 */ #define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */ #define LL_DMAMUX_REQ_TIM16_COM 0x0000002DU /*!< DMAMUX TIM16 COM request */ #define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */ @@ -203,34 +203,34 @@ extern "C" { #if defined(USART3) #define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */ #define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */ -#endif +#endif /* USART3 */ #if defined(USART4) #define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */ #define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */ -#endif +#endif /* USART4 */ #if defined(UCPD1) #define LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU /*!< DMAMUX UCPD1 RX request */ #define LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU /*!< DMAMUX UCPD1 TX request */ -#endif +#endif /* UCPD1 */ #if defined(UCPD2) #define LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU /*!< DMAMUX UCPD2 RX request */ #define LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU /*!< DMAMUX UCPD2 TX request */ -#endif +#endif /* UCPD2 */ #if defined(I2C3) #define LL_DMAMUX_REQ_I2C3_RX 0x0000003EU /*!< DMAMUX I2C3 RX request */ #define LL_DMAMUX_REQ_I2C3_TX 0x0000003FU /*!< DMAMUX I2C3 TX request */ -#endif +#endif /* I2C3 */ #if defined(LPUART2) #define LL_DMAMUX_REQ_LPUART2_RX 0x00000040U /*!< DMAMUX LPUART2 RX request */ #define LL_DMAMUX_REQ_LPUART2_TX 0x00000041U /*!< DMAMUX LPUART2 TX request */ -#endif +#endif /* LPUART2 */ #if defined(SPI3) #define LL_DMAMUX_REQ_SPI3_RX 0x00000042U /*!< DMAMUX SPI3 RX request */ #define LL_DMAMUX_REQ_SPI3_TX 0x00000043U /*!< DMAMUX SPI3 TX request */ -#endif +#endif /* SPI3 */ #if defined(TIM4) #define LL_DMAMUX_REQ_TIM4_CH1 0x00000044U /*!< DMAMUX TIM4 CH1 request */ @@ -239,17 +239,17 @@ extern "C" { #define LL_DMAMUX_REQ_TIM4_CH4 0x00000047U /*!< DMAMUX TIM4 CH4 request */ #define LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U /*!< DMAMUX TIM4 TRIG request */ #define LL_DMAMUX_REQ_TIM4_UP 0x00000049U /*!< DMAMUX TIM4 UP request */ -#endif +#endif /* TIM4 */ #if defined(USART5) #define LL_DMAMUX_REQ_USART5_RX 0x0000004AU /*!< DMAMUX USART5 RX request */ #define LL_DMAMUX_REQ_USART5_TX 0x0000004BU /*!< DMAMUX USART5 TX request */ -#endif +#endif /* USART5 */ #if defined(USART6) #define LL_DMAMUX_REQ_USART6_RX 0x0000004CU /*!< DMAMUX USART6 RX request */ #define LL_DMAMUX_REQ_USART6_TX 0x0000004DU /*!< DMAMUX USART6 TX request */ -#endif +#endif /* USART6 */ #if defined(STM32G0C1xx)||defined(STM32G0B1xx) #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX @@ -261,7 +261,7 @@ extern "C" { #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX #else #define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART2_TX -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @} */ @@ -276,17 +276,17 @@ extern "C" { #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ #if defined(DMAMUX1_Channel5) #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ -#endif +#endif /* DMAMUX1_Channel5 */ #if defined(DMAMUX1_Channel6) #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ -#endif +#endif /* DMAMUX1_Channel6 */ #if defined(DMA2) #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ -#endif +#endif /* DMA2 */ /** * @} */ @@ -327,10 +327,10 @@ extern "C" { #define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ #if defined(LPTIM1) #define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */ -#endif +#endif /* LPTIM1 */ #if defined(LPTIM2) #define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */ -#endif +#endif /* LPTIM2 */ #define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from TIM14 OC */ /** * @} @@ -383,10 +383,10 @@ extern "C" { #define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ #if defined(LPTIM1) #define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */ -#endif +#endif /* LPTIM1 */ #if defined(LPTIM2) #define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */ -#endif +#endif /* LPTIM2 */ #define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from TIM14 OC */ /** * @} @@ -1316,7 +1316,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel5 */ #if defined(DMAMUX1_Channel6) /** * @brief Get Synchronization Event Overrun Flag Channel 6. @@ -1330,7 +1330,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel6 */ #if defined(DMAMUX1_Channel7) /** * @brief Get Synchronization Event Overrun Flag Channel 7. @@ -1344,7 +1344,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel7 */ #if defined(DMAMUX1_Channel8) /** * @brief Get Synchronization Event Overrun Flag Channel 8. @@ -1358,7 +1358,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel8 */ #if defined(DMAMUX1_Channel9) /** * @brief Get Synchronization Event Overrun Flag Channel 9. @@ -1372,7 +1372,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel9 */ #if defined(DMAMUX1_Channel10) /** * @brief Get Synchronization Event Overrun Flag Channel 10. @@ -1386,7 +1386,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel10 */ #if defined(DMAMUX1_Channel11) /** * @brief Get Synchronization Event Overrun Flag Channel 11. @@ -1400,7 +1400,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); } -#endif +#endif /* DMAMUX1_Channel11 */ /** * @brief Get Request Generator 0 Trigger Event Overrun Flag. * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 @@ -1522,7 +1522,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); } -#endif +#endif /* DMAMUX1_Channel5 */ #if defined(DMAMUX1_Channel6) /** * @brief Clear Synchronization Event Overrun Flag Channel 6. @@ -1536,7 +1536,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); } -#endif +#endif /* DMAMUX1_Channel6 */ #if defined(DMAMUX1_Channel7) /** * @brief Clear Synchronization Event Overrun Flag Channel 7. @@ -1550,7 +1550,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); } -#endif +#endif /* DMAMUX1_Channel7 */ #if defined(DMAMUX1_Channel8) /** * @brief Clear Synchronization Event Overrun Flag Channel 8. @@ -1564,7 +1564,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); } -#endif +#endif /* DMAMUX1_Channel8 */ #if defined(DMAMUX1_Channel9) /** * @brief Clear Synchronization Event Overrun Flag Channel 9. @@ -1578,7 +1578,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); } -#endif +#endif /* DMAMUX1_Channel9 */ #if defined(DMAMUX1_Channel10) /** * @brief Clear Synchronization Event Overrun Flag Channel 10. @@ -1592,7 +1592,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); } -#endif +#endif /* DMAMUX1_Channel10 */ #if defined(DMAMUX1_Channel11) /** * @brief Clear Synchronization Event Overrun Flag Channel 11. @@ -1606,7 +1606,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); } -#endif +#endif /* DMAMUX1_Channel11 */ /** * @brief Clear Request Generator 0 Trigger Event Overrun Flag. * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.c index 024de162a08..5128618ccf0 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.c @@ -24,7 +24,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -47,7 +47,7 @@ #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) #define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) @@ -103,7 +103,7 @@ uint32_t LL_EXTI_DeInit(void) #elif defined(STM32G0B0xx) || defined(STM32G070xx) || defined(STM32G050xx) || defined(STM32G030xx) LL_EXTI_WriteReg(RPR1, 0x0000FFFFU); LL_EXTI_WriteReg(FPR1, 0x0000FFFFU); -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ #if defined(STM32G081xx) || defined(STM32G071xx) /* Interrupt mask register 2 set to default reset values */ @@ -129,7 +129,7 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(IMR2, 0x00000010U); /* Event mask register 2 set to default reset values */ LL_EXTI_WriteReg(EMR2, 0x00000000U); -#endif +#endif /* STM32G081xx || STM32G071xx */ return 0x00u; } @@ -149,7 +149,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); @@ -238,7 +238,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) break; } } -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ } /* DISABLE LineCommand */ else @@ -250,7 +250,7 @@ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) /* De-configure EXTI Lines in range from 32 to 63 */ LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ } return status; @@ -266,7 +266,7 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE; -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ EXTI_InitStruct->LineCommand = DISABLE; EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.h index 8b5fa6484fb..8ee8376ef83 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_exti.h @@ -65,7 +65,7 @@ typedef struct #if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 This parameter can be any combination of @ref EXTI_LL_EC_LINE */ -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ @@ -107,68 +107,68 @@ typedef struct #define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ #if defined(EXTI_IMR1_IM16) #define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ -#endif +#endif /* EXTI_IMR1_IM16 */ #if defined(EXTI_IMR1_IM17) #define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ -#endif +#endif /* EXTI_IMR1_IM17 */ #if defined(EXTI_IMR1_IM18) #define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ -#endif +#endif /* EXTI_IMR1_IM18 */ #define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ #if defined(EXTI_IMR1_IM20) #define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ -#endif +#endif /* EXTI_IMR1_IM20 */ #if defined(EXTI_IMR1_IM21) #define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ -#endif +#endif /* EXTI_IMR1_IM21 */ #if defined(EXTI_IMR1_IM22) #define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ -#endif +#endif /* EXTI_IMR1_IM22 */ #define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ #if defined(EXTI_IMR1_IM24) #define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ -#endif +#endif /* EXTI_IMR1_IM24 */ #if defined(EXTI_IMR1_IM25) #define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ -#endif +#endif /* EXTI_IMR1_IM25 */ #if defined(EXTI_IMR1_IM26) #define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ -#endif +#endif /* EXTI_IMR1_IM26 */ #if defined(EXTI_IMR1_IM27) #define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ -#endif +#endif /* EXTI_IMR1_IM27 */ #if defined(EXTI_IMR1_IM28) #define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ -#endif +#endif /* EXTI_IMR1_IM28 */ #if defined(EXTI_IMR1_IM29) #define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ -#endif +#endif /* EXTI_IMR1_IM29 */ #if defined(EXTI_IMR1_IM30) #define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ -#endif +#endif /* EXTI_IMR1_IM30 */ #if defined(EXTI_IMR1_IM31) #define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ -#endif +#endif /* EXTI_IMR1_IM31 */ #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ #if defined(EXTI_IMR2_IM32) #define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ -#endif +#endif /* EXTI_IMR2_IM32 */ #if defined(EXTI_IMR2_IM33) #define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ -#endif +#endif /* EXTI_IMR2_IM33 */ #if defined(EXTI_IMR2_IM34) #define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ -#endif +#endif /* EXTI_IMR2_IM34 */ #if defined(EXTI_IMR2_IM35) #define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ -#endif +#endif /* EXTI_IMR2_IM35 */ #if defined(EXTI_IMR2_IM36) #define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ -#endif +#endif /* EXTI_IMR2_IM36 */ #if defined(EXTI_IMR2_IM32) || defined(EXTI_IMR2_IM33) || defined(EXTI_IMR2_IM34) || defined(EXTI_IMR2_IM35) || defined(EXTI_IMR2_IM36) #define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ -#endif +#endif /* EXTI_IMR2_IM32 || EXTI_IMR2_IM33 || EXTI_IMR2_IM34 || EXTI_IMR2_IM35 || EXTI_IMR2_IM36 */ #define LL_EXTI_LINE_ALL 0xFFFFFFFFU /*!< All Extended line */ @@ -358,7 +358,7 @@ __STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->IMR2, ExtiLine); } -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 @@ -426,7 +426,7 @@ __STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->IMR2, ExtiLine); } -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 @@ -493,7 +493,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @} @@ -564,7 +564,7 @@ __STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->EMR2, ExtiLine); } -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @brief Disable ExtiLine Event request for Lines in range 0 to 31 * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 @@ -686,7 +686,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @} @@ -756,7 +756,7 @@ __STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) SET_BIT(EXTI->RTSR2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 @@ -819,7 +819,7 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) CLEAR_BIT(EXTI->RTSR2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 @@ -865,7 +865,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @} @@ -934,7 +934,7 @@ __STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->FTSR2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 @@ -993,7 +993,7 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) { CLEAR_BIT(EXTI->FTSR2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 @@ -1040,7 +1040,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @} */ @@ -1104,7 +1104,7 @@ __STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) { SET_BIT(EXTI->SWIER2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @} @@ -1163,7 +1163,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 @@ -1214,7 +1214,7 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->FPR2, ExtiLine)); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 @@ -1265,7 +1265,7 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine) { WRITE_REG(EXTI->FPR2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 @@ -1316,7 +1316,7 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine) { return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 @@ -1367,7 +1367,7 @@ __STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine) { return (READ_BIT(EXTI->RPR2, ExtiLine)); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 @@ -1418,7 +1418,7 @@ __STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) { WRITE_REG(EXTI->RPR2, ExtiLine); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.c index 5cada346952..8066f0fdb67 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -89,7 +89,7 @@ ((__VALUE__) == LL_GPIO_AF_5 ) ||\ ((__VALUE__) == LL_GPIO_AF_6 ) ||\ ((__VALUE__) == LL_GPIO_AF_7 )) -#endif +#endif /* GPIOE */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.h index ca4771edf1f..a612ddf7b7f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_gpio.h @@ -200,7 +200,7 @@ typedef struct #define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ #define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ #define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ -#endif +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.c index 1fedaf26c55..0d27cf8f803 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -117,7 +117,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) /* Release reset of I2C clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); } -#endif +#endif /* I2C3 */ else { status = ERROR; diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.h index b8bb7c888fc..0140b88d3db 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_i2c.h @@ -69,38 +69,46 @@ typedef struct uint32_t PeripheralMode; /*!< Specifies the peripheral mode. This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). - This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. - This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. - This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ } LL_I2C_InitTypeDef; /** * @} @@ -170,10 +178,11 @@ typedef struct /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ -#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ -#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} */ @@ -208,14 +217,15 @@ typedef struct /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks * @{ */ -#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ /** * @} */ @@ -250,14 +260,21 @@ typedef struct /** @defgroup I2C_LL_EC_MODE Transfer End Mode * @{ */ -#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ -#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ /** * @} */ @@ -265,14 +282,23 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -280,8 +306,10 @@ typedef struct /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ -#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ /** * @} */ @@ -289,8 +317,10 @@ typedef struct /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ /** * @} */ @@ -298,8 +328,10 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ /** * @} */ @@ -307,9 +339,12 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ -#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ /** * @} */ @@ -353,18 +388,22 @@ typedef struct /** * @brief Configure the SDA setup, hold time and the SCL high, low period. * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) - * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) - * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) - * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -428,7 +467,8 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) * @param AnalogFilter This parameter can be one of the following values: * @arg @ref LL_I2C_ANALOGFILTER_ENABLE * @arg @ref LL_I2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -444,7 +484,8 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt * This filter can only be programmed when the I2C is disabled (PE = 0). * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter * @param I2Cx I2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -583,12 +624,12 @@ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direc if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { /* return address of TXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->TXDR); + data_reg_addr = (uint32_t) &(I2Cx->TXDR); } else { /* return address of RXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->RXDR); + data_reg_addr = (uint32_t) &(I2Cx->RXDR); } return data_reg_addr; @@ -664,7 +705,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) /** * @brief Enable Wakeup from STOP. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @note This bit can only be programmed when Digital Filter is disabled. * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop @@ -678,7 +719,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Disable Wakeup from STOP. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop * @param I2Cx I2C Instance. @@ -691,7 +732,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Check if Wakeup from STOP is enabled or disabled. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop * @param I2Cx I2C Instance. @@ -941,7 +982,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) /** * @brief Configure peripheral mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n * CR1 SMBDEN LL_I2C_SetMode @@ -960,7 +1001,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n * CR1 SMBDEN LL_I2C_GetMode @@ -978,7 +1019,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -996,7 +1037,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -1014,7 +1055,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -1027,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -1040,7 +1081,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -1053,7 +1094,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1066,7 +1107,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n @@ -1089,7 +1130,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA @@ -1104,7 +1145,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA * @param I2Cx I2C Instance. @@ -1117,7 +1158,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode @@ -1134,7 +1175,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode * @param I2Cx I2C Instance. @@ -1149,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB @@ -1164,7 +1205,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB * @param I2Cx I2C Instance. @@ -1177,7 +1218,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout @@ -1195,7 +1236,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock /** * @brief Disable the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout @@ -1213,7 +1254,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout @@ -1226,7 +1267,8 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { - return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1443,7 +1485,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1463,7 +1505,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1645,7 +1687,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1660,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1675,7 +1717,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1782,7 +1824,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1795,7 +1837,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1808,7 +1850,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1923,7 +1965,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) } /** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. * @note Usage in Slave mode only. * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData * @param I2Cx I2C Instance. @@ -1964,7 +2007,8 @@ __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) /** * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead * @param I2Cx I2C Instance. * @retval None @@ -2090,7 +2134,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } @@ -2123,9 +2169,10 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. * This bit has no effect when RELOAD bit is set. * This bit has no effect in device mode when SBC bit is not set. * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare @@ -2139,7 +2186,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -2152,12 +2199,12 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF -*/ + */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_iwdg.h index a4757d2f7d7..77d0ba68ca9 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_iwdg.h @@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) /** * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ @@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.c index 6311512979b..38e604c5715 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.c @@ -28,7 +28,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -48,22 +48,22 @@ * @{ */ #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -259,8 +259,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.h index be278f38d1c..8ea8655d507 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lptim.h @@ -67,22 +67,26 @@ typedef struct uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ uint32_t Prescaler; /*!< Specifies the prescaler division ratio. This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. - This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/ + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ uint32_t Waveform; /*!< Specifies the waveform shape. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ uint32_t Polarity; /*!< Specifies waveform polarity. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ } LL_LPTIM_InitTypeDef; /** @@ -100,9 +104,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -114,13 +118,13 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ /** * @} */ @@ -904,7 +908,8 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) } /** - * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. * @note This function must be called when the LPTIM instance is disabled. * @note When both external clock signal edges are considered active ones, * the LPTIM must also be clocked by an internal clock source with a @@ -1122,7 +1127,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1144,7 +1150,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1166,7 +1173,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1188,7 +1196,8 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). @@ -1340,7 +1349,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) /** * @brief Enable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1351,7 +1360,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Disable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1362,7 +1371,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. - * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ @@ -1373,7 +1382,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Enable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP + * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1384,7 +1393,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP + * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1395,7 +1404,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. - * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP + * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ @@ -1406,7 +1415,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Enable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1417,7 +1426,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1428,7 +1437,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. - * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.c index 629c9d4e055..9f7bb9962ab 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.c @@ -151,7 +151,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) /* Release reset of LPUART peripheral */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART2); } -#endif +#endif /* LPUART2 */ else { status = ERROR; @@ -182,7 +182,7 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; #else uint32_t periphclk; -#endif +#endif /* LPUART2 */ /* Check the parameters */ assert_param(IS_LPUART_INSTANCE(LPUARTx)); @@ -239,7 +239,7 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART } #else periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); -#endif +#endif /* LPUART2 */ /* Configure the LPUART Baud Rate : - prescaler value is required diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.h index 7f00f82d4e2..cb0bb230049 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_lpuart.h @@ -154,16 +154,16 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_WriteReg function * @{ */ -#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -172,27 +172,27 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_ReadReg function * @{ */ -#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ -#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ -#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ -#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ -#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ -#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ /** * @} */ @@ -201,19 +201,21 @@ typedef struct * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions * @{ */ -#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ -#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ -#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ -#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ -#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ /** * @} */ @@ -234,10 +236,10 @@ typedef struct /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ */ -#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ /** * @} */ @@ -245,9 +247,9 @@ typedef struct /** @defgroup LPUART_LL_EC_PARITY Parity Control * @{ */ -#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** * @} */ @@ -255,8 +257,8 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP Wakeup * @{ */ -#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ -#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ /** * @} */ @@ -264,9 +266,9 @@ typedef struct /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth * @{ */ -#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ /** * @} */ @@ -274,18 +276,27 @@ typedef struct /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ -#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ -#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ -#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ -#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ -#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ -#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ -#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ -#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ -#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ -#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ -#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -293,8 +304,8 @@ typedef struct /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ */ -#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ /** * @} */ @@ -302,8 +313,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap * @{ */ -#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} */ @@ -311,8 +322,8 @@ typedef struct /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ -#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} */ @@ -320,8 +331,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ -#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} */ @@ -329,8 +340,11 @@ typedef struct /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ -#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ /** * @} */ @@ -338,8 +352,10 @@ typedef struct /** @defgroup LPUART_LL_EC_BITORDER Bit Order * @{ */ -#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ /** * @} */ @@ -347,8 +363,8 @@ typedef struct /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ -#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} */ @@ -356,10 +372,12 @@ typedef struct /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control * @{ */ -#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ /** * @} */ @@ -367,9 +385,9 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ -#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ -#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ -#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** * @} */ @@ -377,8 +395,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ -#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} */ @@ -386,8 +404,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -559,7 +577,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** @@ -594,7 +612,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** @@ -637,8 +655,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ - (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -651,7 +669,7 @@ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint */ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** @@ -663,7 +681,7 @@ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** @@ -686,7 +704,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); } /** @@ -697,7 +715,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); } /** @@ -708,7 +726,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); } /** @@ -719,7 +737,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); } /** @@ -737,7 +755,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) { - MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -854,7 +872,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); } /** @@ -865,7 +883,7 @@ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); } /** @@ -1928,7 +1946,7 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -1942,7 +1960,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -1953,7 +1971,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -1967,7 +1985,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -1978,7 +1996,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** @@ -1989,7 +2007,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); } /** @@ -2000,7 +2018,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** @@ -2011,7 +2029,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } /** @@ -2026,7 +2044,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** @@ -2037,7 +2055,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** @@ -2048,7 +2066,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } /** @@ -2059,7 +2077,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** @@ -2070,7 +2088,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } /** @@ -2081,7 +2099,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -2095,7 +2113,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -2106,7 +2124,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -2120,7 +2138,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -2131,7 +2149,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** @@ -2142,7 +2160,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); } /** @@ -2153,7 +2171,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** @@ -2164,7 +2182,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } /** @@ -2179,7 +2197,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** @@ -2190,7 +2208,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** @@ -2201,7 +2219,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } /** @@ -2212,7 +2230,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** @@ -2223,7 +2241,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } /** @@ -2391,7 +2409,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** @@ -2402,7 +2420,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** @@ -2424,7 +2442,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** @@ -2435,7 +2453,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.c index 34ab7fc103f..a84c860208d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.c @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.h index b6a8779a6ca..11ef14e0553 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_pwr.h @@ -6,11 +6,11 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * @@ -62,7 +62,7 @@ extern "C" { #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 #if defined(PWR_CR3_EWUP3) #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 -#endif +#endif /* PWR_CR3_EWUP3 */ #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 /** @@ -80,12 +80,12 @@ extern "C" { #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 #if defined(PWR_CR3_EWUP3) #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 -#endif +#endif /* PWR_CR3_EWUP3 */ #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 #if defined(PWR_SR2_PVDO) #define LL_PWR_SR2_PVDO PWR_SR2_PVDO -#endif +#endif /* PWR_SR2_PVDO */ #define LL_PWR_SR2_VOSF PWR_SR2_VOSF #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS @@ -110,7 +110,7 @@ extern "C" { #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1|PWR_CR1_LPMS_0) #if defined (PWR_CR1_LPMS_2) #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2) -#endif +#endif /* PWR_CR1_LPMS_2 */ /** * @} */ @@ -138,7 +138,7 @@ extern "C" { /** * @} */ -#endif +#endif /* PWR_CR2_PVDE */ #if defined(PWR_PVM_SUPPORT) /** @defgroup PWR_LL_EC_PVM_IP PVM_IP @@ -148,8 +148,8 @@ extern "C" { /** * @} */ -#endif - +#endif /* PWR_PVM_SUPPORT */ + /** @defgroup PWR_LL_EC_WAKEUP WAKEUP * @{ */ @@ -157,11 +157,11 @@ extern "C" { #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) #if defined(PWR_CR3_EWUP3) #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) -#endif +#endif /* PWR_CR3_EWUP3 */ #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) #if defined(PWR_CR3_EWUP5) #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) -#endif +#endif /* PWR_CR3_EWUP5 */ #define LL_PWR_WAKEUP_PIN6 (PWR_CR3_EWUP6) /** * @} @@ -185,7 +185,7 @@ extern "C" { #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) #if defined(GPIOE) #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) -#endif +#endif /* GPIOE */ #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) /** * @} @@ -483,9 +483,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) { return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); } -#endif -#if defined(STM32G0C1xx) || defined(STM32G0B1xx) /** * @brief Enable VDDUSB supply * @rmtoll CR2 USV LL_PWR_EnableVddUSB @@ -515,7 +513,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) { return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); } -#endif +#endif /* STM32G0C1xx || STM32G0B1xx */ #if defined (PWR_PVM_SUPPORT) /** @@ -559,7 +557,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) { return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); } -#endif +#endif /* PWR_PVM_SUPPORT */ /** * @brief Set Low-Power mode @@ -691,7 +689,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) { return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR2_PVDE */ /** * @brief Enable Internal Wake-up line @@ -783,7 +781,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAMRetention(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_RRS */ #if defined(PWR_CR3_ENB_ULP) /** @@ -815,7 +813,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnableLPMUResetSamplingMode(void) { return ((READ_BIT(PWR->CR3, PWR_CR3_ENB_ULP) == (PWR_CR3_ENB_ULP)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_ENB_ULP */ /** * @brief Enable the WakeUp PINx functionality @@ -1292,7 +1290,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_EWUP5 */ /** * @brief Get Wake-up Flag 4 @@ -1314,7 +1312,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) { return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); } -#endif +#endif /* PWR_CR3_EWUP3 */ /** * @brief Get Wake-up Flag 2 @@ -1376,7 +1374,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); } -#endif +#endif /* PWR_CR3_EWUP5 */ /** * @brief Clear Wake-up Flag 4 @@ -1398,7 +1396,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) { WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); } -#endif +#endif /* PWR_CR3_EWUP3 */ /** * @brief Clear Wake-up Flag 2 @@ -1431,7 +1429,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMOUSB(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL); } -#endif +#endif /* PWR_PVM_SUPPORT */ #if defined(PWR_SR2_PVDO) /** @@ -1444,7 +1442,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); } -#endif +#endif /* PWR_SR2_PVDO */ /** * @brief Indicate whether the regulator is ready in the selected voltage diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.c index 6460732c316..e3f0120d1fa 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.c @@ -44,32 +44,32 @@ */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) #elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) #else #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE) #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ #if defined(LPUART1) && defined(LPUART2) #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE)) #elif defined(LPUART1) #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) #endif /* LPUART1 && LPUART2 */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) #else #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ #if defined(LPTIM1) || defined(LPTIM2) #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) #endif /* LPTIM1 || LPTIM2 */ #if defined(RNG) @@ -80,7 +80,7 @@ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE)) #else #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ @@ -99,7 +99,7 @@ #if defined(RCC_CCIPR_TIM1SEL) && defined(RCC_CCIPR_TIM15SEL) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE)) #elif defined(RCC_CCIPR_TIM1SEL) #define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)) #endif /* RCC_CCIPR_TIM1SEL */ @@ -114,20 +114,28 @@ /** @defgroup RCC_LL_Private_Functions RCC Private functions * @{ */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -uint32_t RCC_PLL_GetFreqDomain_ADC(void); -uint32_t RCC_PLL_GetFreqDomain_I2S1(void); +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_PLL_GetFreqDomain_SYS(void); +static uint32_t RCC_PLL_GetFreqDomain_ADC(void); +static uint32_t RCC_PLL_GetFreqDomain_I2S1(void); #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) -uint32_t RCC_PLL_GetFreqDomain_I2S2(void); -uint32_t RCC_PLL_GetFreqDomain_USB(void); -uint32_t RCC_PLL_GetFreqDomain_FDCAN(void); +static uint32_t RCC_PLL_GetFreqDomain_I2S2(void); +static uint32_t RCC_PLL_GetFreqDomain_USB(void); #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ -uint32_t RCC_PLL_GetFreqDomain_RNG(void); -uint32_t RCC_PLL_GetFreqDomain_TIM1(void); -uint32_t RCC_PLL_GetFreqDomain_TIM15(void); +#if defined(FDCAN1) || defined(FDCAN2) +static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void); +#endif /* FDCAN1 || FDCAN2 */ +#if defined(RNG) +static uint32_t RCC_PLL_GetFreqDomain_RNG(void); +#endif /* RNG */ +#if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL) +static uint32_t RCC_PLL_GetFreqDomain_TIM1(void); +#endif /* RCC_PLLQ_SUPPORT && RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) +static uint32_t RCC_PLL_GetFreqDomain_TIM15(void); +#endif /* RCC_CCIPR_TIM15SEL */ /** * @} */ @@ -413,6 +421,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) #endif /* RCC_CCIPR_I2C2SEL */ else { + /* nothing to do */ } return i2c_frequency; @@ -513,7 +522,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) if (LPUARTxSource == LL_RCC_LPUART1_CLKSOURCE) { /* LPUART1CLK clock frequency */ - switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) { case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ lpuart_frequency = RCC_GetSystemClockFreq(); @@ -572,7 +581,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) #endif /* LPUART2 */ else { - } + } return lpuart_frequency; } @@ -1004,7 +1013,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) * @brief Return SYSTEM clock frequency * @retval SYSTEM clock frequency (in Hz) */ -uint32_t RCC_GetSystemClockFreq(void) +static uint32_t RCC_GetSystemClockFreq(void) { uint32_t frequency; uint32_t hsidiv; @@ -1035,7 +1044,7 @@ uint32_t RCC_GetSystemClockFreq(void) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK clock frequency (in Hz) */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); @@ -1046,7 +1055,7 @@ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK1 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) { /* PCLK1 clock frequency */ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); @@ -1055,7 +1064,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) +static uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1086,7 +1095,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) * @brief Return PLL clock frequency used for ADC domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_ADC(void) +static uint32_t RCC_PLL_GetFreqDomain_ADC(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1116,7 +1125,7 @@ uint32_t RCC_PLL_GetFreqDomain_ADC(void) * @brief Return PLL clock frequency used for FDCAN domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_FDCAN(void) +static uint32_t RCC_PLL_GetFreqDomain_FDCAN(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1147,7 +1156,7 @@ uint32_t RCC_PLL_GetFreqDomain_FDCAN(void) * @brief Return PLL clock frequency used for I2S1 domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_I2S1(void) +static uint32_t RCC_PLL_GetFreqDomain_I2S1(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1177,7 +1186,7 @@ uint32_t RCC_PLL_GetFreqDomain_I2S1(void) * @brief Return PLL clock frequency used for I2S2 domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_I2S2(void) +static uint32_t RCC_PLL_GetFreqDomain_I2S2(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1208,7 +1217,7 @@ uint32_t RCC_PLL_GetFreqDomain_I2S2(void) * @brief Return PLL clock frequency used for RNG domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_RNG(void) +static uint32_t RCC_PLL_GetFreqDomain_RNG(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1240,7 +1249,7 @@ uint32_t RCC_PLL_GetFreqDomain_RNG(void) * @brief Return PLL clock frequency used for USB domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_USB(void) +static uint32_t RCC_PLL_GetFreqDomain_USB(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1267,12 +1276,12 @@ uint32_t RCC_PLL_GetFreqDomain_USB(void) } #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ -#if defined(RCC_PLLQ_SUPPORT) +#if defined(RCC_PLLQ_SUPPORT) && defined(RCC_CCIPR_TIM1SEL) /** * @brief Return PLL clock frequency used for TIM1 domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_TIM1(void) +static uint32_t RCC_PLL_GetFreqDomain_TIM1(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1299,12 +1308,12 @@ uint32_t RCC_PLL_GetFreqDomain_TIM1(void) } #endif /* RCC_PLLQ_SUPPORT */ -#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15) +#if defined(RCC_CCIPR_TIM15SEL) /** * @brief Return PLL clock frequency used for TIM15 domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_TIM15(void) +static uint32_t RCC_PLL_GetFreqDomain_TIM15(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1329,7 +1338,7 @@ uint32_t RCC_PLL_GetFreqDomain_TIM15(void) return __LL_RCC_CALC_PLLCLK_TIM15_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); } -#endif /* RCC_PLLQ_SUPPORT && TIM15 */ +#endif /* RCC_CCIPR_TIM15SEL */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.h index da063f40173..fdc11b35aea 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rcc.h @@ -495,7 +495,7 @@ typedef struct /** * @} -*/ + */ #endif /* CEC */ #if defined(FDCAN1) || defined(FDCAN2) @@ -508,7 +508,7 @@ typedef struct /** * @} -*/ + */ #endif /* FDCAN1 || FDCAN2 */ #if defined(RNG) @@ -857,7 +857,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) + (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) /** * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain @@ -910,7 +910,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) #if defined(RCC_CCIPR2_I2S2SEL) /** @@ -964,7 +964,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) #endif /* RCC_CCIPR2_I2S2SEL */ /** @@ -1018,7 +1018,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) #if defined(RNG) /** @@ -1048,7 +1048,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) #endif /* RNG */ #if defined(RCC_PLLQ_SUPPORT) @@ -1079,7 +1079,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) #if defined(TIM15) /** * @brief Helper macro to calculate the PLLQCLK frequency used on TIM15 domain @@ -1108,7 +1108,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) #endif /* TIM15 */ #endif /* RCC_PLLQ_SUPPORT */ @@ -1140,7 +1140,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) #endif /* FDCAN1 || FDCAN2 */ #if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) @@ -1171,7 +1171,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ - (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** @@ -2083,7 +2083,7 @@ __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) } #endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ -#if defined (FDCAN1) || defined (FDCAN2) +#if defined (FDCAN1) || defined (FDCAN2) /** * @brief Configure FDCAN clock source * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.c index f9690a0c4d2..926553b6ec2 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -42,7 +42,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup RNG_LL_Private_Macros +/** @defgroup RNG_LL_Private_Macros RNG Private Macros * @{ */ #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.h index 7270bf80bb9..e8a090aabf8 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rng.h @@ -57,8 +57,8 @@ typedef struct { uint32_t ClockErrorDetection; /*!< Clock error detection. This parameter can be one value of @ref RNG_LL_CED. - - This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */ + This parameter can be modified using unitary + functions @ref LL_RNG_EnableClkErrorDetect(). */ } LL_RNG_InitTypeDef; /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.c index dd4c80033d9..cdb70398bfd 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -87,18 +87,7 @@ #define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) -#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ - || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ - || ((__VALUE__) == LL_RTC_MONTH_MAY) \ - || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ - || ((__VALUE__) == LL_RTC_MONTH_JULY) \ - || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ - || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ - || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h index 5a4d518d489..6b8160b8a7f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h @@ -424,7 +424,7 @@ typedef struct #define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ #if defined (TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -436,7 +436,7 @@ typedef struct #define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ #if defined (TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */ -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -448,7 +448,7 @@ typedef struct #define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ #if defined (TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -497,7 +497,7 @@ typedef struct #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ #if defined (TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -3102,7 +3102,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) { - __IO uint32_t *tmp; + const __IO uint32_t *tmp; tmp = &(TAMPx->BKP0R) + BackupRegister; @@ -3573,7 +3573,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL); } -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @brief Get internal tamper 3 detection flag. * @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3 @@ -3652,7 +3652,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL); } -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @brief Get internal tamper 3 interrupt masked flag. @@ -3732,7 +3732,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx) { SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F); } -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @brief Clear internal tamper 3 detection flag. @@ -3993,7 +3993,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx) { CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE); } -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @brief Enable internal tamper 3 interrupt. @@ -4117,7 +4117,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL); } -#endif +#endif /* TAMP_CR1_TAMP3E */ /** * @brief Check if internal tamper 3 interrupt is enabled or not. diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.c index 2402a0b75ac..87eb7d38047 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.c @@ -27,7 +27,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G0xx_LL_Driver * @{ @@ -233,6 +233,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) SPI_CR2_DS | SPI_CR2_SSOE, SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + } + /*---------------------------- SPIx CRCPR Configuration ---------------------- * Configure SPIx CRCPR with parameters: * - CRCPoly: CRCPOLY[15:0] bits diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.h index bba313a9896..ca2ce61a4ea 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_spi.h @@ -1333,7 +1333,7 @@ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) { - return (uint8_t)(READ_REG(SPIx->DR)); + return (*((__IO uint8_t *)&SPIx->DR)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.c index 52d52831a0d..52335a8d4a0 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.c @@ -238,35 +238,35 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } -#endif +#endif /* TIM2 */ #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } -#endif +#endif /* TIM3 */ #if defined(TIM4) else if (TIMx == TIM4) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); } -#endif +#endif /* TIM4 */ #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } -#endif +#endif /* TIM6 */ #if defined(TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } -#endif +#endif /* TIM7 */ else if (TIMx == TIM14) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM14); @@ -278,7 +278,7 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); } -#endif +#endif /* TIM15 */ else if (TIMx == TIM16) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); @@ -290,7 +290,7 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); } -#endif +#endif /* TIM17 */ else { result = ERROR; @@ -318,7 +318,8 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -371,7 +372,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Set the fields of the TIMx output channel configuration data * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) * @retval None */ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) @@ -397,7 +399,8 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * @arg @ref LL_TIM_CHANNEL_CH4 * @arg @ref LL_TIM_CHANNEL_CH5 * @arg @ref LL_TIM_CHANNEL_CH6 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized @@ -436,7 +439,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy /** * @brief Set the fields of the TIMx input channel configuration data * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) * @retval None */ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) @@ -456,7 +460,8 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized @@ -488,7 +493,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy /** * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) * @retval None */ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) @@ -508,7 +514,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct /** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -572,7 +579,8 @@ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *T /** * @brief Set the fields of the TIMx Hall sensor interface configuration data * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) * @retval None */ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) @@ -599,7 +607,8 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable @@ -679,7 +688,8 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType /** * @brief Set the fields of the Break and Dead Time configuration data structure * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval None */ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) @@ -711,7 +721,8 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.h index 2acc314079d..c05a90247ae 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_tim.h @@ -214,24 +214,29 @@ typedef struct uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts @@ -239,10 +244,13 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; /** @@ -253,43 +261,51 @@ typedef struct uint32_t OCMode; /*!< Specifies the output mode. This parameter can be a value of @ref TIM_LL_EC_OCMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ uint32_t OCState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ } LL_TIM_OC_InitTypeDef; /** @@ -302,22 +318,26 @@ typedef struct uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t ICActiveInput; /*!< Specifies the input. This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_IC_InitTypeDef; @@ -329,47 +349,56 @@ typedef struct uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC2Filter; /*!< Specifies the TI2 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_ENCODER_InitTypeDef; @@ -382,26 +411,31 @@ typedef struct uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; /** @@ -412,97 +446,121 @@ typedef struct uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_LL_EC_OSSR - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE - This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() @note Bidirectional break input is only supported by advanced timers instances. - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE - This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() @note Bidirectional break input is only supported by advanced timers instances. - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ } LL_TIM_BDTR_InitTypeDef; /** @@ -596,8 +654,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -1141,7 +1199,7 @@ typedef struct #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */ #if defined(COMP1) #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */ -#endif +#endif /* COMP1 */ /** * @} */ @@ -1152,7 +1210,7 @@ typedef struct #define LL_TIM_TIM1_TI2_RMP_GPIO 0x00000000U /*!< TIM1 input 2 is connected to GPIO */ #if defined(COMP2) #define LL_TIM_TIM1_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM1 input 2 is connected to COMP2_OUT */ -#endif +#endif /* COMP2 */ /** * @} */ @@ -1163,7 +1221,7 @@ typedef struct #define LL_TIM_TIM1_TI3_RMP_GPIO 0x00000000U /*!< TIM1 input 3 is connected to GPIO */ #if defined(COMP3) #define LL_TIM_TIM1_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM1 input 3 is connected to COMP3_OUT */ -#endif +#endif /* COMP3 */ /** * @} */ @@ -1193,11 +1251,11 @@ typedef struct #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */ #if defined(COMP3) #define LL_TIM_TIM2_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP3_OUT */ -#endif +#endif /* COMP3 */ /** * @} */ -#endif +#endif /* TIM2 */ /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap * @{ @@ -1205,7 +1263,7 @@ typedef struct #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */ #if defined(COMP1) #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */ -#endif +#endif /* COMP1 */ /** * @} */ @@ -1216,7 +1274,7 @@ typedef struct #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */ #if defined(COMP2) #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP2_OUT */ -#endif +#endif /* COMP2 */ /** * @} */ @@ -1227,7 +1285,7 @@ typedef struct #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */ #if defined(COMP3) #define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */ -#endif +#endif /* COMP3 */ /** * @} */ @@ -1239,7 +1297,7 @@ typedef struct #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */ #if defined(COMP1) #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */ -#endif +#endif /* COMP1 */ /** * @} */ @@ -1250,7 +1308,7 @@ typedef struct #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */ #if defined(COMP2) #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP2_OUT */ -#endif +#endif /* COMP2 */ /** * @} */ @@ -1261,11 +1319,11 @@ typedef struct #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */ #if defined(COMP3) #define LL_TIM_TIM4_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP3_OUT */ -#endif +#endif /* COMP3 */ /** * @} */ -#endif +#endif /* TIM4 */ /** @defgroup TIM_LL_EC_TIM14_TI1_RMP TIM14 Timer Input Ch1 Remap * @{ @@ -1286,11 +1344,11 @@ typedef struct #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */ #if defined(TIM2) #define LL_TIM_TIM15_TI1_RMP_TIM2_IC1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 input 1 */ -#endif +#endif /* TIM2 */ #if defined(TIM3) #define LL_TIM_TIM15_TI1_RMP_TIM3_IC1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 input 1 */ -#endif -#endif +#endif /* TIM3 */ +#endif /* TIM15 */ /** * @} */ @@ -1302,11 +1360,11 @@ typedef struct #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */ #if defined(TIM2) #define LL_TIM_TIM15_TI2_RMP_TIM2_IC2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to TIM2 input 2 */ -#endif +#endif /* TIM2 */ #if defined(TIM3) #define LL_TIM_TIM15_TI2_RMP_TIM3_IC2 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 2 is connected to TIM3 input 2 */ -#endif -#endif +#endif /* TIM3 */ +#endif /* TIM15 */ /** * @} */ @@ -1418,10 +1476,17 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -1446,7 +1511,8 @@ typedef struct ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1458,7 +1524,8 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1669,7 +1736,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo */ __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** @@ -1706,7 +1782,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) } /** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1724,7 +1801,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi } /** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1866,7 +1944,8 @@ __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) /** * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap * @param TIMx Timer instance * @retval None @@ -2171,7 +2250,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } /** @@ -2210,7 +2289,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } /** @@ -2588,7 +2667,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -2855,7 +2935,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); } @@ -3526,7 +3607,7 @@ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) } #else MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); -#endif +#endif /* COMP3 */ } /** @@ -4430,7 +4511,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4452,7 +4534,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4474,7 +4557,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). @@ -4496,7 +4580,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.c index 12863dc86ab..362023a565b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.c @@ -66,9 +66,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -203,8 +200,9 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /** * @brief Initialize USART registers according to the specified * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure @@ -217,9 +215,9 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; -#if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||!defined(RCC_CCIPR_USART2SEL) ||!defined(RCC_CCIPR_USART5SEL) ||!defined(RCC_CCIPR_USART6SEL) +#if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||(!defined(RCC_CCIPR_USART2SEL))||!defined(RCC_CCIPR_USART5SEL)||!defined(RCC_CCIPR_USART6SEL) LL_RCC_ClocksTypeDef RCC_Clocks; -#endif /* !RCC_CCIPR_USART3SEL && !RCC_CCIPR_USART4SEL || !RCC_CCIPR_USART2SEL */ +#endif /* Check the parameters */ assert_param(IS_UART_INSTANCE(USARTx)); @@ -258,7 +256,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); @@ -277,7 +276,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* USART2 clock is PCLK */ LL_RCC_GetSystemClocksFreq(&RCC_Clocks); periphclk = RCC_Clocks.PCLK1_Frequency; -#endif /* RCC_CCIPR_USART2SEL */ +#endif } #if defined(USART3) else if (USARTx == USART3) @@ -288,7 +287,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* USART3 clock is PCLK */ LL_RCC_GetSystemClocksFreq(&RCC_Clocks); periphclk = RCC_Clocks.PCLK1_Frequency; -#endif /* RCC_CCIPR_USART3SEL */ +#endif } #endif /* USART3 */ #if defined(USART4) @@ -341,9 +340,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } /*---------------------------- USART PRESC Configuration ----------------------- @@ -380,13 +376,15 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) /** * @brief Initialize USART Clock related settings according to the * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) @@ -401,37 +399,25 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); - - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); } /* Else (USART not in Disabled state => return ERROR */ else @@ -452,9 +438,12 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { /* Set LL_USART_ClockInitStruct fields with default values */ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.h index e78dd5ccbaa..241c25b215a 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usart.h @@ -88,41 +88,49 @@ typedef struct uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref USART_LL_EC_PRESCALER. - This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ } LL_USART_InitTypeDef; @@ -141,20 +149,23 @@ typedef struct uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_LL_EC_POLARITY. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). For more details, refer to description of this function. */ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_LL_EC_PHASE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). For more details, refer to description of this function. */ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function. */ } LL_USART_ClockInitTypeDef; @@ -173,21 +184,21 @@ typedef struct * @brief Flags defines which can be used with LL_USART_WriteReg function * @{ */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ -#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -563,8 +574,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -586,8 +598,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @} @@ -699,7 +712,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** @@ -738,7 +751,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** @@ -785,7 +798,8 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -800,7 +814,7 @@ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32 */ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); } /** @@ -814,7 +828,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); } /** @@ -838,7 +852,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -849,7 +863,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -860,7 +874,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -871,7 +885,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -889,7 +903,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) { - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -1008,7 +1022,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); } /** @@ -1019,7 +1033,7 @@ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); } /** @@ -1870,6 +1884,10 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph { /* Do not overstep the size of USART_PRESCALER_TAB */ } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } else if (OverSampling == LL_USART_OVERSAMPLING_8) { usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); @@ -2651,7 +2669,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) { /* In Asynchronous mode, the following bits must be kept cleared: - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); } @@ -2687,7 +2706,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) { /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); /* set the UART/USART in Synchronous mode */ @@ -2727,7 +2747,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) { /* In LIN mode, the following bits must be kept cleared: - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); /* Set the UART/USART in LIN mode */ @@ -2765,7 +2786,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) { /* In Half Duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ + - SCEN and IREN bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); /* set the UART/USART in Half Duplex mode */ @@ -2805,7 +2827,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) { /* In Smartcard mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register.*/ + - IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); /* Configure Stop bits to 1.5 bits */ @@ -2848,7 +2871,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) { /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ + - SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); /* set the UART/USART in IRDA mode */ @@ -2886,7 +2910,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) { /* In Multi Processor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); } @@ -3434,7 +3459,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -3450,7 +3475,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -3461,7 +3486,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -3477,7 +3502,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -3488,7 +3513,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -3499,7 +3524,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_CMIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); } /** @@ -3510,7 +3535,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RTOIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); } /** @@ -3523,7 +3548,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_EOBIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); } /** @@ -3536,7 +3561,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); } /** @@ -3547,7 +3572,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); } /** @@ -3575,7 +3600,7 @@ __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -3588,7 +3613,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -3601,7 +3626,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_WUFIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); } /** @@ -3614,7 +3639,7 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); } /** @@ -3627,7 +3652,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } /** @@ -3640,7 +3665,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); } /** @@ -3651,7 +3676,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -3667,7 +3692,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -3678,7 +3703,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -3694,7 +3719,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -3705,7 +3730,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -3716,7 +3741,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); } /** @@ -3727,7 +3752,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); } /** @@ -3740,7 +3765,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); } /** @@ -3753,7 +3778,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); } /** @@ -3766,7 +3791,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); } /** @@ -3794,7 +3819,7 @@ __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -3807,7 +3832,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -3820,7 +3845,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); } /** @@ -3833,7 +3858,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); } /** @@ -3846,7 +3871,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } /** @@ -3859,7 +3884,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); } /** @@ -4093,7 +4118,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -4104,7 +4129,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -4126,7 +4151,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -4137,7 +4162,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.c index 4867b978b24..a83ddc8ee81 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.c @@ -26,7 +26,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -489,22 +489,73 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* manage isochronous double buffer IN mode */ else { - /* Write the data to the USB endpoint */ + /* enable double buffer */ + PCD_SET_EP_DBUF(USBx, ep->num); + + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + if (len > 0U) + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; - } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + if (len > 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } + } } } @@ -630,7 +681,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) return HAL_OK; } -#endif +#endif /* HAL_PCD_MODULE_ENABLED */ /** * @brief USB_StopDevice Stop the usb device mode @@ -774,7 +825,6 @@ void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr /* When Number of data is not word aligned, write the remaining Byte */ if (remaining_bytes != 0U) { - count = 0U; tmp = 0U; do @@ -831,14 +881,13 @@ void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, /*When Number of data is not word aligned, read the remaining byte*/ if (remaining_bytes != 0U) { - count = 0U; tmp = *(__IO uint32_t *)pdwVal; do { *(uint8_t *)pBuf = (uint8_t)(tmp >> (8U * (uint8_t)(count))); count++; pBuf++; - remaining_bytes-- ; + remaining_bytes--; } while (remaining_bytes != 0U); } } @@ -859,11 +908,10 @@ void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) { UNUSED(cfg); + /* Clear All Pending Interrupt */ USBx->ISTR = 0U; - HAL_Delay(200); - /* Disable all interrupts */ USBx->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | @@ -872,7 +920,7 @@ HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) /* Clear All Pending Interrupt */ USBx->ISTR = 0U; - /*Enable Global interrupt */ + /* Enable Global interrupt */ USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); @@ -908,8 +956,8 @@ HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx) * @param USBx Selected device * @retval speed Host speed * This parameter can be one of these values - * @arg USB_DRD_SPEED_FULL Full speed mode - * @arg USB_DRD_SPEED_LOW Low speed mode + * @arg USB_DRD_SPEED_FS Full speed mode + * @arg USB_DRD_SPEED_LS Low speed mode */ uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx) { @@ -989,6 +1037,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, { HAL_StatusTypeDef ret = HAL_OK; uint32_t wChRegVal; + uint32_t HostCoreSpeed; wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; @@ -1020,8 +1069,11 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | ((uint32_t)epnum & 0x0FU)); + /* Get Host core Speed */ + HostCoreSpeed = USB_GetHostSpeed(USBx); + /* Set the device speed in case using HUB FS with device LS */ - if (speed == USB_DRD_SPEED_LSFS) + if ((speed == USB_DRD_SPEED_LS) && (HostCoreSpeed == USB_DRD_SPEED_FS)) { wChRegVal |= USB_CHEP_LSEP; } @@ -1029,7 +1081,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, /* Set the dev_address & ep type */ USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); - /*Set the Rx Count */ + /* Set the Rx Count */ USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, mps); return ret; @@ -1245,7 +1297,6 @@ static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, /* Multi packet transfer */ if (hc->xfer_len_db > hc->max_packet) { - *len = hc->max_packet; hc->xfer_len_db -= *len; } else diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.h index add322f448f..058bcf555c9 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_usb.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2018 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -103,12 +103,13 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -137,7 +138,7 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint16_t pmaadress; /*!< PMA Address This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ @@ -185,11 +186,12 @@ typedef struct uint8_t ch_dir; /*!< channel direction This parameter store the physical channel direction IN/OUT/BIDIR */ - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -323,7 +325,8 @@ typedef struct /*Set Channel/Endpoint to the USB Register */ -#define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) +#define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ + (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) /*Get Channel/Endpoint from the USB Register */ #define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) @@ -464,8 +467,11 @@ typedef struct * @param bEpChNum Endpoint Number. * @retval status */ -#define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) -#define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) +#define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum))\ + & USB_DRD_CHEP_TX_STTX) + +#define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum))\ + & USB_DRD_CHEP_RX_STRX) /** @@ -695,8 +701,11 @@ typedef struct } while(0) -#define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) -#define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) +#define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF\ + + (bEpChNum))->TXBD), (wCount)) + +#define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF\ + + (bEpChNum))->RXBD), (wCount)) /** @@ -824,7 +833,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDe HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -#endif +#endif /* HAL_PCD_MODULE_ENABLED */ HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_utils.h index a791567b71a..b7987b6a535 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_utils.h @@ -178,7 +178,7 @@ typedef struct #define LL_UTILS_PACKAGETYPE_QFN32_PD 0x00000005U /*!< UFQFPN32 / LQFP32 Power Delivery (PD) package type */ #define LL_UTILS_PACKAGETYPE_QFN48 0x00000008U /*!< UFQFPN48 / LQFP488 package type */ #define LL_UTILS_PACKAGETYPE_QFP64 0x0000000CU /*!< LQPF64 package type */ -#endif +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @} */ @@ -274,7 +274,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); #else return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0xFU); -#endif +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/stm32g0xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/stm32g0xx_hal_conf.h index a2107edb89b..d560bf75434 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/stm32g0xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/stm32g0xx_hal_conf.h @@ -73,83 +73,63 @@ extern "C" { #if !defined (USE_HAL_ADC_REGISTER_CALLBACKS) #define USE_HAL_ADC_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_CEC_REGISTER_CALLBACKS) #define USE_HAL_CEC_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_COMP_REGISTER_CALLBACKS) #define USE_HAL_COMP_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS) #define USE_HAL_CRYP_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_DAC_REGISTER_CALLBACKS) #define USE_HAL_DAC_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_FDCAN_REGISTER_CALLBACKS) #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_I2C_REGISTER_CALLBACKS) #define USE_HAL_I2C_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_I2S_REGISTER_CALLBACKS) #define USE_HAL_I2S_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS) #define USE_HAL_IRDA_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS) #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_HCD_REGISTER_CALLBACKS) #define USE_HAL_HCD_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_PCD_REGISTER_CALLBACKS) #define USE_HAL_PCD_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_RNG_REGISTER_CALLBACKS) #define USE_HAL_RNG_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_RTC_REGISTER_CALLBACKS) #define USE_HAL_RTC_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_SPI_REGISTER_CALLBACKS) #define USE_HAL_SPI_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_TIM_REGISTER_CALLBACKS) #define USE_HAL_TIM_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_UART_REGISTER_CALLBACKS) #define USE_HAL_UART_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_USART_REGISTER_CALLBACKS) #define USE_HAL_USART_REGISTER_CALLBACKS 0u #endif - #if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS) #define USE_HAL_WWDG_REGISTER_CALLBACKS 0u #endif @@ -189,7 +169,7 @@ extern "C" { #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ -#endif +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /** * @brief Internal Low Speed oscillator (LSI) value. @@ -229,7 +209,7 @@ in voltage and temperature.*/ #if !defined (EXTERNAL_I2S2_CLOCK_VALUE) #define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/ #endif /* EXTERNAL_I2S2_CLOCK_VALUE */ -#endif +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ @@ -259,6 +239,7 @@ in voltage and temperature.*/ #define USE_HAL_CRYP_SUSPEND_RESUME 1U #endif + /* ########################## Assert Selection ############################## */ /** * @brief Uncomment the line below to expanse the "assert_param" macro in the @@ -394,17 +375,7 @@ in voltage and temperature.*/ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for functions parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ -#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ -void assert_failed(uint8_t *file, uint32_t line); +#include "stm32_assert.h" // MBED patch #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/system_stm32g0xx.c b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/system_stm32g0xx.c index 79ae3f917ac..37dc683e21c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/system_stm32g0xx.c +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/system_stm32g0xx.c @@ -53,17 +53,15 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - /** @addtogroup CMSIS * @{ */ @@ -111,11 +109,29 @@ */ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. - This value must be a multiple of 0x100. */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** * @} @@ -166,15 +182,10 @@ * @param None * @retval None */ -void SystemInit(void) +__WEAK void SystemInit(void) { - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else #include "nvic_addr.h" // MBED SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED -#endif } /** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/CMakeLists.txt similarity index 53% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/CMakeLists.txt index c7b9c124974..fc080dd7ec4 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/CMakeLists.txt @@ -3,24 +3,24 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g030xx.ld) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g030x8.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g030xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32g030xx.sct) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g030x8.sct) endif() -add_library(mbed-stm32g030xx INTERFACE) +add_library(mbed-stm32g030x8 INTERFACE) -target_sources(mbed-stm32g030xx +target_include_directories(mbed-stm32g030x8 INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32g030xx +target_sources(mbed-stm32g030x8 INTERFACE - . + ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32g030xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-stm32g030x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32g030xx INTERFACE mbed-stm32g0) +target_link_libraries(mbed-stm32g030x8 INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/startup_stm32g030xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/startup_stm32g030xx.S similarity index 95% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/startup_stm32g030xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/startup_stm32g030xx.S index 34e5a688a42..e7c9d9d6133 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/startup_stm32g030xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/startup_stm32g030xx.S @@ -11,18 +11,17 @@ ;* After Reset the CortexM0 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** +;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** - PRESERVE8 THUMB diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/stm32g070xx.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/stm32g030x8.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/stm32g070xx.sct rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/stm32g030x8.sct index eb603cef164..cf04d70e71c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/stm32g070xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/stm32g030x8.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S similarity index 59% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S index 624b1b9b5b1..9d8d38715e4 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g030xx.s * @author MCD Application Team - * @brief STM32G030xx devices vector table for SW4STM32 toolchain. + * @brief STM32G030xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,20 +14,20 @@ ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. All rights reserved. + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb .global g_pfnVectors .global Default_Handler @@ -44,6 +44,15 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function @@ -51,44 +60,45 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 b LoopFillZerobss -/* Zero fill the bss segment. */ + FillZerobss: - movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 + cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit bl _start bx lr LoopForever: - b LoopForever - + b LoopForever .size Reset_Handler, .-Reset_Handler @@ -98,13 +108,14 @@ LoopForever: * the system state for examination by a debugger. * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler + /****************************************************************************** * * The minimal vector table for a Cortex M0. Note that the proper constructs @@ -112,58 +123,57 @@ Infinite_Loop: * 0x0000.0000. * ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* reserved */ - .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* reserved */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* reserved */ - .word 0 /* reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* reserved */ + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* reserved */ + .word 0 /* reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* reserved */ /******************************************************************************* * diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/stm32g030xx.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/stm32g030x8.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/stm32g030xx.ld rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/stm32g030x8.ld diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/startup_stm32g030xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/startup_stm32g030xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/startup_stm32g030xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/startup_stm32g030xx.S index 294828382ac..0d88c7e2443 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/startup_stm32g030xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/startup_stm32g030xx.S @@ -11,16 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;******************************************************************************** ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; ;******************************************************************************* ; ; The modules in this file are included in the libraries, and may be replaced diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/stm32g041xx.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/stm32g030x8.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/stm32g041xx.icf rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/stm32g030x8.icf index 64d37c10db3..3c124741763 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/stm32g041xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/stm32g030x8.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/cmsis_nvic.h similarity index 92% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/cmsis_nvic.h index 6f590036b52..b3522ef7210 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/cmsis_nvic.h @@ -22,11 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#if defined (TARGET_NUCLEO_G031K8) #define MBED_ROM_SIZE 0x10000 // 64 KB -#else -#error "MBED_ROM_SIZE not defined" -#endif #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/CMakeLists.txt similarity index 54% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/CMakeLists.txt index ff40eddb976..73a070af27f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/CMakeLists.txt @@ -5,24 +5,25 @@ add_subdirectory(TARGET_NUCLEO_G031K8 EXCLUDE_FROM_ALL) if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g031xx.ld) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g031x8.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g031xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32g031xx.sct) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g031x8.sct) endif() -add_library(mbed-stm32g031xx INTERFACE) +add_library(mbed-stm32g031x8 INTERFACE) -target_sources(mbed-stm32g031xx +target_include_directories(mbed-stm32g031x8 INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32g031xx +target_sources(mbed-stm32g031x8 INTERFACE - . + ${STARTUP_FILE} + system_clock.c ) -mbed_set_linker_script(mbed-stm32g031xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-stm32g031x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32g031xx INTERFACE mbed-stm32g0) +target_link_libraries(mbed-stm32g031x8 INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/CMakeLists.txt similarity index 92% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/CMakeLists.txt index d3d1481a64b..2128ec0acae 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/CMakeLists.txt @@ -6,7 +6,6 @@ add_library(mbed-nucleo-g031k8 INTERFACE) target_sources(mbed-nucleo-g031k8 INTERFACE PeripheralPins.c - system_clock.c ) target_include_directories(mbed-nucleo-g031k8 @@ -14,4 +13,4 @@ target_include_directories(mbed-nucleo-g031k8 . ) -target_link_libraries(mbed-nucleo-g031k8 INTERFACE mbed-stm32g031xx) +target_link_libraries(mbed-nucleo-g031k8 INTERFACE mbed-stm32g031x8) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PeripheralPins.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PinNames.h similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PinNames.h index a4e071abfeb..4281038e21d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PinNames.h @@ -141,6 +141,13 @@ typedef enum { // Standardized LED and button names #define LED1 PC_6 // LD3 [Green] +#define I2C_SDA D4 +#define I2C_SCL D5 + +#define SPI_SCK D10 +#define SPI_MOSI D11 +#define SPI_MISO D12 +#define SPI_CS D13 #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/startup_stm32g031xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/startup_stm32g031xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/startup_stm32g031xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/startup_stm32g031xx.S index 246e0c7819c..3d7bbe27201 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/startup_stm32g031xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/startup_stm32g031xx.S @@ -11,18 +11,17 @@ ;* After Reset the CortexM0 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** +;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** - PRESERVE8 THUMB diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/stm32g041xx.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/stm32g031x8.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/stm32g041xx.sct rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/stm32g031x8.sct index eb603cef164..cf04d70e71c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/stm32g041xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/stm32g031x8.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S similarity index 60% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S index ca6ed43bb08..082891533d8 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g031xx.s * @author MCD Application Team - * @brief STM32G031xx devices vector table for SW4STM32 toolchain. + * @brief STM32G031xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,20 +14,20 @@ ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. All rights reserved. + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb .global g_pfnVectors .global Default_Handler @@ -44,6 +44,15 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function @@ -51,44 +60,45 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 b LoopFillZerobss -/* Zero fill the bss segment. */ + FillZerobss: - movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 + cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit bl _start bx lr LoopForever: - b LoopForever - + b LoopForever .size Reset_Handler, .-Reset_Handler @@ -98,13 +108,14 @@ LoopForever: * the system state for examination by a debugger. * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler + /****************************************************************************** * * The minimal vector table for a Cortex M0. Note that the proper constructs @@ -112,59 +123,58 @@ Infinite_Loop: * 0x0000.0000. * ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detect */ - .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word LPTIM2_IRQHandler /* LPTIM2 */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word LPUART1_IRQHandler /* LPUART1 */ - .word 0 /* reserved */ + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word LPTIM2_IRQHandler /* LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word LPUART1_IRQHandler /* LPUART1 */ + .word 0 /* reserved */ /******************************************************************************* * diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/stm32g031xx.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/stm32g031x8.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/stm32g031xx.ld rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/stm32g031x8.ld diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/startup_stm32g031xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/startup_stm32g031xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/startup_stm32g031xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/startup_stm32g031xx.S index ae5ed70053e..7c375cb765b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/startup_stm32g031xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/startup_stm32g031xx.S @@ -11,16 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;******************************************************************************** ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; ;******************************************************************************* ; ; The modules in this file are included in the libraries, and may be replaced diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/stm32g030xx.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/stm32g031x8.icf similarity index 94% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/stm32g030xx.icf rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/stm32g031x8.icf index dc897d7a24f..3c124741763 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/stm32g030xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/stm32g031x8.icf @@ -18,7 +18,7 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 45; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ define symbol HEAP_SIZE = 0x1000; /* Common - Do not change */ @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/cmsis_nvic.h similarity index 92% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/cmsis_nvic.h index e428a2e9da6..b3522ef7210 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x20000 +#define MBED_ROM_SIZE 0x10000 // 64 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x9000 +#define MBED_RAM_SIZE 0x2000 // 8 KB #endif #define NVIC_NUM_VECTORS 48 diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/system_clock.c similarity index 85% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/system_clock.c index 6d20b8a9e4e..11a92837ca5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/system_clock.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2020 STMicroelectronics. + * Copyright (c) 2019-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -14,9 +14,11 @@ */ /** - * This file configures the system clock as follows: - *----------------------------------------------------------------- - * System clock source | USE_PLL_HSI (internal 16 MHz) + * This file configures the system clock depending on config from targets.json: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) *----------------------------------------------------------------- * SYSCLK(MHz) | 64 * AHBCLK (MHz) | 64 @@ -28,7 +30,8 @@ #include "stm32g0xx.h" #include "mbed_error.h" -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) #define USE_PLL_HSI 0x2 // Use HSI internal clock @@ -44,12 +47,13 @@ uint8_t SetSysClock_PLL_HSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) + +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -72,19 +76,15 @@ void SetSysClock(void) } } } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); } #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - return 0; + return 0; // FAIL } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h deleted file mode 100644 index 71cc971a62d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * - * Copyright (c) 2015 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE -} ADCName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - LPUART_1 = (int)LPUART1_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 2 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_14 = (int)TIM14_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE -} PWMName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/CMakeLists.txt similarity index 53% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/CMakeLists.txt index 4af5cd12774..fd50fd5e675 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/CMakeLists.txt @@ -3,24 +3,24 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g041xx.ld) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g041x8.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g041xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32g041xx.sct) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g041x8.sct) endif() -add_library(mbed-stm32g041xx INTERFACE) +add_library(mbed-stm32g041x8 INTERFACE) -target_sources(mbed-stm32g041xx +target_include_directories(mbed-stm32g041x8 INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32g041xx +target_sources(mbed-stm32g041x8 INTERFACE - . + ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32g041xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-stm32g041x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32g041xx INTERFACE mbed-stm32g0) +target_link_libraries(mbed-stm32g041x8 INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/startup_stm32g041xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/startup_stm32g041xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/startup_stm32g041xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/startup_stm32g041xx.S index 97056e14daf..d95496bc229 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/startup_stm32g041xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/startup_stm32g041xx.S @@ -11,18 +11,17 @@ ;* After Reset the CortexM0 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** +;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** - PRESERVE8 THUMB diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/stm32g030xx.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/stm32g041x8.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/stm32g030xx.sct rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/stm32g041x8.sct index eb603cef164..cf04d70e71c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/stm32g030xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/stm32g041x8.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S similarity index 60% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S index 2f872a437c9..2bb69e882dc 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g041xx.s * @author MCD Application Team - * @brief STM32G041xx devices vector table for SW4STM32 toolchain. + * @brief STM32G041xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,20 +14,20 @@ ****************************************************************************** * @attention * - * Copyright (c) 2019 STMicroelectronics. All rights reserved. + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb .global g_pfnVectors .global Default_Handler @@ -44,6 +44,15 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function @@ -51,44 +60,45 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 b LoopFillZerobss -/* Zero fill the bss segment. */ + FillZerobss: - movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 + cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit bl _start bx lr LoopForever: - b LoopForever - + b LoopForever .size Reset_Handler, .-Reset_Handler @@ -98,13 +108,14 @@ LoopForever: * the system state for examination by a debugger. * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler + /****************************************************************************** * * The minimal vector table for a Cortex M0. Note that the proper constructs @@ -112,60 +123,59 @@ Infinite_Loop: * 0x0000.0000. * ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detect */ - .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word LPTIM2_IRQHandler /* LPTIM2 */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word LPUART1_IRQHandler /* LPUART1 */ - .word 0 /* reserved */ - .word AES_RNG_IRQHandler /* AES and RNG */ + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 5, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word LPTIM2_IRQHandler /* LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word LPUART1_IRQHandler /* LPUART1 */ + .word 0 /* reserved */ + .word AES_RNG_IRQHandler /* AES and RNG */ /******************************************************************************* * diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/stm32g041xx.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/stm32g041x8.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/stm32g041xx.ld rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/stm32g041x8.ld diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/startup_stm32g041xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/startup_stm32g041xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/startup_stm32g041xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/startup_stm32g041xx.S index a10669b3450..a4f94166dda 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/startup_stm32g041xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/startup_stm32g041xx.S @@ -11,16 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2019 STMicroelectronics. All rights reserved. +;******************************************************************************** ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; ;******************************************************************************* ; ; The modules in this file are included in the libraries, and may be replaced diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/stm32g031xx.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/stm32g041x8.icf similarity index 94% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/stm32g031xx.icf rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/stm32g041x8.icf index 256e8ba2b54..3c124741763 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/stm32g031xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/stm32g041x8.icf @@ -18,7 +18,7 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 46; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ define symbol HEAP_SIZE = 0x1000; /* Common - Do not change */ @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/cmsis_nvic.h similarity index 89% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/cmsis_nvic.h index 546fad304e3..b3522ef7210 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x20000 +#define MBED_ROM_SIZE 0x10000 // 64 KB #endif #if !defined(MBED_RAM_START) @@ -30,10 +30,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x9000 +#define MBED_RAM_SIZE 0x2000 // 8 KB #endif -#define NVIC_NUM_VECTORS 46 +#define NVIC_NUM_VECTORS 48 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h deleted file mode 100644 index 4c135e696f5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h +++ /dev/null @@ -1,41 +0,0 @@ -/* mbed Microcontroller Library - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#if !defined(MBED_ROM_START) -#define MBED_ROM_START 0x8000000 -#endif - -#if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x10000 -// 0x10000 STM32G041Y8Yx STM32G041K8Ux STM32G041C8Ux STM32G041C8Tx STM32G041K8Tx STM32G041G8Ux STM32G041F8Px -// 0x8000 STM32G041G6Ux STM32G041K6Tx STM32G041C6Tx STM32G041J6Mx STM32G041K6Ux STM32G041C6Ux STM32G041F6Px -#endif - -#if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x20000000 -#endif - -#if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x2000 -#endif - -#define NVIC_NUM_VECTORS 48 -#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/CMakeLists.txt new file mode 100644 index 00000000000..972011ff8b8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g050xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g050x8.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g050xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g050x8.sct) +endif() + +add_library(mbed-stm32g050x8 INTERFACE) + +target_include_directories(mbed-stm32g050x8 + INTERFACE + . +) + +target_sources(mbed-stm32g050x8 + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g050x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g050x8 INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/startup_stm32g050xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/startup_stm32g050xx.S new file mode 100644 index 00000000000..272b2c23cbe --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/startup_stm32g050xx.S @@ -0,0 +1,194 @@ +;****************************************************************************** +;* File Name : startup_stm32g050xx.s +;* Author : MCD Application Team +;* Description : STM32G050xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + + +WWDG_IRQHandler +RTC_TAMP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/stm32g031xx.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/stm32g050x8.sct similarity index 90% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/stm32g031xx.sct rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/stm32g050x8.sct index eb603cef164..cf04d70e71c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/stm32g031xx.sct +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_ARM/stm32g050x8.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_GCC_ARM/startup_stm32g050xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_GCC_ARM/startup_stm32g050xx.S new file mode 100644 index 00000000000..99eebcb8009 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_GCC_ARM/startup_stm32g050xx.S @@ -0,0 +1,279 @@ +/** + ****************************************************************************** + * @file startup_stm32g050xx.s + * @author MCD Application Team + * @brief STM32G050xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/stm32g070xx.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_GCC_ARM/stm32g050x8.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/stm32g070xx.ld rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_GCC_ARM/stm32g050x8.ld diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_IAR/startup_stm32g050xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_IAR/startup_stm32g050xx.S new file mode 100644 index 00000000000..bf82a70f500 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_IAR/startup_stm32g050xx.S @@ -0,0 +1,275 @@ +;****************************************************************************** +;* File Name : startup_stm32g050xx.s +;* Author : MCD Application Team +;* Description : STM32G050xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + B DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_IAR/stm32g050x8.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_IAR/stm32g050x8.icf new file mode 100644 index 00000000000..3c124741763 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/TOOLCHAIN_IAR/stm32g050x8.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/cmsis_nvic.h similarity index 82% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/cmsis_nvic.h index 8045b5a794f..cc487ec0eeb 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G050x8/cmsis_nvic.h @@ -22,9 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x10000 -// 0x10000 STM32G030K8Tx STM32G030C8Tx -// 0x8000 STM32G030F6Px STM32G030K6Tx STM32G030C6Tx STM32G030J6Mx +#define MBED_ROM_SIZE 0x10000 // 64 KB #endif #if !defined(MBED_RAM_START) @@ -32,10 +30,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x2000 +#define MBED_RAM_SIZE 0x4800 // 18 B #endif -#define NVIC_NUM_VECTORS 45 +#define NVIC_NUM_VECTORS 48 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/CMakeLists.txt new file mode 100644 index 00000000000..c4589208ee6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g051xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g051x8.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g051xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g051x8.sct) +endif() + +add_library(mbed-stm32g051x8 INTERFACE) + +target_include_directories(mbed-stm32g051x8 + INTERFACE + . +) + +target_sources(mbed-stm32g051x8 + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g051x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g051x8 INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_ARM/startup_stm32g051xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_ARM/startup_stm32g051xx.S new file mode 100644 index 00000000000..4f5570752e5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_ARM/startup_stm32g051xx.S @@ -0,0 +1,203 @@ +;****************************************************************************** +;* File Name : startup_stm32g051xx.s +;* Author : MCD Application Team +;* Description : STM32G051xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD LPUART1_IRQHandler ; LPUART1 + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_TAMP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +LPUART1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_ARM/stm32g051x8.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_ARM/stm32g051x8.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_ARM/stm32g051x8.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_GCC_ARM/startup_stm32g051xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_GCC_ARM/startup_stm32g051xx.S new file mode 100644 index 00000000000..69f486d9c79 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_GCC_ARM/startup_stm32g051xx.S @@ -0,0 +1,289 @@ +/** + ****************************************************************************** + * @file startup_stm32g051xx.s + * @author MCD Application Team + * @brief STM32G051xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC & LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 & LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word LPUART1_IRQHandler /* LPUART1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/stm32g071xx.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_GCC_ARM/stm32g051x8.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/stm32g071xx.ld rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_GCC_ARM/stm32g051x8.ld diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_IAR/startup_stm32g051xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_IAR/startup_stm32g051xx.S new file mode 100644 index 00000000000..95e67c3a6ab --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_IAR/startup_stm32g051xx.S @@ -0,0 +1,290 @@ +;****************************************************************************** +;* File Name : startup_stm32g051xx.s +;* Author : MCD Application Team +;* Description : STM32G051xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD LPUART1_IRQHandler ; LPUART1 + DCD 0 ; Reserved + DCD 0 ; Reserved + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + B DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_IAR/stm32g051x8.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_IAR/stm32g051x8.icf new file mode 100644 index 00000000000..3c124741763 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/TOOLCHAIN_IAR/stm32g051x8.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/cmsis_nvic.h new file mode 100644 index 00000000000..853e2a50a5e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G051x8/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x10000 // 64 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x4800 // 18 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/CMakeLists.txt new file mode 100644 index 00000000000..86142054995 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g061xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g061x8.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g061xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g061x8.sct) +endif() + +add_library(mbed-stm32g061x8 INTERFACE) + +target_include_directories(mbed-stm32g061x8 + INTERFACE + . +) + +target_sources(mbed-stm32g061x8 + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g061x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g061x8 INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_ARM/startup_stm32g061xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_ARM/startup_stm32g061xx.S new file mode 100644 index 00000000000..843c236759e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_ARM/startup_stm32g061xx.S @@ -0,0 +1,205 @@ +;****************************************************************************** +;* File Name : startup_stm32g061xx.s +;* Author : MCD Application Team +;* Description : STM32G061xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD LPUART1_IRQHandler ; LPUART1 + DCD 0 ; Reserved + DCD AES_RNG_IRQHandler ; AES, RNG + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT AES_RNG_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_TAMP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +LPUART1_IRQHandler +AES_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_ARM/stm32g061x8.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_ARM/stm32g061x8.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_ARM/stm32g061x8.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_GCC_ARM/startup_stm32g061xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_GCC_ARM/startup_stm32g061xx.S new file mode 100644 index 00000000000..bcdad9a443d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_GCC_ARM/startup_stm32g061xx.S @@ -0,0 +1,294 @@ +/** + ****************************************************************************** + * @file startup_stm32g061xx.s + * @author MCD Application Team + * @brief STM32G061xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC & LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 & LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word LPUART1_IRQHandler /* LPUART1 */ + .word 0 /* reserved */ + .word AES_RNG_IRQHandler /* AES and RNG */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak AES_RNG_IRQHandler + .thumb_set AES_RNG_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/stm32g081xx.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_GCC_ARM/stm32g061x8.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/stm32g081xx.ld rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_GCC_ARM/stm32g061x8.ld diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_IAR/startup_stm32g061xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_IAR/startup_stm32g061xx.S new file mode 100644 index 00000000000..4f3d98ea3a8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_IAR/startup_stm32g061xx.S @@ -0,0 +1,295 @@ +;****************************************************************************** +;* File Name : startup_stm32g061xx.s +;* Author : MCD Application Team +;* Description : STM32G061xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD LPUART1_IRQHandler ; LPUART1 + DCD 0 ; Reserved + DCD AES_RNG_IRQHandler ; AES, RNG + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + B DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK AES_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_RNG_IRQHandler + B AES_RNG_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_IAR/stm32g061x8.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_IAR/stm32g061x8.icf new file mode 100644 index 00000000000..3c124741763 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/TOOLCHAIN_IAR/stm32g061x8.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/cmsis_nvic.h new file mode 100644 index 00000000000..853e2a50a5e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G061x8/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x10000 // 64 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x4800 // 18 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/CMakeLists.txt similarity index 53% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/CMakeLists.txt index bc48ccc9588..52c4965c5ed 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/CMakeLists.txt @@ -3,24 +3,24 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g070xx.ld) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g070xb.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g070xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32g070xx.sct) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g070xb.sct) endif() -add_library(mbed-stm32g070xx INTERFACE) +add_library(mbed-stm32g070xb INTERFACE) -target_sources(mbed-stm32g070xx +target_include_directories(mbed-stm32g070xb INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32g070xx +target_sources(mbed-stm32g070xb INTERFACE - . + ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32g070xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-stm32g070xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32g070xx INTERFACE mbed-stm32g0) +target_link_libraries(mbed-stm32g070xb INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/startup_stm32g070xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/startup_stm32g070xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/startup_stm32g070xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/startup_stm32g070xx.S index 6cfb82a6eb8..55b62570727 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/startup_stm32g070xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/startup_stm32g070xx.S @@ -11,18 +11,17 @@ ;* After Reset the CortexM0 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** +;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2018 STMicroelectronics. All rights reserved. +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** - PRESERVE8 THUMB diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/stm32g070xb.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/stm32g070xb.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/stm32g070xb.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S similarity index 60% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S index e638c7f7979..9f9f615385b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g070xx.s * @author MCD Application Team - * @brief STM32G070xx devices vector table for SW4STM32 toolchain. + * @brief STM32G070xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,20 +14,20 @@ ****************************************************************************** * @attention * - * Copyright (c) 2018 STMicroelectronics. All rights reserved. + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb .global g_pfnVectors .global Default_Handler @@ -44,6 +44,15 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function @@ -51,44 +60,45 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 b LoopFillZerobss -/* Zero fill the bss segment. */ + FillZerobss: - movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 + cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit bl _start bx lr LoopForever: - b LoopForever - + b LoopForever .size Reset_Handler, .-Reset_Handler @@ -98,13 +108,14 @@ LoopForever: * the system state for examination by a debugger. * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler + /****************************************************************************** * * The minimal vector table for a Cortex M0. Note that the proper constructs @@ -112,58 +123,57 @@ Infinite_Loop: * 0x0000.0000. * ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* reserved */ - .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* reserved */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM6_IRQHandler /* TIM6 */ - .word TIM7_IRQHandler /* TIM7 */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_4_IRQHandler /* USART3, USART4 */ + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_IRQHandler /* USART3, USART4 */ /******************************************************************************* * diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/stm32g070xb.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/stm32g070xb.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/stm32g070xb.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/startup_stm32g070xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/startup_stm32g070xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/startup_stm32g070xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/startup_stm32g070xx.S index 62b87024a70..80f71849ea8 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/startup_stm32g070xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/startup_stm32g070xx.S @@ -11,16 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2018 STMicroelectronics. All rights reserved. +;******************************************************************************** ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; ;******************************************************************************* ; ; The modules in this file are included in the libraries, and may be replaced diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/stm32g081xx.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/stm32g070xb.icf similarity index 97% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/stm32g081xx.icf rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/stm32g070xb.icf index 613ece8b935..ac1f890adfa 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/stm32g081xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/stm32g070xb.icf @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/cmsis_nvic.h new file mode 100644 index 00000000000..52f5f72abb5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x9000 // 36 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/CMakeLists.txt similarity index 54% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/CMakeLists.txt index 3020cbcf16d..730ccdb52bb 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/CMakeLists.txt @@ -5,24 +5,25 @@ add_subdirectory(TARGET_NUCLEO_G071RB EXCLUDE_FROM_ALL) if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g071xx.ld) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g071xb.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g071xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32g071xx.sct) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g071xb.sct) endif() -add_library(mbed-stm32g071xx INTERFACE) +add_library(mbed-stm32g071xb INTERFACE) -target_sources(mbed-stm32g071xx +target_include_directories(mbed-stm32g071xb INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32g071xx +target_sources(mbed-stm32g071xb INTERFACE - . + ${STARTUP_FILE} + system_clock.c ) -mbed_set_linker_script(mbed-stm32g071xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-stm32g071xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32g071xx INTERFACE mbed-stm32g0) +target_link_libraries(mbed-stm32g071xb INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/CMakeLists.txt similarity index 92% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/CMakeLists.txt index 2f2dfdfde76..8b044e78a7c 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/CMakeLists.txt @@ -6,7 +6,6 @@ add_library(mbed-nucleo-g071rb INTERFACE) target_sources(mbed-nucleo-g071rb INTERFACE PeripheralPins.c - system_clock.c ) target_include_directories(mbed-nucleo-g071rb @@ -14,4 +13,4 @@ target_include_directories(mbed-nucleo-g071rb . ) -target_link_libraries(mbed-nucleo-g071rb INTERFACE mbed-stm32g071xx) +target_link_libraries(mbed-nucleo-g071rb INTERFACE mbed-stm32g071xb) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/PeripheralPins.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralPins.c rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/PinNames.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PinNames.h rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/startup_stm32g071xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/startup_stm32g071xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/startup_stm32g071xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/startup_stm32g071xx.S index 6670c790e1d..11910820552 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/startup_stm32g071xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/startup_stm32g071xx.S @@ -11,18 +11,17 @@ ;* After Reset the CortexM0 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** +;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2018 STMicroelectronics. All rights reserved. +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** - PRESERVE8 THUMB diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/stm32g071xb.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/stm32g071xb.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/stm32g071xb.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S similarity index 61% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S index ab2d2778276..270c6191212 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g071xx.s * @author MCD Application Team - * @brief STM32G071xx devices vector table for SW4STM32 toolchain. + * @brief STM32G071xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,20 +14,20 @@ ****************************************************************************** * @attention * - * Copyright (c) 2018 STMicroelectronics. All rights reserved. + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb .global g_pfnVectors .global Default_Handler @@ -44,6 +44,15 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function @@ -51,44 +60,45 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 b LoopFillZerobss -/* Zero fill the bss segment. */ + FillZerobss: - movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 + cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit bl _start bx lr LoopForever: - b LoopForever - + b LoopForever .size Reset_Handler, .-Reset_Handler @@ -98,13 +108,14 @@ LoopForever: * the system state for examination by a debugger. * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler + /****************************************************************************** * * The minimal vector table for a Cortex M0. Note that the proper constructs @@ -112,59 +123,58 @@ Infinite_Loop: * 0x0000.0000. * ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detect */ - .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ - .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ - .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ - .word CEC_IRQHandler /* CEC */ + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ + .word CEC_IRQHandler /* CEC */ /******************************************************************************* * diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/stm32g071xb.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/stm32g071xb.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/stm32g071xb.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/startup_stm32g071xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/startup_stm32g071xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/startup_stm32g071xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/startup_stm32g071xx.S index cfe8d16ed3e..c139ef626ef 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/startup_stm32g071xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/startup_stm32g071xx.S @@ -11,16 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2018 STMicroelectronics. All rights reserved. +;******************************************************************************** ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; ;******************************************************************************* ; ; The modules in this file are included in the libraries, and may be replaced diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/stm32g071xx.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/stm32g071xb.icf similarity index 94% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/stm32g071xx.icf rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/stm32g071xb.icf index 9a0f4dc6dd1..ac1f890adfa 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/stm32g071xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/stm32g071xb.icf @@ -18,7 +18,7 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 47; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ define symbol HEAP_SIZE = 0x2000; /* Common - Do not change */ @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/cmsis_nvic.h new file mode 100644 index 00000000000..52f5f72abb5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x9000 // 36 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/system_clock.c similarity index 85% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/system_clock.c index 996533d1156..4d54810d2e4 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/system_clock.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2019 STMicroelectronics. + * Copyright (c) 2019-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -14,10 +14,10 @@ */ /** - * This file configures the system clock as follows: - *----------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * This file configures the system clock depending on config from targets.json: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) * | 3- USE_PLL_HSI (internal 16 MHz) *----------------------------------------------------------------- * SYSCLK(MHz) | 64 @@ -30,13 +30,8 @@ #include "stm32g0xx.h" #include "mbed_error.h" -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. - This value must be a multiple of 0x100. */ - -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) #define USE_PLL_HSI 0x2 // Use HSI internal clock @@ -52,12 +47,13 @@ uint8_t SetSysClock_PLL_HSI(void); /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) * @param None * @retval None */ -void SetSysClock(void) + +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock */ @@ -80,17 +76,13 @@ void SetSysClock(void) } } } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); } #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/stm32g071xx.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/stm32g071xx.sct deleted file mode 100644 index eb603cef164..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/stm32g071xx.sct +++ /dev/null @@ -1,57 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; Scatter-Loading Description File -; -; SPDX-License-Identifier: BSD-3-Clause -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2016-2020 STMicroelectronics. -;* All rights reserved. -;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;****************************************************************************** - -#include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up - } - - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down - } -} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/CMakeLists.txt similarity index 53% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/CMakeLists.txt rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/CMakeLists.txt index fec2e00dfae..ca78a9ef4d5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/CMakeLists.txt @@ -3,24 +3,24 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S) - set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g081xx.ld) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g081xb.ld) elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g081xx.S) - set(LINKER_FILE TOOLCHAIN_ARM/stm32g081xx.sct) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g081xb.sct) endif() -add_library(mbed-stm32g081xx INTERFACE) +add_library(mbed-stm32g081xb INTERFACE) -target_sources(mbed-stm32g081xx +target_include_directories(mbed-stm32g081xb INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32g081xx +target_sources(mbed-stm32g081xb INTERFACE - . + ${STARTUP_FILE} ) -mbed_set_linker_script(mbed-stm32g081xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-stm32g081xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) -target_link_libraries(mbed-stm32g081xx INTERFACE mbed-stm32g0) +target_link_libraries(mbed-stm32g081xb INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/startup_stm32g081xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/startup_stm32g081xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/startup_stm32g081xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/startup_stm32g081xx.S index 2cf511379b3..249a89c8d36 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/startup_stm32g081xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/startup_stm32g081xx.S @@ -11,18 +11,17 @@ ;* After Reset the CortexM0 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> -;****************************************************************************** +;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2018 STMicroelectronics. All rights reserved. +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** - PRESERVE8 THUMB diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/stm32g081xb.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/stm32g081xb.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/stm32g081xb.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S similarity index 61% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S index b2de8be078f..8fe17aa4869 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S @@ -2,7 +2,7 @@ ****************************************************************************** * @file startup_stm32g081xx.s * @author MCD Application Team - * @brief STM32G081xx devices vector table for SW4STM32 toolchain. + * @brief STM32G081xx devices vector table GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -14,20 +14,20 @@ ****************************************************************************** * @attention * - * Copyright (c) 2018 STMicroelectronics. All rights reserved. + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb .global g_pfnVectors .global Default_Handler @@ -44,6 +44,15 @@ defined in linker script */ /* end address for the .bss section. defined in linker script */ .word _ebss +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function @@ -51,44 +60,45 @@ Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ +/* Call the clock system initialization function.*/ + bl SystemInit + /* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 b LoopCopyDataInit CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 + adds r4, r0, r3 + cmp r4, r1 bcc CopyDataInit + +/* Zero fill the bss segment. */ ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 b LoopFillZerobss -/* Zero fill the bss segment. */ + FillZerobss: - movs r3, #0 str r3, [r2] adds r2, r2, #4 - LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 + cmp r2, r4 bcc FillZerobss -/* Call the clock system intitialization function.*/ - bl SystemInit bl _start bx lr LoopForever: - b LoopForever - + b LoopForever .size Reset_Handler, .-Reset_Handler @@ -98,13 +108,14 @@ LoopForever: * the system state for examination by a debugger. * * @param None - * @retval : None + * @retval None */ - .section .text.Default_Handler,"ax",%progbits + .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler + /****************************************************************************** * * The minimal vector table for a Cortex M0. Note that the proper constructs @@ -112,60 +123,59 @@ Infinite_Loop: * 0x0000.0000. * ******************************************************************************/ - .section .isr_vector,"a",%progbits + .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detect */ - .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ - .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ - .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ - .word TIM14_IRQHandler /* TIM14 */ - .word TIM15_IRQHandler /* TIM15 */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word I2C2_IRQHandler /* I2C2 */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ - .word CEC_IRQHandler /* CEC */ - .word AES_RNG_IRQHandler /* AES and RNG */ + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ + .word CEC_IRQHandler /* CEC */ + .word AES_RNG_IRQHandler /* AES and RNG */ /******************************************************************************* * diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/stm32g081xb.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/stm32g081xb.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/stm32g081xb.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/startup_stm32g081xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/startup_stm32g081xx.S similarity index 96% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/startup_stm32g081xx.S rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/startup_stm32g081xx.S index 9991b2bcd9b..099f08bb4dc 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/startup_stm32g081xx.S +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/startup_stm32g081xx.S @@ -11,16 +11,15 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2018 STMicroelectronics. All rights reserved. +;******************************************************************************** ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. ;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; ;******************************************************************************* ; ; The modules in this file are included in the libraries, and may be replaced diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/stm32g070xx.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/stm32g081xb.icf similarity index 94% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/stm32g070xx.icf rename to targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/stm32g081xb.icf index 7da81746762..ac1f890adfa 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/stm32g070xx.icf +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/stm32g081xb.icf @@ -18,7 +18,7 @@ /* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -define symbol VECTORS = 46; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ define symbol HEAP_SIZE = 0x2000; /* Common - Do not change */ @@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/cmsis_nvic.h new file mode 100644 index 00000000000..52f5f72abb5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x9000 // 36 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/stm32g081xx.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/stm32g081xx.sct deleted file mode 100644 index eb603cef164..00000000000 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/stm32g081xx.sct +++ /dev/null @@ -1,57 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 -; Scatter-Loading Description File -; -; SPDX-License-Identifier: BSD-3-Clause -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2016-2020 STMicroelectronics. -;* All rights reserved. -;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;****************************************************************************** - -#include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up - } - - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down - } -} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/CMakeLists.txt new file mode 100644 index 00000000000..dcd0b170d76 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g0b0xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g0b0xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g0b0xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g0b0xe.sct) +endif() + +add_library(mbed-stm32g0b0xe INTERFACE) + +target_include_directories(mbed-stm32g0b0xe + INTERFACE + . +) + +target_sources(mbed-stm32g0b0xe + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g0b0xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g0b0xe INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_ARM/startup_stm32g0b0xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_ARM/startup_stm32g0b0xx.S new file mode 100644 index 00000000000..175e4050461 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_ARM/startup_stm32g0b0xx.S @@ -0,0 +1,199 @@ +;****************************************************************************** +;* File Name : startup_stm32g0b0xx.s +;* Author : MCD Application Team +;* Description : STM32G0b0xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD USB_IRQHandler ; USB + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 ,DMAMUX1 overrun + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_3_IRQHandler ; I2C2, I2C3 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_3_IRQHandler ; SPI2, SPI3 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_5_6_IRQHandler ; USART3, USART4, USART5, USART6 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM3_TIM4_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_3_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_5_6_IRQHandler [WEAK] + + +WWDG_IRQHandler +RTC_TAMP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +USB_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM3_TIM4_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_3_IRQHandler +SPI1_IRQHandler +SPI2_3_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_5_6_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_ARM/stm32g0b0xe.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_ARM/stm32g0b0xe.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_ARM/stm32g0b0xe.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_GCC_ARM/startup_stm32g0b0xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_GCC_ARM/startup_stm32g0b0xx.S new file mode 100644 index 00000000000..ca3da99d9b9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_GCC_ARM/startup_stm32g0b0xx.S @@ -0,0 +1,286 @@ +/** + ****************************************************************************** + * @file startup_stm32g0b0xx.s + * @author MCD Application Team + * @brief STM32G0b0xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* reserved */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word USB_IRQHandler /* USB */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler /* DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5, DMAMUX1 overrun */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* reserved */ + .word TIM3_TIM4_IRQHandler /* TIM3, TIM4 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_3_IRQHandler /* I2C2, I2C3 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_3_IRQHandler /* SPI2, SPI3 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_5_6_IRQHandler /* USART3, USART4, USART5, USART6 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_TIM4_IRQHandler + .thumb_set TIM3_TIM4_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_IRQHandler + .thumb_set I2C2_3_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_5_6_IRQHandler + .thumb_set USART3_4_5_6_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_GCC_ARM/stm32g0b0xe.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_GCC_ARM/stm32g0b0xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_GCC_ARM/stm32g0b0xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_IAR/startup_stm32g0b0xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_IAR/startup_stm32g0b0xx.S new file mode 100644 index 00000000000..1cb3bdf679b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_IAR/startup_stm32g0b0xx.S @@ -0,0 +1,283 @@ +;****************************************************************************** +;* File Name : startup_stm32g0b0xx.s +;* Author : MCD Application Team +;* Description : STM32G0B0xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD 0 ; Reserved + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD USB_IRQHandler ; USB + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX1 overrun + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_3_IRQHandler ; I2C2, I2C3 + DCD SPI1_IRQHandler ; SPI1/I2S1 + DCD SPI2_3_IRQHandler ; SPI2/I2S2, SPI3/I2S3 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_4_5_6_IRQHandler ; USART3, USART4, USART5, USART6 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + B DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM3_TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_TIM4_IRQHandler + B TIM3_TIM4_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_3_IRQHandler + B I2C2_3_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_3_IRQHandler + B SPI2_3_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_4_5_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_5_6_IRQHandler + B USART3_4_5_6_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_IAR/stm32g0b0xe.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_IAR/stm32g0b0xe.icf new file mode 100644 index 00000000000..3c124741763 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/TOOLCHAIN_IAR/stm32g0b0xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/cmsis_nvic.h new file mode 100644 index 00000000000..5a4e7a7fce7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B0xE/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x24000 // 144 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/CMakeLists.txt new file mode 100644 index 00000000000..15c5553a734 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TARGET_NUCLEO_G0B1RE EXCLUDE_FROM_ALL) + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g0b1xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g0b1xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g0b1xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g0b1xe.sct) +endif() + +add_library(mbed-stm32g0b1xe INTERFACE) + +target_include_directories(mbed-stm32g0b1xe + INTERFACE + . +) + +target_sources(mbed-stm32g0b1xe + INTERFACE + ${STARTUP_FILE} + system_clock.c +) + +mbed_set_linker_script(mbed-stm32g0b1xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g0b1xe INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/CMakeLists.txt new file mode 100644 index 00000000000..bcec1bce059 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/CMakeLists.txt @@ -0,0 +1,16 @@ +# Copyright (c) 2022 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-nucleo-g0b1re INTERFACE) + +target_sources(mbed-nucleo-g0b1re + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-nucleo-g0b1re + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-g0b1re INTERFACE mbed-stm32g0b1xe) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/PeripheralPins.c new file mode 100644 index 00000000000..34c833c94bd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/PeripheralPins.c @@ -0,0 +1,399 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2022 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32G0B1R(B-C-E)Tx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX +// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LED_GREEN + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PB_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PB_10, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PB_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 + {NC, NC, 0} +}; + +// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { +// {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, +// {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, +// {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to LED_GREEN + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_6, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_6_ALT0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_10_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PB_4_ALT0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_7_ALT0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_9_ALT0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PA_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF8_I2C2)}, + {PB_3_ALT0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX +// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM15, 1, 0)}, // TIM15_CH1 // Connected to STDIO_UART_TX +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX +// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM15, 2, 0)}, // TIM15_CH2 // Connected to STDIO_UART_RX + {PA_4, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 // Connected to LED_GREEN + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM15, 1, 1)}, // TIM15_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM15, 2, 0)}, // TIM15_CH2 + {PC_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM15, 1, 0)}, // TIM15_CH1 + {PC_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM15, 2, 0)}, // TIM15_CH2 +// {PC_4, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 +// {PC_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 +// {PC_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 +// {PC_7, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PC_8_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PC_9_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PC_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PC_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PC_12, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PD_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PD_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PD_2, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PD_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PD_4, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PF_0, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM14, 1, 0)}, // TIM14_CH1 + {PF_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM15, 1, 1)}, // TIM15_CH1N + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX + {PA_4, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART6)}, + {PA_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, // Connected to LED_GREEN + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to TCK + {PA_14_ALT0, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_LPUART2)}, // Connected to TCK + {PB_0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)}, + {PB_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_3, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_6_ALT0, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_LPUART2)}, + {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_8_ALT0, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART1)}, + {PC_0, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART6)}, + {PC_0_ALT0, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART1)}, + {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PC_4_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_6, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {PD_3, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PF_2, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_RX + {PA_5, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART6)}, // Connected to LED_GREEN + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_13, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_LPUART2)}, // Connected to TMS + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_1, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)}, + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PB_7_ALT0, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_LPUART2)}, + {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_9_ALT0, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART1)}, + {PC_1, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART6)}, + {PC_1_ALT0, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PC_5_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_7, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART6)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART3)}, + {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)}, + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PB_1_ALT1, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_LPUART2)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_14_ALT0, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_9, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PD_4_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {PF_2, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PA_6_ALT0, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART6)}, + {PA_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_0, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_LPUART2)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PB_6, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART5)}, + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART3)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_LPUART1)}, + {PB_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PC_8, LPUART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART2)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PD_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART5)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { +// {PA_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_TX + {PA_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SPI3)}, + {PB_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PB_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI3)}, + {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PD_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { +// {PA_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, // Connected to STDIO_UART_RX + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI2)}, + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SPI3)}, + {PB_6, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI2)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PD_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to LED_GREEN + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SPI3)}, + {PB_8, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI3)}, + {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PD_8, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SPI3)}, + {PA_8, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_SPI3)}, + {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PD_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI1)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_0, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PC_2, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PC_4, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_1, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PC_3, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN2)}, + {PC_5, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_FDCAN1)}, + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_4, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USB)}, // USB_NOE + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_DP +// {PA_13, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USB)}, // USB_NOE // Connected to TMS +// {PA_15, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USB)}, // USB_NOE +// {PC_9, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USB)}, // USB_NOE + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/PinNames.h new file mode 100644 index 00000000000..5ada1e8567f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TARGET_NUCLEO_G0B1RE/PinNames.h @@ -0,0 +1,218 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2022 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32G0B1R(B-C-E)Tx.xml + */ + +/* MBED TARGET LIST: NUCLEO_G0B1RE */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_6_ALT1 = PA_6 | ALT1, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_14_ALT0 = PA_14 | ALT0, // same pin used for alternate HW + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13 | ALT0, // same pin used for alternate HW + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_4_ALT0 = PD_4 | ALT0, // same pin used for alternate HW + PD_5 = 0x35, + PD_6 = 0x36, + PD_8 = 0x38, + PD_9 = 0x39, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno (Rev3) pins + ARDUINO_UNO_A0 = PA_0, + ARDUINO_UNO_A1 = PA_1, + ARDUINO_UNO_A2 = PA_4, + ARDUINO_UNO_A3 = PB_1, + ARDUINO_UNO_A4 = PB_11, + ARDUINO_UNO_A5 = PB_12, + + ARDUINO_UNO_D0 = PC_5, + ARDUINO_UNO_D1 = PC_4, + ARDUINO_UNO_D2 = PA_10, + ARDUINO_UNO_D3 = PB_3, + ARDUINO_UNO_D4 = PB_5, + ARDUINO_UNO_D5 = PB_4, + ARDUINO_UNO_D6 = PB_14, + ARDUINO_UNO_D7 = PA_8, + ARDUINO_UNO_D8 = PA_9, + ARDUINO_UNO_D9 = PC_7, + ARDUINO_UNO_D10 = PB_0, + ARDUINO_UNO_D11 = PA_7, + ARDUINO_UNO_D12 = PA_6, + ARDUINO_UNO_D13 = PA_5, + ARDUINO_UNO_D14 = PB_9, + ARDUINO_UNO_D15 = PB_8, +#endif + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PA_3, +#endif + + /**** USB pins ****/ + USB_DM = PA_11, + USB_DP = PA_12, + USB_NOE = PA_4, + USB_NOE_ALT0 = PA_13, + USB_NOE_ALT1 = PA_15, + USB_NOE_ALT2 = PC_9, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_EN = PC_15, + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_EN = PC_15, + RCC_OSC_EN_ALT0 = PF_1, + RCC_OSC_IN = PF_0, + RCC_OSC_OUT = PF_1, + + /**** DEBUG pins ****/ + SYS_PVD_IN = PB_7, + SYS_SWCLK = PA_14, + SYS_SWDIO = PA_13, + SYS_WKUP1 = PA_0, + SYS_WKUP2 = PC_13, + SYS_WKUP4 = PA_2, + SYS_WKUP5 = PC_5, + SYS_WKUP6 = PB_5, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 PA_5 // LED_GREEN +#define BUTTON1 PC_13 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_ARM/startup_stm32g0b1xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_ARM/startup_stm32g0b1xx.S new file mode 100644 index 00000000000..bac62f3175d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_ARM/startup_stm32g0b1xx.S @@ -0,0 +1,206 @@ +;****************************************************************************** +;* File Name : startup_stm32g0b1xx.s +;* Author : MCD Application Team +;* Description : STM32G0b1xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC & CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD USB_UCPD1_2_IRQHandler ; USB, UCPD1 & UCPD2 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 ,DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0 + DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_3_IRQHandler ; I2C2, I2C3 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_3_IRQHandler ; SPI2, SPI3 + DCD USART1_IRQHandler ; USART1 + DCD USART2_LPUART2_IRQHandler ; USART2 & LPUART2 + DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1 + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT USB_UCPD1_2_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_TIM4_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_FDCAN_IT0_IRQHandler [WEAK] + EXPORT TIM17_FDCAN_IT1_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_3_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_LPUART2_IRQHandler [WEAK] + EXPORT USART3_4_5_6_LPUART1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_TAMP_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +USB_UCPD1_2_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_TIM4_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_FDCAN_IT0_IRQHandler +TIM17_FDCAN_IT1_IRQHandler +I2C1_IRQHandler +I2C2_3_IRQHandler +SPI1_IRQHandler +SPI2_3_IRQHandler +USART1_IRQHandler +USART2_LPUART2_IRQHandler +USART3_4_5_6_LPUART1_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_ARM/stm32g0b1xe.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_ARM/stm32g0b1xe.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_ARM/stm32g0b1xe.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_GCC_ARM/startup_stm32g0b1xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_GCC_ARM/startup_stm32g0b1xx.S new file mode 100644 index 00000000000..34f7f7af87a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_GCC_ARM/startup_stm32g0b1xx.S @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file startup_stm32g0b1xx.s + * @author MCD Application Team + * @brief STM32G0b1xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC & CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word USB_UCPD1_2_IRQHandler /* USB, UCPD1, UCPD2 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler /* DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_TIM4_IRQHandler /* TIM3, TIM4 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_FDCAN_IT0_IRQHandler /* TIM16 & FDCAN1_IT0 & FDCAN2_IT0 */ + .word TIM17_FDCAN_IT1_IRQHandler /* TIM17 & FDCAN1_IT1 & FDCAN2_IT1 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_3_IRQHandler /* I2C2, I2C3 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_3_IRQHandler /* SPI2, SPI3 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_LPUART2_IRQHandler /* USART2 & LPUART2 */ + .word USART3_4_5_6_LPUART1_IRQHandler /* USART3, USART4, USART5, USART6, LPUART1 */ + .word CEC_IRQHandler /* CEC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_UCPD1_2_IRQHandler + .thumb_set USB_UCPD1_2_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_TIM4_IRQHandler + .thumb_set TIM3_TIM4_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_FDCAN_IT0_IRQHandler + .thumb_set TIM16_FDCAN_IT0_IRQHandler,Default_Handler + + .weak TIM17_FDCAN_IT1_IRQHandler + .thumb_set TIM17_FDCAN_IT1_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_IRQHandler + .thumb_set I2C2_3_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_4_5_6_LPUART1_IRQHandler + .thumb_set USART3_4_5_6_LPUART1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_GCC_ARM/stm32g0b1xe.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_GCC_ARM/stm32g0b1xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_GCC_ARM/stm32g0b1xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_IAR/startup_stm32g0b1xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_IAR/startup_stm32g0b1xx.S new file mode 100644 index 00000000000..56abb5a0691 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_IAR/startup_stm32g0b1xx.S @@ -0,0 +1,299 @@ +;****************************************************************************** +;* File Name : startup_stm32g0b1xx.s +;* Author : MCD Application Team +;* Description : STM32G0B1xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD USB_UCPD1_2_IRQHandler ; UCPD1, UCPD2 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0 + DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_3_IRQHandler ; I2C2, I2C3 + DCD SPI1_IRQHandler ; SPI1/I2S1 + DCD SPI2_3_IRQHandler ; SPI2/I2S2, SPI3/I2S3 + DCD USART1_IRQHandler ; USART1 + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART2 + DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1 + DCD CEC_IRQHandler ; CEC + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK USB_UCPD1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_UCPD1_2_IRQHandler + B USB_UCPD1_2_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + B DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_TIM4_IRQHandler + B TIM3_TIM4_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_FDCAN_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_FDCAN_IT0_IRQHandler + B TIM16_FDCAN_IT0_IRQHandler + + PUBWEAK TIM17_FDCAN_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_FDCAN_IT1_IRQHandler + B TIM17_FDCAN_IT1_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_3_IRQHandler + B I2C2_3_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_3_IRQHandler + B SPI2_3_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_LPUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_LPUART2_IRQHandler + B USART2_LPUART2_IRQHandler + + PUBWEAK USART3_4_5_6_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_5_6_LPUART1_IRQHandler + B USART3_4_5_6_LPUART1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_IAR/stm32g0b1xe.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_IAR/stm32g0b1xe.icf new file mode 100644 index 00000000000..3c124741763 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/TOOLCHAIN_IAR/stm32g0b1xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/cmsis_nvic.h new file mode 100644 index 00000000000..5a4e7a7fce7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x24000 // 144 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/system_clock.c new file mode 100644 index 00000000000..4d54810d2e4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0B1xE/system_clock.c @@ -0,0 +1,167 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2019-2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** + * This file configures the system clock depending on config from targets.json: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external clock) + * | 2- USE_PLL_HSE_XTAL (external xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------- + * SYSCLK(MHz) | 64 + * AHBCLK (MHz) | 64 + * APB1CLK (MHz) | 64 + * USB capable | NO + *----------------------------------------------------------------- + */ + +#include "stm32g0xx.h" +#include "mbed_error.h" + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c) + * and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c) + * @param None + * @retval None + */ + +MBED_WEAK void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 16; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 8; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/CMakeLists.txt new file mode 100644 index 00000000000..cb1a0e7af58 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g0c1xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g0c1xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g0c1xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g0c1xe.sct) +endif() + +add_library(mbed-stm32g0c1xe INTERFACE) + +target_include_directories(mbed-stm32g0c1xe + INTERFACE + . +) + +target_sources(mbed-stm32g0c1xe + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g0c1xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g0c1xe INTERFACE mbed-stm32g0) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_ARM/startup_stm32g0c1xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_ARM/startup_stm32g0c1xx.S new file mode 100644 index 00000000000..5887722a311 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_ARM/startup_stm32g0c1xx.S @@ -0,0 +1,209 @@ +;****************************************************************************** +;* File Name : startup_stm32g0c1xx.s +;* Author : MCD Application Team +;* Description : STM32G0c1xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;****************************************************************************** + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC & CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD USB_UCPD1_2_IRQHandler ; USB, UCPD1 & UCPD2 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5 ,DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0 + DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_3_IRQHandler ; I2C2, I2C3 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_3_IRQHandler ; SPI2, SPI3 + DCD USART1_IRQHandler ; USART1 + DCD USART2_LPUART2_IRQHandler ; USART2 & LPUART2 + DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1 + DCD CEC_IRQHandler ; CEC + DCD AES_RNG_IRQHandler ; AES, RNG + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_TAMP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT USB_UCPD1_2_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_TIM4_IRQHandler [WEAK] + EXPORT TIM6_DAC_LPTIM1_IRQHandler [WEAK] + EXPORT TIM7_LPTIM2_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_FDCAN_IT0_IRQHandler [WEAK] + EXPORT TIM17_FDCAN_IT1_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_3_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_LPUART2_IRQHandler [WEAK] + EXPORT USART3_4_5_6_LPUART1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT AES_RNG_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_TAMP_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +USB_UCPD1_2_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_TIM4_IRQHandler +TIM6_DAC_LPTIM1_IRQHandler +TIM7_LPTIM2_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_FDCAN_IT0_IRQHandler +TIM17_FDCAN_IT1_IRQHandler +I2C1_IRQHandler +I2C2_3_IRQHandler +SPI1_IRQHandler +SPI2_3_IRQHandler +USART1_IRQHandler +USART2_LPUART2_IRQHandler +USART3_4_5_6_LPUART1_IRQHandler +CEC_IRQHandler +AES_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_ARM/stm32g0c1xe.sct b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_ARM/stm32g0c1xe.sct new file mode 100644 index 00000000000..cf04d70e71c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_ARM/stm32g0c1xe.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_GCC_ARM/startup_stm32g0c1xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_GCC_ARM/startup_stm32g0c1xx.S new file mode 100644 index 00000000000..41b263fba17 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_GCC_ARM/startup_stm32g0c1xx.S @@ -0,0 +1,300 @@ +/** + ****************************************************************************** + * @file startup_stm32g0c1xx.s + * @author MCD Application Team + * @brief STM32G0c1xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018-2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC & CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word USB_UCPD1_2_IRQHandler /* USB, UCPD1, UCPD2 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler /* DMA1 Ch4 to Ch7, DMA2 Ch1 to Ch5, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_TIM4_IRQHandler /* TIM3, TIM4 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_FDCAN_IT0_IRQHandler /* TIM16 & FDCAN1_IT0 & FDCAN2_IT0 */ + .word TIM17_FDCAN_IT1_IRQHandler /* TIM17 & FDCAN1_IT1 & FDCAN2_IT1 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_3_IRQHandler /* I2C2, I2C3 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_3_IRQHandler /* SPI2, SPI3 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_LPUART2_IRQHandler /* USART2 & LPUART2 */ + .word USART3_4_5_6_LPUART1_IRQHandler /* USART3, USART4, USART5, USART6, LPUART1 */ + .word CEC_IRQHandler /* CEC */ + .word AES_RNG_IRQHandler /* AES and RNG */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak USB_UCPD1_2_IRQHandler + .thumb_set USB_UCPD1_2_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_TIM4_IRQHandler + .thumb_set TIM3_TIM4_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_FDCAN_IT0_IRQHandler + .thumb_set TIM16_FDCAN_IT0_IRQHandler,Default_Handler + + .weak TIM17_FDCAN_IT1_IRQHandler + .thumb_set TIM17_FDCAN_IT1_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_3_IRQHandler + .thumb_set I2C2_3_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_3_IRQHandler + .thumb_set SPI2_3_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_LPUART2_IRQHandler + .thumb_set USART2_LPUART2_IRQHandler,Default_Handler + + .weak USART3_4_5_6_LPUART1_IRQHandler + .thumb_set USART3_4_5_6_LPUART1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak AES_RNG_IRQHandler + .thumb_set AES_RNG_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_GCC_ARM/stm32g0c1xe.ld b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_GCC_ARM/stm32g0c1xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_GCC_ARM/stm32g0c1xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_IAR/startup_stm32g0c1xx.S b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_IAR/startup_stm32g0c1xx.S new file mode 100644 index 00000000000..b9e6d3dd9db --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_IAR/startup_stm32g0c1xx.S @@ -0,0 +1,305 @@ +;****************************************************************************** +;* File Name : startup_stm32g0c1xx.s +;* Author : MCD Application Team +;* Description : STM32G0C1xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2018-2021 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_TAMP_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD USB_UCPD1_2_IRQHandler ; UCPD1, UCPD2 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler ; DMA1 Channel 4 to Channel 7, DMA2 Channel 1 to Channel 5, DMAMUX1 overrun + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1, COMP2 and COMP3 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_TIM4_IRQHandler ; TIM3, TIM4 + DCD TIM6_DAC_LPTIM1_IRQHandler ; TIM6, DAC & LPTIM1 + DCD TIM7_LPTIM2_IRQHandler ; TIM7 & LPTIM2 + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_FDCAN_IT0_IRQHandler ; TIM16 & FDCAN1_IT0 & FDCAN2_IT0 + DCD TIM17_FDCAN_IT1_IRQHandler ; TIM17 & FDCAN1_IT1 & FDCAN2_IT1 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_3_IRQHandler ; I2C2, I2C3 + DCD SPI1_IRQHandler ; SPI1/I2S1 + DCD SPI2_3_IRQHandler ; SPI2/I2S2, SPI3/I2S3 + DCD USART1_IRQHandler ; USART1 + DCD USART2_LPUART2_IRQHandler ; USART2, LPUART2 + DCD USART3_4_5_6_LPUART1_IRQHandler ; USART3, USART4, USART5, USART6, LPUART1 + DCD CEC_IRQHandler ; CEC + DCD AES_RNG_IRQHandler ; AES, RNG + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_TAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_IRQHandler + B RTC_TAMP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK USB_UCPD1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_UCPD1_2_IRQHandler + B USB_UCPD1_2_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + B DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQHandler + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_TIM4_IRQHandler + B TIM3_TIM4_IRQHandler + + PUBWEAK TIM6_DAC_LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_LPTIM1_IRQHandler + B TIM6_DAC_LPTIM1_IRQHandler + + PUBWEAK TIM7_LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_LPTIM2_IRQHandler + B TIM7_LPTIM2_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_FDCAN_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_FDCAN_IT0_IRQHandler + B TIM16_FDCAN_IT0_IRQHandler + + PUBWEAK TIM17_FDCAN_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_FDCAN_IT1_IRQHandler + B TIM17_FDCAN_IT1_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK I2C2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_3_IRQHandler + B I2C2_3_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_3_IRQHandler + B SPI2_3_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_LPUART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_LPUART2_IRQHandler + B USART2_LPUART2_IRQHandler + + PUBWEAK USART3_4_5_6_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_4_5_6_LPUART1_IRQHandler + B USART3_4_5_6_LPUART1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK AES_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_RNG_IRQHandler + B AES_RNG_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_IAR/stm32g0c1xe.icf b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_IAR/stm32g0c1xe.icf new file mode 100644 index 00000000000..3c124741763 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/TOOLCHAIN_IAR/stm32g0c1xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/cmsis_nvic.h new file mode 100644 index 00000000000..5a4e7a7fce7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G0C1xE/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x24000 // 144 KB +#endif + +#define NVIC_NUM_VECTORS 48 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/flash_api.c b/targets/TARGET_STM/TARGET_STM32G0/flash_api.c index 496e6e7c4fc..ef60cbd7c7a 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32G0/flash_api.c @@ -24,6 +24,44 @@ #include "cmsis.h" +uint32_t GetBank(uint32_t Addr) +{ +#if defined(FLASH_DBANK_SUPPORT) + if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) + { + return FLASH_BANK_1; + } + else + { + return FLASH_BANK_2; + } +#else + return FLASH_BANK_1; +#endif +} + +uint32_t GetPage(uint32_t Addr) +{ + uint32_t page = 0; + +#if defined(FLASH_DBANK_SUPPORT) + if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) + { + /* Bank 1 */ + page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE; + } + else + { + /* Bank 2 */ + page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE; + } +#else + page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE; +#endif + + return page; +} + int32_t flash_init(flash_t *obj) { return 0; @@ -57,7 +95,8 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) /* MBED HAL erases 1 sector at a time */ /* Fill EraseInit structure*/ EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; - EraseInitStruct.Page = (address & 0xFFFFF) / 2048; // page size = 2048 + EraseInitStruct.Banks = GetBank(address); + EraseInitStruct.Page = GetPage(address); EraseInitStruct.NbPages = 1; /* Note: If an erase operation in Flash memory also concerns data in the data or instruction cache, diff --git a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c index e7d9894ba91..694d80bb2c5 100755 --- a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c +++ b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c @@ -45,7 +45,33 @@ uint32_t i2c_get_pclk(I2CName i2c) pclk = HSI_VALUE; break; } - } else { + } + else if (i2c == I2C_2) { +#if defined(RCC_CCIPR_I2C2SEL) + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } +#else + pclk = HAL_RCC_GetPCLK1Freq(); +#endif + } +#if defined I2C3_BASE + else if (i2c == I2C_3) { + pclk = HAL_RCC_GetPCLK1Freq(); + } +#endif + else { // should not happend error("I2C: unknown instance"); } diff --git a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h index dfc765c259b..d16e727581d 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h @@ -37,8 +37,15 @@ extern "C" { #define I2C1_EV_IRQn I2C1_IRQn #define I2C1_ER_IRQn I2C1_IRQn +#if defined (STM32G0B0xx) || defined (STM32G0B1xx) || defined (STM32G0C1xx) +#define I2C2_EV_IRQn I2C2_3_IRQn +#define I2C2_ER_IRQn I2C2_3_IRQn +#define I2C3_EV_IRQn I2C2_3_IRQn +#define I2C3_ER_IRQn I2C2_3_IRQn +#else #define I2C2_EV_IRQn I2C2_IRQn #define I2C2_ER_IRQn I2C2_IRQn +#endif #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) diff --git a/targets/TARGET_STM/TARGET_STM32G0/objects.h b/targets/TARGET_STM/TARGET_STM32G0/objects.h index 3673f6e755d..55dea741cef 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G0/objects.h @@ -114,8 +114,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c index 07f47048f20..af986bebfe5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c @@ -17,14 +17,32 @@ #include "serial_api_hal.h" - -#if defined (STM32G031xx) +#if defined (STM32G030xx) || defined (STM32G050xx) +#define UART_NUM (2) +#define USART_GROUP1_IRQn USART2_IRQn +#elif defined (STM32G031xx) || defined (STM32G041xx) || defined (STM32G051xx) || defined (STM32G061xx) #define UART_NUM (3) -#else +#define USART_GROUP1_IRQn USART2_IRQn +#define USART_GROUP2_IRQn LPUART1_IRQn +#elif defined (STM32G070xx) +#define UART_NUM (4) +#define USART_GROUP1_IRQn USART2_IRQn +#define USART_GROUP2_IRQn USART3_4_IRQn +#elif defined (STM32G071xx) || defined (STM32G081xx) #define UART_NUM (5) +#define USART_GROUP1_IRQn USART2_IRQn +#define USART_GROUP2_IRQn USART3_4_LPUART1_IRQn +#elif defined (STM32G0B0xx) +#define UART_NUM (6) +#define USART_GROUP1_IRQn USART2_IRQn +#define USART_GROUP2_IRQn USART3_4_5_6_IRQn +#elif defined (STM32G0B1xx) || defined (STM32G0C1xx) +#define UART_NUM (8) +#define USART_GROUP1_IRQn USART2_LPUART2_IRQn +#define USART_GROUP2_IRQn USART3_4_5_6_LPUART1_IRQn #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -42,15 +60,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -70,40 +88,45 @@ static void uart1_irq(void) } #endif -#if defined(USART2_BASE) -static void uart2_irq(void) +#if defined (USART_GROUP1_IRQn) +static void uart_group1_irq(void) { +#if defined(USART2_BASE) uart_irq(UART_2); +#endif +#if defined(LPUART2_BASE) + uart_irq(LPUART_2); +#endif } #endif -#if defined(USART3_BASE) -static void uart3_irq(void) +#if defined(USART_GROUP2_IRQn) +static void uart_group2_irq(void) { +#if defined(USART3_BASE) uart_irq(UART_3); -} #endif - #if defined(USART4_BASE) -static void uart4_irq(void) -{ uart_irq(UART_4); -} #endif - +#if defined(USART5_BASE) + uart_irq(UART_5); +#endif +#if defined(USART6_BASE) + uart_irq(UART_6); +#endif #if defined(LPUART1_BASE) -static void lpuart1_irq(void) -{ uart_irq(LPUART_1); +#endif } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -122,41 +145,50 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) #if defined(USART2_BASE) if (obj_s->uart == UART_2) { - irq_n = USART2_IRQn; - vector = (uint32_t)&uart2_irq; + irq_n = USART_GROUP1_IRQn; + vector = (uint32_t)&uart_group1_irq; } #endif #if defined(USART3_BASE) if (obj_s->uart == UART_3) { -#if defined(LPUART1_BASE) - irq_n = USART3_4_LPUART1_IRQn; -#else - irq_n = USART3_4_IRQn; -#endif - vector = (uint32_t)&uart3_irq; + irq_n = USART_GROUP2_IRQn; + vector = (uint32_t)&uart_group2_irq; } #endif #if defined(USART4_BASE) if (obj_s->uart == UART_4) { -#if defined(LPUART1_BASE) - irq_n = USART3_4_LPUART1_IRQn; -#else - irq_n = USART3_4_IRQn; + irq_n = USART_GROUP2_IRQn; + vector = (uint32_t)&uart_group2_irq; + } +#endif + +#if defined(USART5_BASE) + if (obj_s->uart == UART_5) { + irq_n = USART_GROUP2_IRQn; + vector = (uint32_t)&uart_group2_irq; + } #endif - vector = (uint32_t)&uart4_irq; + +#if defined(USART6_BASE) + if (obj_s->uart == UART_6) { + irq_n = USART_GROUP2_IRQn; + vector = (uint32_t)&uart_group2_irq; } #endif #if defined(LPUART1_BASE) if (obj_s->uart == LPUART_1) { -#if defined(USART3_BASE) - irq_n = USART3_4_LPUART1_IRQn; -#else - irq_n = LPUART1_IRQn; + irq_n = USART_GROUP2_IRQn; + vector = (uint32_t)&uart_group2_irq; + } #endif - vector = (uint32_t)&lpuart1_irq; + +#if defined(LPUART2_BASE) + if (obj_s->uart == LPUART_2) { + irq_n = USART_GROUP1_IRQn; + vector = (uint32_t)&uart_group1_irq; } #endif @@ -329,35 +361,37 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) #endif #if defined(USART2_BASE) case UART_2: - irq_n = USART2_IRQn; + irq_n = USART_GROUP1_IRQn; break; #endif #if defined(USART3_BASE) case UART_3: -#if defined(LPUART1_BASE) - irq_n = USART3_4_LPUART1_IRQn; -#else - irq_n = USART3_4_IRQn; -#endif + irq_n = USART_GROUP2_IRQn; break; #endif #if defined(USART4_BASE) case UART_4: -#if defined(LPUART1_BASE) - irq_n = USART3_4_LPUART1_IRQn; -#else - irq_n = USART3_4_IRQn; + irq_n = USART_GROUP2_IRQn; + break; #endif +#if defined(USART5_BASE) + case UART_5: + irq_n = USART_GROUP2_IRQn; + break; +#endif +#if defined(USART6_BASE) + case UART_6: + irq_n = USART_GROUP2_IRQn; break; #endif - #if defined(LPUART1_BASE) case LPUART_1: -#if defined(USART3_BASE) - irq_n = USART3_4_LPUART1_IRQn; -#else - irq_n = LPUART1_IRQn; + irq_n = USART_GROUP2_IRQn; + break; #endif +#if defined(LPUART2_BASE) + case LPUART_2: + irq_n = USART_GROUP1_IRQn; break; #endif default: diff --git a/targets/TARGET_STM/TARGET_STM32G0/spi_api.c b/targets/TARGET_STM/TARGET_STM32G0/spi_api.c index 8ffb4c7bc31..c080738b03b 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32G0/spi_api.c @@ -43,6 +43,9 @@ int spi_get_clock_freq(spi_t *obj) switch ((int)spiobj->spi) { case SPI_1: case SPI_2: +#if defined SPI3_BASE + case SPI_3: +#endif /* SPI_1 and SPI_2. Source CLK is PCKL1 */ spi_hz = HAL_RCC_GetPCLK1Freq(); break; diff --git a/targets/TARGET_STM/TARGET_STM32G0/spi_device.h b/targets/TARGET_STM/TARGET_STM32G0/spi_device.h index 7c03e60b362..74567d7c7e3 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/spi_device.h +++ b/targets/TARGET_STM/TARGET_STM32G0/spi_device.h @@ -17,6 +17,11 @@ #include "stm32g0xx_ll_spi.h" +#if defined (STM32G0B0xx) || defined (STM32G0B1xx) || defined (STM32G0C1xx) +#define SPI2_IRQn SPI2_3_IRQn +#define SPI3_IRQn SPI2_3_IRQn +#endif + // Defines the word legnth capability of the device where Nth bit allows for N window size #define STM32_SPI_CAPABILITY_WORD_LENGTH (0x0000FFF8) diff --git a/targets/TARGET_STM/TARGET_STM32G0/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32G0/us_ticker_data.h index 089e240da83..6ab9fc1cc6a 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32G0/us_ticker_data.h @@ -38,7 +38,11 @@ extern "C" { #else // TIM2_BASE #define TIM_MST TIM3 +#if defined (STM32G0B0xx) +#define TIM_MST_IRQ TIM3_TIM4_IRQn +#else #define TIM_MST_IRQ TIM3_IRQn +#endif #define TIM_MST_RCC __TIM3_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM3() diff --git a/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt index a670385d2d5..6808ec840b3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt @@ -8,6 +8,8 @@ add_subdirectory(TARGET_STM32G473xE EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32G474xE EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32G483xE EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32G484xE EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G491xE EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32G4A1xE EXCLUDE_FROM_ALL) add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL) add_library(mbed-stm32g4 INTERFACE) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h index 100406bf348..605669a2c78 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g431xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g441xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g441xx.h index a1e3d44efaa..3ca377a23c6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g441xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g441xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h index 9a3fe226de4..89dac423a75 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h @@ -7,18 +7,17 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -45,11 +44,11 @@ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ -#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ /** * @} @@ -125,7 +124,6 @@ typedef enum TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ @@ -141,6 +139,10 @@ typedef enum COMP4_IRQn = 65, /*!< COMP4 */ CRS_IRQn = 75, /*!< CRS global interrupt */ SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */ + TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */ + TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */ + TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */ + TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */ I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */ @@ -967,6 +969,10 @@ typedef struct } UCPD_TypeDef; +/** + * @} + */ + /** @addtogroup Peripheral_memory_map * @{ */ @@ -1002,7 +1008,6 @@ typedef struct #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) #define CRS_BASE (APB1PERIPH_BASE + 0x2000UL) @@ -1052,6 +1057,7 @@ typedef struct #define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) #define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) #define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL) #define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) #define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) #define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) @@ -1144,7 +1150,6 @@ typedef struct #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define CRS ((CRS_TypeDef *) CRS_BASE) @@ -1192,6 +1197,7 @@ typedef struct #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM20 ((TIM_TypeDef *) TIM20_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) @@ -1277,6 +1283,15 @@ typedef struct * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2928,9 +2943,6 @@ typedef struct #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U) #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */ #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk -#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) -#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */ -#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */ #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk @@ -2980,6 +2992,9 @@ typedef struct #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */ #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk +#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U) +#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */ +#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk /******************************************************************************/ /* */ @@ -8101,9 +8116,6 @@ typedef struct #define RCC_APB1RSTR1_TIM4RST_Pos (2U) #define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */ #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk -#define RCC_APB1RSTR1_TIM5RST_Pos (3U) -#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */ -#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk #define RCC_APB1RSTR1_TIM6RST_Pos (4U) #define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */ #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk @@ -8192,6 +8204,9 @@ typedef struct #define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_TIM20RST_Pos (20U) +#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */ +#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk #define RCC_APB2RSTR_SAI1RST_Pos (21U) #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */ #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk @@ -8272,9 +8287,6 @@ typedef struct #define RCC_APB1ENR1_TIM4EN_Pos (2U) #define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */ #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk -#define RCC_APB1ENR1_TIM5EN_Pos (3U) -#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */ -#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk #define RCC_APB1ENR1_TIM6EN_Pos (4U) #define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */ #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk @@ -8369,6 +8381,9 @@ typedef struct #define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_TIM20EN_Pos (20U) +#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */ +#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk #define RCC_APB2ENR_SAI1EN_Pos (21U) #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */ #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk @@ -8458,9 +8473,6 @@ typedef struct #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U) #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */ #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk -#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U) -#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */ -#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U) #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */ #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk @@ -8555,6 +8567,9 @@ typedef struct #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */ #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk +#define RCC_APB2SMENR_TIM20SMEN_Pos (20U) +#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */ +#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk #define RCC_APB2SMENR_SAI1SMEN_Pos (21U) #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */ #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk @@ -13396,122 +13411,127 @@ typedef struct ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ - ((INSTANCE) == TIM5)) +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /************** TIM Instances : supporting Break source selection *************/ #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting 2 break inputs *****************/ #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************* TIM Instances : at least 1 capture/compare channel *************/ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : at least 2 capture/compare channels *************/ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : at least 3 capture/compare channels *************/ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : at least 4 capture/compare channels *************/ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : at least 5 capture/compare channels *******/ #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : at least 6 capture/compare channels *******/ #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /******************** TIM Instances : DMA burst feature ***********************/ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /******************* TIM Instances : output(s) available **********************/ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ @@ -13541,12 +13561,6 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ - (((INSTANCE) == TIM5) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ (((INSTANCE) == TIM8) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ @@ -13563,7 +13577,15 @@ typedef struct (((CHANNEL) == TIM_CHANNEL_1))) \ || \ (((INSTANCE) == TIM17) && \ - (((CHANNEL) == TIM_CHANNEL_1)))) + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM20) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6)))) /****************** TIM Instances : supporting complementary output(s) ********/ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ @@ -13586,135 +13608,143 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_1)) \ || \ (((INSTANCE) == TIM17) && \ - ((CHANNEL) == TIM_CHANNEL_1))) + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM20) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4)))) /****************** TIM Instances : supporting clock division *****************/ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15)|| \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15)|| \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting commutation event generation ***/ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting counting mode selection ********/ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting encoder interface **************/ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting Hall sensor interface **********/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /**************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /************* TIM Instances : supporting ETR source selection ***************/ #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/ #define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ @@ -13723,51 +13753,54 @@ typedef struct ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting repetition counter *************/ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /******************* TIM Instances : Timer input XOR function *****************/ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ - ((INSTANCE) == TIM15)) + ((INSTANCE) == TIM15) || \ + ((INSTANCE) == TIM20)) /******************* TIM Instances : Timer input selection ********************/ #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ - ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM15) || \ ((INSTANCE) == TIM16) || \ - ((INSTANCE) == TIM17)) + ((INSTANCE) == TIM17) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : Advanced timer instances *******************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ - ((INSTANCE) == TIM8)) - + ((INSTANCE) == TIM8) || \ + ((INSTANCE) == TIM20)) /****************** TIM Instances : supporting HSE/32 request instances *******************/ #define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \ @@ -13907,4 +13940,3 @@ typedef struct * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g473xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g473xx.h index 3d33331519f..debfe8d2956 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g473xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g473xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h index 46563790faa..50696cde6c9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g483xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g483xx.h index c1bf5ab7fa1..2fc1efaf710 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g483xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g483xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h index 402b8e3c43c..088ae0aea35 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g491xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g491xx.h index f5927aa4f28..e7c3cb532f5 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g491xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g491xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4a1xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4a1xx.h index feae9f28e1d..aa2261724c0 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4a1xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4a1xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h index 65d3559e0ad..eb3c7430d2c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32G4xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32gbk1cb.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32gbk1cb.h index 76781724fa3..b09e705b7f5 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32gbk1cb.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32gbk1cb.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c index 19a03051f12..30782b7d5d6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c @@ -1814,13 +1814,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -2458,13 +2458,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -6597,7 +6597,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } @@ -7159,13 +7159,13 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) { return HAL_ERROR; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c index 43ae8593e16..96d74e24467 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 170MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 24.09s + max timeout before reset: approximately 24.09us (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 197.38ms diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/CMakeLists.txt new file mode 100644 index 00000000000..b87e3ddda67 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g491xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g491xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g491xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g491xe.sct) +endif() + +add_library(mbed-stm32g491xe INTERFACE) + +target_include_directories(mbed-stm32g491xe + INTERFACE + . +) + +target_sources(mbed-stm32g491xe + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g491xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g491xe INTERFACE mbed-stm32g4) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_ARM/startup_stm32g491xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_ARM/startup_stm32g491xx.S new file mode 100644 index 00000000000..0dad61b112a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_ARM/startup_stm32g491xx.S @@ -0,0 +1,404 @@ +;******************************************************************************* +;* @File Name : startup_stm32g491xx.s +;* @Author : MCD Application Team +;* @Brief : Vector table for MDK-ARM toolchain +;******************************************************************************* +;* Description : STM32G491xx Mainstream devices vector table for +;* MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_IRQHandler ; USB Device High Priority + DCD USB_LP_IRQHandler ; USB Device Low Priority + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD UCPD1_IRQHandler ; UCPD1 + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_IRQHandler ; COMP4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CRS_IRQHandler ; CRS Interrupt + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8 + DCD CORDIC_IRQHandler ; CORDIC + DCD FMAC_IRQHandler ; FMAC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT TIM20_BRK_IRQHandler [WEAK] + EXPORT TIM20_UP_IRQHandler [WEAK] + EXPORT TIM20_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT DMAMUX_OVR_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DMA1_Channel8_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel8_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +RTC_TAMP_LSECSS_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +LPTIM1_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +UCPD1_IRQHandler +COMP1_2_3_IRQHandler +COMP4_IRQHandler +CRS_IRQHandler +SAI1_IRQHandler +TIM20_BRK_IRQHandler +TIM20_UP_IRQHandler +TIM20_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +FPU_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler +RNG_IRQHandler +LPUART1_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +DMAMUX_OVR_IRQHandler +QUADSPI_IRQHandler +DMA1_Channel8_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA2_Channel8_IRQHandler +CORDIC_IRQHandler +FMAC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_ARM/stm32g491xe.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_ARM/stm32g491xe.sct new file mode 100644 index 00000000000..7aff08bc288 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_ARM/stm32g491xe.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_GCC_ARM/startup_stm32g491xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_GCC_ARM/startup_stm32g491xx.S new file mode 100644 index 00000000000..05ef6e7965d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_GCC_ARM/startup_stm32g491xx.S @@ -0,0 +1,534 @@ +/** + ****************************************************************************** + * @file startup_stm32g491xx.s + * @author MCD Application Team + * @brief STM32G491xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word 0 + .word LPTIM1_IRQHandler + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_LSECSS_IRQHandler + .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_IRQHandler + .thumb_set COMP4_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak DMAMUX_OVR_IRQHandler + .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_GCC_ARM/stm32g491xe.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_GCC_ARM/stm32g491xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_GCC_ARM/stm32g491xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_IAR/startup_stm32g491xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_IAR/startup_stm32g491xx.S new file mode 100644 index 00000000000..a5c790464ad --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_IAR/startup_stm32g491xx.S @@ -0,0 +1,651 @@ +;******************************************************************************* +;* @File Name : startup_stm32g491xx.s +;* @Author : MCD Application Team +;* @Brief : STM32G491xx Devices vector +;******************************************************************************* +;* Description : This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_IRQHandler ; USB Device High Priority + DCD USB_LP_IRQHandler ; USB Device Low Priority + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD UCPD1_IRQHandler ; UCPD1 + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_IRQHandler ; COMP4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CRS_IRQHandler ; CRS Interrupt + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8 + DCD CORDIC_IRQHandler ; CORDIC + DCD FMAC_IRQHandler ; FMAC + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK RTC_TAMP_LSECSS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_LSECSS_IRQHandler + B RTC_TAMP_LSECSS_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK UCPD1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UCPD1_IRQHandler + B UCPD1_IRQHandler + + PUBWEAK COMP1_2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_2_3_IRQHandler + B COMP1_2_3_IRQHandler + + PUBWEAK COMP4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_IRQHandler + B COMP4_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK TIM20_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_BRK_IRQHandler + B TIM20_BRK_IRQHandler + + PUBWEAK TIM20_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_UP_IRQHandler + B TIM20_UP_IRQHandler + + PUBWEAK TIM20_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_TRG_COM_IRQHandler + B TIM20_TRG_COM_IRQHandler + + PUBWEAK TIM20_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_CC_IRQHandler + B TIM20_CC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK DMAMUX_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX_OVR_IRQHandler + B DMAMUX_OVR_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK DMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel8_IRQHandler + B DMA1_Channel8_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA2_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel8_IRQHandler + B DMA2_Channel8_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + END diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_IAR/stm32g491xe.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_IAR/stm32g491xe.icf new file mode 100644 index 00000000000..18180b93bf2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/TOOLCHAIN_IAR/stm32g491xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 118; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x4000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/cmsis_nvic.h new file mode 100644 index 00000000000..095a5f6dc20 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G491xE/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x1c000 // 112 KB +#endif + +#define NVIC_NUM_VECTORS 118 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/CMakeLists.txt new file mode 100644 index 00000000000..7d35acdfd36 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g4a1xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g4a1xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g4a1xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32g4a1xe.sct) +endif() + +add_library(mbed-stm32g4a1xe INTERFACE) + +target_include_directories(mbed-stm32g4a1xe + INTERFACE + . +) + +target_sources(mbed-stm32g4a1xe + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32g4a1xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32g4a1xe INTERFACE mbed-stm32g4) diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_ARM/startup_stm32g4a1xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_ARM/startup_stm32g4a1xx.S new file mode 100644 index 00000000000..b6aa50c11b9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_ARM/startup_stm32g4a1xx.S @@ -0,0 +1,406 @@ +;******************************************************************************* +;* @File Name : startup_stm32g4a1xx.s +;* @Author : MCD Application Team +;* @Brief : Vector table for MDK-ARM toolchain +;******************************************************************************* +;* Description : STM32G4A1xx Mainstream devices vector table for +;* MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_IRQHandler ; USB Device High Priority + DCD USB_LP_IRQHandler ; USB Device Low Priority + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD UCPD1_IRQHandler ; UCPD1 + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_IRQHandler ; COMP4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CRS_IRQHandler ; CRS Interrupt + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD AES_IRQn ; AES global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8 + DCD CORDIC_IRQHandler ; CORDIC + DCD FMAC_IRQHandler ; FMAC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT RTC_TAMP_LSECSS_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT UCPD1_IRQHandler [WEAK] + EXPORT COMP1_2_3_IRQHandler [WEAK] + EXPORT COMP4_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT TIM20_BRK_IRQHandler [WEAK] + EXPORT TIM20_UP_IRQHandler [WEAK] + EXPORT TIM20_TRG_COM_IRQHandler [WEAK] + EXPORT TIM20_CC_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT AES_IRQn [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT DMAMUX_OVR_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DMA1_Channel8_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel8_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +RTC_TAMP_LSECSS_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +LPTIM1_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +UCPD1_IRQHandler +COMP1_2_3_IRQHandler +COMP4_IRQHandler +CRS_IRQHandler +SAI1_IRQHandler +TIM20_BRK_IRQHandler +TIM20_UP_IRQHandler +TIM20_TRG_COM_IRQHandler +TIM20_CC_IRQHandler +FPU_IRQHandler +AES_IRQn +FDCAN2_IT0_IRQHandler +FDCAN2_IT1_IRQHandler +RNG_IRQHandler +LPUART1_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +DMAMUX_OVR_IRQHandler +QUADSPI_IRQHandler +DMA1_Channel8_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA2_Channel8_IRQHandler +CORDIC_IRQHandler +FMAC_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_ARM/stm32g4a1xe.sct b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_ARM/stm32g4a1xe.sct new file mode 100644 index 00000000000..7aff08bc288 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_ARM/stm32g4a1xe.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_GCC_ARM/startup_stm32g4a1xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_GCC_ARM/startup_stm32g4a1xx.S new file mode 100644 index 00000000000..2dcfe12e53f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_GCC_ARM/startup_stm32g4a1xx.S @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file startup_stm32g4a1xx.s + * @author MCD Application Team + * @brief STM32G4A1xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word RTC_TAMP_LSECSS_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word FDCAN1_IT0_IRQHandler + .word FDCAN1_IT1_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USBWakeUp_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word 0 + .word LPTIM1_IRQHandler + .word 0 + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word UCPD1_IRQHandler + .word COMP1_2_3_IRQHandler + .word COMP4_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word CRS_IRQHandler + .word SAI1_IRQHandler + .word TIM20_BRK_IRQHandler + .word TIM20_UP_IRQHandler + .word TIM20_TRG_COM_IRQHandler + .word TIM20_CC_IRQHandler + .word FPU_IRQHandler + .word 0 + .word 0 + .word 0 + .word AES_IRQHandler + .word FDCAN2_IT0_IRQHandler + .word FDCAN2_IT1_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word LPUART1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word DMAMUX_OVR_IRQHandler + .word QUADSPI_IRQHandler + .word DMA1_Channel8_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word DMA2_Channel8_IRQHandler + .word CORDIC_IRQHandler + .word FMAC_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_LSECSS_IRQHandler + .thumb_set RTC_TAMP_LSECSS_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USBWakeUp_IRQHandler + .thumb_set USBWakeUp_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak UCPD1_IRQHandler + .thumb_set UCPD1_IRQHandler,Default_Handler + + .weak COMP1_2_3_IRQHandler + .thumb_set COMP1_2_3_IRQHandler,Default_Handler + + .weak COMP4_IRQHandler + .thumb_set COMP4_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TIM20_BRK_IRQHandler + .thumb_set TIM20_BRK_IRQHandler,Default_Handler + + .weak TIM20_UP_IRQHandler + .thumb_set TIM20_UP_IRQHandler,Default_Handler + + .weak TIM20_TRG_COM_IRQHandler + .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler + + .weak TIM20_CC_IRQHandler + .thumb_set TIM20_CC_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak DMAMUX_OVR_IRQHandler + .thumb_set DMAMUX_OVR_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DMA1_Channel8_IRQHandler + .thumb_set DMA1_Channel8_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak DMA2_Channel8_IRQHandler + .thumb_set DMA2_Channel8_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_GCC_ARM/stm32g4a1xe.ld b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_GCC_ARM/stm32g4a1xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_GCC_ARM/stm32g4a1xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_IAR/startup_stm32g4a1xx.S b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_IAR/startup_stm32g4a1xx.S new file mode 100644 index 00000000000..909d9ec75cc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_IAR/startup_stm32g4a1xx.S @@ -0,0 +1,656 @@ +;******************************************************************************* +;* @File Name : startup_stm32g4a1xx.s +;* @Author : MCD Application Team +;* @Brief : STM32G4A1xx Devices vector +;******************************************************************************* +;* Description : This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD RTC_TAMP_LSECSS_IRQHandler ; RTC, TAMP and RCC LSE_CSS through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_IRQHandler ; USB Device High Priority + DCD USB_LP_IRQHandler ; USB Device Low Priority + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break, Transition error, Index error and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger, Commutation, Direction change, Index and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break, Transition error and Index error Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger, Commutation, Direction change and Index Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&3 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD UCPD1_IRQHandler ; UCPD1 + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_IRQHandler ; COMP4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CRS_IRQHandler ; CRS Interrupt + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD TIM20_BRK_IRQHandler ; TIM20 Break, Transition error and Index error + DCD TIM20_UP_IRQHandler ; TIM20 Update + DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger, Commutation, Direction change and Index + DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD AES_IRQHandler ; AES global interrupt + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD I2C3_EV_IRQHandler ; I2C3 Event + DCD I2C3_ER_IRQHandler ; I2C3 Error + DCD DMAMUX_OVR_IRQHandler ; DMAMUX overrun global interrupt + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DMA1_Channel8_IRQHandler ; DMA1 Channel 8 + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD DMA2_Channel8_IRQHandler ; DMA2 Channel 8 + DCD CORDIC_IRQHandler ; CORDIC + DCD FMAC_IRQHandler ; FMAC + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK RTC_TAMP_LSECSS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_LSECSS_IRQHandler + B RTC_TAMP_LSECSS_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK UCPD1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UCPD1_IRQHandler + B UCPD1_IRQHandler + + PUBWEAK COMP1_2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_2_3_IRQHandler + B COMP1_2_3_IRQHandler + + PUBWEAK COMP4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_IRQHandler + B COMP4_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK TIM20_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_BRK_IRQHandler + B TIM20_BRK_IRQHandler + + PUBWEAK TIM20_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_UP_IRQHandler + B TIM20_UP_IRQHandler + + PUBWEAK TIM20_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_TRG_COM_IRQHandler + B TIM20_TRG_COM_IRQHandler + + PUBWEAK TIM20_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM20_CC_IRQHandler + B TIM20_CC_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK DMAMUX_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX_OVR_IRQHandler + B DMAMUX_OVR_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK DMA1_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel8_IRQHandler + B DMA1_Channel8_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK DMA2_Channel8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel8_IRQHandler + B DMA2_Channel8_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + END diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_IAR/stm32g4a1xe.icf b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_IAR/stm32g4a1xe.icf new file mode 100644 index 00000000000..095c9824fee --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/TOOLCHAIN_IAR/stm32g4a1xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 118; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/cmsis_nvic.h new file mode 100644 index 00000000000..095a5f6dc20 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G4A1xE/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x1c000 // 112 KB +#endif + +#define NVIC_NUM_VECTORS 118 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/objects.h b/targets/TARGET_STM/TARGET_STM32G4/objects.h index 53098ec6bdb..647c45253d8 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G4/objects.h @@ -113,8 +113,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; @@ -155,6 +155,19 @@ struct trng_s { RNG_HandleTypeDef handle; }; +#if DEVICE_QSPI +struct qspi_s { + QSPI_HandleTypeDef handle; + QSPIName qspi; + PinName io0; + PinName io1; + PinName io2; + PinName io3; + PinName sclk; + PinName ssel; +}; +#endif + //#include "common_objects.h" #include "gpio_object.h" diff --git a/targets/TARGET_STM/TARGET_STM32G4/serial_device.c b/targets/TARGET_STM/TARGET_STM32G4/serial_device.c index 131812e1841..1c49e52bf5a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32G4/serial_device.c @@ -20,7 +20,7 @@ #define UART_NUM (6) -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -38,15 +38,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -94,12 +94,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -641,7 +641,7 @@ static void _serial_set_flow_control_direct(serial_t *obj, FlowControl type, con } if (type == FlowControlRTS) { // Enable RTS - MBED_ASSERT(pinmap->rx_flow_pin != (UARTName)NC); + MBED_ASSERT(pinmap->rx_flow_pin != NC); obj_s->hw_flow_ctl = UART_HWCONTROL_RTS; obj_s->pin_rts = pinmap->rx_flow_pin; // Enable the pin for RTS function @@ -650,7 +650,7 @@ static void _serial_set_flow_control_direct(serial_t *obj, FlowControl type, con } if (type == FlowControlCTS) { // Enable CTS - MBED_ASSERT(pinmap->tx_flow_pin != (UARTName)NC); + MBED_ASSERT(pinmap->tx_flow_pin != NC); obj_s->hw_flow_ctl = UART_HWCONTROL_CTS; obj_s->pin_cts = pinmap->tx_flow_pin; // Enable the pin for CTS function @@ -659,8 +659,8 @@ static void _serial_set_flow_control_direct(serial_t *obj, FlowControl type, con } if (type == FlowControlRTSCTS) { // Enable CTS & RTS - MBED_ASSERT(pinmap->rx_flow_pin != (UARTName)NC); - MBED_ASSERT(pinmap->tx_flow_pin != (UARTName)NC); + MBED_ASSERT(pinmap->rx_flow_pin != NC); + MBED_ASSERT(pinmap->tx_flow_pin != NC); obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS; obj_s->pin_rts = pinmap->rx_flow_pin;; obj_s->pin_cts = pinmap->tx_flow_pin;; diff --git a/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt index 90cdbee37da..3ecc17c99ab 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt @@ -1,10 +1,16 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_STM32H723xG EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32H725xE EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32H735xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32H743xI EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32H745xI EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32H747xI EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32H750xB EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32H753xI EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32H7A3xIQ EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32H7B3xIQ EXCLUDE_FROM_ALL) add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL) add_library(mbed-stm32h7 INTERFACE) diff --git a/targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h index 9c239ab620f..cc80c9458e1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h @@ -69,7 +69,10 @@ typedef enum { I2C_1 = (int)I2C1_BASE, I2C_2 = (int)I2C2_BASE, I2C_3 = (int)I2C3_BASE, - I2C_4 = (int)I2C4_BASE + I2C_4 = (int)I2C4_BASE, +#if I2C5_BASE + I2C_5 = (int)I2C5_BASE, +#endif } I2CName; typedef enum { @@ -81,18 +84,29 @@ typedef enum { PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE, PWM_5 = (int)TIM5_BASE, + PWM_6 = (int)TIM6_BASE, + PWM_7 = (int)TIM7_BASE, PWM_8 = (int)TIM8_BASE, PWM_12 = (int)TIM12_BASE, PWM_13 = (int)TIM13_BASE, PWM_14 = (int)TIM14_BASE, PWM_15 = (int)TIM15_BASE, PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE + PWM_17 = (int)TIM17_BASE, +#if TIM23_BASE + PWM_23 = (int)TIM23_BASE, +#endif +#if TIM24_BASE + PWM_24 = (int)TIM24_BASE, +#endif } PWMName; typedef enum { CAN_1 = (int)FDCAN1_BASE, - CAN_2 = (int)FDCAN2_BASE + CAN_2 = (int)FDCAN2_BASE, +#if FDCAN3_BASE + CAN_3 = (int)FDCAN3_BASE, +#endif } CANName; typedef enum { diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h index f36b58f77c2..4f3c6124179 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32H7xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c index c1febda0d00..baf248d36a4 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c @@ -456,7 +456,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is "don't care" in the DES or TDES modes) data type and Algorithm */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); #if !defined (CRYP_VER_2_2) @@ -567,7 +567,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.B0 = pConf->B0; hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; - /* Set the key size(This bit field is dont care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is "don't care" in the DES or TDES modes) data type, AlgoMode and operating mode*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c index ae247336351..d42c72d9dc5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c @@ -158,7 +158,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - /*ALGODIR bit must be set to 0.*/ + /*ALGODIR bit must be set to '0'.*/ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; /* Enable the CRYP peripheral */ @@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /* Select final phase & ALGODIR bit must be set to 0. */ + /* Select final phase & ALGODIR bit must be set to '0'. */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h index ecc6290f56c..6dcb610cd0f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h @@ -479,7 +479,7 @@ typedef struct This parameter can be a value of @ref FDCAN_TT_time_master */ uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR - numerator : TUR = (Numerator SDL) / Denominator. + numerator : TUR = (Numerator +/- SDL) / Denominator. With : SDL = 2^(SyncDevLimit+5). This parameter must be a number between 0 and 7 */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c index 1d7efa13771..582ebbd4050 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c @@ -1618,13 +1618,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -2235,13 +2235,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) + if ((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { return HAL_ERROR; } @@ -5329,7 +5329,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } @@ -5764,13 +5764,13 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) + if (hhrtim->State == HAL_HRTIM_STATE_BUSY) { return HAL_BUSY; } - if((hhrtim->State == HAL_HRTIM_STATE_READY)) + if (hhrtim->State == HAL_HRTIM_STATE_READY) { - if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) + if ((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) { return HAL_ERROR; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c index 43b55b20354..fbcb267b2d0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c @@ -40,17 +40,17 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values (case of STM32H74x/5x devices): (++) Counter min (T[5;0] = 0x00) @100MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 40.96µs + max timeout before reset: approximately 40.96us (++) Counter max (T[5;0] = 0x3F) @100MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 335.54ms (+) Typical values (case of STM32H7Ax/Bx devices): (++) Counter min (T[5;0] = 0x00) @140MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 29.25µs + max timeout before reset: approximately 29.25us (++) Counter max (T[5;0] = 0x3F) @140MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 239.67ms (+) Typical values (case of STM32H72x/3x devices): (++) Counter min (T[5;0] = 0x00) @125MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 32.76µs + max timeout before reset: approximately 32.76us (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 268.43ms diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt new file mode 100644 index 00000000000..f8f18a8e07d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h723xg.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h723xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32h723xg.sct) +endif() + +add_library(mbed-stm32h723xg INTERFACE) + +target_include_directories(mbed-stm32h723xg + INTERFACE + . +) + +target_sources(mbed-stm32h723xg + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32h723xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h723xg INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/startup_stm32h723xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/startup_stm32h723xx.S new file mode 100644 index 00000000000..abc35f18a73 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/startup_stm32h723xx.S @@ -0,0 +1,573 @@ +;******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h723xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; DTS interrupt + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; UART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrup + DCD TIM24_IRQHandler ; TIM24 global interrup + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_PSSI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT USART10_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT FDCAN3_IT0_IRQHandler [WEAK] + EXPORT FDCAN3_IT1_IRQHandler [WEAK] + EXPORT TIM23_IRQHandler [WEAK] + EXPORT TIM24_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_PSSI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +OCTOSPI1_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DMAMUX1_OVR_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +DTS_IRQHandler +WAKEUP_PIN_IRQHandler +OCTOSPI2_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +UART9_IRQHandler +USART10_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +FDCAN3_IT0_IRQHandler +FDCAN3_IT1_IRQHandler +TIM23_IRQHandler +TIM24_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/stm32h723xg.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/stm32h723xg.sct new file mode 100644 index 00000000000..0c00f2a328c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_ARM/stm32h723xg.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S new file mode 100644 index 00000000000..a9b669f6542 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/startup_stm32h723xx.S @@ -0,0 +1,756 @@ +/** + ****************************************************************************** + * @file startup_stm32h723xx.s + * @author MCD Application Team + * @brief STM32H723xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word 0 /* Reserved */ + .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word 0 /* Reserved */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word 0 /* Reserved */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMAC_IRQHandler /* FMAC Interrupt */ + .word CORDIC_IRQHandler /* CORDIC Interrupt */ + .word UART9_IRQHandler /* UART9 Interrupt */ + .word USART10_IRQHandler /* UART10 Interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */ + .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */ + .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */ + .word TIM23_IRQHandler /* TIM23 global interrupt */ + .word TIM24_IRQHandler /* TIM24 global interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak TIM23_IRQHandler + .thumb_set TIM23_IRQHandler,Default_Handler + + .weak TIM24_IRQHandler + .thumb_set TIM24_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_GCC_ARM/stm32h723xg.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_IAR/startup_stm32h723xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_IAR/startup_stm32h723xx.S new file mode 100644 index 00000000000..d6437200f0e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_IAR/startup_stm32h723xx.S @@ -0,0 +1,984 @@ +;/******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h723xx.s +;* Author : MCD Application Team +;* Description : STM32H723xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; USART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrup + DCD TIM24_IRQHandler ; TIM24 global interrup + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_PSSI_IRQHandler + B DCMI_PSSI_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK OCTOSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler + B OCTOSPI2_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler + B USART10_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler + B FDCAN3_IT0_IRQHandler + + PUBWEAK FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler + B FDCAN3_IT1_IRQHandler + + PUBWEAK TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler + B TIM23_IRQHandler + + PUBWEAK TIM24_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_IAR/stm32h723xg.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_IAR/stm32h723xg.icf new file mode 100644 index 00000000000..b397a3f3110 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/TOOLCHAIN_IAR/stm32h723xg.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 180; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h new file mode 100644 index 00000000000..e981df8aaa0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/cmsis_nvic.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x100000 // 1 MB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x24000000 +#endif + +#if !defined(MBED_RAM_SIZE) +// 0x38000000 - 0x38003FFF 16K SRAM4 +// 0x30004000 - 0x30007FFF 16K SRAM2 +// 0x30000000 - 0x30003FFF 16K SRAM1 +// 0x24000000 - 0x2404FFFF 320K AXI SRAM +// 0x20000000 - 0x2001FFFF 128K DTCM +#define MBED_RAM_SIZE 0x50000 // 320 KB +#endif + +#define NVIC_NUM_VECTORS 180 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c new file mode 100644 index 00000000000..207555501a4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H723xG/system_clock.c @@ -0,0 +1,160 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2015-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 64 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 480 + * AHBCLK (MHz) | 240 + * APB1CLK (MHz) | 120 + * APB2CLK (MHz) | 120 + * APB3CLK (MHz) | 120 + * APB4CLK (MHz) | 120 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32h7xx.h" +#include "mbed_error.h" + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + error("SetSysClock failed\n"); + } + } + } +} + + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /* Configure the main internal regulator output voltage */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass) { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + } + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; +#if HSE_VALUE==8000000 + RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz + RCC_OscInitStruct.PLL.PLLN = 275; // 550 MHz +#else +#error Unsupported externall clock value, check HSE_VALUE define +#endif + RCC_OscInitStruct.PLL.PLLP = 1; // PLLCLK = SYSCLK = 550 MHz + RCC_OscInitStruct.PLL.PLLQ = 5; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + return 0; // FAIL +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt new file mode 100644 index 00000000000..cf69f2d12e9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h725xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h725xe.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h725xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32h725xe.sct) +endif() + +add_library(mbed-stm32h725xe INTERFACE) + +target_include_directories(mbed-stm32h725xe + INTERFACE + . +) + +target_sources(mbed-stm32h725xe + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32h725xe ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h725xe INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_ARM/startup_stm32h725xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_ARM/startup_stm32h725xx.S new file mode 100644 index 00000000000..2b5dec8a2df --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_ARM/startup_stm32h725xx.S @@ -0,0 +1,573 @@ +;******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h725xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; DTS interrupt + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; UART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrup + DCD TIM24_IRQHandler ; TIM24 global interrup + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_PSSI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT USART10_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT FDCAN3_IT0_IRQHandler [WEAK] + EXPORT FDCAN3_IT1_IRQHandler [WEAK] + EXPORT TIM23_IRQHandler [WEAK] + EXPORT TIM24_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_PSSI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +OCTOSPI1_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DMAMUX1_OVR_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +DTS_IRQHandler +WAKEUP_PIN_IRQHandler +OCTOSPI2_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +UART9_IRQHandler +USART10_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +FDCAN3_IT0_IRQHandler +FDCAN3_IT1_IRQHandler +TIM23_IRQHandler +TIM24_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_ARM/stm32h725xe.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_ARM/stm32h725xe.sct new file mode 100644 index 00000000000..0c00f2a328c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_ARM/stm32h725xe.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/startup_stm32h725xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/startup_stm32h725xx.S new file mode 100644 index 00000000000..b0e92a7eb3a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/startup_stm32h725xx.S @@ -0,0 +1,756 @@ +/** + ****************************************************************************** + * @file startup_stm32h725xx.s + * @author MCD Application Team + * @brief STM32H725xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word 0 /* Reserved */ + .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word 0 /* Reserved */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word 0 /* Reserved */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMAC_IRQHandler /* FMAC Interrupt */ + .word CORDIC_IRQHandler /* CORDIC Interrupt */ + .word UART9_IRQHandler /* UART9 Interrupt */ + .word USART10_IRQHandler /* UART10 Interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */ + .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */ + .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */ + .word TIM23_IRQHandler /* TIM23 global interrupt */ + .word TIM24_IRQHandler /* TIM24 global interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak TIM23_IRQHandler + .thumb_set TIM23_IRQHandler,Default_Handler + + .weak TIM24_IRQHandler + .thumb_set TIM24_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_GCC_ARM/stm32h725xe.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_IAR/startup_stm32h725xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_IAR/startup_stm32h725xx.S new file mode 100644 index 00000000000..2b33c11657f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_IAR/startup_stm32h725xx.S @@ -0,0 +1,984 @@ +;/******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h725xx.s +;* Author : MCD Application Team +;* Description : STM32H725xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; USART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrup + DCD TIM24_IRQHandler ; TIM24 global interrup + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_PSSI_IRQHandler + B DCMI_PSSI_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK OCTOSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler + B OCTOSPI2_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler + B USART10_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler + B FDCAN3_IT0_IRQHandler + + PUBWEAK FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler + B FDCAN3_IT1_IRQHandler + + PUBWEAK TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler + B TIM23_IRQHandler + + PUBWEAK TIM24_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_IAR/stm32h725xe.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_IAR/stm32h725xe.icf new file mode 100644 index 00000000000..b397a3f3110 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/TOOLCHAIN_IAR/stm32h725xe.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 180; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h new file mode 100644 index 00000000000..0958fbfedb4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H725xE/cmsis_nvic.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x80000 // 512 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x24000000 +#endif + +#if !defined(MBED_RAM_SIZE) +// 0x38000000 - 0x38003FFF 16K SRAM4 +// 0x30004000 - 0x30007FFF 16K SRAM2 +// 0x30000000 - 0x30003FFF 16K SRAM1 +// 0x24000000 - 0x2404FFFF 320K AXI SRAM +// 0x20000000 - 0x2001FFFF 128K DTCM +#define MBED_RAM_SIZE 0x50000 // 320 KB +#endif + +#define NVIC_NUM_VECTORS 180 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt new file mode 100644 index 00000000000..3ec917d33d8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h735xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h735xg.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h735xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32h735xg.sct) +endif() + +add_library(mbed-stm32h735xg INTERFACE) + +target_include_directories(mbed-stm32h735xg + INTERFACE + . +) + +target_sources(mbed-stm32h735xg + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32h735xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h735xg INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_ARM/startup_stm32h735xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_ARM/startup_stm32h735xx.S new file mode 100644 index 00000000000..47ecd2a056b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_ARM/startup_stm32h735xx.S @@ -0,0 +1,579 @@ +;******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h735xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD CRYP_IRQHandler ; CRYP + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; DTS interrupt + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt + DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; UART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrup + DCD TIM24_IRQHandler ; TIM24 global interrup + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_PSSI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT OTFDEC1_IRQHandler [WEAK] + EXPORT OTFDEC2_IRQHandler [WEAK] + EXPORT FMAC_IRQHandler [WEAK] + EXPORT CORDIC_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT USART10_IRQHandler [WEAK] + EXPORT I2C5_EV_IRQHandler [WEAK] + EXPORT I2C5_ER_IRQHandler [WEAK] + EXPORT FDCAN3_IT0_IRQHandler [WEAK] + EXPORT FDCAN3_IT1_IRQHandler [WEAK] + EXPORT TIM23_IRQHandler [WEAK] + EXPORT TIM24_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_PSSI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +OCTOSPI1_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DMAMUX1_OVR_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +DTS_IRQHandler +WAKEUP_PIN_IRQHandler +OCTOSPI2_IRQHandler +OTFDEC1_IRQHandler +OTFDEC2_IRQHandler +FMAC_IRQHandler +CORDIC_IRQHandler +UART9_IRQHandler +USART10_IRQHandler +I2C5_EV_IRQHandler +I2C5_ER_IRQHandler +FDCAN3_IT0_IRQHandler +FDCAN3_IT1_IRQHandler +TIM23_IRQHandler +TIM24_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_ARM/stm32h735xg.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_ARM/stm32h735xg.sct new file mode 100644 index 00000000000..0c00f2a328c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_ARM/stm32h735xg.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/startup_stm32h735xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/startup_stm32h735xx.S new file mode 100644 index 00000000000..6c83dbc0d30 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/startup_stm32h735xx.S @@ -0,0 +1,765 @@ +/** + ****************************************************************************** + * @file startup_stm32h735xx.s + * @author MCD Application Team + * @brief STM32H735xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ + .word CRYP_IRQHandler /* CRYP */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word 0 /* Reserved */ + .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word 0 /* Reserved */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word 0 /* Reserved */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */ + .word OTFDEC1_IRQHandler /* OTFDEC1 Interrupt */ + .word OTFDEC2_IRQHandler /* OTFDEC2 Interrupt */ + .word FMAC_IRQHandler /* FMAC Interrupt */ + .word CORDIC_IRQHandler /* CORDIC Interrupt */ + .word UART9_IRQHandler /* UART9 Interrupt */ + .word USART10_IRQHandler /* UART10 Interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */ + .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */ + .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */ + .word TIM23_IRQHandler /* TIM23 global interrupt */ + .word TIM24_IRQHandler /* TIM24 global interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak OTFDEC2_IRQHandler + .thumb_set OTFDEC2_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak TIM23_IRQHandler + .thumb_set TIM23_IRQHandler,Default_Handler + + .weak TIM24_IRQHandler + .thumb_set TIM24_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_GCC_ARM/stm32h735xg.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_IAR/startup_stm32h735xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_IAR/startup_stm32h735xx.S new file mode 100644 index 00000000000..f9e770cd3f0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_IAR/startup_stm32h735xx.S @@ -0,0 +1,999 @@ +;/******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h735xx.s +;* Author : MCD Application Team +;* Description : STM32H735xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD 0 ; Reserved + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt + DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt + DCD OTFDEC2_IRQHandler ; OTFDEC2 Interrupt + DCD FMAC_IRQHandler ; FMAC Interrupt + DCD CORDIC_IRQHandler ; CORDIC Interrupt + DCD UART9_IRQHandler ; UART9 Interrupt + DCD USART10_IRQHandler ; USART10 Interrupt + DCD I2C5_EV_IRQHandler ; I2C5 Event Interrupt + DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt + DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 + DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 + DCD TIM23_IRQHandler ; TIM23 global interrup + DCD TIM24_IRQHandler ; TIM24 global interrup + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_PSSI_IRQHandler + B DCMI_PSSI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK OCTOSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler + B OCTOSPI2_IRQHandler + + PUBWEAK OTFDEC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC1_IRQHandler + B OTFDEC1_IRQHandler + + PUBWEAK OTFDEC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC2_IRQHandler + B OTFDEC2_IRQHandler + + PUBWEAK FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler + B FMAC_IRQHandler + + PUBWEAK CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler + B CORDIC_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler + B USART10_IRQHandler + + PUBWEAK I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler + B I2C5_EV_IRQHandler + + PUBWEAK I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler + B I2C5_ER_IRQHandler + + PUBWEAK FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler + B FDCAN3_IT0_IRQHandler + + PUBWEAK FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler + B FDCAN3_IT1_IRQHandler + + PUBWEAK TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler + B TIM23_IRQHandler + + PUBWEAK TIM24_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_IAR/stm32h735xg.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_IAR/stm32h735xg.icf new file mode 100644 index 00000000000..b397a3f3110 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/TOOLCHAIN_IAR/stm32h735xg.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 180; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h new file mode 100644 index 00000000000..e981df8aaa0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H735xG/cmsis_nvic.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x100000 // 1 MB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x24000000 +#endif + +#if !defined(MBED_RAM_SIZE) +// 0x38000000 - 0x38003FFF 16K SRAM4 +// 0x30004000 - 0x30007FFF 16K SRAM2 +// 0x30000000 - 0x30003FFF 16K SRAM1 +// 0x24000000 - 0x2404FFFF 320K AXI SRAM +// 0x20000000 - 0x2001FFFF 128K DTCM +#define MBED_RAM_SIZE 0x50000 // 320 KB +#endif + +#define NVIC_NUM_VECTORS 180 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_ARM/stm32h743xI.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_ARM/stm32h743xI.sct index 630e9a5dde3..95a347d564c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_ARM/stm32h743xI.sct +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_ARM/stm32h743xI.sct @@ -51,14 +51,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data } - RW_IRAM1 (MBED_RAM_START) { ; RW data + RW_IRAM1 (MBED_RAM1_START) { ; RW data .ANY (+RW +ZI) } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM1_START + MBED_RAM1_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up } - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + ARM_LIB_STACK (MBED_RAM1_START + MBED_RAM1_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down } RW_DMARxDscrTab 0x30040000 0x60 { diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld index a70ba7374c0..10f50e391cb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TOOLCHAIN_GCC_ARM/STM32H743xI.ld @@ -41,7 +41,7 @@ MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE - RAM (xrw) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + RAM (xrw) : ORIGIN = MBED_RAM1_START, LENGTH = MBED_RAM1_SIZE RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/cmsis_nvic.h index 348094abac6..05f9eacac71 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/cmsis_nvic.h @@ -22,20 +22,34 @@ #endif #if !defined(MBED_ROM_SIZE) +// 0x0x08000000-0x080FFFFF Bank1 (8 x 128K sectors) +// 0x0x08100000-0x081FFFFF Bank2 (8 x 128K sectors) #define MBED_ROM_SIZE 0x200000 // 2.0 MB #endif #if !defined(MBED_RAM_START) -#define MBED_RAM_START 0x24000000 +#define MBED_RAM_START 0x20000000 #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x80000 // 512 KB +// 0x38000000 - 0x3800FFFF 64K SRAM4 +// 0x30040000 - 0x30047FFF 32K SRAM3 +// 0x30020000 - 0x3003FFFF 128K SRAM2 +// 0x30000000 - 0x3001FFFF 128K SRAM1 +// 0x24000000 - 0x2407FFFF 512K AXI SRAM +// 0x20000000 - 0x2001FFFF 128K DTCM +#define MBED_RAM_SIZE 0x20000 // 128 KB #endif -// DON'T USE MBED_RAM1_START and MBED_RAM1_SIZE (wrong values in tools/arm_pack_manager/index.json) +#if !defined(MBED_RAM1_START) +#define MBED_RAM1_START 0x24000000 +#endif + +#if !defined(MBED_RAM1_SIZE) +#define MBED_RAM1_SIZE 0x80000 // 512 KB +#endif #define NVIC_NUM_VECTORS 166 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt new file mode 100644 index 00000000000..da5979ac9e0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h750xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h750xb.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h750xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32h750xb.sct) +endif() + +add_library(mbed-stm32h750xb INTERFACE) + +target_include_directories(mbed-stm32h750xb + INTERFACE + . +) + +target_sources(mbed-stm32h750xb + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32h750xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h750xb INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_ARM/startup_stm32h750xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_ARM/startup_stm32h750xx.S new file mode 100644 index 00000000000..75878e305ed --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_ARM/startup_stm32h750xx.S @@ -0,0 +1,568 @@ +;******************** (C) COPYRIGHT 2018 STMicroelectronics ******************** +;* File Name : startup_stm32h750xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2018 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_ARM/stm32h750xb.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_ARM/stm32h750xb.sct new file mode 100644 index 00000000000..0c00f2a328c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_ARM/stm32h750xb.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/startup_stm32h750xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/startup_stm32h750xx.S new file mode 100644 index 00000000000..81bfbf80db6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/startup_stm32h750xx.S @@ -0,0 +1,752 @@ +/** + ****************************************************************************** + * @file startup_stm32h750xx.s + * @author MCD Application Team + * @brief STM32H750xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* Crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ + .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ + .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ + .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ + .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ + .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ + .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ + .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word SAI3_IRQHandler /* SAI3 global Interrupt */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_OUT_IRQHandler + .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_IN_IRQHandler + .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SAI3_IRQHandler + .thumb_set SAI3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_GCC_ARM/stm32h750xb.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_IAR/startup_stm32h750xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_IAR/startup_stm32h750xx.S new file mode 100644 index 00000000000..231bd7b3e84 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_IAR/startup_stm32h750xx.S @@ -0,0 +1,984 @@ +;/******************** (C) COPYRIGHT 2018 STMicroelectronics ******************** +;* File Name : startup_stm32h750xx.s +;* Author : MCD Application Team +;* Description : STM32H750xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2018 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler + + PUBWEAK OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler + B OTG_FS_EP1_IN_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler + + PUBWEAK HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler + + PUBWEAK HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler + + PUBWEAK HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler + + PUBWEAK HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler + B HRTIM1_TIMD_IRQHandler + + PUBWEAK HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler + B HRTIM1_TIME_IRQHandler + + PUBWEAK HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler + B HRTIM1_FLT_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler + B SAI3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_IAR/stm32h750xb.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_IAR/stm32h750xb.icf new file mode 100644 index 00000000000..f3f7374be94 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/TOOLCHAIN_IAR/stm32h750xb.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 168; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0xa000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/cmsis_nvic.h new file mode 100644 index 00000000000..8615c071bc6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H750xB/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x24000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x80000 // 512 KB +#endif + +#define NVIC_NUM_VECTORS 168 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt new file mode 100644 index 00000000000..42eed028ac8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h753xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h753xi.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h753xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32h753xi.sct) +endif() + +add_library(mbed-stm32h753xi INTERFACE) + +target_include_directories(mbed-stm32h753xi + INTERFACE + . +) + +target_sources(mbed-stm32h753xi + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32h753xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h753xi INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_ARM/startup_stm32h753xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_ARM/startup_stm32h753xx.S new file mode 100644 index 00000000000..6959afea830 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_ARM/startup_stm32h753xx.S @@ -0,0 +1,566 @@ +;******************************************************************************** +;* File Name : startup_stm32h753xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_ARM/stm32h753xi.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_ARM/stm32h753xi.sct new file mode 100644 index 00000000000..bab412e811d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_ARM/stm32h753xi.sct @@ -0,0 +1,71 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } + + RW_DMARxDscrTab 0x30040000 0x60 { + *(.RxDecripSection) + } + RW_DMATxDscrTab 0x30040100 0x140 { + *(.TxDecripSection) + } + RW_Rx_Buffb 0x30040400 0x1800 { + *(.RxArraySection) + } + RW_Eth_Ram 0x30044000 0x4000 { + *(.ethusbram) + } + +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/startup_stm32h753xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/startup_stm32h753xx.S new file mode 100644 index 00000000000..180a4dca4c9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/startup_stm32h753xx.S @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file startup_stm32h753xx.s + * @author MCD Application Team + * @brief STM32H753xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* Crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ + .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ + .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ + .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ + .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ + .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ + .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ + .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word SAI3_IRQHandler /* SAI3 global Interrupt */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_OUT_IRQHandler + .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_IN_IRQHandler + .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SAI3_IRQHandler + .thumb_set SAI3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld new file mode 100644 index 00000000000..198b8f71d72 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_GCC_ARM/stm32h753xi.ld @@ -0,0 +1,220 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + .lwip_sec (NOLOAD) : { + . = ABSOLUTE(0x30040000); + *(.RxDecripSection) + + . = ABSOLUTE(0x30040100); + *(.TxDecripSection) + + . = ABSOLUTE(0x30040400); + *(.RxArraySection) + + . = ABSOLUTE(0x30044000); + *(.ethusbram) + + } >RAM_D2 AT> FLASH +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_IAR/startup_stm32h753xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_IAR/startup_stm32h753xx.S new file mode 100644 index 00000000000..cf1a6f1512f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_IAR/startup_stm32h753xx.S @@ -0,0 +1,982 @@ +;******************************************************************************** +;* File Name : startup_stm32h753xx.s +;* Author : MCD Application Team +;* Description : STM32H753xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler + + PUBWEAK OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler + B OTG_FS_EP1_IN_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler + + PUBWEAK HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler + + PUBWEAK HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler + + PUBWEAK HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler + + PUBWEAK HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler + B HRTIM1_TIMD_IRQHandler + + PUBWEAK HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler + B HRTIM1_TIME_IRQHandler + + PUBWEAK HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler + B HRTIM1_FLT_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler + B SAI3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + END diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_IAR/stm32h753xi.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_IAR/stm32h753xi.icf new file mode 100644 index 00000000000..5033c83795a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/TOOLCHAIN_IAR/stm32h753xi.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 166; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0xa000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/cmsis_nvic.h similarity index 61% rename from targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/cmsis_nvic.h index 49b2a4318ac..05f9eacac71 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H753xI/cmsis_nvic.h @@ -22,14 +22,9 @@ #endif #if !defined(MBED_ROM_SIZE) -#if defined (TARGET_NUCLEO_G071RB) -#define MBED_ROM_SIZE 0x20000 -#else -// 0x10000 STM32G071C8Ux STM32G071K8TxN STM32G071R8Tx STM32G071K8Ux STM32G071G8UxN STM32G071C8Tx STM32G071K8Tx STM32G071K8UxN STM32G071G8Ux -// 0x8000 STM32G071K6Tx STM32G071G6Ux STM32G071C6Tx STM32G071K6Ux STM32G071R6Tx STM32G071C6Ux -// 0x20000 STM32G071GBUxN STM32G071CBUx STM32G071KBTx STM32G071KBUxN STM32G071RBTx STM32G071EBYx STM32G071GBUx STM32G071CBTx STM32G071KBUx STM32G071RBIx STM32G071KBTxN -#error "MBED_ROM_SIZE not defined" -#endif +// 0x0x08000000-0x080FFFFF Bank1 (8 x 128K sectors) +// 0x0x08100000-0x081FFFFF Bank2 (8 x 128K sectors) +#define MBED_ROM_SIZE 0x200000 // 2.0 MB #endif #if !defined(MBED_RAM_START) @@ -37,10 +32,24 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x9000 +// 0x38000000 - 0x3800FFFF 64K SRAM4 +// 0x30040000 - 0x30047FFF 32K SRAM3 +// 0x30020000 - 0x3003FFFF 128K SRAM2 +// 0x30000000 - 0x3001FFFF 128K SRAM1 +// 0x24000000 - 0x2407FFFF 512K AXI SRAM +// 0x20000000 - 0x2001FFFF 128K DTCM +#define MBED_RAM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM1_START) +#define MBED_RAM1_START 0x24000000 +#endif + +#if !defined(MBED_RAM1_SIZE) +#define MBED_RAM1_SIZE 0x80000 // 512 KB #endif -#define NVIC_NUM_VECTORS 48 +#define NVIC_NUM_VECTORS 166 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h index 3b2e3f7c801..9f347d3fda1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h @@ -33,7 +33,7 @@ #define MBED_RAM_SIZE 0x100000 // 1.0 MB #endif -#define NVIC_NUM_VECTORS 171 +#define NVIC_NUM_VECTORS 172 #define NVIC_RAM_VECTOR_ADDRESS 0x20000000 #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt new file mode 100644 index 00000000000..79325fa9b33 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32h7b3xxq.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32h7b3xxq.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32h7b3xiq.sct) +endif() + +add_library(mbed-stm32h7b3xiq INTERFACE) + +target_include_directories(mbed-stm32h7b3xiq + INTERFACE + . +) + +target_sources(mbed-stm32h7b3xiq + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32h7b3xiq ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32h7b3xiq INTERFACE mbed-stm32h7) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_ARM/startup_stm32h7b3xxq.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_ARM/startup_stm32h7b3xxq.S new file mode 100644 index 00000000000..c2066222e83 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_ARM/startup_stm32h7b3xxq.S @@ -0,0 +1,565 @@ +;******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h7b3xxq.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt + DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt + DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt + DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD DAC2_IRQHandler ; DAC2 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt + DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt + DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt + DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt + DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt + DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt + DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt + DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt + DCD COMP_IRQHandler ; COMP global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD USART10_IRQHandler ; USART10 global interrupt + DCD LPUART1_IRQHandler ; LPUART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC_IRQHandler + DCD 0 ; Reserved + DCD DTS_IRQHandler ; DTS + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 + DCD OTFDEC1_IRQHandler ; OTFDEC1 + DCD OTFDEC2_IRQHandler ; OTFDEC2 + DCD GFXMMU_IRQHandler ; GFXMMU + DCD BDMA1_IRQHandler ; BDMA1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM2_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT DFSDM1_FLT4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT6_IRQHandler [WEAK] + EXPORT DFSDM1_FLT7_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_PSSI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT DAC2_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA2_Channel0_IRQHandler [WEAK] + EXPORT BDMA2_Channel1_IRQHandler [WEAK] + EXPORT BDMA2_Channel2_IRQHandler [WEAK] + EXPORT BDMA2_Channel3_IRQHandler [WEAK] + EXPORT BDMA2_Channel4_IRQHandler [WEAK] + EXPORT BDMA2_Channel5_IRQHandler [WEAK] + EXPORT BDMA2_Channel6_IRQHandler [WEAK] + EXPORT BDMA2_Channel7_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT UART9_IRQHandler [WEAK] + EXPORT USART10_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT DTS_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT OTFDEC1_IRQHandler [WEAK] + EXPORT OTFDEC2_IRQHandler [WEAK] + EXPORT GFXMMU_IRQHandler [WEAK] + EXPORT BDMA1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_PVM_IRQHandler +RTC_TAMP_STAMP_CSS_LSE_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM2_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +FDCAN_CAL_IRQHandler +DFSDM1_FLT4_IRQHandler +DFSDM1_FLT5_IRQHandler +DFSDM1_FLT6_IRQHandler +DFSDM1_FLT7_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_PSSI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +OCTOSPI1_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DMAMUX1_OVR_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +DAC2_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA2_Channel0_IRQHandler +BDMA2_Channel1_IRQHandler +BDMA2_Channel2_IRQHandler +BDMA2_Channel3_IRQHandler +BDMA2_Channel4_IRQHandler +BDMA2_Channel5_IRQHandler +BDMA2_Channel6_IRQHandler +BDMA2_Channel7_IRQHandler +COMP_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +UART9_IRQHandler +USART10_IRQHandler +LPUART1_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +DTS_IRQHandler +WAKEUP_PIN_IRQHandler +OCTOSPI2_IRQHandler +OTFDEC1_IRQHandler +OTFDEC2_IRQHandler +GFXMMU_IRQHandler +BDMA1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_ARM/stm32h7b3xiq.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_ARM/stm32h7b3xiq.sct new file mode 100644 index 00000000000..0c00f2a328c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_ARM/stm32h7b3xiq.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m7 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/startup_stm32h7b3xxq.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/startup_stm32h7b3xxq.S new file mode 100644 index 00000000000..4ab5f2fed16 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/startup_stm32h7b3xxq.S @@ -0,0 +1,751 @@ +/** + ****************************************************************************** + * @file startup_stm32h7b3xxq.s + * @author MCD Application Team + * @brief STM32H7B3xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */ + .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */ + .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */ + .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ + .word CRYP_IRQHandler /* CRYP crypto global interrupt */ + .word HASH_RNG_IRQHandler /* RNG, HASH */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word 0 /* Reserved */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word DAC2_IRQHandler /* DAC2 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */ + .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */ + .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */ + .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */ + .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */ + .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */ + .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */ + .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */ + .word COMP_IRQHandler /* COMP global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word UART9_IRQHandler /* UART9 global interrupt */ + .word USART10_IRQHandler /* USART10 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* DTS */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .word OCTOSPI2_IRQHandler /* OCTOSPI2 */ + .word OTFDEC1_IRQHandler /* OTFDEC1 */ + .word OTFDEC2_IRQHandler /* OTFDEC2 */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word BDMA1_IRQHandler /* BDMA1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM2_IRQHandler + .thumb_set DFSDM2_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DFSDM1_FLT4_IRQHandler + .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT5_IRQHandler + .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT6_IRQHandler + .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler + + .weak DFSDM1_FLT7_IRQHandler + .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak DAC2_IRQHandler + .thumb_set DAC2_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA2_Channel0_IRQHandler + .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler + + .weak BDMA2_Channel1_IRQHandler + .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler + + .weak BDMA2_Channel2_IRQHandler + .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler + + .weak BDMA2_Channel3_IRQHandler + .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler + + .weak BDMA2_Channel4_IRQHandler + .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler + + .weak BDMA2_Channel5_IRQHandler + .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler + + .weak BDMA2_Channel6_IRQHandler + .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler + + .weak BDMA2_Channel7_IRQHandler + .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak OTFDEC1_IRQHandler + .thumb_set OTFDEC1_IRQHandler,Default_Handler + + .weak OTFDEC2_IRQHandler + .thumb_set OTFDEC2_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak BDMA1_IRQHandler + .thumb_set BDMA1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_GCC_ARM/stm32h7b3xiq.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_IAR/startup_stm32h7b3xxq.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_IAR/startup_stm32h7b3xxq.S new file mode 100644 index 00000000000..53c5eec7701 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_IAR/startup_stm32h7b3xxq.S @@ -0,0 +1,971 @@ +;/****************************************************************************** +; * @file startup_stm32h7b3xxq.s +; * @author MCD Application Team +; * @brief STM32H7B3xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt + DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection + DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt + DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt + DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt + DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI + DCD CRYP_IRQHandler ; CRYP crypto global interrupt + DCD HASH_RNG_IRQHandler ; HASH, RNG + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD OCTOSPI1_IRQHandler ; OCTOSPI1 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD DAC2_IRQHandler ; DAC2 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP_IRQHandler ; COMP global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD UART9_IRQHandler ; UART9 global interrupt + DCD USART10_IRQHandler ; USART10 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC + DCD 0 ; Reserved + DCD DTS_IRQHandler ; DTS + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OCTOSPI2_IRQHandler ; OCTOSPI2 + DCD OTFDEC1_IRQHandler ; OTFDEC1 + DCD OTFDEC2_IRQHandler ; OTFDEC2 + DCD GFXMMU_IRQHandler ; GFXMMU + DCD BDMA1_IRQHandler ; BDMA1 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_TAMP_STAMP_CSS_LSE_IRQHandler + B RTC_TAMP_STAMP_CSS_LSE_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DFSDM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM2_IRQHandler + B DFSDM2_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK DFSDM1_FLT4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT4_IRQHandler + B DFSDM1_FLT4_IRQHandler + + PUBWEAK DFSDM1_FLT5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT5_IRQHandler + B DFSDM1_FLT5_IRQHandler + + PUBWEAK DFSDM1_FLT6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT6_IRQHandler + B DFSDM1_FLT6_IRQHandler + + PUBWEAK DFSDM1_FLT7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT7_IRQHandler + B DFSDM1_FLT7_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_PSSI_IRQHandler + B DCMI_PSSI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK OCTOSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) + +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) + +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK DAC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DAC2_IRQHandler + B DAC2_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA2_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel0_IRQHandler + B BDMA2_Channel0_IRQHandler + + PUBWEAK BDMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel1_IRQHandler + B BDMA2_Channel1_IRQHandler + + PUBWEAK BDMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel2_IRQHandler + B BDMA2_Channel2_IRQHandler + + PUBWEAK BDMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel3_IRQHandler + B BDMA2_Channel3_IRQHandler + + PUBWEAK BDMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel4_IRQHandler + B BDMA2_Channel4_IRQHandler + + PUBWEAK BDMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel5_IRQHandler + B BDMA2_Channel5_IRQHandler + + PUBWEAK BDMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel6_IRQHandler + B BDMA2_Channel6_IRQHandler + + PUBWEAK BDMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA2_Channel7_IRQHandler + B BDMA2_Channel7_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler + B UART9_IRQHandler + + PUBWEAK USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler + B USART10_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler + B DTS_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + + PUBWEAK OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler + B OCTOSPI2_IRQHandler + + PUBWEAK OTFDEC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC1_IRQHandler + B OTFDEC1_IRQHandler + + PUBWEAK OTFDEC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC2_IRQHandler + B OTFDEC2_IRQHandler + + PUBWEAK GFXMMU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +GFXMMU_IRQHandler + B GFXMMU_IRQHandler + + PUBWEAK BDMA1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA1_IRQHandler + B BDMA1_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_IAR/stm32h7b3xiq.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_IAR/stm32h7b3xiq.icf new file mode 100644 index 00000000000..ba7066a0433 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/TOOLCHAIN_IAR/stm32h7b3xiq.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 172; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/cmsis_nvic.h new file mode 100644 index 00000000000..9f347d3fda1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7B3xIQ/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x200000 // 2.0 MB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x24000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x100000 // 1.0 MB +#endif + +#define NVIC_NUM_VECTORS 172 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index 3fb41a7997d..449b3a3e015 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -60,7 +60,7 @@ void analogin_init(analogin_t *obj, PinName pin) // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) // are described in PinNames.h and PeripheralPins.c // Pin value must be between 0xF0 and 0xFF - if ((pin < 0xF0) || (pin >= ALT0)) { + if ((pin < 0xF0) || (pin >= (PinName)ALT0)) { // Normal channels // Get the peripheral name from the pin and assign it to the object obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); diff --git a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c index 984c183c67e..da82486f925 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c @@ -80,11 +80,15 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) EraseInitStruct.Sector = GetSector(address); EraseInitStruct.NbSectors = 1; +#if defined (DUAL_BANK) if (address < FLASH_BANK2_BASE) { EraseInitStruct.Banks = FLASH_BANK_1; } else { EraseInitStruct.Banks = FLASH_BANK_2; } +#else + EraseInitStruct.Banks = FLASH_BANK_1; +#endif if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) != HAL_OK) { status = -1; @@ -223,7 +227,9 @@ static uint32_t GetSectorBase(uint32_t SectorId, uint32_t BanksId) if (BanksId == FLASH_BANK_1) { address_sector = FLASH_BANK1_BASE; } else { +#if defined (DUAL_BANK) address_sector = FLASH_BANK2_BASE; +#endif } for (i = 0; i < SectorId; i++) { diff --git a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c index 91a79daccdf..42c6ae58364 100755 --- a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c @@ -76,6 +76,30 @@ uint32_t i2c_get_pclk(I2CName i2c) break; } } +#endif +#if defined I2C5_BASE + else if (i2c == I2C_5) { + clocksource = __HAL_RCC_GET_I2C5_SOURCE(); + switch (clocksource) { + case RCC_I2C5CLKSOURCE_D2PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C5CLKSOURCE_PLL3: + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + pclk = pll3_clocks.PLL3_R_Frequency; + break; + case RCC_I2C5CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + case RCC_I2C5CLKSOURCE_CSI: + pclk = CSI_VALUE; + break; + default: + // should not happend + error("I2C5: Invalid clock source"); + break; + } + } #endif else { // should not happend diff --git a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h index 8765199e3c8..16dbfb932c9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h @@ -41,6 +41,7 @@ extern "C" { #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_D2PCLK1 #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_D2PCLK1 #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_D3PCLK1 +#define I2CAPI_I2C5_CLKSRC RCC_I2C5CLKSOURCE_D2PCLK1 uint32_t i2c_get_pclk(I2CName i2c); uint32_t i2c_get_timing(I2CName i2c, uint32_t current_timing, int current_hz, int hz); diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index 6f171478860..cba64709dfd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -120,8 +120,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32H7/serial_device.c b/targets/TARGET_STM/TARGET_STM32H7/serial_device.c index ab7d8155f51..35cb1a9a903 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/serial_device.c @@ -17,8 +17,13 @@ #include "serial_api_hal.h" +#if defined (STM32h742xx) || defined (STM32h743xx) || defined (STM32h745xx) || defined (STM32h747xx) || defined (STM32h750xx) || defined (STM32h753xx) || defined (STM32h755xx) || defined (STM32h757xx) #define UART_NUM (9) -uint32_t serial_irq_ids[UART_NUM] = {0}; +#else +#define UART_NUM (11) +#endif + +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -36,15 +41,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -113,6 +118,20 @@ static void uart8_irq(void) } #endif +#if defined(UART9_BASE) +static void uart9_irq(void) +{ + uart_irq(UART_9); +} +#endif + +#if defined(USART10_BASE) +static void uart10_irq(void) +{ + uart_irq(UART_10); +} +#endif + #if defined(LPUART1_BASE) static void lpuart1_irq(void) { @@ -120,12 +139,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -184,6 +203,18 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart8_irq; break; #endif +#if defined(UART9_BASE) + case UART_9: + irq_n = UART9_IRQn; + vector = (uint32_t)&uart9_irq; + break; +#endif +#if defined(USART10_BASE) + case UART_10: + irq_n = USART10_IRQn; + vector = (uint32_t)&uart10_irq; + break; +#endif #if defined(LPUART1_BASE) case LPUART_1: irq_n = LPUART1_IRQn; @@ -393,6 +424,16 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) case UART_8: irq_n = UART8_IRQn; break; +#endif +#if defined(UART9_BASE) + case UART_9: + irq_n = UART9_IRQn; + break; +#endif +#if defined(USART10_BASE) + case UART_10: + irq_n = USART10_IRQn; + break; #endif default: irq_n = (IRQn_Type)0; diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_wwdg.c index c298bdcc0b3..3e40136c56c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 32MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 41.79s + max timeout before reset: approximately 41.79us (++) Counter max (T[5;0] = 0x3F) at 32MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 342.38ms diff --git a/targets/TARGET_STM/TARGET_STM32L0/objects.h b/targets/TARGET_STM/TARGET_STM32L0/objects.h index a94dd3f04f3..8ed217b88e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L0/objects.h @@ -116,8 +116,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c index 22e66ccd161..cc1c601bd05 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c @@ -26,7 +26,7 @@ #define UART_NUM (5) #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -44,15 +44,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -79,17 +79,15 @@ static void uart2_irq(void) } #endif -#if defined(USART4_BASE) -static void uart4_irq(void) +#if defined(USART4_BASE) || defined(USART5_BASE) +static void uart4_5_irq(void) { +#if defined(USART4_BASE) uart_irq(UART_4); -} #endif - -#if defined(USART5_BASE) -static void uart5_irq(void) -{ +#if defined(USART4_BASE) uart_irq(UART_5); +#endif } #endif @@ -100,12 +98,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -132,14 +130,14 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) #if defined(USART4_BASE) if (obj_s->uart == UART_4) { irq_n = USART4_5_IRQn; - vector = (uint32_t)&uart4_irq; + vector = (uint32_t)&uart4_5_irq; } #endif #if defined(USART5_BASE) if (obj_s->uart == UART_5) { irq_n = USART4_5_IRQn; - vector = (uint32_t)&uart5_irq; + vector = (uint32_t)&uart4_5_irq; } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L1/CMakeLists.txt index f2f067dc97c..7838edb9e1c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32L1/CMakeLists.txt @@ -4,6 +4,7 @@ add_subdirectory(TARGET_STM32L100xB EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L100xC EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L151xB EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32L151xBA EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L151xC EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L151xD EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L151xE EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_STM/TARGET_STM32L1/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L1/PeripheralNames.h index 2905cdb0dfd..4f39d727477 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32L1/PeripheralNames.h @@ -46,7 +46,9 @@ typedef enum { typedef enum { SPI_1 = (int)SPI1_BASE, SPI_2 = (int)SPI2_BASE, +#if defined SPI3_BASE SPI_3 = (int)SPI3_BASE +#endif } SPIName; typedef enum { @@ -58,7 +60,9 @@ typedef enum { PWM_2 = (int)TIM2_BASE, PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE, +#if defined TIM5_BASE PWM_5 = (int)TIM5_BASE, +#endif PWM_9 = (int)TIM9_BASE, PWM_10 = (int)TIM10_BASE, PWM_11 = (int)TIM11_BASE diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xb.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xb.h index 13f0d6b69ce..eea013c3b26 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xb.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xba.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xba.h index 0bc40565c13..591c3b106a4 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xba.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xba.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xc.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xc.h index e3f01932a1c..0dbaf3b48ef 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l100xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xb.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xb.h index 7c937760b10..d7d64fff58c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xb.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xba.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xba.h index dbb04afae1c..3503e6e2656 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xba.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xba.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xc.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xc.h index 9b6167460f2..f185074cacc 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xca.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xca.h index 8279679094d..e2ddf1256f6 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xca.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xca.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xd.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xd.h index 1074112a212..eeb296da2f8 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xd.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xd.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xdx.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xdx.h index f02fec735a8..2523b406f90 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xdx.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xdx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xe.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xe.h index 58ece570316..8b817e18787 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xe.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l151xe.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xb.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xb.h index d6be6bdb19e..241e6d50495 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xb.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xb.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xba.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xba.h index e71cc6a18c0..79ab93c18d8 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xba.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xba.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xc.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xc.h index 85b034a4703..8cb742d89ee 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xca.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xca.h index 4b1c460f978..85050c0ea7b 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xca.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xca.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xd.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xd.h index 4ab18c43853..4f9c5d472bf 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xd.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xd.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xdx.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xdx.h index 56ad74253be..1a133878082 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xdx.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xdx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xe.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xe.h index 89f2e379e08..c5b5aca874d 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xe.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l152xe.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xc.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xc.h index 524562bf5d5..bb0f13ee8fa 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xc.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xca.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xca.h index 912613451b4..f5582c7d6a5 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xca.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xca.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xd.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xd.h index 51c2fed938c..2d223bcc361 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xd.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xd.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xdx.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xdx.h index 0ec12e81aed..ed336d2d1c7 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xdx.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xdx.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xe.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xe.h index 95f56e13c0d..237b6c370a4 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xe.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l162xe.h @@ -9,7 +9,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l1xx.h b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l1xx.h index 4db526124b3..8b721b21671 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l1xx.h +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/CMSIS/stm32l1xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L1xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_wwdg.c index b5f400e9fc3..4af28830405 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L1/STM32Cube_FW/STM32L1xx_HAL_Driver/stm32l1xx_hal_wwdg.c @@ -33,7 +33,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) @32MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 41.79s + max timeout before reset: approximately 41.79us (++) Counter max (T[5;0] = 0x3F) @32MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 342.38ms diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h index 605a4ee13e4..d784eab2828 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h @@ -30,10 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x8000 // 32 KB -// 0x4000 // 16 KB STM32L151CB STM32L151RB STM32L151VB -// 0x8000 // 32 KB STM32L151CBxxA STM32L151RBxxA STM32L151VBxxA -#warning "check MBED_RAM_SIZE value in cmsis_nvic.h" +#define MBED_RAM_SIZE 0x4000 // 16 KB #endif #define NVIC_NUM_VECTORS 61 diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/CMakeLists.txt new file mode 100644 index 00000000000..6388a16ab89 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32l151xba.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32l151xba.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32l151xba.sct) +endif() + +add_library(mbed-stm32l151xba INTERFACE) + +target_include_directories(mbed-stm32l151xba + INTERFACE + . +) + +target_sources(mbed-stm32l151xba + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32l151xba ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32l151xba INTERFACE mbed-stm32l1) diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_ARM/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_ARM/startup_stm32l151xba.S new file mode 100644 index 00000000000..22c5a462884 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_ARM/startup_stm32l151xba.S @@ -0,0 +1,267 @@ +;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l151xba.s +;* Author : MCD Application Team +;* Description : STM32L151XBA Devices vector for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Copyright (c) 2017 STMicroelectronics. All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD 0 ; Reserved + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT USB_HP_IRQHandler [WEAK] + EXPORT USB_LP_IRQHandler [WEAK] + EXPORT DAC_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT TIM11_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT USB_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +USB_HP_IRQHandler +USB_LP_IRQHandler +DAC_IRQHandler +COMP_IRQHandler +EXTI9_5_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +TIM11_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +USB_FS_WKUP_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_ARM/stm32l151xba.sct b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_ARM/stm32l151xba.sct new file mode 100644 index 00000000000..a3f155aa561 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_ARM/stm32l151xba.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m3 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S new file mode 100644 index 00000000000..ffe0081bfd0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S @@ -0,0 +1,374 @@ +/** + ****************************************************************************** + * @file startup_stm32l151xba.s + * @author MCD Application Team + * @brief STM32L151XBA Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * @attention + * + * Copyright (c) 2017 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + bl _start + bx lr + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word 0 + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L151XBA devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_GCC_ARM/stm32l151xba.ld b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_GCC_ARM/stm32l151xba.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_GCC_ARM/stm32l151xba.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_IAR/startup_stm32l151xba.S b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_IAR/startup_stm32l151xba.S new file mode 100644 index 00000000000..87947a54de7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_IAR/startup_stm32l151xba.S @@ -0,0 +1,454 @@ +;********************* (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l151xba.s +;* Author : MCD Application Team +;* Description : STM32L151XBA Devices vector for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* @attention +;* +;* Copyright (c) 2017 STMicroelectronics. All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp + DCD RTC_WKUP_IRQHandler ; RTC Wakeup + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD USB_HP_IRQHandler ; USB High Priority + DCD USB_LP_IRQHandler ; USB Low Priority + DCD DAC_IRQHandler ; DAC + DCD COMP_IRQHandler ; COMP through EXTI Line + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD 0 ; Reserved + DCD TIM9_IRQHandler ; TIM9 + DCD TIM10_IRQHandler ; TIM10 + DCD TIM11_IRQHandler ; TIM11 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK TAMPER_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMPER_STAMP_IRQHandler + B TAMPER_STAMP_IRQHandler + + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + + PUBWEAK DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC_IRQHandler + B DAC_IRQHandler + + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +COMP_IRQHandler + B COMP_IRQHandler + + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + + PUBWEAK TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM9_IRQHandler + B TIM9_IRQHandler + + + PUBWEAK TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM10_IRQHandler + B TIM10_IRQHandler + + + PUBWEAK TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM11_IRQHandler + B TIM11_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + + PUBWEAK USB_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_FS_WKUP_IRQHandler + B USB_FS_WKUP_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_IAR/stm32l151xba.icf b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_IAR/stm32l151xba.icf new file mode 100644 index 00000000000..5b2d7ec78be --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/TOOLCHAIN_IAR/stm32l151xba.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 61; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x2000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/cmsis_nvic.h new file mode 100644 index 00000000000..8276d8a661e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xBA/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x8000 // 32 KB +#endif + +#define NVIC_NUM_VECTORS 61 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h index 65294f7e490..d784eab2828 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h @@ -30,10 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x8000 // 32 KB -// 0x4000 // 16 KB STM32L152CB STM32L152RB STM32L152VB -// 0x8000 // 32 KB STM32L152CBxxA STM32L152RBxxA STM32L152VBxxA -#warning "check MBED_RAM_SIZE value in cmsis_nvic.h" +#define MBED_RAM_SIZE 0x4000 // 16 KB #endif #define NVIC_NUM_VECTORS 61 diff --git a/targets/TARGET_STM/TARGET_STM32L1/objects.h b/targets/TARGET_STM/TARGET_STM32L1/objects.h index 91589c9a5b1..148be365af4 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L1/objects.h @@ -111,8 +111,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c index 33196a36e11..bbbfffe8e39 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c @@ -19,7 +19,7 @@ #define UART_NUM (5) -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -37,15 +37,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE) != RESET) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE) != RESET) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -93,12 +93,12 @@ static void uart5_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h index c32116dd87f..3c1888d7f64 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h @@ -24,6 +24,8 @@ extern "C" { #include "stm32l1xx_ll_tim.h" #include "cmsis_nvic.h" +#if defined TIM5_BASE + #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() @@ -34,6 +36,20 @@ extern "C" { #define TIM_MST_BIT_WIDTH 32 // 16 or 32 +#else // TIM5_BASE + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() + +#define TIM_MST_RESET_ON __TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() + +#define TIM_MST_BIT_WIDTH 16 // 16 or 32 + +#endif // TIM5_BASE + #define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) diff --git a/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt index 66644730318..2c1d74be056 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt @@ -1,6 +1,7 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_STM32L412xB EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L432xC EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L433xC EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L443xC EXCLUDE_FROM_ALL) @@ -10,6 +11,7 @@ add_subdirectory(TARGET_STM32L475xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L476xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L486xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L496xG EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32L4P5xG EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L4R5xI EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L4R9xI EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32L4S5xI EXCLUDE_FROM_ALL) diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l412xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l412xx.h index d38b033d32b..1062db0e2cf 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l412xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l412xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l422xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l422xx.h index e1bc0e6311e..2939930ec5c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l422xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l422xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l431xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l431xx.h index 9bf6b68b5ba..b72b5b620da 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l431xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l431xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l432xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l432xx.h index d538a229ead..0a302a66d73 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l432xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l432xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l433xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l433xx.h index 56394ad5cd1..4e812049993 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l433xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l433xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l442xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l442xx.h index e3c5de8d917..12206c41209 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l442xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l442xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l443xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l443xx.h index c8b400ae503..aa7179efdf5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l443xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l443xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l451xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l451xx.h index 230d54446d7..bce3d04f136 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l451xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l451xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l452xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l452xx.h index 98f6342c73e..32e7c04a1c5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l452xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l452xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l462xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l462xx.h index affcccc00d8..5eaddee0bb7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l462xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l462xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l471xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l471xx.h index f96b9588268..7ba242c82e1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l471xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l471xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l475xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l475xx.h index 705ffe7edd9..95d076fcbfa 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l475xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l475xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l476xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l476xx.h index 6dc1ab493ed..a2dfb1973f3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l476xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l476xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l485xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l485xx.h index 30ffb6e4ebc..b84e86760b4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l485xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l485xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l486xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l486xx.h index 1bda22672f6..5542d230b7f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l486xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l486xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l496xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l496xx.h index df29998b67f..35d47eca0d2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l496xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l496xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4a6xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4a6xx.h index c0296335dca..62b5e0241b1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4a6xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4a6xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4p5xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4p5xx.h index d5c061f4d3f..b4e3021ee66 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4p5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4p5xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4q5xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4q5xx.h index bdf2425ed1e..3c9543c69b5 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4q5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4q5xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r5xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r5xx.h index 8845449e3a5..0d88ab8ccb3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r5xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r7xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r7xx.h index 1fb241ec5b1..59bf8fc2436 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r7xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r7xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r9xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r9xx.h index 196b0eafe65..838042fbaa1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r9xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4r9xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s5xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s5xx.h index 37a666e64a5..1c1d6b9dcf3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s5xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s7xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s7xx.h index 788723ecd66..e1f8329bdc2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s7xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s7xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s9xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s9xx.h index e3142925fbb..33ecff5b714 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s9xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4s9xx.h @@ -7,7 +7,7 @@ * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4xx.h index f4ae4f7fdf4..edc1b1e172c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4xx.h +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/CMSIS/stm32l4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L4xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/Legacy/stm32l4xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/Legacy/stm32l4xx_hal_can_legacy.c index 8797ec0c545..9dfe829be3a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/Legacy/stm32l4xx_hal_can_legacy.c +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/Legacy/stm32l4xx_hal_can_legacy.c @@ -104,7 +104,8 @@ #error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32l4xx_hal_conf.h file' #endif /* HAL_CAN_MODULE_ENABLED */ -#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' +// MBED current implementation +// #warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' #if defined(CAN1) diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_cryp.c index 708271be6af..716dbbd98a7 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_cryp.c @@ -98,7 +98,7 @@ during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_CRYP_RegisterCallback before calling @ref HAL_CRYP_DeInit - or @ref HAL_CRYP_Init function. + or @ref HAL_CRYP_Init function. When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available diff --git a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_swpmi.c b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_swpmi.c index 3c547a69236..2dab02b79dc 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32L4/STM32Cube_FW/STM32L4xx_HAL_Driver/stm32l4xx_hal_swpmi.c @@ -289,10 +289,10 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi) /* Apply Voltage class selection */ MODIFY_REG(hswpmi->Instance->OR, SWPMI_OR_CLASS, hswpmi->Init.VoltageClass); - /* If Voltage class B, apply 300 s delay */ + /* If Voltage class B, apply 300 us delay */ if(hswpmi->Init.VoltageClass == SWPMI_VOLTAGE_CLASS_B) { - /* Insure 300 s wait to insure SWPMI_IO output not higher than 1.8V */ + /* Insure 300 us wait to insure SWPMI_IO output not higher than 1.8V */ /* Wait loop initialization and execution */ /* Note: Variable divided by 4 to compensate partially CPU processing cycles. */ wait_loop_index = (300U * (SystemCoreClock / (1000000U * 4U))) + 150U; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/CMakeLists.txt new file mode 100644 index 00000000000..2c93d868329 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l412xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32l412xb.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32l412xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32l412xb.sct) +endif() + +add_library(mbed-stm32l412xb INTERFACE) + +target_include_directories(mbed-stm32l412xb + INTERFACE + . +) + +target_sources(mbed-stm32l412xb + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32l412xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32l412xb INTERFACE mbed-stm32l4) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_ARM/startup_stm32l412xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_ARM/startup_stm32l412xx.S new file mode 100644 index 00000000000..7e76950ad71 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_ARM/startup_stm32l412xx.S @@ -0,0 +1,328 @@ +;******************************************************************************* +;* File Name : startup_stm32l412xx.s +;* Author : MCD Application Team +;* Description : STM32L412xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;*

© Copyright (c) 2018 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under Apache License, Version 2.0, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/Apache-2.0 +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1&2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD 0 ; Reserved + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM6_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +USB_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +TSC_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_ARM/stm32l412xb.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_ARM/stm32l412xb.sct new file mode 100644 index 00000000000..7aff08bc288 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_ARM/stm32l412xb.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_GCC_ARM/startup_stm32l412xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_GCC_ARM/startup_stm32l412xx.S new file mode 100644 index 00000000000..9b32dd9c780 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_GCC_ARM/startup_stm32l412xx.S @@ -0,0 +1,433 @@ +/** + ****************************************************************************** + * @file startup_stm32l412xx.s + * @author MCD Application Team + * @brief STM32L412xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word TIM6_IRQHandler + .word 0 + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word USB_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word 0 + .word 0 + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_GCC_ARM/stm32l412xb.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_GCC_ARM/stm32l412xb.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_GCC_ARM/stm32l412xb.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_IAR/startup_stm32l412xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_IAR/startup_stm32l412xx.S new file mode 100644 index 00000000000..b7ecf244122 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_IAR/startup_stm32l412xx.S @@ -0,0 +1,497 @@ +;******************************************************************************** +;* File Name : startup_stm32l412xx.s +;* Author : MCD Application Team +;* Description : STM32L412xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

© Copyright (c) 2018 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under Apache License, Version 2.0, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/Apache-2.0 +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI1 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD 0 ; Reserved + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU interrupt + DCD CRS_IRQHandler ; CRS interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_IAR/stm32l412xb.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_IAR/stm32l412xb.icf new file mode 100644 index 00000000000..216cfcc465f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/TOOLCHAIN_IAR/stm32l412xb.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 99; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/cmsis_nvic.h new file mode 100644 index 00000000000..e4d6d40156e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L412xB/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x20000 // 128 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0xa000 // 40 KB +#endif + +#define NVIC_NUM_VECTORS 99 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h index 48d53dcebc5..4bd52a9e170 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h @@ -134,6 +134,14 @@ typedef enum { #define LED1 PB_3 // LD3 [Green] +#define I2C_SDA D4 +#define I2C_SCL D5 + +#define SPI_SCK D10 +#define SPI_MOSI D11 +#define SPI_MISO D12 +#define SPI_CS D13 + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/CMakeLists.txt new file mode 100644 index 00000000000..5f189c50f25 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32l4p5xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32l4p5xg.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32l4p5xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32l4p5xg.sct) +endif() + +add_library(mbed-stm32l4p5xg INTERFACE) + +target_include_directories(mbed-stm32l4p5xg + INTERFACE + . +) + +target_sources(mbed-stm32l4p5xg + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32l4p5xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32l4p5xg INTERFACE mbed-stm32l4) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_ARM/startup_stm32l4p5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_ARM/startup_stm32l4p5xx.S new file mode 100644 index 00000000000..28a778d7c88 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_ARM/startup_stm32l4p5xx.S @@ -0,0 +1,402 @@ +;******************************************************************************* +;* File Name : startup_stm32l4p5xx.s +;* Author : MCD Application Team +;* Description : STM32L4P5xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under Apache License, Version 2.0, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/Apache-2.0 +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD OCTOSPI2_IRQHandler ; OctoSPI2 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD HASH_CRS_IRQHandler ; HASH and CRS global interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD DCMI_PSSI_IRQHandler ; DCMI and PSSI global global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D global interrupt + DCD LTDC_IRQHandler ; LTDC global interrupt + DCD LTDC_ER_IRQHandler ; LTDC error global interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 overrun global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT OCTOSPI1_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT OCTOSPI2_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT HASH_CRS_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT DCMI_PSSI_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +SDMMC2_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +OCTOSPI1_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +OCTOSPI2_IRQHandler +TSC_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +HASH_CRS_IRQHandler +I2C4_ER_IRQHandler +I2C4_EV_IRQHandler +DCMI_PSSI_IRQHandler +DMA2D_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMAMUX1_OVR_IRQHandler + + + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_ARM/stm32l4p5xg.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_ARM/stm32l4p5xg.sct new file mode 100644 index 00000000000..7aff08bc288 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_ARM/stm32l4p5xg.sct @@ -0,0 +1,57 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_GCC_ARM/startup_stm32l4p5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_GCC_ARM/startup_stm32l4p5xx.S new file mode 100644 index 00000000000..206976234be --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_GCC_ARM/startup_stm32l4p5xx.S @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file startup_stm32l4p5xx.s + * @author MCD Application Team + * @brief STM32L4P5xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word SDMMC2_IRQHandler + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM1_FLT0_IRQHandler + .word DFSDM1_FLT1_IRQHandler + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word OCTOSPI1_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word OCTOSPI2_IRQHandler + .word TSC_IRQHandler + .word 0 + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_CRS_IRQHandler + .word I2C4_ER_IRQHandler + .word I2C4_EV_IRQHandler + .word DCMI_PSSI_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word DMA2D_IRQHandler + .word LTDC_IRQHandler + .word LTDC_ER_IRQHandler + .word 0 + .word DMAMUX1_OVR_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_CRS_IRQHandler + .thumb_set HASH_CRS_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_GCC_ARM/stm32l4p5xg.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_GCC_ARM/stm32l4p5xg.ld new file mode 100644 index 00000000000..5f479936c85 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_GCC_ARM/stm32l4p5xg.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_IAR/startup_stm32l4p5xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_IAR/startup_stm32l4p5xx.S new file mode 100644 index 00000000000..40ce86dd33e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_IAR/startup_stm32l4p5xx.S @@ -0,0 +1,659 @@ +;******************************************************************************** +;* File Name : startup_stm32l4p5xx.s +;* Author : MCD Application Team +;* Description : STM32L4P5xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under Apache License, Version 2.0, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/Apache-2.0 +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) and RTC SSR Underflow through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD OCTOSPI2_IRQHandler ; OctoSPI2 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD HASH_CRS_IRQHandler ; HASH and CRS global interrupt + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD DCMI_PSSI_IRQHandler ; DCMI and PSSI global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2D_IRQHandler ; DMA2D global interrupt + DCD LTDC_IRQHandler ; LTDC global interrupt + DCD LTDC_ER_IRQHandler ; LTDC error global interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 overrun global interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK OCTOSPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler + B OCTOSPI2_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK HASH_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_CRS_IRQHandler + B HASH_CRS_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK DCMI_PSSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_PSSI_IRQHandler + B DCMI_PSSI_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_IAR/stm32l4p5xg.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_IAR/stm32l4p5xg.icf new file mode 100644 index 00000000000..1e07dbcde86 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/TOOLCHAIN_IAR/stm32l4p5xg.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 111; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/cmsis_nvic.h new file mode 100644 index 00000000000..d5166319023 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4P5xG/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x100000 // 1.0 MB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x50000 // 320 KB +#endif + +#define NVIC_NUM_VECTORS 111 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/objects.h b/targets/TARGET_STM/TARGET_STM32L4/objects.h index 1748be21104..136a582b318 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L4/objects.h @@ -112,8 +112,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index 9c866edd41c..1879441dc35 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -27,7 +27,7 @@ #define UART_NUM (6) // max value (TARGET_STM32L475xG / TARGET_STM32L476xG / TARGET_STM32L486xG / TARGET_STM32L496xG) #endif -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -45,15 +45,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -108,12 +108,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h index 5838b81a588..2b4e18c6e8c 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32L5xx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_wwdg.c index b1e0ff33cd0..4f72ee864a2 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_wwdg.c @@ -33,7 +33,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) @110MHz (PCLK1) with zero prescaler: - max timeout before reset: ~37.23s + max timeout before reset: ~37.23us (++) Counter max (T[5;0] = 0x3F) @110MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: ~19.07ms diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PinNames.h index d780f773d49..53a9af16126 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PinNames.h @@ -329,8 +329,8 @@ typedef enum { } PinName; // Standardized LED and button names -#define LED1 PG_12 // LD7 Green -#define LED2 PE_1 // LD9 Red +#define LED1 PG_12 // LD10 Green +#define LED2 PD_3 // LD9 Red #define BUTTON1 PC_13 // USER_BUTTON #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L5/objects.h b/targets/TARGET_STM/TARGET_STM32L5/objects.h index 1760e5cc568..c06bdd71711 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L5/objects.h @@ -120,8 +120,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; @@ -154,10 +154,9 @@ struct dac_s { #if DEVICE_CAN struct can_s { - CAN_HandleTypeDef CanHandle; + FDCAN_HandleTypeDef CanHandle; int index; int hz; - int rxIrqEnabled; }; #endif diff --git a/targets/TARGET_STM/TARGET_STM32L5/serial_device.c b/targets/TARGET_STM/TARGET_STM32L5/serial_device.c index 3f8ed5413b1..24fd018ebe6 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L5/serial_device.c @@ -19,7 +19,7 @@ #define UART_NUM (6) // USART1, USART2, USART3, UART4, UART5, LPUART1 -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -37,15 +37,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -100,12 +100,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -654,7 +654,7 @@ static void _serial_set_flow_control_direct(serial_t *obj, FlowControl type, con } if (type == FlowControlRTS) { // Enable RTS - MBED_ASSERT(pinmap->rx_flow_pin != (UARTName)NC); + MBED_ASSERT(pinmap->rx_flow_pin != NC); obj_s->hw_flow_ctl = UART_HWCONTROL_RTS; obj_s->pin_rts = pinmap->rx_flow_pin; // Enable the pin for RTS function @@ -663,7 +663,7 @@ static void _serial_set_flow_control_direct(serial_t *obj, FlowControl type, con } if (type == FlowControlCTS) { // Enable CTS - MBED_ASSERT(pinmap->tx_flow_pin != (UARTName)NC); + MBED_ASSERT(pinmap->tx_flow_pin != NC); obj_s->hw_flow_ctl = UART_HWCONTROL_CTS; obj_s->pin_cts = pinmap->tx_flow_pin; // Enable the pin for CTS function @@ -672,8 +672,8 @@ static void _serial_set_flow_control_direct(serial_t *obj, FlowControl type, con } if (type == FlowControlRTSCTS) { // Enable CTS & RTS - MBED_ASSERT(pinmap->rx_flow_pin != (UARTName)NC); - MBED_ASSERT(pinmap->tx_flow_pin != (UARTName)NC); + MBED_ASSERT(pinmap->rx_flow_pin != NC); + MBED_ASSERT(pinmap->tx_flow_pin != NC); obj_s->hw_flow_ctl = UART_HWCONTROL_RTS_CTS; obj_s->pin_rts = pinmap->rx_flow_pin;; obj_s->pin_cts = pinmap->tx_flow_pin;; diff --git a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TARGET_B_U585I_IOT02A/PinNames.h b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TARGET_B_U585I_IOT02A/PinNames.h index 8589bf37e98..49fd38ddf3d 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TARGET_B_U585I_IOT02A/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U585xI/TARGET_B_U585I_IOT02A/PinNames.h @@ -402,6 +402,27 @@ typedef enum { SYS_PWR_WKUP8_ALT0 = PA_7, SYS_PWR_WKUP8_ALT1 = PB_10, + /**** OSPI FLASH pins ****/ + OSPI_FLASH1_IO0 = PF_0, + OSPI_FLASH1_IO1 = PF_1, + OSPI_FLASH1_IO2 = PF_2, + OSPI_FLASH1_IO3 = PF_3, + OSPI_FLASH1_IO4 = PH_9, + OSPI_FLASH1_IO5 = PH_10, + OSPI_FLASH1_IO6 = PH_11, + OSPI_FLASH1_IO7 = PH_12, + OSPI_FLASH1_DQS = PF_12, + OSPI_FLASH1_SCK = PF_4, + OSPI_FLASH1_CSN = PI_5, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = OSPI_FLASH1_IO0, + QSPI_FLASH1_IO1 = OSPI_FLASH1_IO1, + QSPI_FLASH1_IO2 = OSPI_FLASH1_IO2, + QSPI_FLASH1_IO3 = OSPI_FLASH1_IO3, + QSPI_FLASH1_SCK = OSPI_FLASH1_SCK, + QSPI_FLASH1_CSN = OSPI_FLASH1_CSN, + // Not connected NC = (int)0xFFFFFFFF } PinName; diff --git a/targets/TARGET_STM/TARGET_STM32U5/objects.h b/targets/TARGET_STM/TARGET_STM32U5/objects.h index 33bf23d23dc..a5e3d328e43 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/objects.h +++ b/targets/TARGET_STM/TARGET_STM32U5/objects.h @@ -120,8 +120,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; @@ -154,10 +154,9 @@ struct dac_s { #if DEVICE_CAN struct can_s { - CAN_HandleTypeDef CanHandle; + FDCAN_HandleTypeDef CanHandle; int index; int hz; - int rxIrqEnabled; }; #endif diff --git a/targets/TARGET_STM/TARGET_STM32U5/serial_device.c b/targets/TARGET_STM/TARGET_STM32U5/serial_device.c index a3e82c4e0bc..8dea598ced0 100644 --- a/targets/TARGET_STM/TARGET_STM32U5/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32U5/serial_device.c @@ -19,7 +19,7 @@ #define UART_NUM (6) // USART1, USART2, USART3, UART4, UART5, LPUART1 -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -37,15 +37,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -100,12 +100,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32WB/README.md b/targets/TARGET_STM/TARGET_STM32WB/README.md index 5dcd2c107f0..5e305819a50 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/README.md +++ b/targets/TARGET_STM/TARGET_STM32WB/README.md @@ -126,14 +126,14 @@ Default BLE FW in ST boards is **stm32wb5x_BLE_Stack_full_fw.bin** - Default "mbed_rom_size" in targets.json is then "0xCA000" (808K) To optimize FLASH size, **stm32wb5x_BLE_HCILayer_fw.bin** is supported for MBED-OS use case -- As explained in Release_Notes.html, this FW is flashed at @ 0x080E0000 -- Then "mbed_rom_size" can be updated to "0xE0000" (896K) +- As explained in Release_Notes.html, this FW is flashed at @ 0x080E1000 for versions 1.12.0 and 1.12.1 and at @ 0x080E0000 for older versions +- Then "mbed_rom_size" can be updated to "0xE1000" (900K) or "0xE0000" (896K) Example in your local mbed_app.json: ``` "target_overrides": { "NUCLEO_WB55RG": { - "target.mbed_rom_size": "0xE0000" + "target.mbed_rom_size": "0xE1000" } ``` diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb10xx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb10xx.h index 23de4031f03..f937d3f7ffd 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb10xx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb10xx.h @@ -756,10 +756,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 0x1FFF787F) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 12 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -772,14 +772,14 @@ typedef struct #define SRAM2B_SIZE 0x00001000UL /*!< SRAM2b default size : 4 KB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 0x20002FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 0x20038FFF) */ +#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x20002FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x20038FFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -8415,100 +8415,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8518,16 +8518,16 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb15xx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb15xx.h index 6c187a4ac48..8a1432cb2e2 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb15xx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb15xx.h @@ -766,10 +766,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 0x1FFF787F) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF7800UL) /*!< Option Bytes : 128B (0x1FFF7800 - 0x1FFF787F) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 12 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -782,14 +782,14 @@ typedef struct #define SRAM2B_SIZE 0x00001000UL /*!< SRAM2b default size : 4 KB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 0x20002FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 0x20038FFF) */ +#define SRAM1_END_ADDR (0x20002FFFUL) /*!< SRAM1 : 12KB (0x20000000 - 0x20002FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x20038FFFUL) /*!< SRAM2b (backup) : 4KB (0x20038000 - 0x20038FFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -8532,100 +8532,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8635,16 +8635,16 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb30xx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb30xx.h index 3420e1dadd9..6ff0a092529 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb30xx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb30xx.h @@ -753,10 +753,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -769,14 +769,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -8454,100 +8454,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8557,100 +8557,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb35xx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb35xx.h index 2bbca541bbe..c5ed95c71d6 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb35xx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb35xx.h @@ -885,10 +885,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -901,14 +901,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 0x20007FFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 - 0x20007FFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -9803,100 +9803,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -9906,100 +9906,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h index df7b10d90d0..4207f7252f6 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h @@ -754,10 +754,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 64 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -770,14 +770,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 0x2000FFFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x2000FFFFUL) /*!< SRAM1 : 64KB (0x20000000 - 0x2000FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -8455,100 +8455,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -8558,100 +8558,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h index 311c9071e7e..ce8a0036ed9 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h @@ -923,10 +923,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -939,14 +939,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 0x2002FFFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 - 0x2002FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -10702,100 +10702,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -10805,100 +10805,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb5mxx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb5mxx.h index 62fcee2d707..0724cfe0e58 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb5mxx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb5mxx.h @@ -923,10 +923,10 @@ typedef struct /*!< Memory, OTP and Option bytes */ /* Base addresses */ -#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ #define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 192 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ @@ -939,14 +939,14 @@ typedef struct #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ /* End addresses */ -#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 0x2002FFFF) */ -#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 0x20037FFF) */ -#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 0x2003FFFF) */ +#define SRAM1_END_ADDR (0x2002FFFFUL) /*!< SRAM1 : 192KB (0x20000000 - 0x2002FFFF) */ +#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 - 0x20037FFF) */ +#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 - 0x2003FFFF) */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 0x1FFF8FFF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 - 0x1FFF8FFF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -10702,100 +10702,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR1 register (SYSCFG SRAM2A write protection register) *********************************************************/ #define SYSCFG_SWPR1_PAGE0_Pos (0U) #define SYSCFG_SWPR1_PAGE0_Msk (0x1UL << SYSCFG_SWPR1_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 0x200303FF) */ +#define SYSCFG_SWPR1_PAGE0 SYSCFG_SWPR1_PAGE0_Msk /*!< SRAM2A Write protection page 0 (0x20030000 - 0x200303FF) */ #define SYSCFG_SWPR1_PAGE1_Pos (1U) #define SYSCFG_SWPR1_PAGE1_Msk (0x1UL << SYSCFG_SWPR1_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 0x200307FF) */ +#define SYSCFG_SWPR1_PAGE1 SYSCFG_SWPR1_PAGE1_Msk /*!< SRAM2A Write protection page 1 (0x20030400 - 0x200307FF) */ #define SYSCFG_SWPR1_PAGE2_Pos (2U) #define SYSCFG_SWPR1_PAGE2_Msk (0x1UL << SYSCFG_SWPR1_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 0x20030BFF) */ +#define SYSCFG_SWPR1_PAGE2 SYSCFG_SWPR1_PAGE2_Msk /*!< SRAM2A Write protection page 2 (0x20030800 - 0x20030BFF) */ #define SYSCFG_SWPR1_PAGE3_Pos (3U) #define SYSCFG_SWPR1_PAGE3_Msk (0x1UL << SYSCFG_SWPR1_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 0x20030FFF) */ +#define SYSCFG_SWPR1_PAGE3 SYSCFG_SWPR1_PAGE3_Msk /*!< SRAM2A Write protection page 3 (0x20030C00 - 0x20030FFF) */ #define SYSCFG_SWPR1_PAGE4_Pos (4U) #define SYSCFG_SWPR1_PAGE4_Msk (0x1UL << SYSCFG_SWPR1_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 0x200313FF) */ +#define SYSCFG_SWPR1_PAGE4 SYSCFG_SWPR1_PAGE4_Msk /*!< SRAM2A Write protection page 4 (0x20031000 - 0x200313FF) */ #define SYSCFG_SWPR1_PAGE5_Pos (5U) #define SYSCFG_SWPR1_PAGE5_Msk (0x1UL << SYSCFG_SWPR1_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 0x200317FF) */ +#define SYSCFG_SWPR1_PAGE5 SYSCFG_SWPR1_PAGE5_Msk /*!< SRAM2A Write protection page 5 (0x20031400 - 0x200317FF) */ #define SYSCFG_SWPR1_PAGE6_Pos (6U) #define SYSCFG_SWPR1_PAGE6_Msk (0x1UL << SYSCFG_SWPR1_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 0x20031BFF) */ +#define SYSCFG_SWPR1_PAGE6 SYSCFG_SWPR1_PAGE6_Msk /*!< SRAM2A Write protection page 6 (0x20031800 - 0x20031BFF) */ #define SYSCFG_SWPR1_PAGE7_Pos (7U) #define SYSCFG_SWPR1_PAGE7_Msk (0x1UL << SYSCFG_SWPR1_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 0x20031FFF) */ +#define SYSCFG_SWPR1_PAGE7 SYSCFG_SWPR1_PAGE7_Msk /*!< SRAM2A Write protection page 7 (0x20031C00 - 0x20031FFF) */ #define SYSCFG_SWPR1_PAGE8_Pos (8U) #define SYSCFG_SWPR1_PAGE8_Msk (0x1UL << SYSCFG_SWPR1_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 0x200323FF) */ +#define SYSCFG_SWPR1_PAGE8 SYSCFG_SWPR1_PAGE8_Msk /*!< SRAM2A Write protection page 8 (0x20032000 - 0x200323FF) */ #define SYSCFG_SWPR1_PAGE9_Pos (9U) #define SYSCFG_SWPR1_PAGE9_Msk (0x1UL << SYSCFG_SWPR1_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 0x200327FF) */ +#define SYSCFG_SWPR1_PAGE9 SYSCFG_SWPR1_PAGE9_Msk /*!< SRAM2A Write protection page 9 (0x20032400 - 0x200327FF) */ #define SYSCFG_SWPR1_PAGE10_Pos (10U) #define SYSCFG_SWPR1_PAGE10_Msk (0x1UL << SYSCFG_SWPR1_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 0x20032BFF) */ +#define SYSCFG_SWPR1_PAGE10 SYSCFG_SWPR1_PAGE10_Msk /*!< SRAM2A Write protection page 10 (0x20032800 - 0x20032BFF) */ #define SYSCFG_SWPR1_PAGE11_Pos (11U) #define SYSCFG_SWPR1_PAGE11_Msk (0x1UL << SYSCFG_SWPR1_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 0x20032FFF) */ +#define SYSCFG_SWPR1_PAGE11 SYSCFG_SWPR1_PAGE11_Msk /*!< SRAM2A Write protection page 11 (0x20032C00 - 0x20032FFF) */ #define SYSCFG_SWPR1_PAGE12_Pos (12U) #define SYSCFG_SWPR1_PAGE12_Msk (0x1UL << SYSCFG_SWPR1_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 0x200333FF) */ +#define SYSCFG_SWPR1_PAGE12 SYSCFG_SWPR1_PAGE12_Msk /*!< SRAM2A Write protection page 12 (0x20033000 - 0x200333FF) */ #define SYSCFG_SWPR1_PAGE13_Pos (13U) #define SYSCFG_SWPR1_PAGE13_Msk (0x1UL << SYSCFG_SWPR1_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 0x200337FF) */ +#define SYSCFG_SWPR1_PAGE13 SYSCFG_SWPR1_PAGE13_Msk /*!< SRAM2A Write protection page 13 (0x20033400 - 0x200337FF) */ #define SYSCFG_SWPR1_PAGE14_Pos (14U) #define SYSCFG_SWPR1_PAGE14_Msk (0x1UL << SYSCFG_SWPR1_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 0x20033BFF) */ +#define SYSCFG_SWPR1_PAGE14 SYSCFG_SWPR1_PAGE14_Msk /*!< SRAM2A Write protection page 14 (0x20033800 - 0x20033BFF) */ #define SYSCFG_SWPR1_PAGE15_Pos (15U) #define SYSCFG_SWPR1_PAGE15_Msk (0x1UL << SYSCFG_SWPR1_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 0x20033FFF) */ +#define SYSCFG_SWPR1_PAGE15 SYSCFG_SWPR1_PAGE15_Msk /*!< SRAM2A Write protection page 15 (0x20033C00 - 0x20033FFF) */ #define SYSCFG_SWPR1_PAGE16_Pos (16U) #define SYSCFG_SWPR1_PAGE16_Msk (0x1UL << SYSCFG_SWPR1_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 0x200343FF) */ +#define SYSCFG_SWPR1_PAGE16 SYSCFG_SWPR1_PAGE16_Msk /*!< SRAM2A Write protection page 16 (0x20034000 - 0x200343FF) */ #define SYSCFG_SWPR1_PAGE17_Pos (17U) #define SYSCFG_SWPR1_PAGE17_Msk (0x1UL << SYSCFG_SWPR1_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 0x200347FF) */ +#define SYSCFG_SWPR1_PAGE17 SYSCFG_SWPR1_PAGE17_Msk /*!< SRAM2A Write protection page 17 (0x20034400 - 0x200347FF) */ #define SYSCFG_SWPR1_PAGE18_Pos (18U) #define SYSCFG_SWPR1_PAGE18_Msk (0x1UL << SYSCFG_SWPR1_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 0x20034BFF) */ +#define SYSCFG_SWPR1_PAGE18 SYSCFG_SWPR1_PAGE18_Msk /*!< SRAM2A Write protection page 18 (0x20034800 - 0x20034BFF) */ #define SYSCFG_SWPR1_PAGE19_Pos (19U) #define SYSCFG_SWPR1_PAGE19_Msk (0x1UL << SYSCFG_SWPR1_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 0x20034FFF) */ +#define SYSCFG_SWPR1_PAGE19 SYSCFG_SWPR1_PAGE19_Msk /*!< SRAM2A Write protection page 19 (0x20034C00 - 0x20034FFF) */ #define SYSCFG_SWPR1_PAGE20_Pos (20U) #define SYSCFG_SWPR1_PAGE20_Msk (0x1UL << SYSCFG_SWPR1_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 0x200353FF) */ +#define SYSCFG_SWPR1_PAGE20 SYSCFG_SWPR1_PAGE20_Msk /*!< SRAM2A Write protection page 20 (0x20035000 - 0x200353FF) */ #define SYSCFG_SWPR1_PAGE21_Pos (21U) #define SYSCFG_SWPR1_PAGE21_Msk (0x1UL << SYSCFG_SWPR1_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 0x200357FF) */ +#define SYSCFG_SWPR1_PAGE21 SYSCFG_SWPR1_PAGE21_Msk /*!< SRAM2A Write protection page 21 (0x20035400 - 0x200357FF) */ #define SYSCFG_SWPR1_PAGE22_Pos (22U) #define SYSCFG_SWPR1_PAGE22_Msk (0x1UL << SYSCFG_SWPR1_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 0x20035BFF) */ +#define SYSCFG_SWPR1_PAGE22 SYSCFG_SWPR1_PAGE22_Msk /*!< SRAM2A Write protection page 22 (0x20035800 - 0x20035BFF) */ #define SYSCFG_SWPR1_PAGE23_Pos (23U) #define SYSCFG_SWPR1_PAGE23_Msk (0x1UL << SYSCFG_SWPR1_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 0x20035FFF) */ +#define SYSCFG_SWPR1_PAGE23 SYSCFG_SWPR1_PAGE23_Msk /*!< SRAM2A Write protection page 23 (0x20035C00 - 0x20035FFF) */ #define SYSCFG_SWPR1_PAGE24_Pos (24U) #define SYSCFG_SWPR1_PAGE24_Msk (0x1UL << SYSCFG_SWPR1_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 0x200363FF) */ +#define SYSCFG_SWPR1_PAGE24 SYSCFG_SWPR1_PAGE24_Msk /*!< SRAM2A Write protection page 24 (0x20036000 - 0x200363FF) */ #define SYSCFG_SWPR1_PAGE25_Pos (25U) #define SYSCFG_SWPR1_PAGE25_Msk (0x1UL << SYSCFG_SWPR1_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 0x200367FF) */ +#define SYSCFG_SWPR1_PAGE25 SYSCFG_SWPR1_PAGE25_Msk /*!< SRAM2A Write protection page 25 (0x20036400 - 0x200367FF) */ #define SYSCFG_SWPR1_PAGE26_Pos (26U) #define SYSCFG_SWPR1_PAGE26_Msk (0x1UL << SYSCFG_SWPR1_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 0x20036BFF) */ +#define SYSCFG_SWPR1_PAGE26 SYSCFG_SWPR1_PAGE26_Msk /*!< SRAM2A Write protection page 26 (0x20036800 - 0x20036BFF) */ #define SYSCFG_SWPR1_PAGE27_Pos (27U) #define SYSCFG_SWPR1_PAGE27_Msk (0x1UL << SYSCFG_SWPR1_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 0x20036FFF) */ +#define SYSCFG_SWPR1_PAGE27 SYSCFG_SWPR1_PAGE27_Msk /*!< SRAM2A Write protection page 27 (0x20036C00 - 0x20036FFF) */ #define SYSCFG_SWPR1_PAGE28_Pos (28U) #define SYSCFG_SWPR1_PAGE28_Msk (0x1UL << SYSCFG_SWPR1_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 0x200373FF) */ +#define SYSCFG_SWPR1_PAGE28 SYSCFG_SWPR1_PAGE28_Msk /*!< SRAM2A Write protection page 28 (0x20037000 - 0x200373FF) */ #define SYSCFG_SWPR1_PAGE29_Pos (29U) #define SYSCFG_SWPR1_PAGE29_Msk (0x1UL << SYSCFG_SWPR1_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 0x200377FF) */ +#define SYSCFG_SWPR1_PAGE29 SYSCFG_SWPR1_PAGE29_Msk /*!< SRAM2A Write protection page 29 (0x20037400 - 0x200377FF) */ #define SYSCFG_SWPR1_PAGE30_Pos (30U) #define SYSCFG_SWPR1_PAGE30_Msk (0x1UL << SYSCFG_SWPR1_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 0x20037BFF) */ +#define SYSCFG_SWPR1_PAGE30 SYSCFG_SWPR1_PAGE30_Msk /*!< SRAM2A Write protection page 30 (0x20037800 - 0x20037BFF) */ #define SYSCFG_SWPR1_PAGE31_Pos (31U) #define SYSCFG_SWPR1_PAGE31_Msk (0x1UL << SYSCFG_SWPR1_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 0x20037FFF) */ +#define SYSCFG_SWPR1_PAGE31 SYSCFG_SWPR1_PAGE31_Msk /*!< SRAM2A Write protection page 31 (0x20037C00 - 0x20037FFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) @@ -10805,100 +10805,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR2 register (SYSCFG SRAM2 write protection register) **********************************************************/ #define SYSCFG_SWPR2_PAGE32_Pos (0U) #define SYSCFG_SWPR2_PAGE32_Msk (0x1UL << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 0x200383FF) */ +#define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2B Write protection page 0 (0x20038000 - 0x200383FF) */ #define SYSCFG_SWPR2_PAGE33_Pos (1U) #define SYSCFG_SWPR2_PAGE33_Msk (0x1UL << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 0x200387FF) */ +#define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2B Write protection page 1 (0x20038400 - 0x200387FF) */ #define SYSCFG_SWPR2_PAGE34_Pos (2U) #define SYSCFG_SWPR2_PAGE34_Msk (0x1UL << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 0x20038bFF) */ +#define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2B Write protection page 2 (0x20038800 - 0x20038bFF) */ #define SYSCFG_SWPR2_PAGE35_Pos (3U) #define SYSCFG_SWPR2_PAGE35_Msk (0x1UL << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 0x20038FFF) */ +#define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2B Write protection page 3 (0x20038C00 - 0x20038FFF) */ #define SYSCFG_SWPR2_PAGE36_Pos (4U) #define SYSCFG_SWPR2_PAGE36_Msk (0x1UL << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 0x200393FF) */ +#define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2B Write protection page 4 (0x20039000 - 0x200393FF) */ #define SYSCFG_SWPR2_PAGE37_Pos (5U) #define SYSCFG_SWPR2_PAGE37_Msk (0x1UL << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 0x200397FF) */ +#define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2B Write protection page 5 (0x20039400 - 0x200397FF) */ #define SYSCFG_SWPR2_PAGE38_Pos (6U) #define SYSCFG_SWPR2_PAGE38_Msk (0x1UL << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 0x20039BFF) */ +#define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2B Write protection page 6 (0x20039800 - 0x20039BFF) */ #define SYSCFG_SWPR2_PAGE39_Pos (7U) #define SYSCFG_SWPR2_PAGE39_Msk (0x1UL << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 0x20039FFF) */ +#define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2B Write protection page 7 (0x20039C00 - 0x20039FFF) */ #define SYSCFG_SWPR2_PAGE40_Pos (8U) #define SYSCFG_SWPR2_PAGE40_Msk (0x1UL << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 0x2003A3FF) */ +#define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2B Write protection page 8 (0x2003A000 - 0x2003A3FF) */ #define SYSCFG_SWPR2_PAGE41_Pos (9U) #define SYSCFG_SWPR2_PAGE41_Msk (0x1UL << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 0x2003A7FF) */ +#define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2B Write protection page 9 (0x2003A400 - 0x2003A7FF) */ #define SYSCFG_SWPR2_PAGE42_Pos (10U) #define SYSCFG_SWPR2_PAGE42_Msk (0x1UL << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 0x2003ABFF) */ +#define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2B Write protection page 10 (0x2003A800 - 0x2003ABFF) */ #define SYSCFG_SWPR2_PAGE43_Pos (11U) #define SYSCFG_SWPR2_PAGE43_Msk (0x1UL << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 0x2003AFFF) */ +#define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2B Write protection page 11 (0x2003AC00 - 0x2003AFFF) */ #define SYSCFG_SWPR2_PAGE44_Pos (12U) #define SYSCFG_SWPR2_PAGE44_Msk (0x1UL << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 0x2003B3FF) */ +#define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2B Write protection page 12 (0x2003B000 - 0x2003B3FF) */ #define SYSCFG_SWPR2_PAGE45_Pos (13U) #define SYSCFG_SWPR2_PAGE45_Msk (0x1UL << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 0x2003B7FF) */ +#define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2B Write protection page 13 (0x2003B400 - 0x2003B7FF) */ #define SYSCFG_SWPR2_PAGE46_Pos (14U) #define SYSCFG_SWPR2_PAGE46_Msk (0x1UL << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 0x2003BBFF) */ +#define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2B Write protection page 14 (0x2003B800 - 0x2003BBFF) */ #define SYSCFG_SWPR2_PAGE47_Pos (15U) #define SYSCFG_SWPR2_PAGE47_Msk (0x1UL << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 0x2003BFFF) */ +#define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2B Write protection page 15 (0x2003BC00 - 0x2003BFFF) */ #define SYSCFG_SWPR2_PAGE48_Pos (16U) #define SYSCFG_SWPR2_PAGE48_Msk (0x1UL << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 0x2003C3FF) */ +#define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2B Write protection page 16 (0x2003C000 - 0x2003C3FF) */ #define SYSCFG_SWPR2_PAGE49_Pos (17U) #define SYSCFG_SWPR2_PAGE49_Msk (0x1UL << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 0x2003C7FF) */ +#define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2B Write protection page 17 (0x2003C400 - 0x2003C7FF) */ #define SYSCFG_SWPR2_PAGE50_Pos (18U) #define SYSCFG_SWPR2_PAGE50_Msk (0x1UL << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 0x2003CBFF) */ +#define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2B Write protection page 18 (0x2003C800 - 0x2003CBFF) */ #define SYSCFG_SWPR2_PAGE51_Pos (19U) #define SYSCFG_SWPR2_PAGE51_Msk (0x1UL << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 0x2003CFFF) */ +#define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2B Write protection page 19 (0x2003CC00 - 0x2003CFFF) */ #define SYSCFG_SWPR2_PAGE52_Pos (20U) #define SYSCFG_SWPR2_PAGE52_Msk (0x1UL << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 0x2003D3FF) */ +#define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2B Write protection page 20 (0x2003D000 - 0x2003D3FF) */ #define SYSCFG_SWPR2_PAGE53_Pos (21U) #define SYSCFG_SWPR2_PAGE53_Msk (0x1UL << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 0x2003D7FF) */ +#define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2B Write protection page 21 (0x2003D400 - 0x2003D7FF) */ #define SYSCFG_SWPR2_PAGE54_Pos (22U) #define SYSCFG_SWPR2_PAGE54_Msk (0x1UL << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 0x2003DBFF) */ +#define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2B Write protection page 22 (0x2003D800 - 0x2003DBFF) */ #define SYSCFG_SWPR2_PAGE55_Pos (23U) #define SYSCFG_SWPR2_PAGE55_Msk (0x1UL << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 0x2003DFFF) */ +#define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2B Write protection page 23 (0x2003DC00 - 0x2003DFFF) */ #define SYSCFG_SWPR2_PAGE56_Pos (24U) #define SYSCFG_SWPR2_PAGE56_Msk (0x1UL << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 0x2003E3FF) */ +#define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2B Write protection page 24 (0x2003E000 - 0x2003E3FF) */ #define SYSCFG_SWPR2_PAGE57_Pos (25U) #define SYSCFG_SWPR2_PAGE57_Msk (0x1UL << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 0x2003E7FF) */ +#define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2B Write protection page 25 (0x2003E400 - 0x2003E7FF) */ #define SYSCFG_SWPR2_PAGE58_Pos (26U) #define SYSCFG_SWPR2_PAGE58_Msk (0x1UL << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 0x2003EBFF) */ +#define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2B Write protection page 26 (0x2003E800 - 0x2003EBFF) */ #define SYSCFG_SWPR2_PAGE59_Pos (27U) #define SYSCFG_SWPR2_PAGE59_Msk (0x1UL << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 0x2003EFFF) */ +#define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2B Write protection page 27 (0x2003EC00 - 0x2003EFFF) */ #define SYSCFG_SWPR2_PAGE60_Pos (28U) #define SYSCFG_SWPR2_PAGE60_Msk (0x1UL << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 0x2003F3FF) */ +#define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2B Write protection page 28 (0x2003F000 - 0x2003F3FF) */ #define SYSCFG_SWPR2_PAGE61_Pos (29U) #define SYSCFG_SWPR2_PAGE61_Msk (0x1UL << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 0x2003F7FF) */ +#define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2B Write protection page 29 (0x2003F400 - 0x2003F7FF) */ #define SYSCFG_SWPR2_PAGE62_Pos (30U) #define SYSCFG_SWPR2_PAGE62_Msk (0x1UL << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 0x2003FBFF) */ +#define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2B Write protection page 30 (0x2003F800 - 0x2003FBFF) */ #define SYSCFG_SWPR2_PAGE63_Pos (31U) #define SYSCFG_SWPR2_PAGE63_Msk (0x1UL << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 0x2003FFFF) */ +#define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2B Write protection page 31 (0x2003FC00 - 0x2003FFFF) */ /***************** Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/ #define SYSCFG_IMR1_TIM1IM_Pos (13U) diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h index 5c38a1b95ee..aea26f16d0f 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32WBxx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c index 9b99d3a0549..798f4e802f8 100755 --- a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c +++ b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c @@ -46,7 +46,7 @@ uint32_t i2c_get_pclk(I2CName i2c) } } #if defined I2C2_BASE - if (i2c == I2C_2) { + else if (i2c == I2C_2) { clocksource = __HAL_RCC_GET_I2C2_SOURCE(); switch (clocksource) { case RCC_I2C2CLKSOURCE_PCLK1: diff --git a/targets/TARGET_STM/TARGET_STM32WB/objects.h b/targets/TARGET_STM/TARGET_STM32WB/objects.h index 7fb437dc546..515846edcbb 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/objects.h +++ b/targets/TARGET_STM/TARGET_STM32WB/objects.h @@ -103,8 +103,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32WB/serial_device.c b/targets/TARGET_STM/TARGET_STM32WB/serial_device.c index 1be620a29c0..646bc270807 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32WB/serial_device.c @@ -21,7 +21,7 @@ #define UART_NUM (2) -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -39,15 +39,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -74,12 +74,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt index 1ad0fa799bc..e2e22782d8a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt @@ -1,13 +1,23 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_STM32WL54xC EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32WL55xC EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32WLE4x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32WLE4xB EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32WLE4xC EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32WLE5x8 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_STM32WLE5xB EXCLUDE_FROM_ALL) add_subdirectory(TARGET_STM32WLE5xC EXCLUDE_FROM_ALL) - add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL) add_library(mbed-stm32wl INTERFACE) +target_include_directories(mbed-stm32wl + INTERFACE + . +) + target_sources(mbed-stm32wl INTERFACE analogin_device.c @@ -21,9 +31,5 @@ target_sources(mbed-stm32wl system_clock.c ) -target_include_directories(mbed-stm32wl - INTERFACE - . -) target_link_libraries(mbed-stm32wl INTERFACE mbed-stm mbed-stm32wlcube-fw) diff --git a/targets/TARGET_STM/TARGET_STM32WL/README.md b/targets/TARGET_STM/TARGET_STM32WL/README.md index 8415b5a2f02..7f14dad9d86 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/README.md +++ b/targets/TARGET_STM/TARGET_STM32WL/README.md @@ -31,11 +31,22 @@ Only M4 core is currently used by mbed-os applications. - Total FLASH is 256KB - RAM: 64 KB +**[tip] mbed-os export feature** -## CUSTOM boards +`mbed export -m NUCLEO_WL55JC -i uvision6` + +This needs to locally add a patch: +https://github.com/ARMmbed/mbed-os/pull/10424/files + +`mbed export -m NUCLEO_WL55JC -i iar` -Check https://github.com/ARMmbed/stm32customtargets +This needs to locally add a patch: +https://github.com/jeromecoutant/mbed/blob/IAR_EXPORT_SUPPORT/tools/export/iar/iar_definitions.json#L62-L64 + + +## CUSTOM boards +Check https://github.com/ARMmbed/stm32customtargets#stm32wl # LoRa @@ -50,7 +61,7 @@ Baremetal is supported. mbed_app.json: ``` { - "requires": ["bare-metal", "lora", "stm32wl-lora-driver"] + "requires": ["bare-metal", "stm32wl-lora-driver"] } ``` diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/LICENSE.txt b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/LICENSE.txt new file mode 100644 index 00000000000..872e82b4670 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h index 871879c12fd..d6229a0badb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl54xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -206,7 +205,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -481,7 +480,7 @@ typedef struct } GPIO_TypeDef; /** - * @brief Global TrustZone Controller + * @brief Global Security Controller */ typedef struct{ __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ @@ -933,9 +932,9 @@ typedef struct /*!< Memory, OTP and Option bytes */ #define RSSLIB_PFUNC_BASE (SYSTEM_FLASH_BASE + 0x00003A00UL) /*!< RSS area */ -#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 0x1FFF7FFF) */ +#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Device Electronic Signature */ #define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ @@ -943,10 +942,10 @@ typedef struct #define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1187,6 +1186,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ @@ -4001,7 +4009,7 @@ typedef struct /******************************************************************************/ /* */ -/* Global TrustZone Control */ +/* Global Security Control */ /* */ /******************************************************************************/ /******************* Bits definition for registers x = 0 ********************/ @@ -9092,100 +9100,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR register (SYSCFG SRAM2 write protection register) ***********************************************************/ #define SYSCFG_SWPR_PAGE0_Pos (0U) #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 0x200083FF) */ +#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */ #define SYSCFG_SWPR_PAGE1_Pos (1U) #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 0x200087FF) */ +#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */ #define SYSCFG_SWPR_PAGE2_Pos (2U) #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 0x20008BFF) */ +#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */ #define SYSCFG_SWPR_PAGE3_Pos (3U) #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 0x20008FFF) */ +#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */ #define SYSCFG_SWPR_PAGE4_Pos (4U) #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 0x200093FF) */ +#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */ #define SYSCFG_SWPR_PAGE5_Pos (5U) #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 0x200097FF) */ +#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */ #define SYSCFG_SWPR_PAGE6_Pos (6U) #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 0x20009BFF) */ +#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */ #define SYSCFG_SWPR_PAGE7_Pos (7U) #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 0x20009FFF) */ +#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */ #define SYSCFG_SWPR_PAGE8_Pos (8U) #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 0x2000A3FF) */ +#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */ #define SYSCFG_SWPR_PAGE9_Pos (9U) #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 0x2000A7FF) */ +#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */ #define SYSCFG_SWPR_PAGE10_Pos (10U) #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 0x2000ABFF) */ +#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */ #define SYSCFG_SWPR_PAGE11_Pos (11U) #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 0x2000AFFF) */ +#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */ #define SYSCFG_SWPR_PAGE12_Pos (12U) #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 0x2000B3FF) */ +#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */ #define SYSCFG_SWPR_PAGE13_Pos (13U) #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 0x2000B7FF) */ +#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */ #define SYSCFG_SWPR_PAGE14_Pos (14U) #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 0x2000BBFF) */ +#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */ #define SYSCFG_SWPR_PAGE15_Pos (15U) #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 0x2000BFFF) */ +#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */ #define SYSCFG_SWPR_PAGE16_Pos (16U) #define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 0x2000C3FF) */ +#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */ #define SYSCFG_SWPR_PAGE17_Pos (17U) #define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 0x2000C7FF) */ +#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */ #define SYSCFG_SWPR_PAGE18_Pos (18U) #define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 0x2000CBFF) */ +#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */ #define SYSCFG_SWPR_PAGE19_Pos (19U) #define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 0x2000CFFF) */ +#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */ #define SYSCFG_SWPR_PAGE20_Pos (20U) #define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 0x2000D3FF) */ +#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */ #define SYSCFG_SWPR_PAGE21_Pos (21U) #define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 0x2000D7FF) */ +#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */ #define SYSCFG_SWPR_PAGE22_Pos (22U) #define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 0x2000DBFF) */ +#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */ #define SYSCFG_SWPR_PAGE23_Pos (23U) #define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 0x2000DFFF) */ +#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */ #define SYSCFG_SWPR_PAGE24_Pos (24U) #define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 0x2000E3FF) */ +#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */ #define SYSCFG_SWPR_PAGE25_Pos (25U) #define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 0x2000E7FF) */ +#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */ #define SYSCFG_SWPR_PAGE26_Pos (26U) #define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 0x2000EBFF) */ +#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */ #define SYSCFG_SWPR_PAGE27_Pos (27U) #define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 0x2000EFFF) */ +#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */ #define SYSCFG_SWPR_PAGE28_Pos (28U) #define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 0x2000F3FF) */ +#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */ #define SYSCFG_SWPR_PAGE29_Pos (29U) #define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 0x2000F7FF) */ +#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */ #define SYSCFG_SWPR_PAGE30_Pos (30U) #define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 0x2000FBFF) */ +#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */ #define SYSCFG_SWPR_PAGE31_Pos (31U) #define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 0x2000FFFF) */ +#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h index 03a4d90bf8d..523a0398f46 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wl55xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -206,7 +205,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -481,7 +480,7 @@ typedef struct } GPIO_TypeDef; /** - * @brief Global TrustZone Controller + * @brief Global Security Controller */ typedef struct{ __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ @@ -933,9 +932,9 @@ typedef struct /*!< Memory, OTP and Option bytes */ #define RSSLIB_PFUNC_BASE (SYSTEM_FLASH_BASE + 0x00003A00UL) /*!< RSS area */ -#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 0x1FFF7FFF) */ +#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Device Electronic Signature */ #define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ @@ -943,10 +942,10 @@ typedef struct #define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1187,6 +1186,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ @@ -4001,7 +4009,7 @@ typedef struct /******************************************************************************/ /* */ -/* Global TrustZone Control */ +/* Global Security Control */ /* */ /******************************************************************************/ /******************* Bits definition for registers x = 0 ********************/ @@ -9092,100 +9100,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR register (SYSCFG SRAM2 write protection register) ***********************************************************/ #define SYSCFG_SWPR_PAGE0_Pos (0U) #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 0x200083FF) */ +#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */ #define SYSCFG_SWPR_PAGE1_Pos (1U) #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 0x200087FF) */ +#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */ #define SYSCFG_SWPR_PAGE2_Pos (2U) #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 0x20008BFF) */ +#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */ #define SYSCFG_SWPR_PAGE3_Pos (3U) #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 0x20008FFF) */ +#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */ #define SYSCFG_SWPR_PAGE4_Pos (4U) #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 0x200093FF) */ +#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */ #define SYSCFG_SWPR_PAGE5_Pos (5U) #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 0x200097FF) */ +#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */ #define SYSCFG_SWPR_PAGE6_Pos (6U) #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 0x20009BFF) */ +#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */ #define SYSCFG_SWPR_PAGE7_Pos (7U) #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 0x20009FFF) */ +#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */ #define SYSCFG_SWPR_PAGE8_Pos (8U) #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 0x2000A3FF) */ +#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */ #define SYSCFG_SWPR_PAGE9_Pos (9U) #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 0x2000A7FF) */ +#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */ #define SYSCFG_SWPR_PAGE10_Pos (10U) #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 0x2000ABFF) */ +#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */ #define SYSCFG_SWPR_PAGE11_Pos (11U) #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 0x2000AFFF) */ +#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */ #define SYSCFG_SWPR_PAGE12_Pos (12U) #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 0x2000B3FF) */ +#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */ #define SYSCFG_SWPR_PAGE13_Pos (13U) #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 0x2000B7FF) */ +#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */ #define SYSCFG_SWPR_PAGE14_Pos (14U) #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 0x2000BBFF) */ +#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */ #define SYSCFG_SWPR_PAGE15_Pos (15U) #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 0x2000BFFF) */ +#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */ #define SYSCFG_SWPR_PAGE16_Pos (16U) #define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 0x2000C3FF) */ +#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */ #define SYSCFG_SWPR_PAGE17_Pos (17U) #define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 0x2000C7FF) */ +#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */ #define SYSCFG_SWPR_PAGE18_Pos (18U) #define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 0x2000CBFF) */ +#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */ #define SYSCFG_SWPR_PAGE19_Pos (19U) #define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 0x2000CFFF) */ +#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */ #define SYSCFG_SWPR_PAGE20_Pos (20U) #define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 0x2000D3FF) */ +#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */ #define SYSCFG_SWPR_PAGE21_Pos (21U) #define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 0x2000D7FF) */ +#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */ #define SYSCFG_SWPR_PAGE22_Pos (22U) #define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 0x2000DBFF) */ +#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */ #define SYSCFG_SWPR_PAGE23_Pos (23U) #define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 0x2000DFFF) */ +#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */ #define SYSCFG_SWPR_PAGE24_Pos (24U) #define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 0x2000E3FF) */ +#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */ #define SYSCFG_SWPR_PAGE25_Pos (25U) #define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 0x2000E7FF) */ +#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */ #define SYSCFG_SWPR_PAGE26_Pos (26U) #define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 0x2000EBFF) */ +#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */ #define SYSCFG_SWPR_PAGE27_Pos (27U) #define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 0x2000EFFF) */ +#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */ #define SYSCFG_SWPR_PAGE28_Pos (28U) #define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 0x2000F3FF) */ +#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */ #define SYSCFG_SWPR_PAGE29_Pos (29U) #define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 0x2000F7FF) */ +#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */ #define SYSCFG_SWPR_PAGE30_Pos (30U) #define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 0x2000FBFF) */ +#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */ #define SYSCFG_SWPR_PAGE31_Pos (31U) #define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 0x2000FFFF) */ +#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle4xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle4xx.h index 385603abcea..54dc505a888 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle4xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle4xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -140,7 +139,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -769,9 +768,9 @@ typedef struct #define SRAM2_SIZE 0x00008000UL /*!< SRAM2 default size : 32 kB */ /*!< Memory, OTP and Option bytes */ -#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 0x1FFF7FFF) */ +#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Device Electronic Signature */ #define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ @@ -779,10 +778,10 @@ typedef struct #define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1005,6 +1004,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ @@ -7975,100 +7983,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR register (SYSCFG SRAM2 write protection register) ***********************************************************/ #define SYSCFG_SWPR_PAGE0_Pos (0U) #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 0x200083FF) */ +#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */ #define SYSCFG_SWPR_PAGE1_Pos (1U) #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 0x200087FF) */ +#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */ #define SYSCFG_SWPR_PAGE2_Pos (2U) #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 0x20008BFF) */ +#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */ #define SYSCFG_SWPR_PAGE3_Pos (3U) #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 0x20008FFF) */ +#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */ #define SYSCFG_SWPR_PAGE4_Pos (4U) #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 0x200093FF) */ +#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */ #define SYSCFG_SWPR_PAGE5_Pos (5U) #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 0x200097FF) */ +#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */ #define SYSCFG_SWPR_PAGE6_Pos (6U) #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 0x20009BFF) */ +#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */ #define SYSCFG_SWPR_PAGE7_Pos (7U) #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 0x20009FFF) */ +#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */ #define SYSCFG_SWPR_PAGE8_Pos (8U) #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 0x2000A3FF) */ +#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */ #define SYSCFG_SWPR_PAGE9_Pos (9U) #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 0x2000A7FF) */ +#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */ #define SYSCFG_SWPR_PAGE10_Pos (10U) #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 0x2000ABFF) */ +#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */ #define SYSCFG_SWPR_PAGE11_Pos (11U) #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 0x2000AFFF) */ +#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */ #define SYSCFG_SWPR_PAGE12_Pos (12U) #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 0x2000B3FF) */ +#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */ #define SYSCFG_SWPR_PAGE13_Pos (13U) #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 0x2000B7FF) */ +#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */ #define SYSCFG_SWPR_PAGE14_Pos (14U) #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 0x2000BBFF) */ +#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */ #define SYSCFG_SWPR_PAGE15_Pos (15U) #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 0x2000BFFF) */ +#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */ #define SYSCFG_SWPR_PAGE16_Pos (16U) #define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 0x2000C3FF) */ +#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */ #define SYSCFG_SWPR_PAGE17_Pos (17U) #define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 0x2000C7FF) */ +#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */ #define SYSCFG_SWPR_PAGE18_Pos (18U) #define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 0x2000CBFF) */ +#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */ #define SYSCFG_SWPR_PAGE19_Pos (19U) #define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 0x2000CFFF) */ +#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */ #define SYSCFG_SWPR_PAGE20_Pos (20U) #define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 0x2000D3FF) */ +#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */ #define SYSCFG_SWPR_PAGE21_Pos (21U) #define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 0x2000D7FF) */ +#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */ #define SYSCFG_SWPR_PAGE22_Pos (22U) #define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 0x2000DBFF) */ +#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */ #define SYSCFG_SWPR_PAGE23_Pos (23U) #define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 0x2000DFFF) */ +#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */ #define SYSCFG_SWPR_PAGE24_Pos (24U) #define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 0x2000E3FF) */ +#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */ #define SYSCFG_SWPR_PAGE25_Pos (25U) #define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 0x2000E7FF) */ +#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */ #define SYSCFG_SWPR_PAGE26_Pos (26U) #define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 0x2000EBFF) */ +#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */ #define SYSCFG_SWPR_PAGE27_Pos (27U) #define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 0x2000EFFF) */ +#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */ #define SYSCFG_SWPR_PAGE28_Pos (28U) #define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 0x2000F3FF) */ +#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */ #define SYSCFG_SWPR_PAGE29_Pos (29U) #define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 0x2000F7FF) */ +#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */ #define SYSCFG_SWPR_PAGE30_Pos (30U) #define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 0x2000FBFF) */ +#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */ #define SYSCFG_SWPR_PAGE31_Pos (31U) #define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 0x2000FFFF) */ +#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h index 5188a07b3f7..cb49d85314c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wle5xx.h @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -140,7 +139,7 @@ typedef enum #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 0U /*!< FPU present */ +#define __FPU_PRESENT 0U /*!< FPU not present */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ @@ -769,9 +768,9 @@ typedef struct #define SRAM2_SIZE 0x00008000UL /*!< SRAM2 default size : 32 kB */ /*!< Memory, OTP and Option bytes */ -#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 0x1FFF7FFF) */ +#define OTP_AREA_BASE (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTES_BASE (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Device Electronic Signature */ #define PACKAGE_BASE (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address */ @@ -779,10 +778,10 @@ typedef struct #define UID_BASE (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */ #define FLASHSIZE_BASE (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address */ -#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 0x1FFF6FFF) */ -#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 0x1FFF73FF) */ -#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 0x1FFF77FF) */ -#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 0x1FFF7FFF) */ +#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 - 0x1FFF6FFF) */ +#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 - 0x1FFF73FF) */ +#define ENGI_BYTE_END_ADDR (0x1FFF77FFUL) /*!< Engi Bytes : 1kB (0x1FFF7400 - 0x1FFF77FF) */ +#define OPTION_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Option Bytes : 2KB (0x1FFF7800 - 0x1FFF7FFF) */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE @@ -1005,6 +1004,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ @@ -7975,100 +7983,100 @@ typedef struct /***************** Bit definition for SYSCFG_SWPR register (SYSCFG SRAM2 write protection register) ***********************************************************/ #define SYSCFG_SWPR_PAGE0_Pos (0U) #define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ -#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 0x200083FF) */ +#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 (0x20008000 - 0x200083FF) */ #define SYSCFG_SWPR_PAGE1_Pos (1U) #define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ -#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 0x200087FF) */ +#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 (0x20008400 - 0x200087FF) */ #define SYSCFG_SWPR_PAGE2_Pos (2U) #define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ -#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 0x20008BFF) */ +#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 (0x20008800 - 0x20008BFF) */ #define SYSCFG_SWPR_PAGE3_Pos (3U) #define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ -#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 0x20008FFF) */ +#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 (0x20008C00 - 0x20008FFF) */ #define SYSCFG_SWPR_PAGE4_Pos (4U) #define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ -#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 0x200093FF) */ +#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 (0x20009000 - 0x200093FF) */ #define SYSCFG_SWPR_PAGE5_Pos (5U) #define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ -#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 0x200097FF) */ +#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 (0x20009400 - 0x200097FF) */ #define SYSCFG_SWPR_PAGE6_Pos (6U) #define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ -#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 0x20009BFF) */ +#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 (0x20009800 - 0x20009BFF) */ #define SYSCFG_SWPR_PAGE7_Pos (7U) #define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ -#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 0x20009FFF) */ +#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 (0x20009C00 - 0x20009FFF) */ #define SYSCFG_SWPR_PAGE8_Pos (8U) #define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ -#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 0x2000A3FF) */ +#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 (0x2000A000 - 0x2000A3FF) */ #define SYSCFG_SWPR_PAGE9_Pos (9U) #define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ -#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 0x2000A7FF) */ +#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 (0x2000A400 - 0x2000A7FF) */ #define SYSCFG_SWPR_PAGE10_Pos (10U) #define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ -#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 0x2000ABFF) */ +#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10 (0x2000A800 - 0x2000ABFF) */ #define SYSCFG_SWPR_PAGE11_Pos (11U) #define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ -#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 0x2000AFFF) */ +#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11 (0x2000AC00 - 0x2000AFFF) */ #define SYSCFG_SWPR_PAGE12_Pos (12U) #define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ -#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 0x2000B3FF) */ +#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12 (0x2000B000 - 0x2000B3FF) */ #define SYSCFG_SWPR_PAGE13_Pos (13U) #define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ -#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 0x2000B7FF) */ +#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13 (0x2000B400 - 0x2000B7FF) */ #define SYSCFG_SWPR_PAGE14_Pos (14U) #define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ -#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 0x2000BBFF) */ +#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14 (0x2000B800 - 0x2000BBFF) */ #define SYSCFG_SWPR_PAGE15_Pos (15U) #define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ -#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 0x2000BFFF) */ +#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15 (0x2000BC00 - 0x2000BFFF) */ #define SYSCFG_SWPR_PAGE16_Pos (16U) #define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */ -#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 0x2000C3FF) */ +#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16 (0x2000C000 - 0x2000C3FF) */ #define SYSCFG_SWPR_PAGE17_Pos (17U) #define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */ -#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 0x2000C7FF) */ +#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17 (0x2000C400 - 0x2000C7FF) */ #define SYSCFG_SWPR_PAGE18_Pos (18U) #define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */ -#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 0x2000CBFF) */ +#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18 (0x2000C800 - 0x2000CBFF) */ #define SYSCFG_SWPR_PAGE19_Pos (19U) #define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */ -#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 0x2000CFFF) */ +#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19 (0x2000CC00 - 0x2000CFFF) */ #define SYSCFG_SWPR_PAGE20_Pos (20U) #define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */ -#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 0x2000D3FF) */ +#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20 (0x2000D000 - 0x2000D3FF) */ #define SYSCFG_SWPR_PAGE21_Pos (21U) #define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */ -#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 0x2000D7FF) */ +#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21 (0x2000D400 - 0x2000D7FF) */ #define SYSCFG_SWPR_PAGE22_Pos (22U) #define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */ -#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 0x2000DBFF) */ +#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22 (0x2000D800 - 0x2000DBFF) */ #define SYSCFG_SWPR_PAGE23_Pos (23U) #define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */ -#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 0x2000DFFF) */ +#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23 (0x2000DC00 - 0x2000DFFF) */ #define SYSCFG_SWPR_PAGE24_Pos (24U) #define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */ -#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 0x2000E3FF) */ +#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24 (0x2000E000 - 0x2000E3FF) */ #define SYSCFG_SWPR_PAGE25_Pos (25U) #define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */ -#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 0x2000E7FF) */ +#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25 (0x2000E400 - 0x2000E7FF) */ #define SYSCFG_SWPR_PAGE26_Pos (26U) #define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */ -#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 0x2000EBFF) */ +#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26 (0x2000E800 - 0x2000EBFF) */ #define SYSCFG_SWPR_PAGE27_Pos (27U) #define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */ -#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 0x2000EFFF) */ +#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27 (0x2000EC00 - 0x2000EFFF) */ #define SYSCFG_SWPR_PAGE28_Pos (28U) #define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */ -#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 0x2000F3FF) */ +#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28 (0x2000F000 - 0x2000F3FF) */ #define SYSCFG_SWPR_PAGE29_Pos (29U) #define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */ -#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 0x2000F7FF) */ +#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29 (0x2000F400 - 0x2000F7FF) */ #define SYSCFG_SWPR_PAGE30_Pos (30U) #define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */ -#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 0x2000FBFF) */ +#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30 (0x2000F800 - 0x2000FBFF) */ #define SYSCFG_SWPR_PAGE31_Pos (31U) #define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */ -#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 0x2000FFFF) */ +#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31 (0x2000FC00 - 0x2000FFFF) */ /***************** Bit definition for SYSCFG_SKR register (SYSCFG SRAM2 key register) *************************************************************************/ #define SYSCFG_SKR_KEY_Pos (0U) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h index 01e41bac810..f53d4dd5ec0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/stm32wlxx.h @@ -8,21 +8,20 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32WLxx device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -80,7 +79,7 @@ * @brief CMSIS Device version number */ #define __STM32WLxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32WLxx_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ #define __STM32WLxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WLxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WLxx_CMSIS_DEVICE_VERSION ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\ @@ -157,9 +156,105 @@ typedef enum #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #if defined(CORE_CM0PLUS) +/* Use of interrupt control for register exclusive access (privileged mode only) */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + SET_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + CLEAR_BIT((REG), (BIT)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t primask; \ + primask = __get_PRIMASK(); \ + __set_PRIMASK(1); \ + MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \ + __set_PRIMASK(primask); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) + #else +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) -#endif +#endif /* CORE_CM0PLUS */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h index 3c435c52edd..b29530621c5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMSIS/system_stm32wlxx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMakeLists.txt index 4f30664f3fc..4cadd11ab59 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/CMakeLists.txt @@ -43,6 +43,7 @@ target_sources(mbed-stm32wlcube-fw STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c + STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c STM32WLxx_HAL_Driver/stm32wlxx_hal_spi_ex.c STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/License.md b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/License.md new file mode 100644 index 00000000000..c6b7c8bd41f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/License.md @@ -0,0 +1,3 @@ +# Copyright (c) 2020 STMicroelectronics + +This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause). \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h index 41b79bd04bc..5057a2d47e3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -23,7 +23,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,6 +38,14 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ /** * @} */ @@ -210,6 +218,18 @@ * @} */ +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif +/** + * @} + */ + /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose * @{ */ @@ -235,7 +255,7 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -382,7 +402,6 @@ #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ - /** * @} */ @@ -470,15 +489,24 @@ #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ /** * @} @@ -521,6 +549,7 @@ #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -595,24 +624,24 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 @@ -773,49 +802,6 @@ #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U @@ -895,7 +881,11 @@ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#endif /* STM32U5 */ /** * @} */ @@ -968,6 +958,11 @@ #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -979,15 +974,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -1022,7 +1017,7 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ @@ -1122,16 +1117,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1417,6 +1412,20 @@ */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1435,6 +1444,16 @@ * @} */ +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -1494,7 +1513,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1502,7 +1522,8 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode @@ -1525,9 +1546,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1537,7 +1558,8 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT @@ -1562,9 +1584,9 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ @@ -1619,9 +1641,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1870,15 +1892,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -2089,8 +2111,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -2146,7 +2168,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2283,7 +2305,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3363,7 +3386,20 @@ #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#endif /** * @} */ @@ -3380,7 +3416,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3400,19 +3436,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3437,13 +3473,17 @@ * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3596,6 +3636,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c index d65629715b2..45d49c610c0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal.c @@ -56,7 +56,7 @@ * @brief STM32WLxx HAL Driver version number */ #define __STM32WLxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32WLxx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __STM32WLxx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ #define __STM32WLxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WLxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WLxx_HAL_VERSION ((__STM32WLxx_HAL_VERSION_MAIN << 24U)\ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c index f56cb361c96..b3eb314a56d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.c @@ -211,11 +211,11 @@ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() + Use Functions HAL_ADC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + Function HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback @@ -229,11 +229,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback @@ -247,27 +247,27 @@ (+) MspDeInitCallback : ADC Msp DeInit callback [..] - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + reset to the legacy weak functions in the HAL_ADC_Init()/HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or @@ -416,7 +416,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - + if (hadc->Init.OversamplingMode == ENABLE) + { + assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); + } assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) @@ -476,7 +481,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -531,7 +536,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* function on the fly (update of a parameter of ADC_InitTypeDef */ /* without needing to reconfigure all other ADC groups/channels */ /* parameters): */ - /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* - internal measurement paths (VrefInt, ...) */ /* (set into HAL_ADC_ConfigChannel() ) */ /* Configuration of ADC resolution */ @@ -540,15 +545,17 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) hadc->Init.Resolution); tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode | hadc->Init.TriggerFrequencyMode ); if (hadc->Init.OversamplingMode == ENABLE) { - SET_BIT(tmpCFGR2, ADC_CFGR2_OVSE); + tmpCFGR2 |= (ADC_CFGR2_OVSE | + (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode + ); } MODIFY_REG(hadc->Instance->CFGR2, @@ -748,7 +755,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_ERROR; } - /* Return function status */ return tmp_hal_status; } @@ -764,9 +770,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) * bypassed without error reporting: it can be the intended behavior in * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. - * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents - * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ @@ -858,12 +861,10 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* ========== Hard reset ADC peripheral ========== */ /* Performs a global reset of the entire ADC peripheral: ADC state is */ /* forced to a similar state after device power-on. */ - /* If needed, copy-paste and uncomment the following reset code into */ - /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ - /* */ - /* __HAL_RCC_ADC_FORCE_RESET() */ - /* __HAL_RCC_ADC_RELEASE_RESET() */ - + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { @@ -886,10 +887,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1192,7 +1191,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ @@ -1230,7 +1228,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } } @@ -1239,7 +1236,6 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1259,7 +1255,6 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC group regular */ @@ -1281,10 +1276,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1309,7 +1302,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; - uint32_t tmp_Flag_End; + uint32_t tmp_flag_end; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1317,7 +1310,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { - tmp_Flag_End = ADC_FLAG_EOS; + tmp_flag_end = ADC_FLAG_EOS; } /* If end of conversion selected to end of unitary conversion */ else /* ADC_EOC_SINGLE_CONV */ @@ -1337,7 +1330,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti } else { - tmp_Flag_End = (ADC_FLAG_EOC); + tmp_flag_end = (ADC_FLAG_EOC); } } @@ -1345,20 +1338,23 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti tickstart = HAL_GetTick(); /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1452,13 +1448,16 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1570,7 +1569,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - /* Process locked */ __HAL_LOCK(hadc); /* Enable the ADC peripheral */ @@ -1633,7 +1631,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) } else { - /* Process unlocked */ __HAL_UNLOCK(hadc); } @@ -1643,7 +1640,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1661,7 +1657,6 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential conversion on going, on ADC group regular */ @@ -1687,10 +1682,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) } } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -1714,7 +1707,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { - /* Process locked */ __HAL_LOCK(hadc); /* Specific case for first call occurrence of this function (DMA transfer */ @@ -1791,7 +1783,6 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui tmp_hal_status = HAL_BUSY; } - /* Return function status */ return tmp_hal_status; } @@ -1809,7 +1800,6 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* 1. Stop potential ADC group regular conversion on going */ @@ -1860,10 +1850,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2100,7 +2088,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* ========== Check channel configuration ready flag ========== */ if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY)) { - /* Level out of window 1 callback */ + /* Channel configuration ready callback */ HAL_ADCEx_ChannelConfigReadyCallback(hadc); /* Clear ADC analog watchdog flag */ @@ -2208,10 +2196,10 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_ChannelConfTypeDef". * @param hadc ADC handle - * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @param pConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_config_internal_channel; @@ -2219,22 +2207,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime)); + assert_param(IS_ADC_CHANNEL(pConfig->Channel)); + assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime)); if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) { - assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank)); + assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank)); } else { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); } - /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ @@ -2252,7 +2239,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Otherwise (sequencer set to fully configurable or to to not fully */ /* configurable with channel rank to be set), configure the selected */ /* channel. */ - if (sConfig->Rank != ADC_RANK_NONE) + if (pConfig->Rank != ADC_RANK_NONE) { /* Regular sequence configuration */ /* Note: ADC channel configuration requires few ADC clock cycles */ @@ -2265,7 +2252,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* Sequencer set to not fully configurable: */ /* Set the channel by enabling the corresponding bitfield. */ - LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel); + LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel); } else { @@ -2274,21 +2261,21 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Memorize the channel set into variable in HAL ADC handle */ MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, - ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL), - __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL)); + ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL), + __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL)); /* If the selected rank is below ADC group regular sequencer length, */ /* apply the configuration in ADC register. */ /* Note: Otherwise, configuration is not applied. */ /* To apply it, parameter'NbrOfConversion' must be increased. */ - if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) + if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) { - LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); } } /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ /* internal measurement paths enable: If internal channel selected, */ @@ -2296,13 +2283,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit() or removing the channel from sequencer with */ /* channel configuration parameter "Rank". */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), @@ -2313,18 +2300,18 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; } } - else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } - else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && + else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), @@ -2348,27 +2335,27 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* Sequencer set to not fully configurable: */ /* Reset the channel by disabling the corresponding bitfield. */ - LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel); + LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel); } /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); } - else if (sConfig->Channel == ADC_CHANNEL_VBAT) + else if (pConfig->Channel == ADC_CHANNEL_VBAT) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel); } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + else if (pConfig->Channel == ADC_CHANNEL_VREFINT) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); @@ -2392,10 +2379,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2418,24 +2403,24 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; + uint32_t tmp_awd_high_threshold_shifted; + uint32_t tmp_awd_low_threshold_shifted; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); - if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) + if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel)); } /* Verify thresholds range */ @@ -2444,17 +2429,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of oversampling enabled: depending on ratio and shift configuration, analog watchdog thresholds can be higher than ADC resolution. Verify if thresholds are within maximum thresholds range. */ - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold)); } else { /* Verify if thresholds are within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); } - /* Process locked */ __HAL_LOCK(hadc); /* Parameters update conditioned to ADC state: */ @@ -2464,16 +2448,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Analog watchdog configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels. */ - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, - __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); break; case ADC_ANALOGWATCHDOG_ALL_REG: @@ -2495,7 +2479,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD1(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -2507,31 +2491,31 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch (AnalogWDGConfig->WatchdogMode) + switch (pAnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: /* Update AWD by bitfield to keep the possibility to monitor */ /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { - SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel))); } else { - SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel))); } break; case ADC_ANALOGWATCHDOG_ALL_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); break; default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); @@ -2543,7 +2527,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD2(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -2552,7 +2536,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_DisableIT_AWD2(hadc->Instance); } } - /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ else { /* Update state, clear previous result related to AWD3 */ @@ -2565,7 +2549,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG LL_ADC_ClearFlag_AWD3(hadc->Instance); /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) + if (pAnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -2579,13 +2563,13 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG } /* Analog watchdog thresholds configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); } /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ else @@ -2593,18 +2577,16 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDG /* No need to shift the offset with respect to the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ /* are set to 0. */ - tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold; - tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold; + tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold; + tmp_awd_low_threshold_shifted = pAnalogWDGConfig->LowThreshold; } /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, - tmpAWDLowThresholdShifted); + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted, + tmp_awd_low_threshold_shifted); - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -2708,13 +2690,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } @@ -2764,7 +2750,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2795,13 +2781,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -2856,13 +2846,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h index e0188e036f0..598e5fd2a80 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc.h @@ -132,8 +132,7 @@ typedef struct FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). - This parameter can be set to ENABLE or DISABLE. - Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ + This parameter can be set to ENABLE or DISABLE. */ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). @@ -473,7 +472,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} @@ -1668,8 +1667,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c index 9cd5322d3b4..267367d08a5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_adc_ex.c @@ -12,12 +12,6 @@ * Other functions (generic functions) are available in file * "stm32wlxx_hal_adc.c". * - @verbatim - [..] - (@) Sections "ADC peripheral features" and "How to use this driver" are - available in file of generic functions "stm32wlxx_hal_adc.c". - [..] - @endverbatim ****************************************************************************** * @attention * @@ -30,6 +24,12 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32wlxx_hal_adc.c". + [..] + @endverbatim */ /* Includes ------------------------------------------------------------------*/ @@ -110,7 +110,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ __HAL_LOCK(hadc); /* Calibration prerequisite: ADC must be disabled. */ @@ -149,7 +148,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; @@ -172,10 +170,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) /* to state "HAL_ERROR" by function disabling the ADC. */ } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } @@ -209,7 +205,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); - /* Process locked */ __HAL_LOCK(hadc); /* Verification of hardware constraints before modifying the calibration */ @@ -234,10 +229,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 tmp_hal_status = HAL_ERROR; } - /* Process unlocked */ __HAL_UNLOCK(hadc); - /* Return function status */ return tmp_hal_status; } diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c index 9d5d83f9945..ccde72415fd 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_comp.c @@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; @@ -733,7 +733,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h index 2b2fe2dbccc..9797364e6b1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cortex.h @@ -187,9 +187,12 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size * @{ */ +#if defined(CORE_CM0PLUS) +#else #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#endif #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) @@ -379,6 +382,33 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); ((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER7)) +#if defined(CORE_CM0PLUS) +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) +#else #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \ @@ -407,7 +437,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); ((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) - +#endif #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c index 55dd871f271..3ba989878cf 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_cryp.c @@ -587,15 +587,17 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD __HAL_LOCK(hcryp); /* Set CRYP parameters */ - hcryp->Init.DataType = pConf->DataType; - hcryp->Init.pKey = pConf->pKey; - hcryp->Init.Algorithm = pConf->Algorithm; - hcryp->Init.KeySize = pConf->KeySize; - hcryp->Init.pInitVect = pConf->pInitVect; - hcryp->Init.Header = pConf->Header; - hcryp->Init.HeaderSize = pConf->HeaderSize; - hcryp->Init.B0 = pConf->B0; - hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); @@ -661,7 +663,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->Header = hcryp->Init.Header ; pConf->HeaderSize = hcryp->Init.HeaderSize; pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -693,8 +697,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ } @@ -709,8 +713,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ } @@ -1929,8 +1933,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } @@ -1945,8 +1949,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -1961,8 +1965,8 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file */ } /** @@ -2570,15 +2574,31 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) /* Initiate payload DMA IN and processed data DMA OUT transfers */ (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); } + else + { + uint32_t algo; + /* ECB, CBC or CTR end of input data feeding + or + end of GCM/CCM payload data feeding through DMA */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; - /* Call input data transfer complete callback */ + /* Don't call input data transfer complete callback only if + it remains some input data to write to the peripheral. + This case can only occur for GCM and CCM with a payload length + not a multiple of 16 bytes */ + if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ + (((hcryp->Size) % 16U) != 0U))) + { + /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */ } /** @@ -2642,6 +2662,14 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) hcryp->Instance->DINR = 0x0U; count++; } + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /*Wait on CCF flag*/ CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); @@ -3380,7 +3408,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3431,6 +3459,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } /* Enter header data */ @@ -3470,15 +3506,6 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; } } - - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { @@ -3528,7 +3555,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3579,6 +3606,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3904,6 +3939,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t npblb; uint32_t mode; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3993,7 +4033,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (headersize_in_bytes == 0U) /* Header phase is skipped */ { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4077,26 +4126,63 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ + /* Enter header data */ + /* Check first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + hcryp->CrypHeaderCount++; + loopcounter++; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; } + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -4105,9 +4191,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; - } - - } /* end of if (DoKeyIVConfig == 1U) */ + }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ + } /* end of if (dokeyivconfig == 1U) */ else /* Key and IV have already been configured, header has already been processed; only process here message payload */ @@ -4182,6 +4267,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4387,9 +4480,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); @@ -4435,6 +4528,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4509,6 +4610,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr hcryp->Instance->DINR = 0U; index++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /* Wait for CCF flag to be raised */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do @@ -4550,6 +4659,15 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr /* Process unlocked */ __HAL_UNLOCK(hcryp); + + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } return HAL_OK; @@ -4947,6 +5065,14 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) @@ -5398,9 +5524,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c index 377bad3721c..f712cd18c22 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dac.c @@ -209,7 +209,7 @@ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -220,7 +220,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -231,12 +231,12 @@ (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init - and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -244,8 +244,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit - or @ref HAL_DAC_Init function. + using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit + or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h index 0cd2aedfe1d..010f9e02c98 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_def.h @@ -28,7 +28,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32wlxx.h" -#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ #include /* Exported types ------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c index 74c8c99bd1e..ee221a4795e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.c @@ -1002,7 +1002,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) This subsection provides functions allowing to (+) Configure the DMA channel(s) privilege and non-privilege attributes (+) Configure the DMA channel(s) secure and non-secure attributes from - secure world when the system implements the security (TZEN=1) + secure world when the system implements the security (ESE=1) (+) Get the DMA channel(s) attributes @endverbatim @@ -1142,7 +1142,7 @@ HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint3 /** * @brief Get the attribute of a DMA channel. * @note Secure and non-secure attributes are only available from secure state - * when the system implements the security (TZEN=1) + * when the system implements the security (ESE=1) * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param ChannelAttributes pointer to return the attributes. diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h index d2b5dd6530f..d281ed43736 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_dma.h @@ -347,7 +347,7 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Channel_Attributes DMA Channel Attributes * @brief DMA channel secure or non-secure and privileged or non-privileged attributes * @note Secure and non-secure attributes are only available from secure when the system - * implements the security (TZEN=1) + * implements the security (ESE=1) * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c index 9eb7e47c49f..74bfae77d61 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_exti.c @@ -330,6 +330,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { @@ -341,10 +345,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); @@ -362,15 +362,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT regval = SYSCFG->EXTICR[linepos >> 2u]; pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24u); } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h index c920de4bcd7..0fbe16b854a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_flash.h @@ -123,7 +123,7 @@ typedef struct uint32_t C2DebugAccessMode; /*!< CPU2 debug access enabled or disabled (used for OPTIONBYTE_C2_DEBUG_ACCESS). This parameter can be a value of @ref FLASH_OB_C2_DEBUG_ACCESS */ uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). - This parameter can be a value of @ref C2_FLASH_OB_BOOT_REGION */ + This parameter can be a value of @ref FLASH_OB_C2_BOOT_REGION */ uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). This parameter contains the CPU2 boot reset start address within the selected memory region. Make sure this parameter is word aligned. */ @@ -561,7 +561,7 @@ typedef struct * @} */ -/** @defgroup C2_FLASH_OB_BOOT_REGION CPU2 Option Bytes Reset Boot Vector +/** @defgroup FLASH_OB_C2_BOOT_REGION CPU2 Option Bytes Reset Boot Vector * @{ */ #define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from SRAM1 or SRAM2 */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c index d11d3dc5bd7..a51154c5037 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.c @@ -117,17 +117,9 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants +/** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) - #define GPIO_NUMBER (16U) /** * @} @@ -183,8 +175,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); @@ -197,18 +188,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); - temp |= ((GPIO_Init->Pull) << (position * 2U)); - GPIOx->PUPDR = temp; + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) { /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); @@ -229,7 +223,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) { temp = SYSCFG->EXTICR[position >> 2u]; temp &= ~(0x07uL << (4U * (position & 0x03U))); @@ -243,7 +237,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->IMR1; #endif /* CORE_CM0PLUS */ temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) { temp |= iocurrent; } @@ -259,7 +253,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->EMR1; #endif /* CORE_CM0PLUS */ temp &= ~(iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) { temp |= iocurrent; } @@ -272,7 +266,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) { temp |= iocurrent; } @@ -280,7 +274,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp = EXTI->FTSR1; temp &= ~(iocurrent); - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) { temp |= iocurrent; } diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h index 88c85b302cf..332a7c379a0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gpio.h @@ -107,26 +107,25 @@ typedef enum /** @defgroup GPIO_mode GPIO mode * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ @@ -135,10 +134,10 @@ typedef enum * @brief GPIO Output Maximum frequency * @{ */ -#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very high speed */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003u /*!< Very high speed */ /** * @} */ @@ -147,9 +146,9 @@ typedef enum * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ /** * @} */ @@ -208,6 +207,32 @@ typedef enum */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) + +/** + * @} + */ + /** @defgroup GPIO_Private_Macros GPIO Private Macros * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c index 36677c94e50..fee8189027b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.c @@ -15,16 +15,16 @@ ##### GTZC main features ##### ============================================================================== [..] - (+) Global TrustZone Controller (GTZC) composed of two sub-blocks: - (++) TZSC: TrustZone security controller + (+) Global Security Controller (GTZC) composed of two sub-blocks: + (++) TZSC: Security controller This sub-block defines the secure/privileged state of slave peripherals. It also controls the unprivileged area size for the watermark memory peripheral controller (MPCWM). - (++) TZIC: TrustZone illegal access controller + (++) TZIC: Security Illegal access controller This sub-block gathers all illegal access events in the system and generates a secure interrupt towards the secure CPU2 NVIC. - (+) These sub-blocks are used to configure TrustZone system security and + (+) These sub-blocks are used to configure system security and privilege such as: (++) on-chip Flash memory and RAM with programmable secure or privilege or both area @@ -112,7 +112,7 @@ ============================================================================== [..] This section provides functions allowing to initialize/configure TZSC - TZSC: TrustZone Security Controller + TZSC: Security Controller @endverbatim * @{ */ @@ -503,7 +503,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd [..] This section provides functions allowing to manage the common TZSC and TZSC-MPCWM lock. It includes lock enable, and current value read. - TZSC: TrustZone Security Controller + TZSC: Security Controller MPCWM: Memory Protection Controller WaterMark @endverbatim * @{ @@ -544,7 +544,7 @@ void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx) ============================================================================== [..] This section provides functions allowing to initialize/configure TZIC - TZIC: Trust Zone Interrupt Controller + TZIC: Security Interrupt Controller @endverbatim * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h index 71fe39c9460..d3aa3be60ad 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_gtzc.h @@ -121,7 +121,7 @@ typedef struct * @note that two maximum values are also defined here: * - max number of securable AHB/APB peripherals or masters (used in * TZSC sub-block) - * - max number of securable and TrustZone-aware AHB/APB peripherals + * - max number of securable and security-aware AHB/APB peripherals * or masters (used in TZIC sub-block) * @{ */ @@ -146,7 +146,7 @@ typedef struct /* Note that two maximum values are also defined here: * - max number of securable peripherals * (used in TZSC sub-block) - * - max number of securable and TrustZone-aware peripherals or masters + * - max number of securable and security-aware peripherals or masters * (used in TZIC sub-block) */ #define GTZC_TZSC_PERIPH_NUMBER 4U diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c index 8b3d7367894..1f3bc9323e8 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.c @@ -20,15 +20,15 @@ ============================================================================== [..] (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters : - (++) the semaphore ID from 0 to 31 + (++) the semaphore ID from 0 to 15 (++) the process ID from 0 to 255 (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter : - (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero + (++) the semaphore ID from 0 to 15. Note that the process ID value is implicitly assumed as zero (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter : - (++) the semaphore ID from 0_ID to 31 + (++) the semaphore ID from 0 to 15 (++) It returns 1 if the given semaphore is taken otherwise (Free) zero (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters : - (++) the semaphore ID from 0 to 31 + (++) the semaphore ID from 0 to 15 (++) the process ID from 0 to 255: (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt may be generated when enabled (notification activated). If ProcessID or MasterID does not match, @@ -144,7 +144,7 @@ /** * @brief Take a semaphore in 2 Step mode. - * @param SemID: semaphore ID from 0 to 31 + * @param SemID: semaphore ID from 0 to 15 * @param ProcessID: Process ID from 0 to 255 * @retval HAL status */ @@ -170,7 +170,7 @@ HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID) /** * @brief Fast Take a semaphore with 1 Step mode. - * @param SemID: semaphore ID from 0 to 31 + * @param SemID: semaphore ID from 0 to 15 * @retval HAL status */ HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID) @@ -201,7 +201,7 @@ uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID) /** * @brief Release a semaphore. - * @param SemID: semaphore ID from 0 to 31 + * @param SemID: semaphore ID from 0 to 15 * @param ProcessID: Process ID from 0 to 255 * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h index 44ff4088695..3455d0e7010 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_hsem.h @@ -43,7 +43,7 @@ extern "C" { /** * @brief SemID to mask helper Macro. - * @param __SEMID__: semaphore ID from 0 to 31 + * @param __SEMID__: semaphore ID from 0 to 15 * @retval Semaphore Mask. */ #define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c index 17feea72e8b..1bf9eb747a1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.c @@ -19,7 +19,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -28,7 +28,8 @@ (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx channel @@ -39,49 +40,49 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -92,120 +93,137 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() - or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and without a final stop condition in both cases (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and with a final stop condition in both cases - (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential - interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. - (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential interface. - Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) - or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). - Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() - or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() - or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() - or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() - or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointerHAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() + or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() + or usingHAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro. + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -213,23 +231,23 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + Function HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -244,11 +262,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). [..] - Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -263,24 +281,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() - or @ref HAL_I2C_Init() function. + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -336,28 +354,48 @@ #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ - -#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ -#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ -#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -390,24 +428,34 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); @@ -559,7 +607,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ @@ -1065,8 +1114,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1097,12 +1146,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); } while (hi2c->XferCount > 0U) @@ -1132,12 +1183,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1180,8 +1233,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1212,12 +1265,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } while (hi2c->XferCount > 0U) @@ -1248,12 +1303,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } @@ -1294,7 +1351,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1431,7 +1489,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1606,7 +1665,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -1627,7 +1687,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1675,7 +1736,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -1724,7 +1786,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1773,7 +1836,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); return HAL_OK; @@ -1846,7 +1910,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -1906,7 +1971,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1916,7 +1982,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -1990,7 +2057,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2050,7 +2118,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2060,7 +2129,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -2118,7 +2188,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2221,7 +2292,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -2374,12 +2446,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } @@ -2474,12 +2548,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); } do @@ -2510,12 +2586,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); } } } while (hi2c->XferCount > 0U); @@ -2608,7 +2686,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2627,7 +2706,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -2719,7 +2799,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); return HAL_OK; @@ -2792,7 +2873,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd } /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) + != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2813,7 +2895,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -2957,7 +3040,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3028,7 +3112,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3205,9 +3290,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3291,9 +3378,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3324,7 +3413,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -3383,7 +3473,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3393,7 +3484,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3453,9 +3545,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3539,9 +3633,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = I2C_NO_STARTSTOP; } @@ -3572,7 +3668,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); } else { @@ -3631,7 +3728,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3641,7 +3739,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } @@ -3862,7 +3961,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); } else { @@ -4138,7 +4238,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t hi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); } else { @@ -4356,7 +4457,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) uint32_t tmperror; /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; @@ -4365,7 +4467,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; @@ -4374,7 +4477,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) } /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -4628,7 +4732,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4636,7 +4741,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4649,7 +4755,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~I2C_FLAG_RXNE; @@ -4663,7 +4770,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR */ hi2c->Instance->TXDR = *hi2c->pBuffPtr; @@ -4674,7 +4782,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) { @@ -4690,11 +4799,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize = hi2c->XferCount; if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); } else { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } } @@ -4714,7 +4825,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -4745,7 +4857,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin /* Nothing to do */ } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, tmpITFlags); @@ -4765,7 +4878,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4774,13 +4888,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4788,8 +4904,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4828,7 +4945,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint } } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) { if (hi2c->XferCount > 0U) { @@ -4854,7 +4972,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { I2C_ITAddrCplt(hi2c, tmpITFlags); } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ @@ -4900,7 +5019,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -4908,7 +5028,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Process Locked */ __HAL_LOCK(hi2c); - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -4924,7 +5045,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Flush TX register */ I2C_Flush_TXDR(hi2c); } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); @@ -4985,7 +5107,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui } } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { if (hi2c->XferCount == 0U) { @@ -5011,7 +5134,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -5035,7 +5159,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5045,13 +5170,15 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_LOCK(hi2c); /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) { /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5086,8 +5213,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5148,7 +5276,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, ITFlags); } @@ -5175,8 +5304,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5229,8 +5359,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5298,7 +5429,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If 10bits addressing mode is selected */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) { slaveaddrcode = ownadd1code; hi2c->AddrEventCount++; @@ -6025,7 +6156,8 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) */ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -6053,7 +6185,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -6073,7 +6206,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) @@ -6100,7 +6234,8 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -6128,7 +6263,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); @@ -6148,7 +6284,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hi2c->XferOptions; if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \ @@ -6175,7 +6312,8 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) */ static void I2C_DMAError(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -6192,7 +6330,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma) */ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ if (hi2c->hdmatx != NULL) @@ -6248,7 +6387,8 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { @@ -6285,7 +6425,8 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { @@ -6319,7 +6460,8 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { @@ -6386,6 +6528,12 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 { if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { + /* In case of Soft End condition, generate the STOP condition */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } /* Wait until STOP Flag is reset */ /* AutoEnd should be initiate after AF */ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) @@ -6461,9 +6609,11 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h index 52884b3615e..ce949ac6a0d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c.h @@ -48,29 +48,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization - section in Reference manual */ + This parameter calculated by referring to I2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ } I2C_InitTypeDef; @@ -200,7 +201,8 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ @@ -217,20 +219,32 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */ - - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */ - - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } I2C_HandleTypeDef; @@ -259,8 +273,11 @@ typedef enum /** * @brief HAL I2C Callback pointer definition */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @@ -440,14 +457,14 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -#endif +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ /** @brief Enable the specified I2C interrupt. * @param __HANDLE__ specifies the I2C Handle. @@ -542,26 +559,27 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Disable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) /** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. * @param __HANDLE__ specifies the I2C Handle. * @retval None */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) /** * @} */ @@ -601,12 +619,14 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, @@ -757,10 +777,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) #define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) #define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) #define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) #define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) @@ -772,10 +796,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c index 189f884e6c9..bb0332432e1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.c @@ -71,17 +71,15 @@ * @{ */ -/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters - (+) Configure Wake Up Feature - (+) Configure Fast Mode Plus @endverbatim * @{ @@ -182,6 +180,23 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ /** * @brief Enable I2C wakeup from Stop mode(s). @@ -260,6 +275,23 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ /** * @brief Enable the I2C fast mode plus driving capability. @@ -308,7 +340,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); } - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h index acd29b5d12c..fd5e4b0c0bb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2c_ex.h @@ -38,7 +38,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -71,24 +70,50 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -115,9 +140,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)) - - - /** * @} */ @@ -139,14 +161,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c index e5336eb2770..8890e8ab334 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_i2s.c @@ -741,7 +741,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -858,7 +858,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -959,7 +959,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1023,7 +1023,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization @@ -1089,7 +1089,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1180,7 +1180,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c index e53a26ab165..5f5951dfebb 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.c @@ -113,8 +113,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -129,9 +129,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -146,13 +146,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -161,8 +161,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -2362,7 +2362,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) uint32_t tmpreg; IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the communication parameters */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h index 627c482d78b..8fa70cd3b9b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_irda.h @@ -89,7 +89,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -106,7 +106,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c index 67d19e559bd..d95f3681d14 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.c @@ -65,13 +65,13 @@ (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) Wait for status flags to be reset. (++) Depending on window parameter: (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. (+++) Else modify Window register. This will automatically reload watchdog counter. + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -121,11 +121,14 @@ /* Status register needs up to 5 LSI clock periods divided by the clock prescaler to be updated. The number of LSI clock periods is upper-rounded to 6 for the timeout value calculation. - The timeout value is also calculated using the highest prescaler (256) and + The timeout value is calculated using the highest prescaler (256) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} */ @@ -196,11 +199,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != 0x00u) + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { - return HAL_TIMEOUT; + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } } } @@ -223,6 +229,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ @@ -242,7 +249,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ - /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains @@ -258,6 +264,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h index 5627957eec7..cf6667214f0 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_iwdg.h @@ -87,7 +87,6 @@ typedef struct #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ - /** * @} */ @@ -100,7 +99,6 @@ typedef struct * @} */ - /** * @} */ @@ -138,7 +136,7 @@ typedef struct * @{ */ /* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ @@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c index db28046e75e..9b849c8ec09 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_lptim.c @@ -96,13 +96,13 @@ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. - @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: @@ -122,7 +122,7 @@ [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -136,7 +136,7 @@ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or @@ -251,19 +251,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); @@ -322,21 +320,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ @@ -355,19 +350,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UltraLowPowerClock.SampleTime); } - /* Configure the active edge or edges used by the counter only if LPTIM is - * clocked by an external clock source - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); } + /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c index 7faf33b32f8..edc23a197cc 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pka.c @@ -174,11 +174,11 @@ The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_PKA_RegisterCallback() + Use Functions HAL_PKA_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_PKA_RegisterCallback() allows to register following callbacks: + Function HAL_PKA_RegisterCallback() allows to register following callbacks: (+) OperationCpltCallback : callback for End of operation. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : callback for Msp Init. @@ -187,11 +187,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_PKA_UnRegisterCallback to reset a callback to the default + Use function HAL_PKA_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) OperationCpltCallback : callback for End of operation. @@ -200,27 +200,27 @@ (+) MspDeInitCallback : callback for Msp DeInit. [..] - By default, after the @ref HAL_PKA_Init() and when the state is @ref HAL_PKA_STATE_RESET + By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_PKA_OperationCpltCallback(), @ref HAL_PKA_ErrorCallback(). + examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() only when + reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_PKA_Init()/ @ref HAL_PKA_DeInit() + If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_PKA_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_PKA_STATE_READY or @ref HAL_PKA_STATE_RESET state, + in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_PKA_RegisterCallback() before calling @ref HAL_PKA_DeInit() - or @ref HAL_PKA_Init() function. + using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit() + or HAL_PKA_Init() function. [..] When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c index 5c861177aae..34613a5d1f1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_pwr_ex.c @@ -198,7 +198,7 @@ void HAL_PWREx_EnableInternalWakeUpLine(void) void HAL_PWREx_DisableInternalWakeUpLine(void) { #ifdef CORE_CM0PLUS - CLEAR_BIT(PWR->CR3, PWR_C2CR3_EIWUL); + CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL); #else CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); #endif diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c index d90562204bc..27b9281c036 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.c @@ -133,7 +133,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. The number of flash wait states is automatically adjusted when MSI range is updated with - @ref HAL_RCC_OscConfig() and the MSI is used as System clock source. + HAL_RCC_OscConfig() and the MSI is used as System clock source. (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC clock source. @@ -173,14 +173,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these buses. You can use - "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. The AHB3 clock (HCLK3) is derived from System clock through configurable prescaler and used to clock the FLASH. APB3 (PCLK3) is derived from AHB3 clock. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 32. - You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function + You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function to configure this clock. (+@) IWDG clock which is always the LSI clock. @@ -1591,6 +1591,25 @@ __weak void HAL_RCC_CSSCallback(void) */ } +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->CSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->CSR |= RCC_CSR_RMVF; + + return reset; +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h index 5d26e16a30f..eb82375a157 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc.h @@ -51,6 +51,9 @@ extern "C" { #define RCC_FLAG_MASK 0x1FU +/* Defines Oscillator Masks */ +#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE) /*!< All Oscillator to configure */ + /** @defgroup RCC_Timeout_Value Timeout Values * @{ */ @@ -61,6 +64,23 @@ extern "C" { * @} */ +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + /** * @} */ @@ -70,13 +90,8 @@ extern "C" { * @{ */ -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ - (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ @@ -2360,6 +2375,7 @@ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); +uint32_t HAL_RCC_GetResetSource(void); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c index 89cad9d71cb..4a719257277 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.c @@ -78,7 +78,7 @@ static uint32_t RCC_PLL_GetFreqDomain_Q(void); This subsection provides a set of functions allowing to control the RCC Clocks frequencies. [..] - (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select the RTC clock source; in this case the Backup domain will be reset in order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register are set to their reset values. diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h index 7647347d364..d14a81ed26a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rcc_ex.h @@ -38,6 +38,19 @@ extern "C" { * @{ */ /* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/* Define used for IS_RCC_* macros below */ +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2S2 | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \ + RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_RTC ) +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCCEx_Private_Macros * @{ @@ -46,19 +59,8 @@ extern "C" { #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) -#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ + (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c index 457f60853f8..60dd1b7f367 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.c @@ -31,8 +31,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. - Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + Use FunctionHAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : RNG Error Callback. (+) MspInitCallback : RNG MspInit. (+) MspDeInitCallback : RNG MspDeInit. @@ -40,9 +40,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : RNG Error Callback. @@ -51,16 +51,16 @@ [..] For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). [..] - By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - example @ref HAL_RNG_ErrorCallback(). + example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() - and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -69,8 +69,8 @@ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() - or @ref HAL_RNG_Init() function. + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or @@ -227,9 +227,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -249,9 +253,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_ERROR; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -295,11 +303,15 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -665,11 +677,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h index 7a0c7550d07..cc62fd8f979 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng.h @@ -363,15 +363,14 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); * @} */ -/* Private functions----------------------------------------------------------*/ -/** @defgroup RNG_Private_Functions RNG Private Functions +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private functions * @{ */ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); /** * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c index 09fd3f71206..34591bc868b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.c @@ -31,7 +31,7 @@ #if defined(RNG) -/** @addtogroup RNGEx +/** @addtogroup RNG_Ex * @brief RNG Extended HAL module driver. * @{ */ @@ -40,7 +40,7 @@ #if defined(RNG_CR_CONDRST) /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Defines RNGEx Private Defines +/** @defgroup RNG_Ex_Private_Defines RNGEx Private Defines * @{ */ /* Health test control register information to use in CCM algorithm */ @@ -51,7 +51,7 @@ */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @defgroup RNG_Ex_Private_Constants RNGEx Private Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -63,11 +63,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNGEx_Exported_Functions +/** @addtogroup RNG_Ex_Exported_Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @addtogroup RNG_Ex_Exported_Functions_Group1 * @brief Configuration functions * @verbatim @@ -152,9 +152,13 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -276,7 +280,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @addtogroup RNG_Ex_Exported_Functions_Group2 * @brief Recover from seed error function * @verbatim diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h index f93507ce1f2..c1792c73df2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rng_ex.h @@ -35,19 +35,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNGEx RNGEx +/** @defgroup RNG_Ex RNG_Ex * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Types RNGEx Exported Types - * @brief RNGEx Exported types +/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types + * @brief RNG_Ex Exported types * @{ */ /** - * @brief RNGEX Configuration Structure definition + * @brief RNG_Ex Configuration Structure definition */ typedef struct @@ -56,9 +56,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNGEX_Clock_Divider_Factor */ + be a value of @ref RNG_Ex_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNGEX_NIST_Compliance */ + value of @ref RNG_Ex_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -66,11 +66,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants +/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants * @{ */ -/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -109,7 +109,7 @@ typedef struct * @} */ -/** @defgroup RNGEX_NIST_Compliance NIST Compliance configuration +/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -124,7 +124,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Types RNGEx Private Types +/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types * @{ */ @@ -133,7 +133,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Variables RNGEx Private Variables +/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables * @{ */ @@ -142,7 +142,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Constants RNGEx Private Constants +/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants * @{ */ @@ -151,7 +151,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Macros RNGEx Private Macros +/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros * @{ */ @@ -188,7 +188,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNGEx_Private_Functions RNGEx Private Functions +/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions * @{ */ @@ -197,11 +197,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions +/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions * @{ */ -/** @addtogroup RNGEx_Exported_Functions_Group1 +/** @addtogroup RNG_Ex_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); @@ -212,7 +212,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNGEx_Exported_Functions_Group2 +/** @addtogroup RNG_Ex_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); @@ -245,6 +245,6 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); #endif -#endif /* STM32WLxx_HAL_RNGEX_H */ +#endif /* STM32WLxx_HAL_RNG_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c index 93ac670f7e9..67c97889b9d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc.c @@ -1174,14 +1174,18 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if( sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY ) { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ @@ -1192,30 +1196,37 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } else /* format BCD */ { - if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + if( sAlarm->AlarmMask != RTC_ALARMMASK_ALL ) { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + if( sAlarm->AlarmMask != RTC_ALARMMASK_HOURS ) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + } -#ifdef USE_FULL_ASSERT - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); } - else +#ifdef USE_FULL_ASSERT + if( ( sAlarm->AlarmMask != RTC_ALARMMASK_ALL ) && ( sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY ) ) { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } } - #endif /* USE_FULL_ASSERT */ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ @@ -1369,14 +1380,18 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if( sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY ) { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ @@ -1387,30 +1402,38 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } else /* Format BCD */ { - if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else + if( sAlarm->AlarmMask != RTC_ALARMMASK_ALL ) { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } + if( sAlarm->AlarmMask != RTC_ALARMMASK_HOURS ) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + } #ifdef USE_FULL_ASSERT - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if( ( sAlarm->AlarmMask != RTC_ALARMMASK_ALL ) && ( sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY ) ) { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } } - #endif /* USE_FULL_ASSERT */ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ @@ -1516,26 +1539,33 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar if (Alarm == RTC_ALARM_A) { - /* AlarmA, Clear SSCLR */ - CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); - /* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + /* Store in the handle the Alarm A disabled */ CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + + /* Clear AlarmA flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); } else { - /* AlarmB, Clear SSCLR */ - CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); - /* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + /* Store in the handle the Alarm B disabled */ CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + + /* Clear AlarmB flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); } + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1742,7 +1772,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) UNUSED(hrtc); /* Clear RSF flag */ - SET_BIT(RTC->ICSR, RTC_RSF_MASK); + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); tickstart = HAL_GetTick(); diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c index 815977e416d..f4c85267b14 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.c @@ -282,6 +282,12 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /* In case of interrupt mode is used, the interrupt source must disabled */ CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); + /* Clear timestamp flag only if internal timestamp flag not set */ + if( READ_BIT( RTC->SR, RTC_SR_ITSF) == 0U ) + { + WRITE_REG(RTC->SCR, RTC_SCR_CTSF); + } + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -342,6 +348,16 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) /* Configure the internal Time Stamp Enable bits */ CLEAR_BIT(RTC->CR, RTC_CR_ITSE); + /* Clear internal timestamp flag if Timestamp not enabled and TSOVF not set */ + WRITE_REG(RTC->SCR, RTC_SCR_CITSF); + if ( READ_BIT(RTC->SR, RTC_SR_TSOVF) == 0U ) + { + if ( READ_BIT(RTC->CR, RTC_CR_TSE) == 0U ) + { + WRITE_REG(RTC->SCR, RTC_SCR_CTSF); + } + } + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -710,6 +726,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) } } + /* Clear wakeup timer flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1355,6 +1374,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) /* In case of interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_TS); + /* Clear SSR underflow flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h index f6abf908df8..6906e9f1366 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_rtc_ex.h @@ -322,13 +322,13 @@ typedef struct #define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ #define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ #define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */ -#define RTC_IT_TAMP_ALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE) +#define RTC_IT_TAMP_ALL (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE) #define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE #define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE #define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE #define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE -#define RTC_IT_INT_TAMP_ALL (TAMP_IT_INT_TAMP3 | TAMP_IT_INT_TAMP5 | TAMP_IT_INT_TAMP6 | TAMP_IT_INT_TAMP8) +#define RTC_IT_INT_TAMP_ALL (TAMP_IER_ITAMP3IE | TAMP_IER_ITAMP5IE | TAMP_IER_ITAMP6IE | TAMP_IER_ITAMP8IE) /** * @} */ @@ -339,7 +339,7 @@ typedef struct #define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F #define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F #define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F -#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3 ) +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3 ) #define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F @@ -727,13 +727,13 @@ typedef struct #if defined(CORE_CM0PLUS) #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) -#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) -#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) #else #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) -#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) -#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) +#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) +#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) #endif /** @@ -866,9 +866,14 @@ typedef struct * @arg RTC_TAMPER_1: Tamper1 * @arg RTC_TAMPER_2: Tamper2 * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) ((TAMP->CR1 |= (__TAMPER__)) +#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__)) /** * @brief Disable the TAMP Tamper input detection. @@ -879,8 +884,13 @@ typedef struct * @arg RTC_TAMPER_1: Tamper1 * @arg RTC_TAMPER_2: Tamper2 * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt */ -#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) ((TAMP->CR1 &= ~(__TAMPER__)) +#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) /**************************************************************************************************/ @@ -893,9 +903,14 @@ typedef struct * @arg RTC_IT_TAMP_1: Tamper1 interrupt * @arg RTC_IT_TAMP_2: Tamper2 interrupt * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((TAMP->IER |= (__INTERRUPT__)) +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__)) /** * @brief Disable the TAMP Tamper interrupt. @@ -906,10 +921,14 @@ typedef struct * @arg RTC_IT_TAMP_1: Tamper1 interrupt * @arg RTC_IT_TAMP_2: Tamper2 interrupt * @arg RTC_IT_TAMP_3: Tamper3 interrupt - + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((TAMP->IER &= ~(__INTERRUPT__)) +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__)) /**************************************************************************************************/ @@ -929,7 +948,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) /** @@ -948,7 +967,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) /** @@ -990,13 +1009,13 @@ typedef struct #if defined(CORE_CM0PLUS) #define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) #define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) -#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) -#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) +#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) +#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) #else #define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) #define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) -#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) -#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) +#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) +#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) #endif /** @@ -1037,7 +1056,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c index f811a6b036e..67f585ec2e3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.c @@ -107,8 +107,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -123,9 +123,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -140,13 +140,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -155,8 +155,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -2327,7 +2327,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the parameters */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h index cb80428c341..4d20df41e41 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard.h @@ -159,7 +159,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -176,7 +176,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c index 823dc41d737..6a27ed4709a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smartcard_ex.c @@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c index 5754a500a9e..63210321ce5 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.c @@ -20,7 +20,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -33,69 +33,75 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API: + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError() - (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_SMBUS_GetError() + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using + HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in SMBUS HAL driver. - (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral - (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral - (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not - (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt - (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -107,11 +113,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback. [..] - Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -123,24 +129,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. [..] - By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after theHAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() - or @ref HAL_SMBUS_Init() function. + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -203,8 +209,8 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); @@ -215,8 +221,8 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); /** * @} */ @@ -364,15 +370,20 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ /* Configure SMBUSx: Dual mode and Own Address2 */ - hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U)); + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ + (hsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ /* Configure SMBUSx: Generalcall and NoStretch mode */ - hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ + hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ + hsmbus->Init.AnalogFilter); - /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) - && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and SMBUS Peripheral is set in Slave mode */ + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ + ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; } @@ -581,7 +592,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -695,7 +707,8 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -790,7 +803,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_ * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -914,8 +928,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -955,7 +969,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); } else { @@ -965,9 +980,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Store current volatile XferOptions, misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -976,7 +993,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ @@ -1057,7 +1076,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_READ); } else { @@ -1067,9 +1087,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Store current volatile XferOptions, Misra rule */ tmp = hsmbus->XferOptions; - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1078,7 +1100,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_READ); } } @@ -1222,12 +1246,14 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1313,7 +1339,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); } else { @@ -1576,7 +1603,8 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || @@ -1600,7 +1628,8 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || @@ -1720,7 +1749,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsmbus); @@ -1879,7 +1909,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* re-enable the selected SMBUS peripheral */ + /* Re-enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); /* Call the corresponding callback to inform upper layer of End of Transfer */ @@ -1967,13 +1997,15 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t if (hsmbus->XferCount > MAX_NBYTE_SIZE) { SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, - (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2225,7 +2257,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S else { /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, 1, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; @@ -2237,14 +2271,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else { hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) @@ -2489,7 +2525,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmperror; /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; @@ -2498,7 +2535,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; @@ -2507,7 +2545,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; @@ -2516,7 +2555,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; @@ -2525,7 +2565,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; @@ -2534,7 +2575,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) { hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; @@ -2582,8 +2624,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2632,8 +2674,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2644,9 +2686,10 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h index 51bd713f1ca..8db5112e2bf 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32wlxx_hal_def.h" +#include "stm32wlxx_hal_smbus_ex.h" /** @addtogroup STM32WLxx_HAL_Driver * @{ @@ -48,42 +49,43 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref SMBUS_Analog_Filter */ + This parameter can be a value of @ref SMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. - This parameter can be a value of @ref SMBUS_addressing_mode */ + This parameter can be a value of @ref SMBUS_addressing_mode */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref SMBUS_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref SMBUS_nostretch_mode */ + This parameter can be a value of @ref SMBUS_nostretch_mode */ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref SMBUS_peripheral_mode */ + This parameter can be a value of @ref SMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization - section in Reference manual */ + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ } SMBUS_InitTypeDef; /** * @} @@ -102,7 +104,7 @@ typedef struct #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -121,7 +123,7 @@ typedef struct #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** @@ -159,17 +161,26 @@ typedef struct __IO uint32_t ErrorCode; /*!< SMBUS Error code */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ - - void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp DeInit callback */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } SMBUS_HandleTypeDef; @@ -195,8 +206,11 @@ typedef enum /** * @brief HAL SMBUS Callback pointer definition */ -typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ -typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); +/*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an SMBUS Address Match callback function */ #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -358,9 +372,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE #define SMBUS_IT_RXI I2C_CR1_RXIE #define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \ - SMBUS_IT_TXI) -#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ + SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ + SMBUS_IT_RXI) #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) /** @@ -408,14 +423,14 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval None */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) -#endif +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @brief Enable the specified SMBUS interrupts. * @param __HANDLE__ specifies the SMBUS Handle. @@ -491,7 +506,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #define SMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ - (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -574,43 +590,52 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ + SMBUS_RELOAD_MODE ))) #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) -#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ + I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ + (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) @@ -648,11 +673,14 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ /** @@ -678,10 +706,10 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t * @{ */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c new file mode 100644 index 00000000000..f249e07dfdc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.c @@ -0,0 +1,146 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32WLxx + devices contains the following additional features + + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_EnableFastModePlus() + (++) HAL_SMBUSEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h new file mode 100644 index 00000000000..82327b188f5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_smbus_ex.h @@ -0,0 +1,138 @@ +/** + ****************************************************************************** + * @file stm32wlxx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WLxx_HAL_SMBUS_EX_H +#define STM32WLxx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wlxx_hal_def.h" + +/** @addtogroup STM32WLxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions + * @{ + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32wlxx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WLxx_HAL_SMBUS_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c index f494700bc1c..dd824024111 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_spi.c @@ -1007,6 +1007,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1173,12 +1178,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { @@ -1190,7 +1201,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -1241,8 +1254,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; #if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; uint32_t spi_cr1; uint32_t spi_cr2; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ @@ -1476,12 +1492,18 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1493,7 +1515,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -3048,6 +3072,11 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3072,12 +3101,18 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -3087,7 +3122,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } } } @@ -3152,6 +3189,11 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3174,8 +3216,12 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } - /* Read CRC to Flush DR and RXNE flag */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } else { @@ -3185,7 +3231,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } #endif /* USE_SPI_CRC */ @@ -3520,8 +3568,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); hspi->CRCSize--; @@ -3628,8 +3683,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3684,8 +3743,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); hspi->CRCSize--; @@ -3738,8 +3804,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3917,11 +3987,16 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; + __IO uint8_t * ptmpreg8; + __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); tmp_tickstart = HAL_GetTick(); + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); @@ -3929,8 +4004,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - /* Read 8bit CRC to flush Data Register */ - READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); } if (Timeout != HAL_MAX_DELAY) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c index e2fa9a8ee9c..bc5a3f72a75 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.c @@ -155,6 +155,7 @@ /* SystemCoreClock dividers. Corresponding to time execution of while loop. */ #define SUBGHZ_DEFAULT_LOOP_TIME ((SystemCoreClock*28U)>>19U) #define SUBGHZ_RFBUSY_LOOP_TIME ((SystemCoreClock*24U)>>20U) +#define SUBGHZ_NSS_LOOP_TIME ((SystemCoreClock*24U)>>16U) /** * @} */ @@ -319,6 +320,7 @@ HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz) { HAL_StatusTypeDef status; + __IO uint32_t count; /* Check the SUBGHZ handle allocation */ if (hsubghz == NULL) @@ -363,8 +365,25 @@ HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz) LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_NONE); #endif /* CM0PLUS */ - /* Disable the Radio peripheral Reset signal */ - LL_RCC_RF_DisableReset(); + /* Clear Pending Flag */ + LL_PWR_ClearFlag_RFBUSY(); + + /* Re-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_EnableReset(); + + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + + do + { + if (count == 0U) + { + status = HAL_ERROR; + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + break; + } + count--; + } while (LL_RCC_IsRFUnderReset() != 1UL); hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; hsubghz->State = HAL_SUBGHZ_STATE_RESET; @@ -1677,13 +1696,22 @@ HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, */ HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) { + __IO uint32_t count; + /* Wakeup radio in case of sleep mode: Select-Unselect radio */ if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) { + /* Initialize NSS switch Delay */ + count = SUBGHZ_NSS_LOOP_TIME; + /* NSS = 0; */ LL_PWR_SelectSUBGHZSPI_NSS(); - HAL_Delay(1); + /* Wait Radio wakeup */ + do + { + count--; + } while (count != 0UL); /* NSS = 1 */ LL_PWR_UnselectSUBGHZSPI_NSS(); diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h index 754c805fcce..1d5ff01cec7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_subghz.h @@ -51,7 +51,7 @@ typedef struct { uint32_t BaudratePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure SUBGHZSPI clock. - This parameter can be a value of @ref SUBGHZSPI_BAUDRATE_Prescaler */ + This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler */ } SUBGHZ_InitTypeDef; /** @@ -207,7 +207,7 @@ typedef enum * @} */ -/** @defgroup SUBGHZSPI_BAUDRATE_Prescaler SUBGHZ BaudRate Prescaler +/** @defgroup SUBGHZ_SPI_BAUDRATE_Prescaler SUBGHZ BaudRate Prescaler * @{ */ #define SUBGHZSPI_BAUDRATEPRESCALER_2 (0x00000000U) @@ -305,7 +305,7 @@ typedef enum /** @brief Checks if SUBGHZSPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SUBGHZSPI Baudrate prescaler. - * This parameter can be a value of @ref SUBGHZSPI_BAUDRATE_Prescaler + * This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler * @retval None */ #define IS_SUBGHZSPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_2) || \ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c index be883ae59c2..a2575c2fcee 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.c @@ -103,14 +103,14 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] @@ -147,7 +147,7 @@ [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -161,7 +161,7 @@ all interrupt callbacks are set to the corresponding weak functions: in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or @@ -2333,6 +2333,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + switch (Channel) { case TIM_CHANNEL_1: @@ -2419,23 +2436,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - /* Return function status */ return HAL_OK; } @@ -2690,11 +2690,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2726,7 +2727,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2746,11 +2747,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2762,7 +2764,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2788,11 +2790,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2824,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2850,11 +2853,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2872,7 +2876,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h index dd7a9e0172a..6efaa4016fd 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim.h @@ -1073,24 +1073,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c index 0e7270c78df..379e3674fa1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_tim_ex.c @@ -1532,8 +1532,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1542,22 +1544,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); @@ -1573,8 +1581,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1598,8 +1608,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1608,8 +1620,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1618,22 +1632,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -1655,8 +1675,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1686,8 +1708,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2370,15 +2394,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } @@ -2391,15 +2417,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c index ccbd0bf617b..d466234670d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.c @@ -76,8 +76,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -95,9 +95,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -116,16 +116,16 @@ [..] For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -134,8 +134,8 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or @@ -1380,7 +1380,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ - SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } else { @@ -1397,7 +1397,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } return HAL_OK; @@ -1452,6 +1452,16 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + return(UART_Start_Receive_IT(huart, pData, Size)); } else @@ -1543,7 +1553,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1599,6 +1609,16 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + return(UART_Start_Receive_DMA(huart, pData, Size)); } else @@ -1623,17 +1643,17 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) (gstate == HAL_UART_STATE_BUSY_TX)) { /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1653,7 +1673,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if (huart->RxState == HAL_UART_STATE_BUSY_RX) { @@ -1661,11 +1681,11 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } __HAL_UNLOCK(huart); @@ -1694,7 +1714,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel */ if (huart->hdmatx != NULL) @@ -1718,7 +1738,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -1756,20 +1776,20 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | - USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1794,7 +1814,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1857,13 +1877,13 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1915,19 +1935,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1984,14 +2004,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) uint32_t abortcplt = 1U; /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | - USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -2029,7 +2049,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2052,7 +2072,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2134,13 +2154,13 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2224,19 +2244,19 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2417,7 +2437,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) @@ -2502,18 +2522,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); @@ -2538,10 +2558,10 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) &&(nb_rx_data > 0U) ) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -2550,7 +2570,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2900,7 +2920,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2920,7 +2940,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); huart->gState = HAL_UART_STATE_READY; @@ -2949,10 +2969,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); huart->gState = HAL_UART_STATE_READY; @@ -2972,10 +2992,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); huart->gState = HAL_UART_STATE_READY; @@ -3452,8 +3472,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3472,8 +3493,9 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3515,7 +3537,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxState = HAL_UART_STATE_BUSY_RX; /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) @@ -3533,8 +3555,8 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); } else { @@ -3551,7 +3573,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); } return HAL_OK; } @@ -3597,8 +3619,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } @@ -3606,14 +3628,14 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -3627,8 +3649,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, TXFT interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3643,13 +3665,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } /* At end of Rx process, restore huart->RxState to Ready */ @@ -3677,10 +3699,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ else @@ -3728,12 +3750,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) huart->RxXferCount = 0U; /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3741,7 +3763,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } } @@ -4053,10 +4075,10 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { @@ -4084,10 +4106,10 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } else { @@ -4118,10 +4140,10 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } @@ -4159,10 +4181,10 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->TxXferCount == 0U) { /* Disable the TX FIFO threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } @@ -4190,7 +4212,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -4228,10 +4250,10 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4243,9 +4265,17 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4265,7 +4295,6 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -4300,10 +4329,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4315,9 +4344,17 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4337,7 +4374,6 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -4422,11 +4458,11 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4438,9 +4474,17 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4460,7 +4504,6 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4472,13 +4515,13 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else @@ -4565,11 +4608,11 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -4581,9 +4624,17 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4603,7 +4654,6 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4615,13 +4665,13 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) { /* Disable the UART RXFT interrupt*/ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; /* Enable the UART Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); } } else diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h index b8f4a235245..f2006d507b4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart.h @@ -1137,10 +1137,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) /** @brief Disable CTS flow control. @@ -1156,10 +1156,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) /** @brief Enable RTS flow control. @@ -1175,10 +1175,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) /** @brief Disable RTS flow control. @@ -1194,10 +1194,10 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c index f942f33315b..ef07235709a 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_uart_ex.c @@ -483,7 +483,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -502,7 +502,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) __HAL_LOCK(huart); /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -890,7 +890,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -969,7 +969,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1031,8 +1031,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c index f855cb614e2..aa7d901d5ce 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart.c @@ -62,8 +62,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_USART_RegisterCallback() to register a user callback. - Function @ref HAL_USART_RegisterCallback() allows to register following callbacks: + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -79,9 +79,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -97,13 +97,13 @@ (+) MspDeInitCallback : USART MspDeInit. [..] - By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback(). + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init() - and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -112,8 +112,8 @@ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit() - or @ref HAL_USART_Init() function. + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c index 59c21845eee..a10093d6d6d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_hal_usart_ex.c @@ -502,8 +502,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c index 05fade2db71..ba94eb11697 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.c @@ -232,18 +232,18 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) * must be disabled. * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC common registers are initialized * - ERROR: ADC common registers are not initialized */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()": */ @@ -256,7 +256,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - common to several ADC */ /* (all ADC instances belonging to the same ADC common instance) */ /* - Set ADC clock (conversion clock) */ - LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); + LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); } else { @@ -270,16 +270,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /** * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) { - /* Set ADC_CommonInitStruct fields to default values */ + /* Set pADC_CommonInitStruct fields to default values */ /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ - ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; } @@ -506,22 +506,22 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); - assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock)); + assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode)); /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ @@ -538,15 +538,15 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) | ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF , - ADC_InitStruct->Resolution - | ADC_InitStruct->DataAlignment - | ADC_InitStruct->LowPowerMode + pADC_InitStruct->Resolution + | pADC_InitStruct->DataAlignment + | pADC_InitStruct->LowPowerMode ); MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE , - ADC_InitStruct->Clock + pADC_InitStruct->Clock ); } else @@ -560,18 +560,18 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /** * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) { - /* Set ADC_InitStruct fields to default values */ + /* Set pADC_InitStruct fields to default values */ /* Set fields of ADC instance */ - ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; - ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; } @@ -610,37 +610,37 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); * Refer to function LL_ADC_SetChannelSamplingTime(); * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * @retval An ErrorStatus enumeration value: * - SUCCESS: ADC registers are initialized * - ERROR: ADC registers are not initialized */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); - assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun)); if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); } if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) - || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) ) { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ - assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) - || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } /* Note: Hardware constraint (refer to description of this function): */ @@ -659,7 +659,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) - || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) ) { /* Case of sequencer mode fixed @@ -674,11 +674,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR1_DMACFG | ADC_CFGR1_OVRMOD , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun + pADC_RegInitStruct->TriggerSource + | pADC_RegInitStruct->SequencerDiscont + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun ); } else @@ -695,18 +695,18 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I | ADC_CFGR1_DMACFG | ADC_CFGR1_OVRMOD , - ADC_REG_InitStruct->TriggerSource + pADC_RegInitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun ); } /* Set ADC group regular sequencer length */ if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) { - LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength); } } else @@ -719,22 +719,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /** * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure * whose fields will be set to default values. * @retval None */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) { - /* Set ADC_REG_InitStruct fields to default values */ + /* Set pADC_RegInitStruct fields to default values */ /* Set fields of ADC group regular */ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; - ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; - ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; + pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h index a5dee265e8c..17de5aa020d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_adc.h @@ -54,14 +54,14 @@ extern "C" { /* Definition of ADC group regular sequencer bits information to be inserted */ /* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ @@ -88,8 +88,8 @@ extern "C" { ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ @@ -101,8 +101,8 @@ extern "C" { /* GPIO pins) and internal channels (connected to internal paths) */ #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ @@ -210,31 +210,31 @@ extern "C" { /* ADC registers bits positions */ -#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */ -#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ -#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ -#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ -#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ -#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ -#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ -#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ -#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ -#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ -#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ -#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ -#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ -#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ -#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ -#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ -#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ -#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ -#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ -#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ -#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ -#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ -#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */ -#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */ -#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ +#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */ +#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */ +#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ /* ADC registers bits groups */ @@ -329,7 +329,6 @@ typedef struct ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). - This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). For more details, refer to description of this function. */ @@ -2318,17 +2317,17 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) + return ((trigger_source + & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN) ); } @@ -2575,21 +2574,21 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) { - __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); - uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; - uint32_t RankIndex; + __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; + uint32_t rank_index; /* Parse register for end of sequence identifier */ - for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U) + for (rank_index = 0UL; rank_index < (32U - 4U); rank_index += 4U) { - if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex)) + if ((channels_ranks & (ADC_CHSELR_SQ2 << rank_index)) == (ADC_CHSELR_SQ2 << rank_index)) { - SequencerLength = (ADC_CHSELR_SQ2 << RankIndex); + sequencer_length = (ADC_CHSELR_SQ2 << rank_index); break; } } - return SequencerLength; + return sequencer_length; } /** @@ -3194,26 +3193,26 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) { - uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); - - return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) + uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) + | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) + | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) + | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) + | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) + | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) + | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) + | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) ); } @@ -3717,55 +3716,55 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if (AnalogWDMonitChannels != 0UL) + if (analog_wd_monit_channels != 0UL) { if (AWDy == LL_ADC_AWD1) { - if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL) + if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ((AnalogWDMonitChannels - | (ADC_AWD_CR23_CHANNEL_MASK) - ) - & (~(ADC_CFGR1_AWD1CH)) - ); + analog_wd_monit_channels = ((analog_wd_monit_channels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR1_AWD1CH)) + ); } else { /* AWD monitoring a single channel */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos)) - ); + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos)) + ); } } else { - if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK - | (ADC_CFGR1_AWD1EN) - ); + analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK + | (ADC_CFGR1_AWD1EN) + ); } else { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) - | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos) - ); + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos) + ); } } } - return AnalogWDMonitChannels; + return analog_wd_monit_channels; } /** @@ -4731,7 +4730,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) /** * @brief Enable interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY + * @rmtoll IER CCRDYIE LL_ADC_EnableIT_CCRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ @@ -4841,7 +4840,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) /** * @brief Disable interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY + * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ @@ -4952,7 +4951,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) /** * @brief Get state of interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY + * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY * @param ADCx ADC instance * @retval State of bit (1 or 0). */ @@ -5068,19 +5067,19 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) /* Initialization of some features of ADC common parameters and multimode */ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h index 4fc39ec8412..8723f1af7e6 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_bus.h @@ -1819,7 +1819,7 @@ __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClockSleep(uint32_t Periphs) * @rmtoll C2AHB2SMENR GPIOASMEN LL_C2_AHB2_GRP1_DisableClockSleep\n * C2AHB2SMENR GPIOBSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n * C2AHB2SMENR GPIOCSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n - * C2AHB2SMENR GPIODSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * C2AHB2SMENR GPIOHSMEN LL_C2_AHB2_GRP1_DisableClockSleep\n * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_C2_AHB2_GRP1_PERIPH_GPIOA diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h index 12765e06e11..300b7bb0ba2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_cortex.h @@ -83,10 +83,9 @@ extern "C" { /** * @} */ - #endif /* CORE_CM0PLUS */ -#if __MPU_PRESENT +#if __MPU_PRESENT /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control * @{ */ @@ -116,9 +115,12 @@ extern "C" { /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size * @{ */ +#if defined(CORE_CM0PLUS) +#else #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#endif #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ @@ -569,7 +571,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) * @param Address Value of region base address * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B + * @arg @ref LL_MPU_REGION_SIZE_32B (*) or @ref LL_MPU_REGION_SIZE_64B (*) or @ref LL_MPU_REGION_SIZE_128B (*) * or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B or @ref LL_MPU_REGION_SIZE_1KB * or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB * or @ref LL_MPU_REGION_SIZE_16KB or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB @@ -586,6 +588,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * (*) value not defined for CM0+ core. * @retval None */ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c index 1e8dd13b25e..43921ec348f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32WLxx_LL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h index d85ec67f57a..92823afbe90 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_i2c.h @@ -69,38 +69,46 @@ typedef struct uint32_t PeripheralMode; /*!< Specifies the peripheral mode. This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). - This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. - This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. - This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ } LL_I2C_InitTypeDef; /** * @} @@ -170,10 +178,11 @@ typedef struct /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ -#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ -#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} */ @@ -208,14 +217,15 @@ typedef struct /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks * @{ */ -#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ /** * @} */ @@ -250,14 +260,21 @@ typedef struct /** @defgroup I2C_LL_EC_MODE Transfer End Mode * @{ */ -#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ -#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ /** * @} */ @@ -265,14 +282,23 @@ typedef struct /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -280,8 +306,10 @@ typedef struct /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ -#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ /** * @} */ @@ -289,8 +317,10 @@ typedef struct /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ /** * @} */ @@ -298,8 +328,10 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ /** * @} */ @@ -307,9 +339,12 @@ typedef struct /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection * @{ */ -#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ -#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ /** * @} */ @@ -353,18 +388,22 @@ typedef struct /** * @brief Configure the SDA setup, hold time and the SCL high, low period. * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) - * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) - * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) - * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -428,7 +467,8 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) * @param AnalogFilter This parameter can be one of the following values: * @arg @ref LL_I2C_ANALOGFILTER_ENABLE * @arg @ref LL_I2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -444,7 +484,8 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt * This filter can only be programmed when the I2C is disabled (PE = 0). * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter * @param I2Cx I2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. * @retval None @@ -664,7 +705,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) /** * @brief Enable Wakeup from STOP. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @note This bit can only be programmed when Digital Filter is disabled. * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop @@ -678,7 +719,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Disable Wakeup from STOP. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop * @param I2Cx I2C Instance. @@ -691,7 +732,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) /** * @brief Check if Wakeup from STOP is enabled or disabled. - * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not * WakeUpFromStop feature is supported by the I2Cx Instance. * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop * @param I2Cx I2C Instance. @@ -941,7 +982,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) /** * @brief Configure peripheral mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n * CR1 SMBDEN LL_I2C_SetMode @@ -960,7 +1001,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n * CR1 SMBDEN LL_I2C_GetMode @@ -978,7 +1019,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -996,7 +1037,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -1014,7 +1055,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -1027,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -1040,7 +1081,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -1053,7 +1094,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1066,7 +1107,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n @@ -1089,7 +1130,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA @@ -1104,7 +1145,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA * @param I2Cx I2C Instance. @@ -1117,7 +1158,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode @@ -1134,7 +1175,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode * @param I2Cx I2C Instance. @@ -1149,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB @@ -1164,7 +1205,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB * @param I2Cx I2C Instance. @@ -1177,7 +1218,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout @@ -1195,7 +1236,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock /** * @brief Disable the SMBus Clock Timeout. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout @@ -1213,7 +1254,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout @@ -1226,7 +1267,8 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc */ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) { - return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1443,7 +1485,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1463,7 +1505,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1645,7 +1687,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1660,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1675,7 +1717,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1782,7 +1824,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1795,7 +1837,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1808,7 +1850,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -1923,7 +1965,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) } /** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. * @note Usage in Slave mode only. * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData * @param I2Cx I2C Instance. @@ -1964,7 +2007,8 @@ __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) /** * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead * @param I2Cx I2C Instance. * @retval None @@ -2125,9 +2169,10 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. * This bit has no effect when RELOAD bit is set. * This bit has no effect in device mode when SBC bit is not set. * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare @@ -2141,7 +2186,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -2154,7 +2199,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h index e3d3093a828..dc43d8f0920 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_iwdg.h @@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) /** * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ @@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h index 493a3f2a41b..013c67dd3e4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_lpuart.h @@ -559,7 +559,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** @@ -594,7 +594,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** @@ -637,8 +637,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ - (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -651,7 +651,7 @@ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint */ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** @@ -663,7 +663,7 @@ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); } /** @@ -686,7 +686,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); } /** @@ -697,7 +697,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); } /** @@ -708,7 +708,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); } /** @@ -719,7 +719,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); } /** @@ -737,7 +737,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) { - MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -854,7 +854,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); } /** @@ -865,7 +865,7 @@ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); } /** @@ -1928,7 +1928,7 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -1942,7 +1942,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -1967,7 +1967,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -1978,7 +1978,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** @@ -1989,7 +1989,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); } /** @@ -2000,7 +2000,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** @@ -2011,7 +2011,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } /** @@ -2026,7 +2026,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** @@ -2037,7 +2037,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** @@ -2048,7 +2048,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } /** @@ -2059,7 +2059,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** @@ -2070,7 +2070,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } /** @@ -2081,7 +2081,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -2095,7 +2095,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -2106,7 +2106,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -2120,7 +2120,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -2131,7 +2131,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); } /** @@ -2142,7 +2142,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); } /** @@ -2153,7 +2153,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); } /** @@ -2164,7 +2164,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); } /** @@ -2179,7 +2179,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); } /** @@ -2190,7 +2190,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); } /** @@ -2201,7 +2201,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); } /** @@ -2212,7 +2212,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); } /** @@ -2223,7 +2223,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); } /** @@ -2391,7 +2391,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** @@ -2402,7 +2402,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); } /** @@ -2424,7 +2424,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) { - SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** @@ -2435,7 +2435,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) { - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c index 313c1f97f04..91efbd2d188 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rcc.c @@ -69,22 +69,22 @@ /** @defgroup RCC_LL_Private_Functions RCC Private functions * @{ */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -uint32_t RCC_PLL_GetFreqDomain_ADC(void); -uint32_t RCC_PLL_GetFreqDomain_RNG(void); -uint32_t RCC_PLL_GetFreqDomain_I2S(void); +static uint32_t RCC_PLL_GetFreqDomain_SYS(void); +static uint32_t RCC_PLL_GetFreqDomain_ADC(void); +static uint32_t RCC_PLL_GetFreqDomain_RNG(void); +static uint32_t RCC_PLL_GetFreqDomain_I2S(void); -uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency); #if defined(DUAL_CORE) -uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency); #endif /* DUAL_CORE */ -uint32_t RCC_GetHCLK3ClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetHCLK3ClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); /** * @} */ @@ -778,7 +778,7 @@ uint32_t LL_RCC_GetRTCClockFreq(void) * @brief Return SYSTEM clock (SYSCLK) frequency * @retval SYSTEM clock frequency (in Hz) */ -uint32_t RCC_GetSystemClockFreq(void) +static uint32_t RCC_GetSystemClockFreq(void) { uint32_t frequency; @@ -828,7 +828,7 @@ uint32_t RCC_GetSystemClockFreq(void) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK1 clock frequency (in Hz) */ -uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK1_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); @@ -840,7 +840,7 @@ uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK2 clock frequency (in Hz) */ -uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK2_FREQ(SYSCLK_Frequency, LL_C2_RCC_GetAHBPrescaler()); @@ -852,7 +852,7 @@ uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK3 clock frequency (in Hz) */ -uint32_t RCC_GetHCLK3ClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLK3ClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK3_FREQ(SYSCLK_Frequency, LL_RCC_GetAHB3Prescaler()); @@ -863,7 +863,7 @@ uint32_t RCC_GetHCLK3ClockFreq(uint32_t SYSCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK1 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) { /* PCLK1 clock frequency */ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); @@ -874,7 +874,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK2 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) { /* PCLK2 clock frequency */ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); @@ -884,7 +884,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) * @brief Return PLL clock (PLLRCLK) frequency used for system domain * @retval PLLRCLK clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) +static uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -934,7 +934,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) * @brief Return PLL clock (PLLPCLK) frequency used for ADC domain * @retval PLLPCLK clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_ADC(void) +static uint32_t RCC_PLL_GetFreqDomain_ADC(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -982,7 +982,7 @@ uint32_t RCC_PLL_GetFreqDomain_ADC(void) * @brief Return PLL clock (PLLQCLK) frequency used for RNG domain * @retval PLLQCLK clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_RNG(void) +static uint32_t RCC_PLL_GetFreqDomain_RNG(void) { uint32_t pllinputfreq; uint32_t pllsource; @@ -1030,7 +1030,7 @@ uint32_t RCC_PLL_GetFreqDomain_RNG(void) * @brief Return PLL clock (PLLQCLK) frequency used for I2S domain * @retval PLLQCLK clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_I2S(void) +static uint32_t RCC_PLL_GetFreqDomain_I2S(void) { uint32_t pllinputfreq; uint32_t pllsource; diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c index 57d10fc6aae..6ef53964e21 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rng.c @@ -42,7 +42,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup RNG_LL_Private_Macros +/** @defgroup RNG_LL_Private_Macros RNG Private Macros * @{ */ #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c index 1e85f481879..b80c475b601 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_rtc.c @@ -343,7 +343,7 @@ ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Time } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) @@ -431,7 +431,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c index c39fdfcb2b3..3478ef6633c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.c @@ -221,6 +221,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) SPI_CR2_DS | SPI_CR2_SSOE, SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + } + /*---------------------------- SPIx CRCPR Configuration ---------------------- * Configure SPIx CRCPR with parameters: * - CRCPoly: CRCPOLY[15:0] bits diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h index 0765aedd861..3e04ef1a224 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_spi.h @@ -1333,7 +1333,7 @@ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) { - return (uint8_t)(READ_REG(SPIx->DR)); + return (*((__IO uint8_t *)&SPIx->DR)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h index 1aefeb77e90..649049acfd4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_tim.h @@ -598,8 +598,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -1515,7 +1515,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo */ __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c index b5f8ce148a6..4f1a4583a02 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.c @@ -66,9 +66,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -252,9 +249,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } /*---------------------------- USART PRESC Configuration ----------------------- @@ -312,37 +306,25 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); - - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); } /* Else (USART not in Disabled state => return ERROR */ else diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h index de04ac3e1d1..830b0ad9e55 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/STM32WLxx_HAL_Driver/stm32wlxx_ll_usart.h @@ -88,41 +88,49 @@ typedef struct uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref USART_LL_EC_PRESCALER. - This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ } LL_USART_InitTypeDef; @@ -141,20 +149,23 @@ typedef struct uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_LL_EC_POLARITY. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). For more details, refer to description of this function. */ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_LL_EC_PHASE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). For more details, refer to description of this function. */ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function. */ } LL_USART_ClockInitTypeDef; @@ -699,7 +710,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); } /** @@ -738,7 +749,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); } /** @@ -785,7 +796,8 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, + (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -800,7 +812,7 @@ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32 */ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_UESM); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); } /** @@ -814,7 +826,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); } /** @@ -838,7 +850,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -849,7 +861,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -860,7 +872,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -871,7 +883,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -889,7 +901,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) { - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -1008,7 +1020,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_MME); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); } /** @@ -1019,7 +1031,7 @@ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_MME); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); } /** @@ -1870,6 +1882,10 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph { /* Do not overstep the size of USART_PRESCALER_TAB */ } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } else if (OverSampling == LL_USART_OVERSAMPLING_8) { usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); @@ -3434,7 +3450,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -3450,7 +3466,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -3461,7 +3477,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -3477,7 +3493,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -3488,7 +3504,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -3499,7 +3515,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_CMIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); } /** @@ -3510,7 +3526,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RTOIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); } /** @@ -3523,7 +3539,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_EOBIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); } /** @@ -3536,7 +3552,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); } /** @@ -3547,7 +3563,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); } /** @@ -3575,7 +3591,7 @@ __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -3588,7 +3604,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -3601,7 +3617,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_WUFIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); } /** @@ -3614,7 +3630,7 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); } /** @@ -3627,7 +3643,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } /** @@ -3640,7 +3656,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); } /** @@ -3651,7 +3667,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /* Legacy define */ @@ -3667,7 +3683,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); } /** @@ -3678,7 +3694,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } /* Legacy define */ @@ -3694,7 +3710,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); } /** @@ -3705,7 +3721,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -3716,7 +3732,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); } /** @@ -3727,7 +3743,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); } /** @@ -3740,7 +3756,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); } /** @@ -3753,7 +3769,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); } /** @@ -3766,7 +3782,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); } /** @@ -3794,7 +3810,7 @@ __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -3807,7 +3823,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -3820,7 +3836,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); } /** @@ -3833,7 +3849,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); } /** @@ -3846,7 +3862,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); } /** @@ -3859,7 +3875,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); } /** @@ -4093,7 +4109,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -4104,7 +4120,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -4126,7 +4142,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -4137,7 +4153,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); } /** diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h index 82170f12fe5..d10d8aa0b0e 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h @@ -69,25 +69,63 @@ /** * @brief This is the list of modules where register callback can be used */ +#if !defined (USE_HAL_ADC_REGISTER_CALLBACKS) #define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_COMP_REGISTER_CALLBACKS) #define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS) #define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_DAC_REGISTER_CALLBACKS) #define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_I2C_REGISTER_CALLBACKS) #define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_I2S_REGISTER_CALLBACKS) #define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS) #define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS) #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_PKA_REGISTER_CALLBACKS) #define USE_HAL_PKA_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_RNG_REGISTER_CALLBACKS) #define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_RTC_REGISTER_CALLBACKS) #define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_SPI_REGISTER_CALLBACKS) #define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_SUBGHZ_REGISTER_CALLBACKS) #define USE_HAL_SUBGHZ_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_TIM_REGISTER_CALLBACKS) #define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_UART_REGISTER_CALLBACKS) #define USE_HAL_UART_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_USART_REGISTER_CALLBACKS) #define USE_HAL_USART_REGISTER_CALLBACKS 0u +#endif +#if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS) #define USE_HAL_WWDG_REGISTER_CALLBACKS 0u +#endif /* ########################## Oscillator Values adaptation ####################*/ /** @@ -183,7 +221,9 @@ /* ################## CRYP peripheral configuration ########################## */ +#if !defined (USE_HAL_CRYP_SUSPEND_RESUME) #define USE_HAL_CRYP_SUSPEND_RESUME 1U +#endif /* Includes ------------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c index 06134172f62..745619ea3e4 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c +++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c @@ -4,6 +4,17 @@ * @author MCD Application Team * @brief CMSIS Cortex Device Peripheral Access Layer System Source File * + ****************************************************************************** + * @attention + * + * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** * This file provides two functions and one global variable to be called from * user application: * - SystemInit(): This function is called at startup just after reset and @@ -57,18 +68,6 @@ * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 - * - ****************************************************************************** */ /** @addtogroup CMSIS @@ -138,8 +137,7 @@ #define VECT_TAB_OFFSET 0x00008000U /*!< Vector Table base offset field. This value must be a multiple of 0x100. */ #else -#include "nvic_addr.h" // MBED - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x100. */ #define VECT_TAB_OFFSET 0x00020000U /*!< Vector Table base offset field. This value must be a multiple of 0x100. */ @@ -154,8 +152,7 @@ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #else -#include "nvic_addr.h" // MBED - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -211,11 +208,12 @@ * @param None * @retval None */ -void SystemInit(void) +__WEAK void SystemInit(void) { +#include "nvic_addr.h" // MBED + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED #if defined(USER_VECT_TAB_ADDRESS) /* Configure the Vector Table location add offset address ------------------*/ - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; #endif /* FPU settings ------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/CMakeLists.txt new file mode 100644 index 00000000000..2afb1ebf770 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wl54xc.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wl54xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wl54xc.sct) +endif() + +add_library(mbed-stm32wl54xc INTERFACE) + +target_include_directories(mbed-stm32wl54xc + INTERFACE + . +) + +target_sources(mbed-stm32wl54xc + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32wl54xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wl54xc INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S index 8e5c4c7bd00..9c73e12f39b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/startup_stm32wl54xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S index 522022f27bc..6f7d6c2542b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S index 39d1eb27881..3c5af0fbfff 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_IAR/startup_stm32wl54xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h index a18342e7d4a..dd7de71408c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x40000 // 256 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0x10000 // 64 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt index c2316f419eb..b4fd9aabffd 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/CMakeLists.txt @@ -13,14 +13,14 @@ endif() add_library(mbed-stm32wl55xc INTERFACE) -target_sources(mbed-stm32wl55xc +target_include_directories(mbed-stm32wl55xc INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32wl55xc +target_sources(mbed-stm32wl55xc INTERFACE - . + ${STARTUP_FILE} ) mbed_set_linker_script(mbed-stm32wl55xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S index 95c90b54b5f..5ad897f0478 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/startup_stm32wl55xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S index 350c3dab5a3..e93d3a46405 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_GCC_ARM/startup_stm32wl55xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S index 1431e7f3075..658ca8e559d 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_IAR/startup_stm32wl55xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h index c5ec327d699..dd7de71408c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x40000 +#define MBED_ROM_SIZE 0x40000 // 256 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x10000 +#define MBED_RAM_SIZE 0x10000 // 64 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/CMakeLists.txt new file mode 100644 index 00000000000..31a63cf52ae --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle4x8.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle4xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wle4x8.sct) +endif() + +add_library(mbed-stm32wle4x8 INTERFACE) + +target_include_directories(mbed-stm32wle4x8 + INTERFACE + . +) + +target_sources(mbed-stm32wle4x8 + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32wle4x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wle4x8 INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S index 002a57473a2..e92914ce599 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/startup_stm32wle4xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S index c919abb4fd9..3b46de6b6fa 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S index 0072684fb7d..378328d121b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_IAR/startup_stm32wle4xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h index a18342e7d4a..9407c41f6a7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x10000 // 64 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0x5000 // 20 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/CMakeLists.txt new file mode 100644 index 00000000000..dd127f4d032 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle4xb.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle4xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wle4xb.sct) +endif() + +add_library(mbed-stm32wle4xb INTERFACE) + +target_include_directories(mbed-stm32wle4xb + INTERFACE + . +) + +target_sources(mbed-stm32wle4xb + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32wle4xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wle4xb INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S index 002a57473a2..e92914ce599 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/startup_stm32wle4xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S index c919abb4fd9..3b46de6b6fa 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S index 0072684fb7d..378328d121b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_IAR/startup_stm32wle4xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h index a18342e7d4a..7f3b390a437 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x20000 // 128 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0xC000 // 48 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/CMakeLists.txt new file mode 100644 index 00000000000..1388309f85b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle4xc.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle4xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wle4xc.sct) +endif() + +add_library(mbed-stm32wle4xc INTERFACE) + +target_include_directories(mbed-stm32wle4xc + INTERFACE + . +) + +target_sources(mbed-stm32wle4xc + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32wle4xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wle4xc INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S index 002a57473a2..e92914ce599 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/startup_stm32wle4xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S index c919abb4fd9..3b46de6b6fa 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S index 0072684fb7d..378328d121b 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_IAR/startup_stm32wle4xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h index a18342e7d4a..dd7de71408c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x40000 // 256 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0x10000 // 64 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/CMakeLists.txt new file mode 100644 index 00000000000..b3aafa52c78 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5x8.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wle5x8.sct) +endif() + +add_library(mbed-stm32wle5x8 INTERFACE) + +target_include_directories(mbed-stm32wle5x8 + INTERFACE + . +) + +target_sources(mbed-stm32wle5x8 + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32wle5x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wle5x8 INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S index 29f645e6c84..af8290137e3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/startup_stm32wle5xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S index 69a5b330bb3..17eb3cbe214 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S index 341ee9eaf5b..d8367da1ed9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_IAR/startup_stm32wle5xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h index a18342e7d4a..9407c41f6a7 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x10000 // 64 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0x5000 // 20 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/CMakeLists.txt new file mode 100644 index 00000000000..40091927502 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S) + set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5xb.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S) + set(LINKER_FILE TOOLCHAIN_ARM/stm32wle5xb.sct) +endif() + +add_library(mbed-stm32wle5xb INTERFACE) + +target_include_directories(mbed-stm32wle5xb + INTERFACE + . +) + +target_sources(mbed-stm32wle5xb + INTERFACE + ${STARTUP_FILE} +) + +mbed_set_linker_script(mbed-stm32wle5xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +target_link_libraries(mbed-stm32wle5xb INTERFACE mbed-stm32wl) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S index 29f645e6c84..af8290137e3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/startup_stm32wle5xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S index 69a5b330bb3..17eb3cbe214 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S index 341ee9eaf5b..d8367da1ed9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_IAR/startup_stm32wle5xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h index a18342e7d4a..7f3b390a437 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x20000 // 128 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0xC000 // 48 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt index e080aafd286..2faf76b2c61 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt @@ -11,14 +11,14 @@ endif() add_library(mbed-stm32wle5xc INTERFACE) -target_sources(mbed-stm32wle5xc +target_include_directories(mbed-stm32wle5xc INTERFACE - ${STARTUP_FILE} + . ) -target_include_directories(mbed-stm32wle5xc +target_sources(mbed-stm32wle5xc INTERFACE - . + ${STARTUP_FILE} ) mbed_set_linker_script(mbed-stm32wle5xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S index 29f645e6c84..af8290137e3 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/startup_stm32wle5xx.S @@ -14,12 +14,12 @@ ;****************************************************************************** ;* @attention ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ;* ;****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct index 9258e6a699b..7aff08bc288 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct @@ -1,4 +1,4 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4 +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 ; Scatter-Loading Description File ; ; SPDX-License-Identifier: BSD-3-Clause diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S index 69a5b330bb3..17eb3cbe214 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S @@ -14,13 +14,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020(-2021) STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S index 341ee9eaf5b..d8367da1ed9 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_IAR/startup_stm32wle5xx.S @@ -15,12 +15,12 @@ ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* -;* Copyright (c) 2020 STMicroelectronics. All rights reserved. +;* Copyright (c) 2020(2021) STMicroelectronics. +;* All rights reserved. ;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. ; ;******************************************************************************* ; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h index a18342e7d4a..dd7de71408c 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h @@ -22,7 +22,7 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +#define MBED_ROM_SIZE 0x40000 // 256 KB #endif #if !defined(MBED_RAM_START) @@ -30,7 +30,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0x10000 // 64 KB #endif #define NVIC_NUM_VECTORS 78 diff --git a/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c b/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c index d4c022b3b55..10c30ec2391 100755 --- a/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c +++ b/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c @@ -47,7 +47,7 @@ uint32_t i2c_get_pclk(I2CName i2c) } } #if defined I2C2_BASE - if (i2c == I2C_2) { + else if (i2c == I2C_2) { clocksource = __HAL_RCC_GET_I2C2_SOURCE(); switch (clocksource) { case RCC_I2C2CLKSOURCE_PCLK1: diff --git a/targets/TARGET_STM/TARGET_STM32WL/objects.h b/targets/TARGET_STM/TARGET_STM32WL/objects.h index 66f06eab289..a8fd7b93d32 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/objects.h +++ b/targets/TARGET_STM/TARGET_STM32WL/objects.h @@ -106,8 +106,8 @@ struct i2c_s { volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; uint8_t *slave_rx_buffer; - volatile uint8_t slave_rx_buffer_size; - volatile uint8_t slave_rx_count; + volatile uint16_t slave_rx_buffer_size; + volatile uint16_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32WL/serial_device.c b/targets/TARGET_STM/TARGET_STM32WL/serial_device.c index ed6023fc46e..85569478ed1 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32WL/serial_device.c @@ -19,7 +19,7 @@ #define UART_NUM (3) -uint32_t serial_irq_ids[UART_NUM] = {0}; +uintptr_t serial_irq_contexts[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; static uart_irq_handler irq_handler; @@ -37,15 +37,15 @@ static void uart_irq(UARTName uart_name) if (id >= 0) { UART_HandleTypeDef *huart = &uart_handlers[id]; - if (serial_irq_ids[id] != 0) { + if (serial_irq_contexts[id] != 0) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TXE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_TXE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE)) { - irq_handler(serial_irq_ids[id], TxIrq); + irq_handler(serial_irq_contexts[id], TxIrq); } } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_RXNE) != RESET && __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE)) { - irq_handler(serial_irq_ids[id], RxIrq); + irq_handler(serial_irq_contexts[id], RxIrq); /* Flag has been cleared when reading the content */ } } @@ -65,6 +65,13 @@ static void uart1_irq(void) } #endif +#if defined(USART2_BASE) +static void uart2_irq(void) +{ + uart_irq(UART_2); +} +#endif + #if defined(LPUART1_BASE) static void lpuart1_irq(void) { @@ -72,12 +79,12 @@ static void lpuart1_irq(void) } #endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *obj_s = SERIAL_S(obj); irq_handler = handler; - serial_irq_ids[obj_s->index] = id; + serial_irq_contexts[obj_s->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -94,6 +101,12 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&uart1_irq; break; #endif +#if defined(USART2_BASE) + case UART_2: + irq_n = USART2_IRQn; + vector = (uint32_t)&uart2_irq; + break; +#endif #if defined(LPUART1_BASE) case LPUART_1: irq_n = LPUART1_IRQn; @@ -272,6 +285,11 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) irq_n = USART1_IRQn; break; #endif +#if defined(USART2_BASE) + case UART_2: + irq_n = USART2_IRQn; + break; +#endif #if defined(LPUART1_BASE) case LPUART_1: irq_n = LPUART1_IRQn; diff --git a/targets/TARGET_STM/USBPhyHw.h b/targets/TARGET_STM/USBPhyHw.h index fc3f8c64a6c..3bce84f633e 100644 --- a/targets/TARGET_STM/USBPhyHw.h +++ b/targets/TARGET_STM/USBPhyHw.h @@ -43,8 +43,10 @@ #if MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG -#if defined(TARGET_STM32F1) || defined(TARGET_STM32F3) || defined(TARGET_STM32L1) || defined(TARGET_STM32WB) || defined(TARGET_STM32G4) +#if defined(TARGET_STM32F1) || defined(TARGET_STM32L1) || defined(TARGET_STM32WB) || defined(TARGET_STM32G4) #define USBHAL_IRQn USB_LP_IRQn +#elif defined(TARGET_STM32F3) +#define USBHAL_IRQn USB_LP_CAN_RX0_IRQn #elif defined(TARGET_STM32L5) #define USBHAL_IRQn USB_FS_IRQn #else diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index 7f0c8d31420..c45150de4b2 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -192,9 +192,9 @@ USBPhyHw::~USBPhyHw() } -#if defined(TARGET_STM32F1) || defined(SYSCFG_PMC_USB_PU) +#if defined(TARGET_STM32F1) || defined(TARGET_STM32F3) || defined(SYSCFG_PMC_USB_PU) -#include "drivers/DigitalOut.h" +#include "drivers/DigitalInOut.h" void USB_reenumerate() { @@ -203,10 +203,16 @@ void USB_reenumerate() LL_SYSCFG_DisableUSBPullUp(); wait_us(10000); // 10ms LL_SYSCFG_EnableUSBPullUp(); +#elif defined(USB_PULLUP_CONTROL) + mbed::DigitalInOut usb_dp_pin(USB_PULLUP_CONTROL, PIN_OUTPUT, PullNone, 0); + wait_us(1000); + usb_dp_pin = 1; + wait_us(1000); #else // Force USB_DP pin (with external pull up) to 0 - mbed::DigitalOut usb_dp_pin(USB_DP, 0) ; + mbed::DigitalInOut usb_dp_pin(USB_DP, PIN_OUTPUT, PullNone, 0); wait_us(10000); // 10ms + usb_dp_pin.input(); // revert as input #endif } #endif @@ -295,7 +301,7 @@ void USBPhyHw::init(USBPhyEvents *events) map = PinMap_USB_FS; -#if defined(TARGET_STM32F1) || defined(SYSCFG_PMC_USB_PU) +#if defined(TARGET_STM32F1) || defined(TARGET_STM32F3) || defined(SYSCFG_PMC_USB_PU) // USB_DevConnect is empty USB_reenumerate(); #endif @@ -418,7 +424,7 @@ void USBPhyHw::connect() // Initializes the USB controller registers USB_DevInit(hpcd.Instance, hpcd.Init); // hpcd.Init not used -#if defined(TARGET_STM32F1) || defined(SYSCFG_PMC_USB_PU) +#if defined(TARGET_STM32F1) || defined(TARGET_STM32F3) || defined(SYSCFG_PMC_USB_PU) // USB_DevConnect is empty USB_reenumerate(); #endif diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index e1468abfd8d..a2f34a96df7 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -24,7 +24,7 @@ #include "PeripheralPins.h" #include "mbed_error.h" -static uint32_t can_irq_ids[2] = {0}; +static uintptr_t can_irq_contexts[2] = {0}; static can_irq_handler irq_handler; /** Call all the init functions @@ -68,7 +68,11 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz { MBED_ASSERT((int)pinmap->peripheral != NC); +#if defined(__HAL_RCC_FDCAN1_CLK_ENABLE) + __HAL_RCC_FDCAN1_CLK_ENABLE(); +#else __HAL_RCC_FDCAN_CLK_ENABLE(); +#endif if (pinmap->peripheral == CAN_1) { obj->index = 0; @@ -90,8 +94,13 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz // Select PLL1Q as source of FDCAN clock RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; +#if (defined RCC_PERIPHCLK_FDCAN1) + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN1; + RCC_PeriphClkInit.Fdcan1ClockSelection = RCC_FDCAN1CLKSOURCE_PLL1; +#else RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; - RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80) + RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; +#endif #if defined(DUAL_CORE) && (TARGET_STM32H7) while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } @@ -128,17 +137,21 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz // !Attention Not all bitrates can be covered with all fdcan-core-clk values. When a clk // does not work for the desired bitrate, change system_clock settings for FDCAN_CLK // (default FDCAN_CLK is PLLQ) -#ifdef TARGET_STM32G4 - int ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN) / hz; -#else +#if (defined TARGET_STM32H7) // STM32H7 doesn't support yet HAL_RCCEx_GetPeriphCLKFreq for FDCAN // We use PLL1.Q clock right now so get its frequency PLL1_ClocksTypeDef pll1_clocks; HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - int ntq = pll1_clocks.PLL1_Q_Frequency / hz; + uint32_t ntq = pll1_clocks.PLL1_Q_Frequency / (uint32_t)hz; +#else +#if (defined RCC_PERIPHCLK_FDCAN1) + uint32_t ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN1) / (uint32_t)hz; +#else + uint32_t ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN) / (uint32_t)hz; +#endif #endif - int nominalPrescaler = 1; + uint32_t nominalPrescaler = 1; // !When the sample point should be lower than 50%, this must be changed to // !IS_FDCAN_NOMINAL_TSEG2(ntq/nominalPrescaler), since // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% @@ -222,10 +235,10 @@ void can_init(can_t *obj, PinName rd, PinName td) can_init_freq(obj, rd, td, 100000); } -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_handler = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; } void can_irq_free(can_t *obj) @@ -250,10 +263,10 @@ void can_irq_free(can_t *obj) else { return; } -#ifndef TARGET_STM32G4 +#if (defined TARGET_STM32H7) HAL_NVIC_DisableIRQ(FDCAN_CAL_IRQn); #endif - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; } void can_free(can_t *obj) @@ -262,12 +275,21 @@ void can_free(can_t *obj) while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) { } #endif /* DUAL_CORE */ +#if defined(__HAL_RCC_FDCAN1_FORCE_RESET) + __HAL_RCC_FDCAN1_FORCE_RESET(); + __HAL_RCC_FDCAN1_RELEASE_RESET(); +#else __HAL_RCC_FDCAN_FORCE_RESET(); __HAL_RCC_FDCAN_RELEASE_RESET(); +#endif #if defined(DUAL_CORE) && (TARGET_STM32H7) LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); #endif /* DUAL_CORE */ +#if defined(__HAL_RCC_FDCAN1_CLK_DISABLE) + __HAL_RCC_FDCAN1_CLK_DISABLE(); +#else __HAL_RCC_FDCAN_CLK_DISABLE(); +#endif } @@ -296,16 +318,20 @@ int can_frequency(can_t *obj, int f) * does not work for the desired bitrate, change system_clock settings for FDCAN_CLK * (default FDCAN_CLK is PLLQ) */ -#ifdef TARGET_STM32G4 - int ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN) / f; -#else +#if (defined TARGET_STM32H7) // STM32H7 doesn't support yet HAL_RCCEx_GetPeriphCLKFreq for FDCAN PLL1_ClocksTypeDef pll1_clocks; HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - int ntq = pll1_clocks.PLL1_Q_Frequency / f; + uint32_t ntq = pll1_clocks.PLL1_Q_Frequency / (uint32_t)f; +#else +#if (defined RCC_PERIPHCLK_FDCAN1) + uint32_t ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN1) / (uint32_t)f; +#else + uint32_t ntq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_FDCAN) / (uint32_t)f; +#endif #endif - int nominalPrescaler = 1; + uint32_t nominalPrescaler = 1; // !When the sample point should be lower than 50%, this must be changed to // !IS_FDCAN_DATA_TSEG2(ntq/nominalPrescaler), since // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% @@ -517,42 +543,42 @@ static void can_irq(CANName name, int id) if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_TX_COMPLETE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_FLAG_TX_COMPLETE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_FLAG_TX_COMPLETE); - irq_handler(can_irq_ids[id], IRQ_TX); + irq_handler(can_irq_contexts[id], IRQ_TX); } } -#ifndef TARGET_STM32G4 +#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_BUFFER_NEW_MESSAGE); - irq_handler(can_irq_ids[id], IRQ_RX); + irq_handler(can_irq_contexts[id], IRQ_RX); } } #else if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE); - irq_handler(can_irq_ids[id], IRQ_RX); + irq_handler(can_irq_contexts[id], IRQ_RX); } } #endif if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_ERROR_WARNING)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_FLAG_ERROR_WARNING)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_FLAG_ERROR_WARNING); - irq_handler(can_irq_ids[id], IRQ_ERROR); + irq_handler(can_irq_contexts[id], IRQ_ERROR); } } if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_ERROR_PASSIVE)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_FLAG_ERROR_PASSIVE)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_FLAG_ERROR_PASSIVE); - irq_handler(can_irq_ids[id], IRQ_PASSIVE); + irq_handler(can_irq_contexts[id], IRQ_PASSIVE); } } if (__HAL_FDCAN_GET_IT_SOURCE(&CanHandle, FDCAN_IT_BUS_OFF)) { if (__HAL_FDCAN_GET_FLAG(&CanHandle, FDCAN_FLAG_BUS_OFF)) { __HAL_FDCAN_CLEAR_FLAG(&CanHandle, FDCAN_FLAG_BUS_OFF); - irq_handler(can_irq_ids[id], IRQ_BUS); + irq_handler(can_irq_contexts[id], IRQ_BUS); } } } @@ -602,7 +628,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) interrupts = FDCAN_IT_TX_COMPLETE; break; case IRQ_RX: -#ifndef TARGET_STM32G4 +#if (defined FDCAN_IT_RX_BUFFER_NEW_MESSAGE) interrupts = FDCAN_IT_RX_BUFFER_NEW_MESSAGE; #else interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE; @@ -666,7 +692,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) #define DEFAULT_RXFIFO 0 // default rx fifo for can by hardware is FIFO0 -static uint32_t can_irq_ids[CAN_NUM] = {0}; +static uint32_t can_irq_contexts[CAN_NUM] = {0}; static can_irq_handler irq_handler; static void can_registers_init(can_t *obj) @@ -774,10 +800,10 @@ void can_init(can_t *obj, PinName rd, PinName td) can_init_freq(obj, rd, td, 100000); } -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { irq_handler = handler; - can_irq_ids[obj->index] = id; + can_irq_contexts[obj->index] = context; obj->rxIrqEnabled = false; } @@ -787,7 +813,7 @@ void can_irq_free(can_t *obj) can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \ CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF); - can_irq_ids[obj->index] = 0; + can_irq_contexts[obj->index] = 0; obj->rxIrqEnabled = false; } @@ -1177,7 +1203,7 @@ static void can_irq(CANName name, int id) __HAL_CAN_CLEAR_FLAG(&CanHandle, CAN_FLAG_RQCP2); } if (tmp1 || tmp2 || tmp3) { - irq_handler(can_irq_ids[id], IRQ_TX); + irq_handler(can_irq_contexts[id], IRQ_TX); } } @@ -1191,7 +1217,7 @@ static void can_irq(CANName name, int id) __HAL_CAN_DISABLE_IT(&CanHandle, CAN_IT_FMP0); if ((tmp1 != 0) && tmp2) { - irq_handler(can_irq_ids[id], IRQ_RX); + irq_handler(can_irq_contexts[id], IRQ_RX); } tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_EPV); @@ -1199,19 +1225,19 @@ static void can_irq(CANName name, int id) tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR); if (tmp1 && tmp2 && tmp3) { - irq_handler(can_irq_ids[id], IRQ_PASSIVE); + irq_handler(can_irq_contexts[id], IRQ_PASSIVE); } tmp1 = __HAL_CAN_GET_FLAG(&CanHandle, CAN_FLAG_BOF); tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_BOF); tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR); if (tmp1 && tmp2 && tmp3) { - irq_handler(can_irq_ids[id], IRQ_BUS); + irq_handler(can_irq_contexts[id], IRQ_BUS); } tmp3 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_ERR); if (tmp1 && tmp2 && tmp3) { - irq_handler(can_irq_ids[id], IRQ_ERROR); + irq_handler(can_irq_contexts[id], IRQ_ERROR); } } diff --git a/targets/TARGET_STM/gpio_irq_api.c b/targets/TARGET_STM/gpio_irq_api.c index 0536843afd6..3afd4df9bee 100644 --- a/targets/TARGET_STM/gpio_irq_api.c +++ b/targets/TARGET_STM/gpio_irq_api.c @@ -47,7 +47,7 @@ typedef struct gpio_channel { uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts - uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance + uintptr_t channel_contexts[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance GPIO_TypeDef *channel_gpio[MAX_PIN_LINE]; // base address of gpio port group uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group } gpio_channel_t; @@ -124,12 +124,12 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) if (LL_EXTI_IsActiveRisingFlag_0_31(pin) != RESET) { LL_EXTI_ClearRisingFlag_0_31(pin); - if (gpio_channel->channel_ids[gpio_idx] == 0) { + if (gpio_channel->channel_contexts[gpio_idx] == 0) { continue; } gpio_irq_event event = IRQ_RISE; - irq_handler(gpio_channel->channel_ids[gpio_idx], event); + irq_handler(gpio_channel->channel_contexts[gpio_idx], event); return; } @@ -137,12 +137,12 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) if (LL_EXTI_IsActiveFallingFlag_0_31(pin) != RESET) { LL_EXTI_ClearFallingFlag_0_31(pin); - if (gpio_channel->channel_ids[gpio_idx] == 0) { + if (gpio_channel->channel_contexts[gpio_idx] == 0) { continue; } gpio_irq_event event = IRQ_FALL; - irq_handler(gpio_channel->channel_ids[gpio_idx], event); + irq_handler(gpio_channel->channel_contexts[gpio_idx], event); return; } @@ -157,7 +157,7 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { __HAL_GPIO_EXTI_CLEAR_FLAG(pin); #endif - if (gpio_channel->channel_ids[gpio_idx] == 0) { + if (gpio_channel->channel_contexts[gpio_idx] == 0) { continue; } @@ -183,7 +183,7 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) } } - irq_handler(gpio_channel->channel_ids[gpio_idx], event); + irq_handler(gpio_channel->channel_contexts[gpio_idx], event); return; } @@ -310,7 +310,7 @@ static void gpio_irq15(void) extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx); extern void pin_function_gpiomode(PinName pin, uint32_t gpiomode); -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { uint32_t vector = 0; uint32_t irq_index; @@ -438,7 +438,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 gpio_channel = &channels[irq_index]; gpio_idx = pin_lines_desc[pin_index].gpio_idx; gpio_channel->pin_mask |= (1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = id; + gpio_channel->channel_contexts[gpio_idx] = context; gpio_channel->channel_gpio[gpio_idx] = gpio_add; gpio_channel->channel_pin[gpio_idx] = pin_index; @@ -462,7 +462,7 @@ void gpio_irq_free(gpio_irq_t *obj) gpio_irq_disable(obj); gpio_channel->pin_mask &= ~(1 << gpio_idx); - gpio_channel->channel_ids[gpio_idx] = 0; + gpio_channel->channel_contexts[gpio_idx] = 0; gpio_channel->channel_gpio[gpio_idx] = 0; gpio_channel->channel_pin[gpio_idx] = 0; diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 5c1d8f1af59..d83292a60af 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -242,7 +242,15 @@ static void i2c4_irq(void) HAL_I2C_ER_IRQHandler(handle); } #endif -#if defined(FMPI2C1_BASE) +#if defined(I2C5_BASE) // STM32H7 +static void i2c5_irq(void) +{ + I2C_HandleTypeDef *handle = i2c_handles[4]; + HAL_I2C_EV_IRQHandler(handle); + HAL_I2C_ER_IRQHandler(handle); +} +#endif +#if defined(FMPI2C1_BASE) // STM32F4 static void i2c5_irq(void) { I2C_HandleTypeDef *handle = i2c_handles[4]; @@ -316,6 +324,11 @@ uint32_t i2c_get_irq_handler(i2c_t *obj) handler = (uint32_t)&i2c4_irq; break; #endif +#if defined(I2C5_BASE) + case 4: + handler = (uint32_t)&i2c5_irq; + break; +#endif #if defined(FMPI2C1_BASE) case 4: handler = (uint32_t)&i2c5_irq; @@ -366,6 +379,12 @@ void i2c_hw_reset(i2c_t *obj) __HAL_RCC_I2C4_RELEASE_RESET(); } #endif +#if defined I2C5_BASE + if (obj_s->i2c == I2C_5) { + __HAL_RCC_I2C5_FORCE_RESET(); + __HAL_RCC_I2C5_RELEASE_RESET(); + } +#endif #if defined FMPI2C1_BASE if (obj_s->i2c == FMPI2C_1) { __HAL_RCC_FMPI2C1_FORCE_RESET(); @@ -456,7 +475,7 @@ void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap) } #endif #if defined I2C4_BASE - // Enable I2C3 clock and pinout if not done + // Enable I2C4 clock and pinout if not done if (obj_s->i2c == I2C_4) { obj_s->index = 3; __HAL_RCC_I2C4_CLK_ENABLE(); @@ -464,6 +483,15 @@ void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap) obj_s->error_i2cIRQ = I2C4_ER_IRQn; } #endif +#if defined I2C5_BASE + // Enable I2C5 clock and pinout if not done + if (obj_s->i2c == I2C_5) { + obj_s->index = 4; + __HAL_RCC_I2C5_CLK_ENABLE(); + obj_s->event_i2cIRQ = I2C5_EV_IRQn; + obj_s->error_i2cIRQ = I2C5_ER_IRQn; + } +#endif #if defined FMPI2C1_BASE // Enable I2C3 clock and pinout if not done if (obj_s->i2c == FMPI2C_1) { @@ -548,6 +576,11 @@ void i2c_deinit_internal(i2c_t *obj) __HAL_RCC_I2C4_CLK_DISABLE(); } #endif +#if defined I2C5_BASE + if (obj_s->i2c == I2C_5) { + __HAL_RCC_I2C5_CLK_DISABLE(); + } +#endif #if defined FMPI2C1_BASE if (obj_s->i2c == FMPI2C_1) { __HAL_RCC_FMPI2C1_CLK_DISABLE(); @@ -638,6 +671,13 @@ void i2c_frequency(i2c_t *obj, int hz) HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C4); } #endif +#endif +#if defined(I2C5_BASE) && defined (I2C_FASTMODEPLUS_I2C5) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip +#if defined(SYSCFG_CFGR1_I2C_FMP_I2C5) || defined(SYSCFG_CFGR1_I2C5_FMP) || defined(SYSCFG_PMC_I2C5_FMP) || defined(SYSCFG_PMCR_I2C5_FMP) || defined(SYSCFG_CFGR2_I2C5_FMP) + if (obj_s->i2c == I2C_5) { + HAL_I2CEx_EnableFastModePlus(I2C_FASTMODEPLUS_I2C5); + } +#endif #endif } #endif //I2C_IP_VERSION_V2 @@ -667,6 +707,11 @@ void i2c_frequency(i2c_t *obj, int hz) __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC); } #endif +#if defined(I2C5_BASE) && defined(__HAL_RCC_I2C5_CONFIG) + if (obj_s->i2c == I2C_5) { + __HAL_RCC_I2C5_CONFIG(I2CAPI_I2C5_CLKSRC); + } +#endif #if defined(DUAL_CORE) && (TARGET_STM32H7) LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); #endif /* DUAL_CORE */ @@ -1840,6 +1885,7 @@ uint32_t i2c_get_timing(I2CName i2c, uint32_t current_timing, int current_hz, switch (hz) { case 100000: tim = TIMING_VAL_64M_CLK_100KHZ; + break; case 400000: tim = TIMING_VAL_64M_CLK_400KHZ; break; diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index b5d12f1eda6..d5292566e55 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -101,10 +101,10 @@ } #define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM5_FORCE_RESET #define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM5_RELEASE_RESET -#else +#else // (CORE_CM7) or (CORE_CM4) #error "Core not supported" #endif -#else +#else // (DUAL_CORE) && (TARGET_STM32H7) #define LPTIM_MST_BASE LPTIM1_BASE #define LPTIM_MST ((LPTIM_TypeDef *)LPTIM_MST_BASE) @@ -112,16 +112,16 @@ #define RCC_LPTIMCLKSOURCE_LSE RCC_LPTIM1CLKSOURCE_LSE #define RCC_LPTIMCLKSOURCE_LSI RCC_LPTIM1CLKSOURCE_LSI -#if defined(STM32G071xx) +#if defined(STM32G051xx) || defined(STM32G061xx) || defined(STM32G071xx) || defined(STM32G081xx) || defined(STM32G0B1xx) || defined(STM32G0C1xx) #define LPTIM_MST_IRQ TIM6_DAC_LPTIM1_IRQn -#else +#else // STM32G0xx #define LPTIM_MST_IRQ LPTIM1_IRQn -#endif +#endif // STM32G0xx #define LPTIM_MST_RCC __HAL_RCC_LPTIM1_CLK_ENABLE - #define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM1_FORCE_RESET #define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM1_RELEASE_RESET -#endif + +#endif // (DUAL_CORE) && (TARGET_STM32H7) diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index 6ce5514e1b4..f7afd6335ce 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -55,7 +55,7 @@ static uint32_t get_alt_bytes_size(const uint32_t num_bytes) ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCmdTypeDef *st_command) { - debug_if(ospi_api_c_debug, "ospi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", + debug_if(ospi_api_c_debug, "ospi_prepare_command In: instruction.value %x dummy_count %u address.bus_width %x address.disabled %x address.value %x address.size %x\n", command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); st_command->FlashId = HAL_OSPI_FLASH_ID_1; @@ -255,18 +255,21 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, obj->handle.Init.DeviceSize = 32; obj->handle.Init.ChipSelectHighTime = 3; obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; -#if defined(HAL_OSPI_WRAP_NOT_SUPPORTED) // removed in STM32L4 +#if defined(HAL_OSPI_WRAP_NOT_SUPPORTED) obj->handle.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED; #endif obj->handle.Init.ClockMode = mode == 0 ? HAL_OSPI_CLOCK_MODE_0 : HAL_OSPI_CLOCK_MODE_3; obj->handle.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE; obj->handle.Init.ChipSelectBoundary = 0; -#if defined(HAL_OSPI_DELAY_BLOCK_USED) // STM32L5 +#if defined(HAL_OSPI_DELAY_BLOCK_USED) obj->handle.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED; #endif -#if defined(TARGET_STM32L5) +#if defined(TARGET_STM32L5) || defined(TARGET_STM32U5) obj->handle.Init.Refresh = 0; #endif +#if defined(OCTOSPI_DCR3_MAXTRAN) + obj->handle.Init.MaxTran = 0; +#endif // tested all combinations, take first obj->ospi = pinmap->peripheral; @@ -371,13 +374,13 @@ ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinN OSPIName ospiio1name = (OSPIName)pinmap_peripheral(io1, PinMap_OSPI_DATA1); OSPIName ospiio2name = (OSPIName)pinmap_peripheral(io2, PinMap_OSPI_DATA2); OSPIName ospiio3name = (OSPIName)pinmap_peripheral(io3, PinMap_OSPI_DATA3); - OSPIName ospiio4name = (OSPIName)pinmap_peripheral(io4, PinMap_OSPI_DATA4); - OSPIName ospiio5name = (OSPIName)pinmap_peripheral(io5, PinMap_OSPI_DATA5); - OSPIName ospiio6name = (OSPIName)pinmap_peripheral(io6, PinMap_OSPI_DATA6); - OSPIName ospiio7name = (OSPIName)pinmap_peripheral(io7, PinMap_OSPI_DATA7); + // OSPIName ospiio4name = (OSPIName)pinmap_peripheral(io4, PinMap_OSPI_DATA4); // IO4 pin not checked + // OSPIName ospiio5name = (OSPIName)pinmap_peripheral(io5, PinMap_OSPI_DATA5); // IO5 pin not checked + // OSPIName ospiio6name = (OSPIName)pinmap_peripheral(io6, PinMap_OSPI_DATA6); // IO6 pin not checked + // OSPIName ospiio7name = (OSPIName)pinmap_peripheral(io7, PinMap_OSPI_DATA7); // IO7 pin not checked OSPIName ospiclkname = (OSPIName)pinmap_peripheral(sclk, PinMap_OSPI_SCLK); OSPIName ospisselname = (OSPIName)pinmap_peripheral(ssel, PinMap_OSPI_SSEL); - OSPIName ospidqsname = (OSPIName)pinmap_peripheral(dqs, PinMap_OSPI_DQS); + // OSPIName ospidqsname = (OSPIName)pinmap_peripheral(dqs, PinMap_OSPI_DQS); // DQS pin not checked OSPIName ospi_data_first = (OSPIName)pinmap_merge(ospiio0name, ospiio1name); OSPIName ospi_data_second = (OSPIName)pinmap_merge(ospiio2name, ospiio3name); @@ -451,24 +454,29 @@ ospi_status_t ospi_free(ospi_t *obj) ospi_status_t ospi_frequency(ospi_t *obj, int hz) { - tr_debug("ospi_frequency hz %d", hz); ospi_status_t status = OSPI_STATUS_OK; - /* HCLK drives OSPI. OSPI clock depends on prescaler value: + /* OSPI clock depends on prescaler value: * 0: Freq = HCLK * 1: Freq = HCLK/2 * ... * 255: Freq = HCLK/256 (minimum value) */ - int div = HAL_RCC_GetHCLKFreq() / hz; +#if defined(TARGET_STM32L5) + uint32_t OSPI_clock_source = HAL_RCC_GetSysClockFreq(); +#else + uint32_t OSPI_clock_source = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_OSPI); +#endif + int div = OSPI_clock_source / hz; if (div > 255) { div = 255; } else { - if (div == 1) { + if (OSPI_clock_source % hz != 0) { div = div + 1; } } + tr_debug("ospi_frequency hz %d source %d Prescaler %d", hz, OSPI_clock_source, div); obj->handle.Init.ClockPrescaler = div; diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 1c24b3f7f6b..3fb6cc73209 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -148,9 +148,9 @@ void rtc_init(void) error("RTC initialization failed\n"); } -#if !(TARGET_STM32F1) && !(TARGET_STM32F2) +#if !(TARGET_STM32F1) && !(TARGET_STM32F2) && !(STM32L151xB) /* STM32F1 : there are no shadow registers */ - /* STM32F2 : shadow registers can not be bypassed */ + /* STM32F2/STM32L151xB : shadow registers can not be bypassed */ if (HAL_RTCEx_EnableBypassShadow(&RtcHandle) != HAL_OK) { error("EnableBypassShadow error\n"); } diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index 63572659b83..61bec6352f1 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -939,6 +939,33 @@ static inline int datasize_to_transfer_bitshift(uint32_t DataSize) } } +static inline int spi_get_word_from_buffer(const void *buffer, int bitshift) +{ + if (bitshift == 1) { + return *((uint16_t *)buffer); +#ifdef HAS_32BIT_SPI_TRANSFERS + } else if (bitshift == 2) { + return *((uint32_t *)buffer); +#endif /* HAS_32BIT_SPI_TRANSFERS */ + } else { + return *((uint8_t *)buffer); + } +} + +static inline void spi_put_word_to_buffer(void *buffer, int bitshift, int data) +{ + if (bitshift == 1) { + *((uint16_t *)buffer) = data; +#ifdef HAS_32BIT_SPI_TRANSFERS + } else if (bitshift == 2) { + *((uint32_t *)buffer) = data; +#endif /* HAS_32BIT_SPI_TRANSFERS */ + } else { + *((uint8_t *)buffer) = data; + } +} + + /** * Check if SPI master interface is writable. * @@ -1057,6 +1084,7 @@ static int spi_master_one_wire_transfer(spi_t *obj, const char *tx_buffer, int t SPI_HandleTypeDef *handle = &(spiobj->handle); const int bitshift = datasize_to_transfer_bitshift(handle->Init.DataSize); MBED_ASSERT(bitshift >= 0); + const int word_size = 0x01 << bitshift; /* Ensure that spi is disabled */ LL_SPI_Disable(SPI_INST(obj)); @@ -1066,7 +1094,7 @@ static int spi_master_one_wire_transfer(spi_t *obj, const char *tx_buffer, int t LL_SPI_SetTransferDirection(SPI_INST(obj), LL_SPI_HALF_DUPLEX_TX); #if defined(SPI_IP_VERSION_V2) /* Set transaction size */ - LL_SPI_SetTransferSize(SPI_INST(obj), tx_length); + LL_SPI_SetTransferSize(SPI_INST(obj), tx_length >> bitshift); #endif /* SPI_IP_VERSION_V2 */ LL_SPI_Enable(SPI_INST(obj)); #if defined(SPI_IP_VERSION_V2) @@ -1074,9 +1102,9 @@ static int spi_master_one_wire_transfer(spi_t *obj, const char *tx_buffer, int t LL_SPI_StartMasterTransfer(SPI_INST(obj)); #endif /* SPI_IP_VERSION_V2 */ - for (int i = 0; i < tx_length; i++) { + for (int i = 0; i < tx_length; i += word_size) { msp_wait_writable(obj); - msp_write_data(obj, tx_buffer[i], bitshift); + msp_write_data(obj, spi_get_word_from_buffer(tx_buffer + i, bitshift), bitshift); } /* Wait end of transaction */ @@ -1098,14 +1126,14 @@ static int spi_master_one_wire_transfer(spi_t *obj, const char *tx_buffer, int t LL_SPI_SetTransferDirection(SPI_INST(obj), LL_SPI_HALF_DUPLEX_RX); #if defined(SPI_IP_VERSION_V2) /* Set transaction size and run SPI */ - LL_SPI_SetTransferSize(SPI_INST(obj), rx_length); + LL_SPI_SetTransferSize(SPI_INST(obj), rx_length >> bitshift); LL_SPI_Enable(SPI_INST(obj)); LL_SPI_StartMasterTransfer(SPI_INST(obj)); /* Receive data */ - for (int i = 0; i < rx_length; i++) { + for (int i = 0; i < rx_length; i += word_size) { msp_wait_readable(obj); - rx_buffer[i] = msp_read_data(obj, bitshift); + spi_put_word_to_buffer(rx_buffer + i, bitshift, msp_read_data(obj, bitshift)); } /* Stop SPI */ @@ -1134,7 +1162,7 @@ static int spi_master_one_wire_transfer(spi_t *obj, const char *tx_buffer, int t /* get estimation about one SPI clock cycle */ uint32_t baudrate_period_ns = 1000000000 / spi_get_baudrate(obj); - for (int i = 0; i < rx_length; i++) { + for (int i = 0; i < rx_length; i += word_size) { core_util_critical_section_enter(); LL_SPI_Enable(SPI_INST(obj)); /* Wait single SPI clock cycle. */ @@ -1143,7 +1171,7 @@ static int spi_master_one_wire_transfer(spi_t *obj, const char *tx_buffer, int t core_util_critical_section_exit(); msp_wait_readable(obj); - rx_buffer[i] = msp_read_data(obj, bitshift); + spi_put_word_to_buffer(rx_buffer + i, bitshift, msp_read_data(obj, bitshift)); } #endif /* SPI_IP_VERSION_V2 */ @@ -1198,13 +1226,25 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, { struct spi_s *spiobj = SPI_S(obj); SPI_HandleTypeDef *handle = &(spiobj->handle); + const int bitshift = datasize_to_transfer_bitshift(handle->Init.DataSize); + /* check buffer sizes are multiple of spi word size */ + MBED_ASSERT(tx_length >> bitshift << bitshift == tx_length); + MBED_ASSERT(rx_length >> bitshift << bitshift == rx_length); int total = (tx_length > rx_length) ? tx_length : rx_length; + if (handle->Init.Direction == SPI_DIRECTION_2LINES) { - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); + int write_fill_frame = write_fill; + /* extend fill symbols for 16/32 bit modes */ + for (int i = 0; i < bitshift; i++) { + write_fill_frame = (write_fill_frame << 8) | write_fill; + } + + const int word_size = 0x01 << bitshift; + for (int i = 0; i < total; i += word_size) { + int out = (i < tx_length) ? spi_get_word_from_buffer(tx_buffer + i, bitshift) : write_fill_frame; + int in = spi_master_write(obj, out); if (i < rx_length) { - rx_buffer[i] = in; + spi_put_word_to_buffer(rx_buffer + i, bitshift, in); } } } else { @@ -1349,6 +1389,11 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer // enable the right hal transfer int rc = 0; +#if defined(SPI_IP_VERSION_V2) + // HAL SPI API assumes that SPI disabled between transfers and + // doesn't work properly if SPI is enabled. + LL_SPI_Disable(SPI_INST(obj)); +#endif switch (transfer_type) { case SPI_TRANSFER_TYPE_TXRX: rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t *)tx, (uint8_t *)rx, words); @@ -1367,6 +1412,12 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer } if (rc) { +#if defined(SPI_IP_VERSION_V2) + // enable SPI back in case of error + if (handle->Init.Direction != SPI_DIRECTION_1LINE) { + LL_SPI_Enable(SPI_INST(obj)); + } +#endif DEBUG_PRINTF("SPI: RC=%u\n", rc); length = 0; } @@ -1466,6 +1517,16 @@ inline uint32_t spi_irq_handler_asynch(spi_t *obj) */ spi_flush_rx(obj); } +#else + // reset transfer size + LL_SPI_SetTransferSize(SPI_INST(obj), 0); + + // HAL_SPI_TransmitReceive_IT/HAL_SPI_Transmit_IT/HAL_SPI_Receive_IT + // function disable SPI after transfer. So we need enabled it back, + // otherwise spi_master_block_write/spi_master_write won't work in 4-wire mode. + if (handle->Init.Direction != SPI_DIRECTION_1LINE) { + LL_SPI_Enable(SPI_INST(obj)); + } #endif /* SPI_IP_VERSION_V2 */ } diff --git a/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py b/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py index be07c911b68..63f0e875998 100644 --- a/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py +++ b/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py @@ -27,7 +27,7 @@ from argparse import RawTextHelpFormatter import subprocess -GENPINMAP_VERSION = "1.20.3" +GENPINMAP_VERSION = "1.20.5" ADD_DEVICE_IF = 0 ADD_GPIO_PINMAP = 0 @@ -191,6 +191,8 @@ def get_gpio_af_num(pintofind, iptofind): if mygpioaf != "": mygpioaf += " " mygpioaf += mygpioaflist.data + if "STM32L1" in mcu_file and mygpioaf == "GPIO_AF10_USB": + mygpioaf = "GPIO_AF_NONE" if mygpioaf == "": mygpioaf = "GPIO_AF_NONE" return mygpioaf @@ -240,25 +242,10 @@ def get_gpio_af_num_stm32f1(pintofind, iptofind): ) in myc.childNodes: if mygpioaf != "": mygpioaf += " " - mygpioaf += mygpioaflist.data.replace( - "__HAL_", "" - ).replace( - "_REMAP", "" - ) + mygpioaf += mygpioaflist.data.replace("__HAL_", "") if mygpioaf == "": mygpioaf = "AFIO_NONE" - return mygpioaf.replace("AFIO_NONE", "0")\ - .replace("AFIO_SPI1_ENABLE", "1")\ - .replace("AFIO_I2C1_ENABLE", "2")\ - .replace("AFIO_USART1_ENABLE", "3")\ - .replace("AFIO_USART3_PARTIAL", "5")\ - .replace("AFIO_TIM1_PARTIAL", "6")\ - .replace("AFIO_TIM3_PARTIAL", "7")\ - .replace("AFIO_TIM2_ENABLE", "8")\ - .replace("AFIO_TIM2_PARTIAL_1", "8")\ - .replace("AFIO_TIM2_PARTIAL_2", "8")\ - .replace("AFIO_TIM3_ENABLE", "9")\ - .replace("AFIO_CAN1_2", "10") + return mygpioaf def store_pin(pin, name, functionality): # store pin I/O @@ -395,6 +382,9 @@ def store_sys(pin, name, signal): def make_cmakelist(): + global TARGET_NAME + if TARGET_NAME == "": + TARGET_NAME = "xxx" mbed_target = "mbed-" + TARGET_NAME.replace("_", "-").lower() mbed_family = "mbed-" + TARGET_SUBFAMILY.lower() @@ -534,7 +524,10 @@ def print_footer(): for EachLED in sorted(StandardLED): led_label = " // %s" % EachLED - out_h_file.write("#define LED%i %-5s %s\n" % (name_counter, re.sub(r'(P.)', r'\1_', StandardLED[EachLED]), led_label)) + commented_line = "" + if "TODO" in led_label: + commented_line = "// " + out_h_file.write("%s#define LED%i %-5s %s\n" % (commented_line, name_counter, re.sub(r'(P.)', r'\1_', StandardLED[EachLED]), led_label)) name_counter += 1 name_counter = 1 @@ -544,7 +537,10 @@ def print_footer(): button_label = "" if EachBUTTON in PinLabel: button_label = " // %s" % PinLabel[EachBUTTON] - out_h_file.write("#define BUTTON%i %-5s %s\n" % (name_counter, re.sub(r'(P.)', r'\1_', EachBUTTON).split('/')[0].split('-')[0], button_label)) + commented_line = "" + if "TODO" in button_label: + commented_line = "// " + out_h_file.write("%s#define BUTTON%i %-5s %s\n" % (commented_line, name_counter, re.sub(r'(P.)', r'\1_', EachBUTTON).split('/')[0].split('-')[0], button_label)) name_counter += 1 line_to_write = (""" @@ -1594,7 +1590,7 @@ def parse_board_file(file_name): parser.add_argument("-g", "--gpio", help="Add GPIO PinMap table", action="store_true") parser.add_argument("-n", "--nopull", help="Avoid STM32_open_pin_data git pull", action="store_true") -parser.add_argument("-f", "--flat", help="All targets stored in targets_custom/TARGET_STM/", action="store_true") +parser.add_argument("-f", "--flat", help="All targets stored in TARGET_CUSTOM/TARGET_STM/", action="store_true") parser.add_argument("-d", "--debug", help="Few debug info in console", action="store_true") args = parser.parse_args() @@ -1846,7 +1842,10 @@ def parse_board_file(file_name): if args.mcu: m = re.match("(STM32[\w]{7})", EachTargetName) if m: - out_path = os.path.join(cur_dir, 'targets_custom', 'TARGET_STM', 'TARGET_%s' %TARGET_FAMILY, 'TARGET_%s' %TARGET_SUBFAMILY, 'TARGET_%s' % m.group(0)) + if FLAT_DIRECTORY == 0: + out_path = os.path.join(cur_dir, 'TARGET_CUSTOM', 'TARGET_STM', 'TARGET_%s' %TARGET_FAMILY, 'TARGET_%s' %TARGET_SUBFAMILY, 'TARGET_%s' % m.group(0)) + else: + out_path = os.path.join(cur_dir, 'TARGET_CUSTOM', 'TARGET_%s' % m.group(0)) if EachTargetName.endswith('A'): out_path += "_A" elif EachTargetName.endswith('P'): @@ -1865,9 +1864,9 @@ def parse_board_file(file_name): else: if EachTargetName == MCU_USERNAME: if FLAT_DIRECTORY == 0: - out_path = os.path.join(cur_dir, 'targets_custom', 'TARGET_STM', 'TARGET_%s' % TARGET_FAMILY, 'TARGET_%s' % TARGET_SUBFAMILY, 'TARGET_%s' % TARGET_NAME) + out_path = os.path.join(cur_dir, 'TARGET_CUSTOM', 'TARGET_STM', 'TARGET_%s' % TARGET_FAMILY, 'TARGET_%s' % TARGET_SUBFAMILY, 'TARGET_%s' % TARGET_NAME) else: - out_path = os.path.join(cur_dir, 'targets_custom', 'TARGET_STM', 'TARGET_%s' % TARGET_NAME) + out_path = os.path.join(cur_dir, 'TARGET_CUSTOM', 'TARGET_%s' % TARGET_NAME) else: continue @@ -1891,6 +1890,7 @@ def parse_board_file(file_name): cmake_file = open(cmake_filename, 'w') #open input file + DUAL_PAD = False try: xml_mcu = parse(input_file_name) except: diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/gpio_irq_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/gpio_irq_api.c index a3c39f82d44..fd71365e389 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/gpio_irq_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/gpio_irq_api.c @@ -32,7 +32,7 @@ #define CHANNEL_NUM 48 #define MAX_PIN_PER_PORT 16 static gpio_irq_handler irq_handler; -static uint32_t channel_ids[CHANNEL_NUM]; +static uintptr_t channel_contexts[CHANNEL_NUM]; static gpio_irq_event pins_event[CHANNEL_NUM]; static inline void handle_gpio_irq(uint32_t port) @@ -47,7 +47,7 @@ static inline void handle_gpio_irq(uint32_t port) pin_name += i; NVIC_ClearPendingIRQ(PORT0_0_IRQn + port * 16 + i); gpio_base->INTCLR = 1u << i; - irq_handler(channel_ids[pin_name], pins_event[pin_name]); + irq_handler(channel_contexts[pin_name], pins_event[pin_name]); break; } } @@ -70,7 +70,7 @@ void gpio2_irq(void) } int gpio_irq_init(gpio_irq_t *obj, PinName pin, - gpio_irq_handler handler, uint32_t id) + gpio_irq_handler handler, uintptr_t context) { if (pin == (PinName)NC) { return -1; @@ -78,7 +78,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, obj->pin = pin; irq_handler = handler; - channel_ids[pin] = id; + channel_contexts[pin] = context; bp6a_gpio_set_dir(BP6A_PORT_IDX(obj->pin), BP6A_PIN_IDX(obj->pin), true); return 0; @@ -86,7 +86,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->pin] = 0; + channel_contexts[obj->pin] = 0; gpio_irq_disable(obj); } diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/serial_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/serial_api.c index 99f9c13bb3e..c27aeb31dfa 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/serial_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/serial_api.c @@ -39,7 +39,7 @@ #define UART_HWCONTROL_RTS 1 #define UART_HWCONTROL_CTS 2 #define UART_HWCONTROL_RTS_CTS 3 -static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; static uart_irq_handler irq_handler; int stdio_uart_inited = 0; @@ -172,8 +172,8 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b ******************************************************************************/ static inline void _uart_irq_handler(SerialIrq irq_type, uint32_t index) { - if (serial_irq_ids[index] != 0) { - irq_handler(serial_irq_ids[index], irq_type); + if (serial_irq_contexts[index] != 0) { + irq_handler(serial_irq_contexts[index], irq_type); } } @@ -231,10 +231,10 @@ void uart2_irq(void) NVIC_ClearPendingIRQ((IRQn_Type)UARTR2_IRQn); } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/gpio_irq_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/gpio_irq_api.c index 6d40b980e23..e5dd51bd793 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/gpio_irq_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/gpio_irq_api.c @@ -54,7 +54,7 @@ struct pin_info { uint8_t minor; - uint32_t ids; + uintptr_t context; uint32_t pincfg; gpio_irq_event event; @@ -152,7 +152,7 @@ static inline void handle_interrupt_in(uint32_t channel) event = pins[pin].event; MBED_ASSERT(pin < PIN_NUM); - irq_handler(pins[pin].ids, pins[pin].event); //should be fixed by polarity + irq_handler(pins[pin].context, pins[pin].event); //should be fixed by polarity #if GPIO_EINT_DEBOUNCE hw_delay_us(200000); #endif @@ -199,7 +199,7 @@ int gpio_pin_mode(PinName pin, PinMode mode) } int gpio_irq_init(gpio_irq_t *obj, PinName pin, - gpio_irq_handler handler, uint32_t id) + gpio_irq_handler handler, uintptr_t context) { if (pin == NC) { return -1; @@ -210,7 +210,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, irq_handler = handler; // set handler for apps - pins[obj->ch].ids = id; + pins[obj->ch].context = context; NVIC_SetVector((IRQn_Type)(PININT_IRQ0), (uint32_t)gpio0_irq); NVIC_SetVector((IRQn_Type)(PININT_IRQ1), (uint32_t)gpio1_irq); diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/objects.h b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/objects.h index 8513b23e8f5..32add1cde18 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/objects.h +++ b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/objects.h @@ -67,7 +67,7 @@ typedef enum { struct uart_ops_s { void (*serial_baud)(void *obj, int baudrate); void (*serial_format)(void *obj, int data_bits, SerialParity parity, int stop_bits); - void (*serial_irq_handler)(void *obj, uart_irq_handler handler, uint32_t id); + void (*serial_irq_handler)(void *obj, uart_irq_handler handler, uintptr_t context); void (*serial_irq_set)(void *obj, SerialIrq irq, uint32_t enable); void (*serial_putc)(void *obj, int c); int (*serial_writable)(void *obj); diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_api.c index 394ab65835e..503ac079d4c 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_api.c @@ -158,9 +158,9 @@ void serial_format(serial_t *obj, int data_bits, } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { - obj->ops.serial_irq_handler(obj, handler, id); + obj->ops.serial_irq_handler(obj, handler, context); } diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_dummy_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_dummy_api.c index c510e31fa44..ef210a1ce42 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_dummy_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_dummy_api.c @@ -48,7 +48,7 @@ static void dummy_serial_format(void *obj, int data_bits, { } -static void dummy_serial_irq_handler(void *obj, uart_irq_handler handler, uint32_t id) +static void dummy_serial_irq_handler(void *obj, uart_irq_handler handler, uintptr_t context) { } diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_pl011_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_pl011_api.c index 860138226f5..e90aa3c0632 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_pl011_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_pl011_api.c @@ -38,7 +38,7 @@ static uart_irq_handler irq_handler[PL011_UART_MAX]; struct serial_context_data_s { - uint32_t serial_irq_id; + uint32_t serial_irq_context; gpio_t sw_rts, sw_cts; uint8_t count, rx_irq_set_flow, rx_irq_set_api; }; @@ -73,7 +73,7 @@ static inline void uart_irq(t_pl011_ports_enum index, if (irq_type == RxIrq) { if (uart_data[index].rx_irq_set_api) { - (irq_handler[index])(uart_data[index].serial_irq_id, irq_type); + (irq_handler[index])(uart_data[index].serial_irq_context, irq_type); } } @@ -197,12 +197,12 @@ static void pl011_serial_format(void *obj, int data_bits, p_PL011_UART->LCRH = reg; } -static void pl011_serial_irq_handler(void *obj, uart_irq_handler handler, uint32_t id) +static void pl011_serial_irq_handler(void *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *priv = (struct serial_s *)obj; irq_handler[priv->index] = handler; - uart_data[priv->index].serial_irq_id = id; + uart_data[priv->index].serial_irq_context = context; } diff --git a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_usi_api.c b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_usi_api.c index 4a14906e59f..704c7586fe7 100644 --- a/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_usi_api.c +++ b/targets/TARGET_Samsung/TARGET_SIDK_S5JS100/serial_usi_api.c @@ -39,7 +39,7 @@ #define USI_PTR(ptr) ((S5JS100_USI_UART_TypeDef *)(ptr)) static uart_irq_handler irq_handler[USI_MAX_PORTS]; -static uint32_t serial_irq_id[USI_MAX_PORTS] = {0}; +static uintptr_t serial_irq_context[USI_MAX_PORTS] = {0}; @@ -50,11 +50,11 @@ static inline void uart_irq(uint32_t intstatus, uint32_t index, { if (intstatus & (1 << 0)) { - (irq_handler[index])(serial_irq_id[index], RxIrq); + (irq_handler[index])(serial_irq_context[index], RxIrq); } else if (intstatus & (1 << 1)) { // RTS Int } else if (intstatus & (1 << 2)) { - (irq_handler[index])(serial_irq_id[index], TxIrq); + (irq_handler[index])(serial_irq_context[index], TxIrq); } else if (intstatus & (1 << 3)) { // CTS Int } else { @@ -157,12 +157,12 @@ static void usi_serial_format(void *obj, int data_bits, } -static void usi_serial_irq_handler(void *obj, uart_irq_handler handler, uint32_t id) +static void usi_serial_irq_handler(void *obj, uart_irq_handler handler, uintptr_t context) { struct serial_s *priv = (struct serial_s *)obj; irq_handler[priv->index] = handler; - serial_irq_id[priv->index] = id; + serial_irq_context[priv->index] = context; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/can_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/can_api.c index 0e847400de9..412e9a0bf4c 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/can_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/can_api.c @@ -27,7 +27,7 @@ #include "em_cmu.h" #include "em_can.h" -static uint32_t can_irq_ids[CAN_COUNT] = {0}; +static uintptr_t can_irq_contexts[CAN_COUNT] = {0}; static can_irq_handler irq_handler; // CAN bus interfaces @@ -104,7 +104,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) CAN_SetIdAndFilter(obj->instance, CAN_RX_IF, true, &receiver, true); } -void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) +void can_irq_init(can_t *obj, can_irq_handler handler, uintptr_t context) { int index = 0; @@ -122,7 +122,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) } irq_handler = handler; - can_irq_ids[index] = id; + can_irq_contexts[index] = context; } void can_irq_free(can_t *obj) @@ -294,12 +294,12 @@ static void can_irq(CANName name, int id) can = (CAN_TypeDef *)name; if (can->STATUS & CAN_STATUS_RXOK) { - irq_handler(can_irq_ids[id], IRQ_RX); + irq_handler(can_irq_contexts[id], IRQ_RX); CAN_MessageIntClear(can, 0xFFFFFFFF); } if (can->STATUS & CAN_STATUS_TXOK) { - irq_handler(can_irq_ids[id], IRQ_TX); + irq_handler(can_irq_contexts[id], IRQ_TX); CAN_MessageIntClear(can, 0xFFFFFFFF); } } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c index f2aa6172ccc..f885d60e633 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c @@ -49,7 +49,7 @@ __STATIC_INLINE uint32_t countTrailingZeros(uint32_t mask) #error Unsupported architecture. #endif -static uint32_t channel_ids[NUM_GPIO_CHANNELS] = { 0 }; // Relates pin number with interrupt action id +static uintptr_t channel_contexts[NUM_GPIO_CHANNELS] = { 0 }; // Relates pin number with interrupt action context static uint8_t channel_ports[NUM_GPIO_CHANNELS/2] = { 0 }; // Storing 2 ports in each uint8 static gpio_irq_handler irq_handler; static void GPIOINT_IRQDispatcher(uint32_t iflags); @@ -57,7 +57,7 @@ static void GPIOINT_IRQDispatcher(uint32_t iflags); static void handle_interrupt_in(uint8_t pin) { // Return if pin not linked with an interrupt function - if (channel_ids[pin] == 0) { + if (channel_contexts[pin] == 0) { return; } @@ -83,7 +83,7 @@ static void handle_interrupt_in(uint8_t pin) event = (isRise == 1 ? IRQ_RISE : IRQ_FALL); } GPIO_IntClear(pin); - irq_handler(channel_ids[pin], event); + irq_handler(channel_contexts[pin], event); } void gpio_irq_preinit(gpio_irq_t *obj, PinName pin) @@ -98,7 +98,7 @@ void gpio_irq_preinit(gpio_irq_t *obj, PinName pin) obj->fallingEdge = 0; } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { // Init pins gpio_irq_preinit(obj, pin); @@ -110,8 +110,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 NVIC_ClearPendingIRQ(GPIO_EVEN_IRQn); NVIC_EnableIRQ(GPIO_EVEN_IRQn); - /* Relate pin to interrupt action id */ - channel_ids[obj->pin & 0xF] = id; + /* Relate pin to interrupt action context */ + channel_contexts[obj->pin & 0xF] = context; // Relate the pin number to a port. If pin in is odd store in the 4 most significant bits, if pin is even store in the 4 least significant bits channel_ports[(obj->pin >> 1) & 0x7] = (obj->pin & 0x1) ? (channel_ports[(obj->pin >> 1) & 0x7] & 0x0F) | (obj->pin & 0xF0) : (channel_ports[(obj->pin >> 1) & 0x7] & 0xF0) | ((obj->pin >> 4) & 0xF); @@ -125,7 +125,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 void gpio_irq_free(gpio_irq_t *obj) { // Destructor - channel_ids[obj->pin & 0xF] = 0; + channel_contexts[obj->pin & 0xF] = 0; gpio_irq_disable(obj); // Disable interrupt channel pin_mode(obj->pin, Disabled); // Disable input pin } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index ede181441ef..06eba1d7872 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -70,9 +70,8 @@ #define MODULES_SIZE_SERIAL (UART_COUNT + USART_COUNT + LEUART_COUNT) -/* Store IRQ id for each UART */ -static uint32_t serial_irq_ids[MODULES_SIZE_SERIAL] = { 0 }; -/* Interrupt handler from mbed common */ +/* Store IRQ context for each UART */ +static uintptr_t serial_irq_contexts[MODULES_SIZE_SERIAL] = { 0 }; /* Interrupt handler from mbed common */ static uart_irq_handler irq_handler; /* Keep track of incoming DMA IRQ's */ static bool serial_dma_irq_fired[DMA_CHAN_COUNT] = { false }; @@ -721,7 +720,7 @@ static void serial_enable(serial_t *obj, uint8_t enable) USART_Enable(obj->serial.periph.uart, usartDisable); } } - serial_irq_ids[serial_get_index(obj)] = 0; + serial_irq_contexts[serial_get_index(obj)] = 0; } /** @@ -1017,13 +1016,13 @@ uint8_t serial_interrupt_enabled(serial_t *obj) /** * Set handler for all serial interrupts (is probably SerialBase::_handler()) - * and store IRQ ID to be returned to the handler upon interrupt. ID is + * and store IRQ Context to be returned to the handler upon interrupt. Context is * probably a pointer to the calling Serial object. */ -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[serial_get_index(obj)] = id; + serial_irq_contexts[serial_get_index(obj)] = context; } /** @@ -1032,9 +1031,9 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) static void uart_irq(UARTName name, SerialIrq irq) { uint8_t index = serial_pointer_get_index((uint32_t)name); - if (serial_irq_ids[index] != 0) { + if (serial_irq_contexts[index] != 0) { /* Pass interrupt on to mbed common handler */ - irq_handler(serial_irq_ids[index], irq); + irq_handler(serial_irq_contexts[index], irq); /* Clearing interrupt not necessary */ } } diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_irq_api.c index 4ff11d98784..3b40f469452 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_irq_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_irq_api.c @@ -32,7 +32,7 @@ const PinMap PinMap_GPIO_IRQ[] = { {NC, NC, 0} }; -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index) @@ -51,11 +51,11 @@ static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index) switch (val) { // Falling edge detection case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); + hal_irq_handler[index](channel_contexts[index], IRQ_FALL); break; // Rising edge detection case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); + hal_irq_handler[index](channel_contexts[index], IRQ_RISE); break; default: break; @@ -97,7 +97,7 @@ void INTF_IRQHandler(void) INT_IRQHandler(PC1, GPIO_IRQ_6, 6); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { // Get gpio interrupt ID obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); @@ -139,8 +139,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 } // Save irq handler hal_irq_handler[obj->irq_src] = handler; - // Save irq id - channel_ids[obj->irq_src] = id; + // Save irq context + channel_contexts[obj->irq_src] = context; // Initialize interrupt event as both edges detection obj->event = CG_INT_ACTIVE_STATE_INVALID; // Clear gpio pending interrupt @@ -157,8 +157,8 @@ void gpio_irq_free(gpio_irq_t *obj) NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); // Reset interrupt handler hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; + // Reset interrupt context + channel_contexts[obj->irq_src] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c index 090b1599fbd..3f89d680b70 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c @@ -60,7 +60,7 @@ static const PinMap PinMap_UART_RTS[] = { }; -static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; static uart_irq_handler irq_handler; void serial_init_UART_configure(int uartname, serial_t *obj, PinName tx, PinName rx); @@ -261,42 +261,42 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b void INTTX0_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_0], TxIrq); } void INTRX0_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_0], RxIrq); } void INTTX1_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_1], TxIrq); } void INTRX1_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_1], RxIrq); } void INTTX2_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_2], TxIrq); } void INTRX2_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_2], RxIrq); } void INTTX3_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_3], TxIrq); } void INTRX3_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_3], RxIrq); } void INTUART0_IRQHandler(void) @@ -304,10 +304,10 @@ void INTUART0_IRQHandler(void) FUART_INTStatus fuart_int; fuart_int = FUART_GetMaskedINTStatus(FUART0); if (fuart_int.Bit.TxFIFO == 1) { - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_4], TxIrq); } if (fuart_int.Bit.RxFIFO == 1) { - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_4], RxIrq); } } @@ -316,17 +316,17 @@ void INTUART1_IRQHandler(void) FUART_INTStatus fuart_int; fuart_int = FUART_GetMaskedINTStatus(FUART1); if (fuart_int.Bit.TxFIFO == 1) { - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_5], TxIrq); } if (fuart_int.Bit.RxFIFO == 1) { - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_5], RxIrq); } } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_irq_api.c index 2d817519db7..c0e24264bed 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_irq_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/gpio_irq_api.c @@ -50,7 +50,7 @@ const PinMap PinMap_GPIO_IRQ[] = { extern _gpio_t gpio_port_add; -static uint32_t channel_ids[CHANNEL_NUM] = {0}; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; static CG_INTActiveState CurrentState; @@ -134,7 +134,7 @@ void INT15_IRQHandler(void) INT_IRQHandler(PC7, 15); } -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) { // Get gpio interrupt ID obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); @@ -150,8 +150,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->irq_src = (CG_INTSrc)obj->irq_id; // Save irq handler hal_irq_handler[obj->irq_src] = handler; - // Save irq id - channel_ids[obj->irq_src] = id; + // Save irq context + channel_contexts[obj->irq_src] = context; // Initialize interrupt event as both edges detection obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; // Clear gpio pending interrupt @@ -169,8 +169,8 @@ void gpio_irq_free(gpio_irq_t *obj) NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); // Reset interrupt handler hal_irq_handler[obj->irq_src] = NULL; - // Reset interrupt id - channel_ids[obj->irq_src] = 0; + // Reset interrupt context + channel_contexts[obj->irq_src] = 0; } void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) @@ -263,11 +263,11 @@ static void INT_IRQHandler(PinName pin, uint32_t index) switch (data) { // Falling edge detection case 0: - hal_irq_handler[index](channel_ids[index], IRQ_FALL); + hal_irq_handler[index](channel_contexts[index], IRQ_FALL); break; // Rising edge detection case 1: - hal_irq_handler[index](channel_ids[index], IRQ_RISE); + hal_irq_handler[index](channel_contexts[index], IRQ_RISE); break; default: break; diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/serial_api.c index bd14d8a566f..e7ee00671c2 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/serial_api.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4G9/serial_api.c @@ -89,7 +89,7 @@ static const PinMap PinMap_UART_CTS[] = { {NC, NC, 0} }; -static int serial_irq_ids[UART_NUM] = {0}; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; static uart_irq_handler irq_handler; int stdio_uart_inited = 0; @@ -300,62 +300,62 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b // INTERRUPT HANDLING void INTUART0RX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_0], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_0], RxIrq); } void INTUART0TX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_0], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_0], TxIrq); } void INTUART1RX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_1], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_1], RxIrq); } void INTUART1TX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_1], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_1], TxIrq); } void INTUART2RX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_2], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_2], RxIrq); } void INTUART2TX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_2], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_2], TxIrq); } void INTUART3RX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_3], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_3], RxIrq); } void INTUART3TX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_3], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_3], TxIrq); } void INTUART4RX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_4], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_4], RxIrq); } void INTUART4TX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_4], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_4], TxIrq); } void INTUART5RX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_5], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_5], RxIrq); } void INTUART5TX_IRQHandler(void) { - irq_handler(serial_irq_ids[SERIAL_5], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_5], TxIrq); } void INTFUART0_IRQHandler(void) @@ -364,9 +364,9 @@ void INTFUART0_IRQHandler(void) int_status = TSB_FURT0->MIS; if (int_status & (1 << 4U)) { - irq_handler(serial_irq_ids[SERIAL_6], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_6], RxIrq); } else if (int_status & (1 << 5U)) { - irq_handler(serial_irq_ids[SERIAL_6], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_6], TxIrq); } else { return; } @@ -378,18 +378,18 @@ void INTFUART1_IRQHandler(void) int_status = TSB_FURT1->MIS; if (int_status & (1 << 4U)) { - irq_handler(serial_irq_ids[SERIAL_7], RxIrq); + irq_handler(serial_irq_contexts[SERIAL_7], RxIrq); } else if (int_status & (1 << 5U)) { - irq_handler(serial_irq_ids[SERIAL_7], TxIrq); + irq_handler(serial_irq_contexts[SERIAL_7], TxIrq); } else { return; } } -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_contexts[obj->index] = context; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h new file mode 100644 index 00000000000..57a1f648321 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/flash.h @@ -0,0 +1,47 @@ +/** + ******************************************************************************* + * @file flash.h + * @brief This file provides flash definition.\n + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __FLASH_H +#define __FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "rda_flash512ud32_b.h" +#include "txzp_driver_def.h" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FLASH_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/rda_flash512ud32_b.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/rda_flash512ud32_b.h new file mode 100644 index 00000000000..a2bc3bcd545 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/rda_flash512ud32_b.h @@ -0,0 +1,502 @@ +/** + ******************************************************************************* + * @file rda_flash512ud32_b.h + * @brief This file provides rda_flash512ud32 definition.\n + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RDA_FLASH512UD32_B_H +#define __RDA_FLASH512UD32_B_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "flash.h" +//#include "driver_com.h" +#include "TMPM4KNA.h" + + +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup RDA_FLASH512UD32 RDA_FLASH512UD32 + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +#if defined ( __CC_ARM ) /* RealView Compiler */ +extern uint32_t Load$$FLASH_CODE_RAM$$Base; +extern uint32_t Image$$FLASH_CODE_RAM$$Base; +extern uint32_t Load$$FLASH_CODE_RAM$$Length; +extern uint32_t Image$$FLASH_DEMO_A$$Base; +extern uint32_t Load$$FLASH_DEMO_B$$Base; +extern uint32_t Image$$RAM_DEMO_A$$Base; +extern uint32_t Image$$RAM_DEMO_B$$Base; + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma section = "FLASH_CODE_RAM" +#pragma section = "FLASH_CODE_ROM" +#pragma section = "FLASH_DEMO_A" +#pragma section = "FLASH_DEMO_B" +#pragma section = "RAM_DEMO_A" +#pragma section = "RAM_DEMO_B" + +#endif + +/** + * @addtogroup RDA_FLASH512UD32_Private_define RDA_FLASH512UD32 Private Define + * @{ + */ +#if defined ( __CC_ARM ) /* RealView Compiler */ +#define FLASH_API_ROM (uint32_t *)&Load$$FLASH_CODE_RAM$$Base + +#define FLASH_API_RAM (uint32_t *)&Image$$FLASH_CODE_RAM$$Base +#define SIZE_FLASH_API (uint32_t)&Load$$FLASH_CODE_RAM$$Length + +#define DEMO_A_FLASH (uint32_t *)&Image$$FLASH_DEMO_A$$Base +#define DEMO_B_FLASH (uint32_t *)&Load$$FLASH_DEMO_B$$Base + +#define DEMO_A_RAM (uint32_t *)&Image$$RAM_DEMO_A$$Base +#define DEMO_B_RAM (uint32_t *)&Image$$RAM_DEMO_B$$Base + + +#elif defined ( __ICCARM__ ) /* IAR Compiler */ +#define FLASH_API_ROM ((uint32_t *)__section_begin("FLASH_CODE_ROM")) + +#define FLASH_API_RAM ((uint32_t *)__section_begin("FLASH_CODE_RAM")) +#define SIZE_FLASH_API ((uint32_t)__section_size("FLASH_CODE_ROM")) + +#define DEMO_A_FLASH ((uint32_t *)__section_begin("FLASH_DEMO_A")) +#define DEMO_B_FLASH ((uint32_t *)__section_begin("FLASH_DEMO_B")) + +#define DEMO_A_RAM ((uint32_t *)__section_begin("RAM_DEMO_A")) +#define DEMO_B_RAM ((uint32_t *)__section_begin("RAM_DEMO_B")) + +#endif + +/* code start address */ +#define DEMO_START_ADDR ((uint32_t)DEMO_A_FLASH) + +#define USERINFOSIZE (128) /*= num) { + result = ADC_PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group ADC_Private_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ADC_INCLUDE_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_cg.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_cg.h new file mode 100644 index 00000000000..2d88d299699 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_cg.h @@ -0,0 +1,129 @@ +/** + ******************************************************************************* + * @file txzp_cg.h + * @brief This file provides all the functions prototypes for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __CG_H +#define __CG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup CG CG + * @brief CG Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/** + * @defgroup CG_CGOSCCR_OSCF fosc high-speed oscillator Select Status. + * @brief fosc high-speed oscillator Select Status. + * @{ + */ +#define CG_CGOSCCR_OSCF_IHOSC ((uint32_t)0x00000000) /*!< IHOSC */ +#define CG_CGOSCCR_OSCF_EHOSC ((uint32_t)0x00000200) /*!< EHOSC */ +/** + * @} + */ /* End of group CG_CGOSCCR_OSCF */ +/** + * @} + */ /* End of group CG_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_define CG Exported Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_typedef CG Exported Typedef + * @{ + */ +/** + * @brief CG member. +*/ +/*----------------------------------*/ +typedef struct { + TSB_CG_TypeDef *p_instance; /*!< Registers base address. */ +} cg_t; + +/** + * @} + */ /* End of group CG_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +uint32_t cg_get_mphyt0(cg_t *p_obj); +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __CG_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_driver_def.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_driver_def.h new file mode 100644 index 00000000000..002cac76bba --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_driver_def.h @@ -0,0 +1,109 @@ +/** + ******************************************************************************* + * @file txzp_driver_def.h + * @brief All common macro and definition for TXZ peripheral drivers + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TXZ_DRIVER_DEF_H +#define __TXZ_DRIVER_DEF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF + * @brief All common macro and definition for TXZ peripheral drivers + * @{ + */ + +/** @defgroup Device_Header_Included Device Header Included + * @brief Include the Device header file of a Target. + * @{ + */ +#include "TMPM4KNA.h" /*!< TMPM4KNA Group Header file. */ +/** + * @} + */ /* End of group Device_Header */ + + +/** @defgroup TXZ_Exported_typedef TXZ Exported typedef + * @{ + */ +typedef enum { + TXZ_SUCCESS = 0U, + TXZ_ERROR = 1U +} TXZ_Result; + +typedef enum { + TXZ_BUSY = 0U, + TXZ_DONE = 1U +} TXZ_WorkState; + +typedef enum { + TXZ_DISABLE = 0U, + TXZ_ENABLE = 1U +} TXZ_FunctionalState; +/** + * @} + */ /* End of group TXZ_Exported_typedef */ + +/** @defgroup TXZ_Exported_macro TXZ Exported macro + * @{ + */ +#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0) + +/** + * @brief To report the name of the source file and source line number where the + * assert_param error has occurred, "DEBUG" must be defined. And detailed + * definition of assert_failed() is needed to be implemented, which can be + * done, for example, in the main.c file. + */ +#ifdef DEBUG +void assert_failed(char *file, int32_t line); +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__)) +#else +#define assert_param(expr) +#endif /* DEBUG */ + +/** + * @} + */ /* End of group TXZ_Exported_macro */ + +/** + * @} + */ /* End of group Periph_Driver */ + +/** + * @} + */ /* End of group TXZ_DRIVER_DEF */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __TXZ_DRIVER_DEF_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_gpio.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_gpio.h new file mode 100644 index 00000000000..0dd0bfcbbe4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_gpio.h @@ -0,0 +1,1284 @@ +/** + ******************************************************************************* + * @file txzp_gpio.h + * @brief This file provides all the functions prototypes for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __GPIO_H +#define __GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*selects perticularly TMPM4KNA out of TMPM4KyA family */ +#ifndef TMPM4KNA +#define TMPM4KNA +#endif +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup GPIO GPIO + * @brief GPIO Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_define GPIO Exported Define + * @{ + */ + + +/** + * @defgroup GPIO_Result Result + * @brief GPIO Result Macro Definition. + * @{ + */ +#define GPIO_RESULT_SUCCESS (0) /*!< Success */ +#define GPIO_RESULT_FAILURE (-1) /*!< Failure */ +#define GPIO_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group GPIO_Result */ + +/** + * @} + */ /* End of group GPIO_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ + +/** + * @enum gpio_pinstate_t + * @brief Pin State Reset/Set Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_RESET = 0, /*!< 0: Clear */ + GPIO_PIN_SET, /*!< 1: Set */ +} gpio_pinstate_t; + +/** + * @enum gpio_pininout_t + * @brief Pin Input/Output Enumerated Type Definition. + */ +typedef enum { + GPIO_PIN_INPUT = 0, /*!< 0: Input */ + GPIO_PIN_OUTPUT, /*!< 1: Output */ + GPIO_PIN_INOUT, /*!< 2: Input/Output */ +} gpio_pininout_t; + +/** + * @enum gpio_gr_t + * @brief Port Group Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_A = 0x0, /*!< 0: PA */ + GPIO_PORT_B, /*!< 1: PB */ + GPIO_PORT_C, /*!< 2: PC */ + GPIO_PORT_D, /*!< 3: PD */ + GPIO_PORT_E, /*!< 4: PE */ + GPIO_PORT_F, /*!< 5: PF */ + GPIO_PORT_G, /*!< 6: PG */ + GPIO_PORT_H, /*!< 7: PH */ + GPIO_PORT_J, /*!< 8: PJ */ + GPIO_PORT_K, /*!< 9: PK */ + GPIO_PORT_L, /*!< 10:PL */ + GPIO_PORT_M, /*!< 11:PM */ + GPIO_PORT_N, /*!< 12:PN */ + GPIO_PORT_U, /*!< 13:PU */ + GPIO_PORT_V, /*!< 14:PV */ + GPIO_GROUP_Max /*!< Max Number */ +} gpio_gr_t; + +/** + * @enum gpio_num_t + * @brief Port Number Enumerated Type Definition. + */ +typedef enum { + GPIO_PORT_0 = 0x0, /*!< 0: Port0 */ + GPIO_PORT_1 = 0x1, /*!< 1: Port1 */ + GPIO_PORT_2 = 0x2, /*!< 2: Port2 */ + GPIO_PORT_3 = 0x3, /*!< 3: Port3 */ + GPIO_PORT_4 = 0x4, /*!< 4: Port4 */ + GPIO_PORT_5 = 0x5, /*!< 5: Port5 */ + GPIO_PORT_6 = 0x6, /*!< 6: Port6 */ + GPIO_PORT_7 = 0x7, /*!< 7: Port7 */ + GPIO_PORT_Max = 0x08 /*!< Max Number */ +} gpio_num_t; + +/** + * @enum gpio_mode_t + * @brief Port Mode Enumerated Type Definition. + */ +typedef enum { + GPIO_Mode_DATA = 0x0, /*!< 0x0: PxDATA */ + GPIO_Mode_CR = 0x4, /*!< 0x4: PxCR */ + GPIO_Mode_FR1 = 0x8, /*!< 0x8: PxFR1 */ + GPIO_Mode_FR2 = 0xC, /*!< 0xC: PxFR2 */ + GPIO_Mode_FR3 = 0x10, /*!< 0x10: PxFR3 */ + GPIO_Mode_FR4 = 0x14, /*!< 0x14: PxFR4 */ + GPIO_Mode_FR5 = 0x18, /*!< 0x18: PxFR5 */ + GPIO_Mode_FR6 = 0x1C, /*!< 0x1C: PxFR6 */ + GPIO_Mode_FR7 = 0x20, /*!< 0x1C: PxFR7 */ + GPIO_Mode_OD = 0x28, /*!< 0x28: PxOD */ + GPIO_Mode_PUP = 0x2C, /*!< 0x2C: PxPUP */ + GPIO_Mode_PDN = 0x30, /*!< 0x30: PxPDN */ + GPIO_Mode_IE = 0x38 /*!< 0x38: PxIE */ +} gpio_mode_t; + +/** + * @enum gpio_fr_t + * @brief Port Function Number Enumerated Type Definition. + */ +typedef enum { + GPIO_FR_1 = 1, /*!< 1: PxFR1 */ + GPIO_FR_2, /*!< 2: PxFR2 */ + GPIO_FR_3, /*!< 3: PxFR3 */ + GPIO_FR_4, /*!< 4: PxFR4 */ + GPIO_FR_5, /*!< 5: PxFR5 */ + GPIO_FR_6, /*!< 6: PxFR6 */ + GPIO_FR_7, /*!< 7: PxFR7 */ + GPIO_FR_NA, /*!< 8: N/A */ + GPIO_FR_Max, /*!< Max Number */ +} gpio_fr_t; +/** + * @enum gpio_pa0_func_t + * @brief PortA0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA0_TSPI0CSIN = 0x1, /*!< 1: TSPI0CSIN */ + GPIO_PA0_T32A00INB0 = 0x4, /*!< 4: T32A00INB0 */ +} gpio_pa0_func_t; + +/** + * @enum gpio_pa1_func_t + * @brief PortA1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA1_INT15 = 0x0, /*!< 0: INT15 */ + GPIO_PA1_TSPI0CS1 = 0x1, /*!< 1: TSPI0CS1 */ + GPIO_PA1_T32A00INB1 = 0x4, /*!< 4: T32A00INB1 */ +} gpio_pa1_func_t; + +/** + * @enum gpio_pa2_func_t + * @brief PortA2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA2_INT00 = 0x0, /*!< 0: INT00 */ + GPIO_PA2_TSPI0RXD = 0x1, /*!< 1: TSPI0RXD */ + GPIO_PA2_T32A00INA0 = 0x4, /*!< 4: T32A00INA0 */ + GPIO_PA2_T32A00INC0 = 0x5, /*!< 5: T32A00INC0 */ + GPIO_PA2_PMD2DBG = 0x6, /*!< 6: PMD2DBG */ + GPIO_PA2_TRGIN0 = 0x7, /*!< 7: TRGIN0 */ +} gpio_pa2_func_t; + +/** + * @enum gpio_pa3_func_t + * @brief PortA3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA3_INT01b = 0x0, /*!< 0: INT00 */ + GPIO_PA3_TSPI0TXD = 0x1, /*!< 1: TSPI0TXD */ + GPIO_PA3_T32A00OUTA = 0x4, /*!< 4: T32A00OUTA */ + GPIO_PA3_T32A00OUTC = 0x5, /*!< 5: T32A00OUTC */ + GPIO_PA3_TRGIN1 = 0x7, /*!< 7: TRGIN1 */ +} gpio_pa3_func_t; + +/** + * @enum gpio_pa4_func_t + * @brief PortA4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PA4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PA4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PA4_INT01a = 0x0, /*!< 0: INT01a */ + GPIO_PA4_TSPI0SCK = 0x1, /*!< 1: TSPI0SCK */ + GPIO_PA4_T32A00OUTB = 0x4, /*!< 4: T32A00OUTB */ + GPIO_PA4_TRGIN2 = 0x7, /*!< 7: TRGIN2 */ +} gpio_pa4_func_t; + +/** + * @enum gpio_pb0_func_t + * @brief PortB0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB0_UO0 = 0x4, /*!< 4: UO0 */ +} gpio_pb0_func_t; + +/** + * @enum gpio_pb1_func_t + * @brief PortB1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB1_XO0 = 0x4, /*!< 4: XO0 */ +} gpio_pb1_func_t; + +/** + * @enum gpio_pb2_func_t + * @brief PortB2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB2_VO0 = 0x4, /*!< 4: VO0 */ +} gpio_pb2_func_t; + +/** + * @enum gpio_pb3_func_t + * @brief PortB3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB3_YO0 = 0x4, /*!< 4: YO0 */ +} gpio_pb3_func_t; + +/** + * @enum gpio_pb4_func_t + * @brief PortB4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB4_WO0 = 0x4, /*!< 4: WO0 */ +} gpio_pb4_func_t; + +/** + * @enum gpio_pb5_func_t + * @brief PortB5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB5_ZO0 = 0x4, /*!< 4: ZO0 */ +} gpio_pb5_func_t; + +/** + * @enum gpio_pb6_func_t + * @brief PortB6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB6_EMG0 = 0x4, /*!< 4: EMG0 */ +} gpio_pb6_func_t; + +/** + * @enum gpio_pb7_func_t + * @brief PortB7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PB7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PB7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PB7_OVV0 = 0x4, /*!< 4: OVV0 */ + GPIO_PB7_PMD0DBG = 0x5, /*!< 5: PMD0DBG */ +} gpio_pb7_func_t; + +/** + * @enum gpio_pc0_func_t + * @brief PortC0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC0_UT0TXDA = 0x1, /*!< 1: UT0TXDA */ + GPIO_PC0_UT0RXD = 0x2, /*!< 2: UT0RXD */ + GPIO_PC0_EI2C0SDA = 0x3, /*!< 3: EI2C0SDA */ + GPIO_PC0_I2C0SDA = 0x4, /*!< 4: I2C0SDA */ + GPIO_PC0_T32A02INA0 = 0x5, /*!< 5: T32A02INA0 */ + GPIO_PC0_T32A02INC0 = 0x6, /*!< 6: T32A02INC0 */ +} gpio_pc0_func_t; + +/** + * @enum gpio_pc1_func_t + * @brief PortC1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC1_INT02a = 0x0, /*!< 0: INT10 */ + GPIO_PC1_UT0RXD = 0x1, /*!< 1: UT3RXD */ + GPIO_PC1_UT0TXDA = 0x2, /*!< 2: UT3TXDA */ + GPIO_PC1_EI2C0SCL = 0x3, /*!< 3: TSPI3RXD */ + GPIO_PC1_I2C0SCL = 0x4, /*!< 4: T32A3INA0 */ + GPIO_PC1_T32A02OUTA = 0x5, /*!< 5: T32A2INC0 */ + GPIO_PC1_T32A02OUTC = 0x6, /*!< 5: T32A2INC0 */ +} gpio_pc1_func_t; + +/** + * @enum gpio_pc2_func_t + * @brief PortC2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC2_INT10 = 0x0, /*!< 0: INT10 */ + GPIO_PC2_TSPI0CS0 = 0x3, /*!< 3: TSPI0CS0 */ + GPIO_PC2_T32A03OUTA = 0x5, /*!< 5: T32A03OUTA */ + GPIO_PC2_T32A03OUTC = 0x6, /*!< 6: T32A03OUTC */ + GPIO_PC2_PMD0DBG = 0x7, /*!< 7: PMD0DBG */ +} gpio_pc2_func_t; + +/** + * @enum gpio_pc3_func_t + * @brief PortC3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC3_INT03a = 0x0, /*!< 0: INT03a */ + GPIO_PC3_TSPI0RXD = 0x3, /*!< 3: TSPI0CS0 */ + GPIO_PC3_T32A03OUTB = 0x5, /*!< 5: T32A03OUTB */ + GPIO_PC3_PMD1DBG = 0x7, /*!< 7: PMD1DBG */ +} gpio_pc3_func_t; + +/** + * @enum gpio_pc4_func_t + * @brief PortC4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC4_UT1TXDA = 0x1, /*!< 1: UT1TXDA */ + GPIO_PC4_UT1RXD = 0x2, /*!< 2: UT1RXD */ + GPIO_PC4_TSPI0TXD = 0x3, /*!< 3: TSPI0TXD */ +} gpio_pc4_func_t; + +/** + * @enum gpio_pc5_func_t + * @brief PortC5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC5_UT1RXD = 0x1, /*!< 1: UT1RXD */ + GPIO_PC5_UT1TXDA = 0x2, /*!< 2: UT1TXDA */ + GPIO_PC5_TSPI0SCK = 0x3, /*!< 3: TSPI0SCK */ +} gpio_pc5_func_t; + +/** + * @enum gpio_pc6_func_t + * @brief PortC6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC6_INT02b = 0x0, /*!< 0: INT02b */ + GPIO_PC6_TSPI0CS1 = 0x3, /*!< 3: TSPI0CS1 */ + GPIO_PC6_T32A02INA1 = 0x5, /*!< 5: T32A02INA1 */ + GPIO_PC6_T32A02INC1 = 0x6, /*!< 6: T32A02INC1 */ +} gpio_pc6_func_t; +/** + * @enum gpio_pc7_func_t + * @brief PortC7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PC7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PC7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PC7_TSPI0CSIN = 0x3, /*!< 3: TSPI0CSIN */ + GPIO_PC7_T32A02INB0 = 0x5, /*!< 5: T32A02INB0 */ +} gpio_pc7_func_t; + +/** + * @enum gpio_pd0_func_t + * @brief PortD0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD0_INT17b = 0x0, /*!< 0: INT17b */ + GPIO_PD0_T32A02INB1 = 0x4, /*!< 4: T32A02INB1 */ +} gpio_pd0_func_t; + +/** + * @enum gpio_pd1_func_t + * @brief PortD1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD1_INT17a = 0x0, /*!< 0: INT17a */ + GPIO_PD1_T32A02OUTB = 0x4, /*!< 4: T32A02OUTB */ +} gpio_pd1_func_t; + +/** + * @enum gpio_pd2_func_t + * @brief PortD2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD2_INT03b = 0x0, /*!< 0: INT03b */ + GPIO_PD2_UT0CTS_N = 0x1, /*!< 1: UT0CTS_N */ + GPIO_PD2_T32A03INA0 = 0x4, /*!< 4: T32A03INA0 */ + GPIO_PD2_T32A03INC0 = 0x5, /*!< 5: T32A03INC0 */ +} gpio_pd2_func_t; + +/** + * @enum gpio_pd3_func_t + * @brief PortD3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD3_UT0RTS_N = 0x1, /*!< 1: UT0RTS_N */ + GPIO_PD3_I2C1SDA = 0x2, /*!< 2: I2C1SDA */ + GPIO_PD3_EI2C1SDA = 0x3, /*!< 3: EI2C1SDA */ + GPIO_PD3_T32A03INA1 = 0x4, /*!< 4: T32A03INA1 */ + GPIO_PD3_T32A03INC1 = 0x5, /*!< 5: T32A03INC1 */ + GPIO_PD3_ENC2A = 0x6, /*!< 6: ENC2A */ +} gpio_pd3_func_t; + +/** + * @enum gpio_pd4_func_t + * @brief PortD4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD4_INT18b = 0x0, /*!< 0: INT18b */ + GPIO_PD4_I2C1SCL = 0x2, /*!< 2: I2C1SCL */ + GPIO_PD4_EI2C1SCL = 0x3, /*!< 3: EI2C1SCL */ + GPIO_PD4_T32A03INB0 = 0x4, /*!< 4: T32A03INB0 */ + GPIO_PD4_ENC2B = 0x6, /*!< 6: ENC2B */ +} gpio_pd4_func_t; + +/** + * @enum gpio_pd5_func_t + * @brief PortD5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PD5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PD5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PD5_INT18a = 0x0, /*!< 0: INT18a */ + GPIO_PD5_T32A03INB1 = 0x4, /*!< 4: T32A03INB1 */ + GPIO_PD5_ENC2Z = 0x6, /*!< 6: ENC2Z */ +} gpio_pd5_func_t; + +/** + * @enum gpio_pe0_func_t + * @brief PortE0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE0_UO1 = 0x6, /*!< 6: UO1 */ +} gpio_pe0_func_t; + +/** + * @enum gpio_pe1_func_t + * @brief PortE1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE1_INT04b = 0x0, /*!< 0: INT04b */ + GPIO_PE1_T32A03INA0 = 0x4, /*!< 4: T32A03INA0 */ + GPIO_PE1_T32A03INC0 = 0x5, /*!< 5: T32A03INC0 */ + GPIO_PE1_XO1 = 0x6, /*!< 6: XO1 */ +} gpio_pe1_func_t; + +/** + * @enum gpio_pe2_func_t + * @brief PortE2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE2_T32A03OUTA = 0x4, /*!< 4: T32A03OUTA */ + GPIO_PE2_T32A03OUTC = 0x5, /*!< 5: T32A03OUTC */ + GPIO_PE2_VO1 = 0x6, /*!< 6: VO1 */ +} gpio_pe2_func_t; + +/** +* @enum gpio_pe3_func_t +* @brief PortE3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE3_INT04a = 0x0, /*!< 0: INT04a */ + GPIO_PE3_T32A03INA1 = 0x4, /*!< 4: T32A03INA1 */ + GPIO_PE3_T32A03INC1 = 0x5, /*!< 5: T32A03INC1 */ + GPIO_PE3_YO1 = 0x6, /*!< 6: YO1 */ +} gpio_pe3_func_t; + +/** +* @enum gpio_pe4_func_t +* @brief PortE4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PE4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE4_INT11a = 0x0, /*!< 0: INT11a */ + GPIO_PE4_T32A03INB0 = 0x4, /*!< 4: T32A03INB0 */ + GPIO_PE4_WO1 = 0x6, /*!< 6: WO1 */ +} gpio_pe4_func_t; + +/** + * @enum gpio_pe5_func_t + * @brief PortE5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE5_INT05a = 0x0, /*!< 0: INT05a */ + GPIO_PE5_INT11b = 0x0, /*!< 0: INT11b */ + GPIO_PE5_T32A03INB1 = 0x4, /*!< 4: T32A03INB1 */ + GPIO_PE5_ZO1 = 0x6, /*!< 6: ZO1 */ +} gpio_pe5_func_t; + +/** + * @enum gpio_pe6_func_t + * @brief PortE6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE6_INT05b = 0x0, /*!< 0: INT05a */ + GPIO_PE6_T32A03OUTB = 0x4, /*!< 4: T32A03OUTB */ + GPIO_PE6_EMG1 = 0x6, /*!< 6: EMG1 */ +} gpio_pe6_func_t; + +/** + * @enum gpio_pe7_func_t + * @brief PortE7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PE7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PE7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PE7_OVV1 = 0x6, /*!< 6: OVV1 */ + GPIO_PE7_PMD1DBG = 0x7, /*!< 7: PMD1DBG */ +} gpio_pe7_func_t; + +/** + * @enum gpio_pf0_func_t + * @brief PortF0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF0_UT2TXDA = 0x1, /*!< 1: UT2TXDA */ + GPIO_PF0_UT2RXD = 0x2, /*!< 2: UT2RXD */ + GPIO_PF0_T32A05INA0 = 0x4, /*!< 4: T32A05INA0 */ + GPIO_PF0_T32A05INC0 = 0x5, /*!< 5: T32A05INC0 */ + GPIO_PF0_TMS_SWDIO = 0x7, /*!< 7: TMS_SWDIO */ +} gpio_pf0_func_t; + +/** + * @enum gpio_pf1_func_t + * @brief PortF1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF1_INT06a = 0x0, /*!< 0: INT06a */ + GPIO_PF1_UT2RXD = 0x1, /*!< 1: UT2RXD */ + GPIO_PF1_UT2TXDA = 0x2, /*!< 2: UT2TXDA */ + GPIO_PF1_T32A05OUTA = 0x4, /*!< 4: T32A05OUTA */ + GPIO_PF1_T32A05OUTC = 0x5, /*!< 5: T32A05OUTC */ + GPIO_PF1_TCK_SWCLK = 0x7, /*!< 7: TCK_SWCLK */ +} gpio_pf1_func_t; + +/** + * @enum gpio_pf2_func_t + * @brief PortF2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF2_INT06b = 0x0, /*!< 0: INT06b */ + GPIO_PF2_T32A05INA1 = 0x4, /*!< 4: T32A05INA1 */ + GPIO_PF2_T32A05INC1 = 0x5, /*!< 5: TRGIN2 */ + GPIO_PF2_TDO_SWV = 0x7, /*!< 7: TDO_SWV */ +} gpio_pf2_func_t; + +/** + * @enum gpio_pf3_func_t + * @brief PortF3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF3_UT3TXDA = 0x1, /*!< 1: UT3TXDA */ + GPIO_PF3_UT3RXD = 0x2, /*!< 2: UT3RXD */ + GPIO_PF3_T32A01INA0 = 0x4, /*!< 4: T32A01INA0 */ + GPIO_PF3_T32A01INC0 = 0x5, /*!< 5: T32A01INC0 */ + GPIO_PF3_ENC1A = 0x6, /*!< 6: ENC1A */ + GPIO_PF3_TDI = 0x7, /*!< 7: TDI */ +} gpio_pf3_func_t; + +/** + * @enum gpio_pf4_func_t + * @brief PortF4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF4_INT14a = 0x0, /*!< 0: INT14a */ + GPIO_PF4_UT3RXD = 0x1, /*!< 1: UT3RXD */ + GPIO_PF4_UT3TXDA = 0x2, /*!< 2: UT3TXDA */ + GPIO_PF4_NBDSYNC = 0x3, /*!< 3: NBDSYNC */ + GPIO_PF4_T32A01OUTA = 0x4, /*!< 4: NBDSYNC */ + GPIO_PF4_T32A01OUTC = 0x5, /*!< 5: T32A01OUTC */ + GPIO_PF4_ENC1B = 0x6, /*!< 6: ENC1B */ + GPIO_PF4_TRST_N = 0x7, /*!< 7: TRST_N */ +} gpio_pf4_func_t; + +/** + * @enum gpio_pf5_func_t + * @brief PortF5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF5_INT14b = 0x0, /*!< 0: INT14b */ + GPIO_PF5_NBDCLK = 0x3, /*!< 3: NBDCLK */ + GPIO_PF5_T32A01INA1 = 0x4, /*!< 4: T32A01INA1 */ + GPIO_PF5_T32A01INC1 = 0x5, /*!< 5: T32A01INC1 */ + GPIO_PF5_ENC1Z = 0x6, /*!< 6: ENC1Z */ + GPIO_PF5_TRACECLK = 0x7, /*!< 7: TRACECLK */ +} gpio_pf5_func_t; + +/** + * @enum gpio_pf6_func_t + * @brief PortF6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF6_UT3TXDA = 0x1, /*!< 1: UT3TXDA */ + GPIO_PF6_UT3RXD = 0x2, /*!< 2: UT3RXD */ + GPIO_PF6_NBDDATA0 = 0x3, /*!< 3: NBDDATA0 */ + GPIO_PF6_T32A01INB0 = 0x4, /*!< 4: T32A01INB0 */ + GPIO_PF6_TRACEDATA0 = 0x7, /*!< 7: TRACEDATA0 */ +} gpio_pf6_func_t; + +/** + * @enum gpio_pf7_func_t + * @brief PortF7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PF7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PF7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PF7_UT3RXD = 0x1, /*!< 1: UT3RXD */ + GPIO_PF7_UT3TXDA = 0x2, /*!< 2: UT3TXDA */ + GPIO_PF7_NBDDATA1 = 0x3, /*!< 3: NBDDATA1 */ + GPIO_PF7_T32A01INB1 = 0x4, /*!< 4: T32A01INB1 */ + GPIO_PF7_TRACEDATA1 = 0x7, /*!< 7: TRACEDATA1 */ +} gpio_pf7_func_t; + +/** + * @enum gpio_pg0_func_t + * @brief PortG0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PG0_T32A04INA0 = 0x4, /*!< 4: T32A04INA0 */ + GPIO_PG0_T32A04INC0 = 0x5, /*!< 5: T32A04INC0 */ +} gpio_pg0_func_t; + +/** + * @enum gpio_pg1_func_t + * @brief PortG1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG1_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG1_TSPI1CS1 = 0x1, /*!< 1: TSPI1CS1 */ + GPIO_PG1_T32A04INA1 = 0x4, /*!< 4: T32A04INA1 */ + GPIO_PG1_T32A04INC1 = 0x5, /*!< 5: T32A04INC1 */ +} gpio_pg1_func_t; + +/** + * @enum gpio_pg2_func_t + * @brief PortG2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG2_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG2_TSPI1CS0 = 0x1, /*!< 1: TSPI1CS0 */ + GPIO_PG2_T32A04OUTA = 0x4, /*!< 4: T32A04OUTA */ + GPIO_PG2_T32A04OUTC = 0x5, /*!< 5: T32A04OUTC */ +} gpio_pg2_func_t; + +/** + * @enum gpio_pg3_func_t + * @brief PortG3 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG3_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG3_INT21 = 0x0, /*!< 0: XO1 */ + GPIO_PG3_TSPI1CSIN = 0x1, /*!< 1: TSPI1CSIN */ + GPIO_PG3_T32A04OUTB = 0x4, /*!< 4: T32A04OUTB */ +} gpio_pg3_func_t; + +/** + * @enum gpio_pg4_func_t + * @brief PortG4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG4_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG4_TSPI1RXD = 0x1, /*!< 1: TSPI1RXD */ + GPIO_PG4_T32A04INB0 = 0x4, /*!< 4: T32A04INB0 */ +} gpio_pg4_func_t; + +/** + * @enum gpio_pg5_func_t + * @brief PortG5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG5_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG5_TSPI1TXD = 0x1, /*!< 1: TSPI1TXD */ + GPIO_PG5_T32A04INB1 = 0x4, /*!< 4: T32A04INB1 */ +} gpio_pg5_func_t; + +/** + * @enum gpio_pg6_func_t + * @brief PortG6 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PG6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PG6_OUTUT = 0x0, /*!< 0: Output Port */ + GPIO_PG6_TSPI1SCK = 0x1, /*!< 1: TSPI1TXD */ +} gpio_pg6_func_t; + +/** + * @enum gpio_ph0_func_t + * @brief PortH0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PH0_X1 = 0x0, /*!< 0: X1 */ + GPIO_PH0_EHCLKIN = 0x0, /*!< 0: X1 */ +} gpio_ph0_func_t; + +/** + * @enum gpio_ph1_func_t + * @brief PortH1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PH1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PH1_X2 = 0x0, /*!< 0: X2 */ +} gpio_ph1_func_t; + +/** + * @enum gpio_pj0_func_t + * @brief PortJ0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ0_AINC00 = 0x0, /*!< 0: AINC00 */ +} gpio_pj0_func_t; + +/** + * @enum gpio_pj1_func_t + * @brief PortJ1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ1_AINC01 = 0x0, /*!< 0: AINC01 */ +} gpio_pj1_func_t; + +/** + * @enum gpio_pj2_func_t + * @brief PortJ2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ2_AINC02 = 0x0, /*!< 0: AINC02 */ +} gpio_pj2_func_t; + +/** +* @enum gpio_pj3_func_t +* @brief PortJ3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ3_AINC03 = 0x0, /*!< 0: AINC03 */ +} gpio_pj3_func_t; + +/** +* @enum gpio_pj4_func_t +* @brief PortJ4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PJ4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ4_AINC04 = 0x0, /*!< 0: AINC04 */ +} gpio_pj4_func_t; + +/** + * @enum gpio_pj5_func_t + * @brief PortJ5 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PJ5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PJ5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PJ5_AINC05 = 0x0, /*!< 0: AINC05 */ +} gpio_pj5_func_t; + +/** + * @enum gpio_pk0_func_t + * @brief PortK0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK0_AINB00 = 0x0, /*!< 0: AINB00 */ +} gpio_pk0_func_t; + +/** + * @enum gpio_pk1_func_t + * @brief PortK1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK1_AINB01 = 0x0, /*!< 0: AINB01 */ +} gpio_pk1_func_t; + +/** + * @enum gpio_pk2_func_t + * @brief PortK2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PK2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK2_AINB02 = 0x0, /*!< 0: AINB02 */ +} gpio_pk2_func_t; + +/** +* @enum gpio_pk3_func_t +* @brief PortK3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK3_AINB03 = 0x0, /*!< 0: AINB03 */ +} gpio_pk3_func_t; + +/** +* @enum gpio_pk4_func_t +* @brief PortK4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PK4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PK4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PK4_AINB04 = 0x0, /*!< 0: AINB01 */ +} gpio_pk4_func_t; + +/** + * @enum gpio_pl0_func_t + * @brief PortL0 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL0_AINA16 = 0x0, /*!< 0: AINA16 */ +} gpio_pl0_func_t; + +/** + * @enum gpio_pl1_func_t + * @brief PortL1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL1_AINA15 = 0x0, /*!< 0: AINA15 */ +} gpio_pl1_func_t; + +/** + * @enum gpio_pl2_func_t + * @brief PortL2 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PL2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL2_AINA17 = 0x0, /*!< 0: NBDDATA2 */ +} gpio_pl2_func_t; + +/** +* @enum gpio_pl3_func_t +* @brief PortL3 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL3_AINA14 = 0x0, /*!< 0: AINA14 */ +} gpio_pl3_func_t; + +/** +* @enum gpio_pl4_func_t +* @brief PortL4 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL4_AINA18 = 0x0, /*!< 0: AINA18 */ +} gpio_pl4_func_t; + +/** +* @enum gpio_pl5_func_t +* @brief PortL5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL5_AINA13 = 0x0, /*!< 0: AINA13 */ +} gpio_pl5_func_t; + +/** +* @enum gpio_pl6_func_t +* @brief PortL6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL6_AINA09 = 0x0, /*!< 0: AINA09 */ +} gpio_pl6_func_t; + +/** +* @enum gpio_pl7_func_t +* @brief PortL7 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PL7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PL7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PL7_AINA08 = 0x0, /*!< 0: AINA08 */ +} gpio_pl7_func_t; + +/** +* @enum gpio_pm0_func_t +* @brief PortM0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PM0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PM0_AINA07 = 0x0, /*!< 0: AINA07 */ +} gpio_pm0_func_t; + +/** + * @enum gpio_pm1_func_t + * @brief PortM1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PM1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PM1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PM1_AINA06 = 0x0, /*!< 0: AINA06 */ +} gpio_pm1_func_t; + +/** +* @enum gpio_pm2_func_t +* @brief PortM2 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PM2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PM2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PM2_AINA05 = 0x0, /*!< 0: AINA05 */ +} gpio_pm2_func_t; + +/** +* @enum gpio_pn0_func_t +* @brief PortN0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PN0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PN0_UT0TXDA = 0x1, /*!< 0: UT0TXDA */ + GPIO_PN0_UT0RXD = 0x2, /*!< 0: UT0RXD */ + GPIO_PN0_NBDDATA2 = 0x3, /*!< 0: NBDDATA2 */ + GPIO_PN0_T32A05INA0 = 0x4, /*!< 0: T32A05INA0 */ + GPIO_PN0_T32A05INC0 = 0x5, /*!< 0: T32A05INC0 */ + GPIO_PN0_ENC0A = 0x6, /*!< 0: ENC0A */ + GPIO_PN0_TRACEDATA2 = 0x7, /*!< 0: TRACEDATA2 */ +} gpio_pn0_func_t; + +/** + * @enum gpio_pn1_func_t + * @brief PortN1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PN1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PN1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PN1_INT16a = 0x0, /*!< 0: INT16a */ + GPIO_PN1_UT0RXD = 0x1, /*!< 0: UT0RXD */ + GPIO_PN1_UT0TXDA = 0x2, /*!< 0: UT0TXDA */ + GPIO_PN1_NBDDATA3 = 0x3, /*!< 0: NBDDATA3 */ + GPIO_PN1_T32A05OUTA = 0x4, /*!< 0: T32A05OUTA */ + GPIO_PN1_T32A05OUTC = 0x5, /*!< 0: T32A05OUTC */ + GPIO_PN1_ENC0B = 0x6, /*!< 0: ENC0B */ + GPIO_PN1_TRACEDATA3 = 0x7, /*!< 0: TRACEDATA3 */ +} gpio_pn1_func_t; + +/** +* @enum gpio_pn2_func_t +* @brief PortN2 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PN2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PN2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PN2_INT16b = 0x0, /*!< 0: INT16b */ + GPIO_PN2_UT0CTS_N = 0x1, /*!< 0: UT0CTS */ + GPIO_PN2_T32A05INA1 = 0x4, /*!< 0: T32A05INA1 */ + GPIO_PN2_T32A05INC1 = 0x5, /*!< 0: T32A05INC1 */ + GPIO_PN2_ENC0Z = 0x6, /*!< 0: ENC0Z */ +} gpio_pn2_func_t; +/** +* @enum gpio_pu0_func_t +* @brief PortU0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU0_INT12 = 0x0, /*!< 0: INT12 */ + GPIO_PU0_UT2TXDA = 0x1, /*!< 0: UT2TXDA */ + GPIO_PU0_UT2RXD = 0x2, /*!< 0: UT2RXD */ + GPIO_PU0_I2C1SDA = 0x3, /*!< 0: I2C1SDA */ + GPIO_PU0_T32A02INB1 = 0x4, /*!< 0: T32A02INB1 */ + GPIO_PU0_UO2 = 0x6, /*!< 0: UO2 */ + GPIO_PU0_EI2C1SDA = 0x7, /*!< 0: EI2C1SDA */ +} gpio_pu0_func_t; + +/** + * @enum gpio_pu1_func_t + * @brief PortU1 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU1_INT07a = 0x0, /*!< 0: INT07a */ + GPIO_PU1_UT2RXD = 0x1, /*!< 0: UT2RXD */ + GPIO_PU1_UT2TXDA = 0x2, /*!< 0: UT2TXDA */ + GPIO_PU1_I2C1SCL = 0x3, /*!< 0: I2C1SCL */ + GPIO_PU1_T32A02INA0 = 0x4, /*!< 0: T32A02INA0 */ + GPIO_PU1_T32A02INC0 = 0x5, /*!< 0: T32A02INC0 */ + GPIO_PU1_XO2 = 0x6, /*!< 0: XO2 */ + GPIO_PU1_EI2C1SCL = 0x7, /*!< 0: EI2C1SCL */ +} gpio_pu1_func_t; + +/** +* @enum gpio_pu2_func_t +* @brief PortU2 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU2_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU2_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU2_INT07b = 0x0, /*!< 0: INT07b */ + GPIO_PU2_T32A02OUTA = 0x4, /*!< 0: T32A02OUTA */ + GPIO_PU2_T32A02OUTC = 0x5, /*!< 0: T32A02OUTC */ + GPIO_PU2_VO2 = 0x6, /*!< 0: VO2 */ +} gpio_pu2_func_t; +/** +* @enum gpio_pu3_func_t +* @brief PortU0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU3_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU3_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU3_INT08a = 0x0, /*!< 0: INT08a */ + GPIO_PU3_UT1RTS_N = 0x1, /*!< 0: UT1RTS_N */ + GPIO_PU3_T32A02INB0 = 0x4, /*!< 0: T32A02INB0 */ + GPIO_PU3_ENC2A = 0x5, /*!< 0: ENC2A */ + GPIO_PU3_YO2 = 0x6, /*!< 0: YO2 */ +} gpio_pu3_func_t; + +/** + * @enum gpio_pu4_func_t + * @brief PortU4 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU4_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU4_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU4_INT08b = 0x0, /*!< 0: INT08b */ + GPIO_PU4_UT1CTS_N = 0x1, /*!< 0: UT1CTS_N */ + GPIO_PU4_T32A02OUTB = 0x4, /*!< 0: T32A02OUTB */ + GPIO_PU4_T32A02INC1 = 0x5, /*!< 0: T32A02INC1 */ + GPIO_PU4_WO2 = 0x6, /*!< 0: WO2 */ +} gpio_pu4_func_t; + +/** +* @enum gpio_pu5_func_t +* @brief PortU5 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU5_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU5_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU5_INT13 = 0x0, /*!< 0: INT13 */ + GPIO_PU5_UT1TXDA = 0x1, /*!< 0: UT1TXDA */ + GPIO_PU5_UT1RXD = 0x2, /*!< 0: UT1RXD */ + GPIO_PU5_T32A02INA1 = 0x4, /*!< 0: T32A02INA1 */ + GPIO_PU5_ENC2B = 0x5, /*!< 0: ENC2B */ + GPIO_PU5_ZO2 = 0x6, /*!< 0: ZO2 */ +} gpio_pu5_func_t; + +/** +* @enum gpio_pu6_func_t +* @brief PortU6 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PU6_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU6_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU6_INT09 = 0x0, /*!< 0: INT09 */ + GPIO_PU6_UX1RXD = 0x1, /*!< 0: UX1RXD */ + GPIO_PU6_UT1TXDA = 0x2, /*!< 0: UT1TXDA */ + GPIO_PU6_ENC2Z = 0x5, /*!< 0: ENC2Z */ + GPIO_PU6_EMG2 = 0x6, /*!< 0: EMG2 */ +} gpio_pu6_func_t; + +/** + * @enum gpio_pu7_func_t + * @brief PortU7 Function Enumerated Type Definition. + */ +typedef enum { + GPIO_PU7_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PU7_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PU7_OVV2 = 0x6, /*!< 0: OVV2 */ + GPIO_PU7_PMD2DBG = 0x7, /*!< 0: PMD2DBG */ +} gpio_pu7_func_t; + +/** +* @enum gpio_pv0_func_t +* @brief PortV0 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PV0_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PV0_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PV0_TSPI1CSIN = 0x2, /*!< 0: TSPI1CSIN */ + GPIO_PV0_T32A01OUTB = 0x4, /*!< 0: T32A01OUTB */ +} gpio_pv0_func_t; + +/** +* @enum gpio_pv1_func_t +* @brief PortV1 Function Enumerated Type Definition. +*/ +typedef enum { + GPIO_PV1_INPUT = 0x0, /*!< 0: Input Port */ + GPIO_PV1_OUTPUT = 0x0, /*!< 0: Output Port */ + GPIO_PV1_UT0RTS_N = 0x1, /*!< 0: UT0RTS_N */ + GPIO_PV1_TSPI1RXD = 0x2, /*!< 0: TSPI1RXD */ +} gpio_pv1_func_t; + +/** + * @} + */ /* End of group GPIO_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_Typedef GPIO Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief GPIO handle structure definenition. +*/ +/*----------------------------------*/ + +typedef struct gpio_pa_handle { + TSB_PA_TypeDef *p_pa_instance; /*!< Registers base address. */ + TSB_PB_TypeDef *p_pb_instance; /*!< Registers base address. */ + TSB_PC_TypeDef *p_pc_instance; /*!< Registers base address. */ + TSB_PD_TypeDef *p_pd_instance; /*!< Registers base address. */ + TSB_PE_TypeDef *p_pe_instance; /*!< Registers base address. */ + TSB_PF_TypeDef *p_pf_instance; /*!< Registers base address. */ + TSB_PG_TypeDef *p_pg_instance; /*!< Registers base address. */ + TSB_PH_TypeDef *p_ph_instance; /*!< Registers base address. */ + TSB_PJ_TypeDef *p_pj_instance; /*!< Registers base address. */ + TSB_PK_TypeDef *p_pk_instance; /*!< Registers base address. */ + TSB_PL_TypeDef *p_pl_instance; /*!< Registers base address. */ + TSB_PM_TypeDef *p_pm_instance; /*!< Registers base address. */ + TSB_PN_TypeDef *p_pn_instance; /*!< Registers base address. */ + TSB_PU_TypeDef *p_pu_instance; /*!< Registers base address. */ + TSB_PV_TypeDef *p_pv_instance; /*!< Registers base address. */ +} _gpio_t; + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Exported_functions GPIO Exported Functions + * @{ + */ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group); +TXZ_Result gpio_func(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func, uint32_t inout); +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val); +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val); +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate); + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __GPIO_H */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c.h new file mode 100644 index 00000000000..34493c222e1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c.h @@ -0,0 +1,819 @@ +/** + ******************************************************************************* + * @file txzp_i2c.h + * @brief This file provides all the functions prototypes for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_H +#define __I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +#ifdef DEBUG +/** + * @name I2C_NULL Pointer + * @brief NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of name I2C_NULL Pointer */ +#endif + +/** + * @name I2CxST Macro Definition. + * @brief I2CxST Register Macro Definition. + * @{ + */ +#define I2CxST_NACK ((uint32_t)0x00000008) /*!< NACK Interrupt Status. */ +#define I2CxST_I2CBF ((uint32_t)0x00000004) /*!< I2CBF Interrupt Status. */ +#define I2CxST_I2CAL ((uint32_t)0x00000002) /*!< I2CAL Interrupt Status. */ +#define I2CxST_I2C ((uint32_t)0x00000001) /*!< I2C Interrupt Status. */ +#define I2CxST_CLEAR ((uint32_t)0x0000000F) /*!< All Bits Clear. */ +/** + * @} + */ /* End of name I2CxST Macro Definition */ + +/** + * @name I2CxCR1 Macro Definition. + * @brief I2CxCR1 Register Macro Definition. + * @{ + */ +#define I2CxCR1_ACK ((uint32_t)0x00000010) /*!< ACK */ +#define I2CxCR1_NOACK ((uint32_t)0x00000008) /*!< NOACK */ +#define I2CxCR1_BC ((uint32_t)0x000000E0) /*!< BC */ + +/** + * @} + */ /* End of name I2CxCR1 Macro Definition */ + +/** + * @name I2CxDBR Macro Definition. + * @brief I2CxDBR Register Macro Definition. + * @{ + */ +#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF) /* !< DB 7-0 bits mask. */ +/** + * @} + */ /* End of name I2CxDBR Macro Definition */ + + +/** + * @name I2CxCR2 Macro Definition. + * @brief I2CxCR2 Register Macro Definition. + * @{ + */ +#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010) /*!< PIN=1 */ +#define I2CxCR2_I2CM_DISABLE ((uint32_t)0x00000000) /*!< I2CM=0 */ +#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000008) /*!< I2CM=1 */ +#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002) /*!< SWRES=10 */ +#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001) /*!< SWRES=01 */ +#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8) /*!< MST=1,TRX=1,BB=1,PIN=1,I2CM=1 */ +#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8) /*!< MST=1,TRX=1,BB=0,PIN=1,I2CM=1 */ +#define I2CxCR2_INIT ((uint32_t)0x00000008) /*!< MST=0,TRX=0,BB=0,PIN=0,I2CM=1,SWRES=00 */ + +/** + * @} + */ /* End of name I2CxCR2 Macro Definition */ + +/** + * @name I2CxSR Macro Definition. + * @brief I2CxSR Register Macro Definition. + * @{ + */ +#define I2CxSR_MST ((uint32_t)0x00000080) /*!< MST */ +#define I2CxSR_TRX ((uint32_t)0x00000040) /*!< TRX */ +#define I2CxSR_BB ((uint32_t)0x00000020) /*!< BB */ +#define I2CxSR_PIN ((uint32_t)0x00000010) /*!< PIN */ +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +#define I2CxSR_AAS ((uint32_t)0x00000004) /*!< AAS */ +#define I2CxSR_AD0 ((uint32_t)0x00000002) /*!< AD0 */ +#define I2CxSR_LRB ((uint32_t)0x00000001) /*!< LRB */ +/** + * @} + */ /* End of name I2CxSR Macro Definition */ + +/** + * @name I2CxPRS Macro Definition. + * @brief I2CxPRS Register Macro Definition. + * @{ + */ +#define I2CxPRS_PRCK ((uint32_t)0x0000001F) /*!< PRCK */ +/** + * @} + */ /* End of name I2CxPRS Macro Definition */ + +/** + * @name I2CxIE Macro Definition. + * @brief I2CxIE Register Macro Definition. + * @{ + */ +#define I2CxIE_SELPINCD ((uint32_t)0x00000040) /*!< SELPINCD */ +#define I2CxIE_DMARI2CTX ((uint32_t)0x00000020) /*!< DMARI2CTX */ +#define I2CxIE_DMARI2CRX ((uint32_t)0x00000010) /*!< DMARI2CRX */ +#define I2CxIE_I2C ((uint32_t)0x00000001) /*!< INTI2C */ +#define I2CxIE_CLEAR ((uint32_t)0x00000000) /*!< All Clear Setting */ + +/** + * @} + */ /* End of name I2CxIE Macro Definition */ + + +/** + * @name I2CxOP Macro Definition. + * @brief I2CxOP Register Macro Definition. + * @{ + */ +#define I2CxOP_DISAL ((uint32_t)0x00000080) /*!< DISAL */ +#define I2CxOP_SA2ST ((uint32_t)0x00000040) /*!< SA2ST */ +#define I2CxOP_SAST ((uint32_t)0x00000020) /*!< SAST */ +#define I2CxOP_NFSEL ((uint32_t)0x00000010) /*!< NFSEL */ +#define I2CxOP_RSTA ((uint32_t)0x00000008) /*!< RSTA */ +#define I2CxOP_GCDI ((uint32_t)0x00000004) /*!< GDDI */ +#define I2CxOP_SREN ((uint32_t)0x00000002) /*!< SREN */ +#define I2CxOP_MFACK ((uint32_t)0x00000001) /*!< MFACK */ +#ifndef I2C_MULTI_MASTER +#define I2CxOP_INIT ((uint32_t)0x00000084) /*!< Initial Settings. */ +#else +#define I2CxOP_INIT ((uint32_t)0x00000004) /*!< Initial Settings. */ +#endif +#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084) /*!< Slave Initial Settings. */ +/** + * @} + */ /* End of name I2CxOP Macro Definition */ + +/** + * @name I2CxAR Macro Definition. + * @brief I2CxAR Register Macro Definition. + * @{ + */ +#define I2CxAR_ALS ((uint32_t)0x00000001) /*!< ALS. */ +#define I2CxAR_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ +#define I2CxAR2_INIT ((uint32_t)0x00000000) /*!< Initial Settings. */ + +/** + * @} + */ /* End of name I2CxAR Macro Definition */ + + +/** + * @name I2CxPM Macro Definition. + * @brief I2CxPM Register Macro Definition. + * @{ + */ +#define I2CxPM_SDA_SCL ((uint32_t)0x00000003) /* SDA and SCL level. */ +/** + * @} + */ /* End of name I2CxPM Macro Definition */ + +/** + * @name I2CxWUPCR_INT Macro Definition. + * @brief I2CxWUPCR_INT Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_INT_RELESE ((uint32_t)0x00000001) /* Interrupt Release. */ +#define I2CxWUPCR_INT_HOLD ((uint32_t)0x00000000) /* Interrupt setting keep it. */ +/** + * @} + */ /* End of name I2CxWUPCR_INT Macro Definition */ + +/** + * @name I2CxWUPCR_RST Macro Definition. + * @brief I2CxWUPCR_RST Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_RST_RESET ((uint32_t)0x00000010) /* I2C BUS Reset. */ +#define I2CxWUPCR_RST_RELEASE ((uint32_t)0x00000000) /* I2C BUS Reset Release. */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ + + +/** + * @name I2CxWUPCR_ACK Macro Definition. + * @brief I2CxWUPCR_ACK Register Macro Definition. + * @{ + */ +#define I2CxWUPCR_ACK ((uint32_t)0x00000020) /* ACK Output. Output "0" */ +#define I2CxWUPCR_NACK ((uint32_t)0x00000000) /* ACL No Output. Output "1" NACK Output */ +/** + * @} + */ /* End of name I2CxWUPCR_RST Macro Definition */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sck; /*!< Select internal SCL output clock frequency. */ + uint32_t prsck; /*!< Prescaler clock frequency for generating the Serial clock. */ +} I2C_clock_setting_t; + +/*----------------------------------*/ +/** + * @brief Wakeup Control setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sgcdi; /*!< Select general call detect ON/OFF. */ + uint32_t ack; /*!< Select ACK output. */ + uint32_t reset; /*!< I2C BUS Rest. */ + uint32_t intend; /*!< Interrupt release. */ +} I2CS_wup_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_clock_setting_t clock; /*!< Serial clock setting. */ +} I2C_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2CS_wup_setting_t wup; /*!< Wakeup Control setting. */ +} I2CS_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2C_TypeDef *p_instance; /*!< Registers base address. */ + I2C_initial_setting_t init; /*!< Initial setting. */ +} I2C_t; +#if defined(I2CSxWUP_EN) +/*----------------------------------*/ +/** + * @brief I2CS handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_I2CS_TypeDef *p_instance; /*!< Registers base address. */ + I2CS_initial_setting_t init; /*!< Initial setting. */ +} I2CS_t; +#endif +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj); +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj); +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj); +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data); +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack); +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj); +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx); +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj); +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr); +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj); + +/*--------------------------------------------------*/ +/** + * @brief I2C software reset. + * @param p_obj :I2C object. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_reset(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_SWRES_10; + p_obj->p_instance->CR2 = I2CxCR2_SWRES_01; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief I2C bus port high + * @param p_obj :I2C object. + * @retval true :SDA and SCL Port High. + * @retval false :Bus Error. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_port_high(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); + } + return (0); +#else + return (((p_obj->p_instance->PM & I2CxPM_SDA_SCL) == I2CxPM_SDA_SCL)); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Generate stop condition. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_stop_condition(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; + } +#else + p_obj->p_instance->CR2 = I2CxCR2_STOP_CONDITION; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Read from Data buffer + * @param p_obj :I2C object. + * @retval result :Read data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t I2C_read_data(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); + } + return (0); +#else + return (p_obj->p_instance->DBR & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Write to Data buffer. + * @param p_obj :I2C object. + * @param data :Write data. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_write_data(I2C_t *p_obj, uint32_t data) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + } +#else + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return restart condition + * @param p_obj :I2C object. + * @retval true :Restart Detected. + * @retval false :Restart Non-Detected. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_restart(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); + } + return (0); +#else + __IO uint32_t opreg = p_obj->p_instance->OP; + p_obj->p_instance->OP &= ~I2CxOP_RSTA; + return ((opreg & I2CxOP_RSTA) == I2CxOP_RSTA); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set Ack condition + * @param p_obj :I2C object. + * @param nack :1 NACK, 0 ACK. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_ack(I2C_t *p_obj, int32_t nack) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } + } +#else + if (nack) { + p_obj->p_instance->OP |= I2CxOP_MFACK; + } else { + p_obj->p_instance->OP &= ~I2CxOP_MFACK; + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return received Ack condition + * @param p_obj :I2C object. + * @retval true :NACK Received. + * @retval false :ACK Received. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_get_ack(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_LRB) == I2CxSR_LRB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return Busy condition + * @param p_obj :I2C object. + * @retval true :I2C bus busy. + * @retval false :I2C bus free. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_status_busy(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_BB) == I2CxSR_BB); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Master status + * @param p_obj :I2C object. + * @retval true :Master mode. + * @retval false :Slave mode. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_master(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_MST) == I2CxSR_MST); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Return The Transmitter + * @param p_obj :I2C object. + * @retval true :Transmitter. + * @retval false :Receiver. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_transmitter(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_TRX) == I2CxSR_TRX); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status + * @param p_obj :I2C object. + * @retval true :Interruput Occured. + * @retval false :No Interruput Occured. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_int_status(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); + } + return (0); +#else + return ((p_obj->p_instance->ST & I2CxST_I2C) == I2CxST_I2C); +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Interrupt Status Clear + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_clear_int_status(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->ST = I2CxST_CLEAR; + } +#else + p_obj->p_instance->ST = I2CxST_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_I2C; + } +#else + p_obj->p_instance->IE = I2CxIE_I2C; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt setting. + * @param p_obj :I2C object. + * @param tx :Direction of transfer(1=tx 0=rx). + * @retval - + * @note For DMA transfer. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_enable_interrupt_dma(I2C_t *p_obj, int32_t tx) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } + } +#else + if (tx) { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CTX); + } else { + p_obj->p_instance->IE = (I2CxIE_SELPINCD | I2CxIE_DMARI2CRX); + } +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_disable_interrupt(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->IE = I2CxIE_CLEAR; + } +#else + p_obj->p_instance->IE = I2CxIE_CLEAR; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Set slave address. + * @param p_obj :I2C object. + * @param addr :slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void I2C_set_address(I2C_t *p_obj, uint32_t addr) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; + } +#else + p_obj->p_instance->AR = (addr & ~I2CxAR_ALS); + p_obj->p_instance->AR2 = I2CxAR2_INIT; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Detecting Slave Address + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t I2C_slave_detected(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); + } + return (0); +#else + return (((p_obj->p_instance->SR & I2CxSR_AAS) == I2CxSR_AAS) + && ((p_obj->p_instance->OP & I2CxOP_SAST) == I2CxOP_SAST)); +#endif +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +void I2C_init(I2C_t *p_obj); +void I2C_start_condition(I2C_t *p_obj, uint32_t data); +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting); +void I2C_slave_init(I2C_t *p_obj); +#if defined(I2CSxWUP_EN) +void I2CS_init(I2CS_t *p_obj); +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr); +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c_api.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c_api.h new file mode 100644 index 00000000000..4fdf3eee92b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_i2c_api.h @@ -0,0 +1,320 @@ +/** + ******************************************************************************* + * @file txzp_i2c_api.h + * @brief This file provides all the functions prototypes for I2C Driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __I2C_API_H +#define __I2C_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_i2c.h" + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Exported_macro */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ +/** + * @defgroup I2C_NullPointer Null Pointer + * @brief I2C NULL Pointer. + * @{ + */ +#define I2C_NULL ((void *)0) +/** + * @} + */ /* End of group I2C_NullPointer */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/** + * @defgroup I2C_ACK I2C ACK Macros + * @brief I2C Type of Acknowledge. + * @{ + */ +#define I2C_NACK (0) /*!< NACK Received. */ +#define I2C_ACK (1) /*!< ACK Received. */ +/** + * @} + */ /* End of group I2C_ACK */ + + +/** + * @defgroup I2C_ERROR I2C ERROR Macros + * @brief I2C Error definitions. + * @{ + */ +#define I2C_ERROR_NO_ERROR (0) /*!< No Error. */ +#if 0 +#define I2C_ERROR_NO_SLAVE (-1) /*!< No Slave Error. */ +#define I2C_ERROR_BUS_BUSY (-2) /*!< Bus Busy Error.(now, not support) */ +#endif +#define I2C_ERROR_PARAM (-3) /*!< Parameter Error. */ +#define I2C_ERROR_OTHERS (-4) /*!< Others Error. */ +#define I2C_ERROR_ARBITRATION (-5) /*!< Arbitration Error. */ +/** + * @} + */ /* End of group I2C_ERROR */ + + +/** + * @defgroup I2C_Events I2C Events Macros + * @brief I2C Asynch Events. + * @{ + */ +#define I2C_EVENT_ERROR (1 << 1) /*!< Error. */ +#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2) /*!< No Slave. */ +#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3) /*!< Transfer Complete. */ +#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4) /*!< End of Transfer. */ +#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK) +/** + * @} + */ /* End of group I2C_Events */ + +/** + * @defgroup I2C_SlaveReceive I2C Slave Receive Return Macros + * @brief I2C Received Contents of Slave. + * @{ + */ +#define I2C_NO_DATA (0) /*!< the slave has not been addressed. */ +#define I2C_READ_ADDRESSED (1) /*!< the master has requested a read from this slave. */ +#define I2C_WRITE_GENERAL (2) /*!< the master is writing to all slave.(now, not support) */ +#define I2C_WRITE_ADDRESSED (3) /*!< the master is writing to this slave. */ +/** + * @} + */ /* End of group I2C_SlaveReceive */ + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_define + * @{ + */ + +/*----------------------------------*/ +/** + * @brief i2c Port Enumerated Type Definition. +*/ +/*----------------------------------*/ +typedef enum { + I2C_PORT_PG2 = 0, /*!< 0: PG2 I2C0 */ + I2C_PORT_PG3, /*!< 1: PG3 I2C0 */ + I2C_PORT_PF2, /*!< 2: PF2 I2C1 */ + I2C_PORT_PF3, /*!< 3: PF3 I2C1 */ + I2C_PORT_PG4, /*!< 4: PG4 I2C2 */ + I2C_PORT_PG5, /*!< 5: PG5 I2C2 */ + I2C_PORT_PJ6, /*!< 6: PJ6 I2C3 */ + I2C_PORT_PJ7, /*!< 7: PJ7 I2C3 */ + I2C_PORT_PJ2, /*!< 8: PJ2 I2C4 */ + I2C_PORT_PJ3, /*!< 9: PJ3 I2C4 */ +} +i2c_port_t; + +/*----------------------*/ +/* I2C Setting */ +/*----------------------*/ +/* #define I2C_CHANNEL0 */ +#define I2C_CHANNEL3 +/* #define I2C_CHANNEL2 */ +/* #define I2C_CHANNEL3 */ +/* #define I2C_CHANNEL4 */ +#if defined(I2C_CHANNEL0) +#define I2Cx_TEXT "I2C0" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL1) +#define I2Cx_TEXT "I2C1" +#define I2C_CFG_PORT_SCL (I2C_PORT_PF3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PF2) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL2) +#define I2Cx_TEXT "I2C2" +#define I2C_CFG_PORT_SCL (I2C_PORT_PG5) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PG4) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL3) +#define I2Cx_TEXT "I2C3" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ7) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ6) /*!< SDA Port. */ +#elif defined(I2C_CHANNEL4) +#define I2Cx_TEXT "I2C4" +#define I2C_CFG_PORT_SCL (I2C_PORT_PJ3) /*!< SCL Port. */ +#define I2C_CFG_PORT_SDA (I2C_PORT_PJ2) /*!< SDA Port. */ +#else +#error "target channel is non-select." +#endif + +/** + * @} + */ /* End of group UTILITIES_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief I2C internal information structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t bus_free; /*!< Bus free information. */ + uint8_t start; /*!< Start condition information. */ + uint32_t irqn; /*!< IRQ number table pointer. */ + struct { + uint32_t address; /*!< Slave address. */ + uint32_t stop; /*!< Stop control */ + uint32_t event; /*!< I2C Event information. */ + uint32_t state; /*!< Transfer State. */ + } asynch; +} i2c_internal_info_t; + +/*----------------------------------*/ +/** + * @brief I2C buffer structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_buffer; /*!< Buffer address. */ + uint32_t length; /*!< Buffer length. */ + uint32_t pos; /*!< Buffer pointer. */ +} i2c_buffer_t; + +/*----------------------------------*/ +/** + * @brief I2C handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + I2C_t i2c; /*!< I2C class structure. */ + i2c_internal_info_t info; /*!< Internal Information. */ + i2c_buffer_t tx_buff; /*!< Tx buffer structure. */ + i2c_buffer_t rx_buff; /*!< Rx buffer structure. */ +} _i2c_t; + +/** + * @} + */ /* End of group UTILITIES_Exported_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ +TXZ_Result i2c_init_t(_i2c_t *p_obj, i2c_port_t sda, i2c_port_t scl); +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz); +void i2c_reset_t(_i2c_t *p_obj); +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj); +TXZ_Result i2c_start_t(_i2c_t *p_obj); +TXZ_Result i2c_stop_t(_i2c_t *p_obj); +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop); +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last); +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data); +uint8_t i2c_active_t(_i2c_t *p_obj); +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop); +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_abort_asynch_t(_i2c_t *p_obj); + +/* For slave */ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave); +int32_t i2c_slave_receive_t(_i2c_t *p_obj); +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length); +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address); +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length); +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj); +void i2c_slave_abort_asynch_t(_i2c_t *p_obj); + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __I2C_API_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_t32a.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_t32a.h new file mode 100644 index 00000000000..cff3563c80c --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_t32a.h @@ -0,0 +1,1037 @@ +/** + ******************************************************************************* + * @file txzp_t32a.h + * @brief This file provides all the functions prototypes for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __T32A_H +#define __T32A_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup T32A T32A + * @brief T32A Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_define T32A Exported Define + * @{ + */ + +/** + * @defgroup T32A_Result Result + * @brief T32A Result Macro Definition. + * @{ + */ +#define T32A_RESULT_SUCCESS (0) /*!< Success */ +#define T32A_RESULT_FAILURE (-1) /*!< Failure */ +#define T32A_READ_FAILURE (0xFFFFFFFF) /*!< Failure */ +/** + * @} + */ /* End of group T32A_Result */ + +/** + * @defgroup T32A_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define T32A_NULL ((void *)0) /*!< NULL Pointer For T32A */ +/** + * @} + */ /* End of group T32A_NullPointer */ + +/** +* @defgroup T32A_HALT T32A Debug HALT Control +* @brief Debug HALT Control Run/Stop HALT Macro Definition. +* @{ +*/ +#define T32A_DBG_HALT_RUN ((uint32_t)0x00000000) /*!< Run */ +#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002) /*!< Stop */ +/** + * @} + */ /* End of group T32A_HALT */ + +/** +* @defgroup T32A_MODE32 T32A 16bit/32bit MODE +* @brief T32A 16bit/32bit MODE MODE32 Macro Definition. +* @{ +*/ +#define T32A_MODE_16 ((uint32_t)0x00000000) /*!< 16bit Mode */ +#define T32A_MODE_32 ((uint32_t)0x00000001) /*!< 32bit Mode */ +/** + * @} + */ /* End of group T32A_MODE32 */ + +/** +* @defgroup T32A_RUNFLGx T32A RUNFLG Control +* @brief Run/Stop RUNFLGx Macro Definition. +* @{ +*/ +#define T32A_RUNFLG_RUN ((uint32_t)0x00000010) /*!< Run */ +#define T32A_RUNFLG_STOP ((uint32_t)0x00000000) /*!< Stop */ +/** + * @} + */ /* End of group T32A_RUNFLGx */ + +/** + * @defgroup T32A_SFTSTPx T32A SW STOP Control + * @brief T32A SW STOPx SFTSTPx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_STOP ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_STOP ((uint32_t)0x0000004) /*!< Counter Stop */ +/** + * @} + */ /* End of group T32A_SFTSTPx */ + +/** + * @defgroup T32A_SFTSTAx T32A SW START Control + * @brief T32A SW STARTx SFTSTAx Macro Definition. + * @{ + */ +#define T32A_COUNT_DONT_START ((uint32_t)0x0000000) /*!< No effect */ +#define T32A_COUNT_START ((uint32_t)0x0000002) /*!< Counter Start */ +/** + * @} + */ /* End of group T32A_SFTSTAx */ + +/** + * @defgroup T32A_RUNx T32A RUN Disable/Enable Control + * @brief RUN Disable/Enable RUNx Macro Definition. + * @{ + */ +#define T32A_RUN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_RUN_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group T32A_RUNx */ + + +/** + * @defgroup T32A_PRSCLx T32A PRESCALER Control + * @brief PRESCALER Control PRSCLx Macro Definition. + * @{ + */ +#define T32A_PRSCLx_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define T32A_PRSCLx_2 ((uint32_t)0x10000000) /*!< 1/2 */ +#define T32A_PRSCLx_8 ((uint32_t)0x20000000) /*!< 1/8 */ +#define T32A_PRSCLx_32 ((uint32_t)0x30000000) /*!< 1/32 */ +#define T32A_PRSCLx_128 ((uint32_t)0x40000000) /*!< 1/128 */ +#define T32A_PRSCLx_256 ((uint32_t)0x50000000) /*!< 1/256 */ +#define T32A_PRSCLx_512 ((uint32_t)0x60000000) /*!< 1/512 */ +#define T32A_PRSCLx_1024 ((uint32_t)0x70000000) /*!< 1/1024 */ +/** + * @} + */ /* End of group T32A_PRSCLx */ + +/** + * @defgroup T32A_CLKx T32A COLCK Control + * @brief CLOCK Control CLKA Macro Definition. + * @{ + */ +#define T32A_CLKx_PRSCLx ((uint32_t)0x00000000) /*!< prescaler */ +#define T32A_CLKx_INTRG ((uint32_t)0x01000000) /*!< internal triger */ +#define T32A_CLKx_TIM_RISING_EDGE ((uint32_t)0x02000000) /*!< other timer rising edge */ +#define T32A_CLKx_TIM_TRAILING_EDGE ((uint32_t)0x03000000) /*!< other timer trailing edge */ +#define T32A_CLKx_EXTTRG_RISING_EDGE ((uint32_t)0x04000000) /*!< external triger rising edge */ +#define T32A_CLKx_EXTTRG_TRAILING_EDGE ((uint32_t)0x05000000) /*!< external triger trailing edge */ +/** + * @} + */ /* End of group T32A_CLKx */ + +/** + * @defgroup T32A_WBFx T32A Double Buffer Disable/Enable Control + * @brief Double Buffer Disable/Enable WBFx Macro Definition. + * @{ + */ +#define T32A_WBF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define T32A_WBF_ENABLE ((uint32_t)0x00100000) /*!< Enable */ +/** + * @} + */ /* End of group T32A_WBFx */ + +/** +* @defgroup T32A_UPDNx T32A Counter Up/Down Control +* @brief Counter Up/Down Control UPDNx Macro Definition. +* @{ +*/ +#define T32A_COUNT_UP ((uint32_t)0x00000000) /*!< count up */ +#define T32A_COUNT_DOWN ((uint32_t)0x00010000) /*!< count down */ +#define T32A_COUNT_UPDOWN ((uint32_t)0x00020000) /*!< count updown */ +#define T32A_COUNT_PLS ((uint32_t)0x00030000) /*!< count pulse */ +/** + * @} + */ /* End of group T32A_UPDNx */ + +/** +* @defgroup T32A_RELDx T32A Counter Reload Control +* @brief Counter Reload Control RELDx Macro Definition. +* @{ +*/ +#define T32A_RELOAD_NON ((uint32_t)0x00000000) /*!< Nothing(Free run) */ +#define T32A_RELOAD_INTRG ((uint32_t)0x00000100) /*!< internal trigger */ +#define T32A_RELOAD_EXTTRG_RISING_EDGE ((uint32_t)0x00000200) /*!< external trigger rising edge */ +#define T32A_RELOAD_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000300) /*!< external trigger trailing edge */ +#define T32A_RELOAD_TIM_RISING_EDGE ((uint32_t)0x00000400) /*!< other timer rising edge */ +#define T32A_RELOAD_TIM_TRAILING_EDGE ((uint32_t)0x00000500) /*!< other timer trailing edge */ +#define T32A_RELOAD_SYNC ((uint32_t)0x00000600) /*!< sync(slave channel) */ +#define T32A_RELOAD_TREGx ((uint32_t)0x00000700) /*!< match up Timer Register */ +/** + * @} + */ /* End of group T32A_RELDx */ + +/** +* @defgroup T32A_STOPx T32A Counter Stop Control +* @brief Counter Stop Control STOPx Macro Definition. +* @{ +*/ +#define T32A_STOP_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_STOP_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_STOP_EXTTRG_RISING_EDGE ((uint32_t)0x00000020) /*!< external trigger rising edge */ +#define T32A_STOP_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000030) /*!< external trigger trailing edge */ +#define T32A_STOP_TIM_RISING_EDGE ((uint32_t)0x00000040) /*!< other timer rising edge */ +#define T32A_STOP_TIM_TRAILING_EDGE ((uint32_t)0x00000050) /*!< other timer trailing edge */ +#define T32A_STOP_SYNC ((uint32_t)0x00000060) /*!< sync(slave channel) */ +#define T32A_STOP_TREGx ((uint32_t)0x00000070) /*!< match up Timer Register A */ +/** + * @} + */ /* End of group T32A_STOPx */ + + +/** +* @defgroup T32A_STARTx T32A Counter Start Control +* @brief Counter Start Control STARTx Macro Definition. +* @{ +*/ +#define T32A_START_NON ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_START_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_START_EXTTRG_RISING_EDGE ((uint32_t)0x00000002) /*!< external trigger rising edge */ +#define T32A_START_EXTTRG_TRAILING_EDGE ((uint32_t)0x00000003) /*!< external trigger trailing edge */ +#define T32A_START_TIM_RISING_EDGE ((uint32_t)0x00000004) /*!< other timer rising edge */ +#define T32A_START_TIM_TRAILING_EDGE ((uint32_t)0x00000005) /*!< other timer trailing edge */ +#define T32A_START_SYNC ((uint32_t)0x00000006) /*!< sync(slave channel) */ +#define T32A_START_Rsvd ((uint32_t)0x00000007) /*!< Reserved */ +/** + * @} + */ /* End of group T32A_STARTx */ + +/** + * @defgroup T32A_OCRx T32AxOUTA Control + * @brief T32AxOUTA Control OCRx Macro Definition. + * @{ + */ +#define T32A_OCR_DISABLE ((uint32_t)0x00000000) /*!< Nothig */ +#define T32A_OCR_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCR_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCR_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRx */ + +/** + * @defgroup T32A_OCRCAPx1 T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 + * @brief T32AxOUTA Control of T32AxCAPx1 T32AxRGx1 OCRCAPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx1_SET ((uint32_t)0x00000040) /*!< Hi */ +#define T32A_OCRCAPx1_CLR ((uint32_t)0x00000080) /*!< Low */ +#define T32A_OCRCAPx1_INVERSION ((uint32_t)0x000000C0) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx1 */ + +/** + * @defgroup T32A_OCRCAPx0 T32AxOUTA Control of T32AxCAPx0 counter value + * @brief T32AxOUTA Control of T32AxCAPx0 T32AxRGx1 OCRCAPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCAPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCAPx0_SET ((uint32_t)0x00000010) /*!< Hi */ +#define T32A_OCRCAPx0_CLR ((uint32_t)0x00000020) /*!< Low */ +#define T32A_OCRCAPx0_INVERSION ((uint32_t)0x00000030) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCAPx0 */ + +/** + * @defgroup T32A_OCRCMPx1 T32AxOUTA Control of T32AxRGx1 Counter Value + * @brief T32AxOUTA Control of T32AxRGx1 Counter Value OCRCMPx1 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx1_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx1_SET ((uint32_t)0x00000004) /*!< Hi */ +#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008) /*!< Low */ +#define T32A_OCRCMPx1_INVERSION ((uint32_t)0x0000000C) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx1 */ + +/** + * @defgroup T32A_OCRCMPx0 T32AxOUTA Control of T32AxRGx0 Counter Value + * @brief T32AxOUTA Control of T32AxRGx0 Counter Value OCRCMPx0 Macro Definition. + * @{ + */ +#define T32A_OCRCMPx0_DISABLE ((uint32_t)0x00000000) /*!< No effect */ +#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001) /*!< Hi */ +#define T32A_OCRCMPx0_CLR ((uint32_t)0x00000002) /*!< Low */ +#define T32A_OCRCMPx0_INVERSION ((uint32_t)0x00000003) /*!< inversion */ +/** + * @} + */ /* End of group T32A_OCRCMPx0 */ + +/** + * @defgroup T32A_RGx0 T32A Timer Register x0 MASK + * @brief T32A Timer Register A0 MASK RGx0 Macro Definition. + * @{ + */ +#define T32A_RGx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_RGx1 T32A Timer Register x1 MASK + * @brief T32A Timer Register A1 MASK RGx1 Macro Definition. + * @{ + */ +#define T32A_RGx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RGC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RGx0 */ + +/** + * @defgroup T32A_TMRx T32A Counter Capture Register x MASK + * @brief T32A Counter Capture Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_TMRx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_TMRC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_TMRx */ + +/** + * @defgroup T32A_RELD T32A Counter Reload Register x MASK + * @brief T32A Counter Reload Register x MASK TMRx Macro Definition. + * @{ + */ +#define T32A_RELDx_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_RELDC_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_RELD */ + +/** +* @defgroup T32A_CAPMx1 T32A Capture Control Register x1 +* @brief Capture Control Register A1 CAPMx1 Macro Definition. +* @{ +*/ +#define T32A_CAPMx1_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx1_INTRG ((uint32_t)0x00000010) /*!< internal trigger */ +#define T32A_CAPMx1_INx0_RISING_EDGE ((uint32_t)0x00000020) /*!< INx0 rising edge */ +#define T32A_CAPMx1_INx0_TRAILING_EDGE ((uint32_t)0x00000030) /*!< INx0 trailing edge */ +#define T32A_CAPMx1_INx1_RISING_EDGE ((uint32_t)0x00000040) /*!< INx1 rising edge */ +#define T32A_CAPMx1_INx1_TRAILING_EDGE ((uint32_t)0x00000050) /*!< INx1 trailing edge */ +#define T32A_CAPMx1_TIM_RISING_EDGE ((uint32_t)0x00000060) /*!< other timer rising edge */ +#define T32A_CAPMx1_TIM_TRAILING_EDGE ((uint32_t)0x00000070) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx1 */ + +/** +* @defgroup T32A_CAPMx0 T32A Capture Control Register x0 +* @brief Capture Control Register x0 CAPMx0 Macro Definition. +* @{ +*/ +#define T32A_CAPMx0_DISABLE ((uint32_t)0x00000000) /*!< No use trigger */ +#define T32A_CAPMx0_INTRG ((uint32_t)0x00000001) /*!< internal trigger */ +#define T32A_CAPMx0_INx0_RISING_EDGE ((uint32_t)0x00000002) /*!< INx0 rising edge */ +#define T32A_CAPMx0_INx0_TRAILING_EDGE ((uint32_t)0x00000003) /*!< INx0 trailing edge */ +#define T32A_CAPMx0_INx1_RISING_EDGE ((uint32_t)0x00000004) /*!< INx1 rising edge */ +#define T32A_CAPMx0_INx1_TRAILING_EDGE ((uint32_t)0x00000005) /*!< INx1 trailing edge */ +#define T32A_CAPMx0_TIM_RISING_EDGE ((uint32_t)0x00000006) /*!< other timer rising edge */ +#define T32A_CAPMx0_TIM_TRAILING_EDGE ((uint32_t)0x00000007) /*!< other timer trailing edge */ +/** + * @} + */ /* End of group T32A_CAPMx0 */ + +/** + * @defgroup T32A_CAPx0 T32A Capture Register x0 MASK + * @brief T32A Capture Register x0 MASK CAPx0 Macro Definition. + * @{ + */ +#define T32A_CAPx0_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC0_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx0 */ + +/** + * @defgroup T32A_CAPx1 T32A Capture Register x1 MASK + * @brief T32A Capture Register x1 MASK CAPx1 Macro Definition. + * @{ + */ +#define T32A_CAPx1_MASK ((uint32_t)0x0000FFFF) /*!< register value mask */ +#define T32A_CAPC1_MASK ((uint32_t)0xFFFFFFFF) /*!< register value mask */ +/** + * @} + */ /* End of group T32A_CAPx1 */ + +/** + * @defgroup T32A_IMSTERR T32A Statuserr Interrupt Request MASK + * @brief T32A Statuserr Interrupt Request MASK IMSTERR Macro Definition. + * @{ + */ +#define T32A_IMSTERR_MASK_NOREQ ((uint32_t)0x00000000) +#define T32A_IMSTERR_MASK_REQ ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_IMSTERR */ + +/** + * @defgroup T32A_IMUFx T32A Underflow Interrupt Request MASK + * @brief T32A Underflow Interrupt Request MASK IMUFx Macro Definition. + * @{ + */ +#define T32A_IMUFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008) /*!< request */ +/** + * @} + */ /* End of group T32A_IMUFx */ + +/** + * @defgroup T32A_IMOFx T32A Overflow Interrupt Request MASK + * @brief T32A Overflow Interrupt Request MASK IMOFx Macro Definition. + * @{ + */ +#define T32A_IMOFx_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004) /*!< request */ +/** + * @} + */ /* End of group T32A_IMOFx */ + +/** + * @defgroup T32A_IMx1 T32A Match Up T32AxRGx1 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx1 Interrupt Request MASK IMx1 Macro Definition. + * @{ + */ +#define T32A_IMx1_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx1_MASK_REQ ((uint32_t)0x00000002) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx1 */ + +/** + * @defgroup T32A_IMx0 T32A Match Up T32AxRGx0 Interrupt Request MASK + * @brief T32A Match Up T32AxRGx0 Interrupt Request MASK IMx0 Macro Definition. + * @{ + */ +#define T32A_IMx0_MASK_NOREQ ((uint32_t)0x00000000) /*!< don't request */ +#define T32A_IMx0_MASK_REQ ((uint32_t)0x00000001) /*!< request */ +/** + * @} + */ /* End of group T32A_IMx0 */ + +/** + * @defgroup T32A_INTSTERR T32A_Statuerr Flag Status + * @brief T32A Statuserr Flag Status INTSTERR Macro Definition. + * @{ + */ +#define T32A_INTSTERR_FLG_MASK ((uint32_t)0x00000010) +#define T32A_INTSTERR_FLG_CLR ((uint32_t)0x00000010) +/** + * @} + */ /* End of group T32A_INTSTERR */ + +/** + * @defgroup T32A_INTUFA T32A Underflow Flag Status + * @brief T32A Underflow Flag Status INTUFA Macro Definition. + * @{ + */ +#define T32A_INTUFx_FLG_MASK ((uint32_t)0x00000008) /*!< Underflow Flag Mask */ +#define T32A_INTUFx_FLG_CLR ((uint32_t)0x00000008) /*!< Underflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTUFA */ + +/** + * @defgroup T32A_INTOFA T32A Overflow Flag Status + * @brief T32A Overflow Flag Status INTOFA Macro Definition. + * @{ + */ +#define T32A_INTOFx_FLG_MASK ((uint32_t)0x00000004) /*!< Overflow Flag Mask */ +#define T32A_INTOFx_FLG_CLR ((uint32_t)0x00000004) /*!< Overflow Flag Clear */ +/** + * @} + */ /* End of group T32A_INTOFA */ + +/** + * @defgroup T32A_INTA1 T32A Match Up T32AxRGx1 Flag Status + * @brief T32A Match Up T32AxRGx1 Flag Status INTA1 Macro Definition. + * @{ + */ +#define T32A_INTx1_FLG_MASK ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Mask */ +#define T32A_INTx1_FLG_CLR ((uint32_t)0x00000002) /*!< Match Up T32AxRGx1 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA1 */ + +/** + * @defgroup T32A_INTA0 T32A Match Up T32AxRGx0 Flag Status + * @brief T32A Match Up T32AxRGx0 Flag Status INTA0 Macro Definition. + * @{ + */ +#define T32A_INTx0_FLG_MASK ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Mask */ +#define T32A_INTx0_FLG_CLR ((uint32_t)0x00000001) /*!< Match Up T32AxRGx0 Flag Clear */ +/** + * @} + */ /* End of group T32A_INTA0 */ + +/** + * @defgroup T32A_DMAENx2 T32A DMA Converter1 Request control + * @brief T32A DMA Converter1 Disable/Enable DMAENx2 Macro Definition. + * @{ + */ +#define T32A_DMAENx2_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx2_ENABLE ((uint32_t)0x00000004) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx2 */ + +/** + * @defgroup T32A_DMAENx1 T32A DMA InputCapture1 Request control + * @brief T32A DMA InputCapture1 Disable/Enable DMAENx1 Macro Definition. + * @{ + */ +#define T32A_DMAENx1_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx1_ENABLE ((uint32_t)0x00000002) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx1 */ + +/** + * @defgroup T32A_DMAENx0 T32A DMA InputCapture0 Request control + * @brief T32A DMA InputCapture0 Disable/Enable DMAENx0 Macro Definition. + * @{ + */ +#define T32A_DMAENx0_DISABLE ((uint32_t)0x00000000) /*!< disable */ +#define T32A_DMAENx0_ENABLE ((uint32_t)0x00000001) /*!< enable */ +/** + * @} + */ /* End of group T32A_DMAENx0 */ + +/** +* @defgroup T32A_PDN T32A Pulse Mode Count Down Control +* @brief Pulse Mode Count Down Control PDN Macro Definition. +* @{ +*/ +#define T32A_PDN_NON0 ((uint32_t)0x00000000) /*!< Do not count down */ +#define T32A_PDN_NON1 ((uint32_t)0x00001000) /*!< Do not count down */ +#define T32A_PDN_INC0_RISING_EDGE ((uint32_t)0x00002000) /*!< T32AxINC0 rising edge */ +#define T32A_PDN_INC0_TRAILING_EDGE ((uint32_t)0x00003000) /*!< T32AxINC0 trailing edge */ +#define T32A_PDN_INC1_RISING_EDGE ((uint32_t)0x00004000) /*!< T32AxINC1 rising edge */ +#define T32A_PDN_INC1_TRAILING_EDGE ((uint32_t)0x00005000) /*!< T32AxINC1 trailing edge */ +#define T32A_PDN_INC0_BOTH_EDGE ((uint32_t)0x00006000) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PDN_INC1_BOTH_EDGE ((uint32_t)0x00007000) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PDN */ + +/** +* @defgroup T32A_PUP T32A Pulse Mode Count UP Control +* @brief Pulse Mode Count UP Control PUP Macro Definition. +* @{ +*/ +#define T32A_PUP_NON0 ((uint32_t)0x00000000) /*!< Do not count up */ +#define T32A_PUP_NON1 ((uint32_t)0x00000100) /*!< Do not count up */ +#define T32A_PUP_INC0_RISING_EDGE ((uint32_t)0x00000200) /*!< T32AxINC0 rising edge */ +#define T32A_PUP_INC0_TRAILING_EDGE ((uint32_t)0x00000300) /*!< T32AxINC0 trailing edge */ +#define T32A_PUP_INC1_RISING_EDGE ((uint32_t)0x00000400) /*!< T32AxINC1 rising edge */ +#define T32A_PUP_INC1_TRAILING_EDGE ((uint32_t)0x00000500) /*!< T32AxINC1 trailing edge */ +#define T32A_PUP_INC0_BOTH_EDGE ((uint32_t)0x00000600) /*!< T32AxINC0 rising edge/trailing edge */ +#define T32A_PUP_INC1_BOTH_EDGE ((uint32_t)0x00000700) /*!< T32AxINC1 rising edge/trailing edge */ +/** + * @} + */ /* End of group T32A_PUP */ + +/** +* @defgroup T32A_NF T32A Noise Filter control +* @brief Noise Filter control NF Macro Definition. +* @{ +*/ +#define T32A_NF_NON ((uint32_t)0x00000000) /*!< Nothing */ +#define T32A_NF_2 ((uint32_t)0x00000010) /*!< Noise Filter less than 2/T0 */ +#define T32A_NF_4 ((uint32_t)0x00000020) /*!< Noise Filter less than 4/T0 */ +#define T32A_NF_8 ((uint32_t)0x00000030) /*!< Noise Filter less than 8/T0 */ +/** + * @} + */ /* End of group T32A_NF */ + +/** + * @defgroup T32A_PDIR T32A Phase 2 Pulse Direction control + * @brief Phase 2 Pulse Direction control PDIR Macro Definition. + * @{ + */ +#define T32A_PDIR_FORWARD ((uint32_t)0x00000000) /*!< forward */ +#define T32A_PDIR_BACKWARD ((uint32_t)0x00000002) /*!< backward */ +/** + * @} + */ /* End of group T32A_PDIR */ + +/** + * @defgroup T32A_PMODE T32A Pulse Count Mode control + * @brief Pulse Count Mode control PDIR Macro Definition. + * @{ + */ +#define T32A_PMODE_PHASE_2 ((uint32_t)0x00000000) /*!< Phase 2 Pulse Counter Mode */ +#define T32A_PMODE_PHASE_1 ((uint32_t)0x00000001) /*!< Phase 1 Pulse Counter Mode */ +/** + * @} + */ /* End of group T32A_PMODE */ + +/** + * @} + */ /* End of group T32A_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** @defgroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ + +/** + * @enum t32_type_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_TIMERA = 0, /*!< 0: Timer A */ + T32A_TIMERB, /*!< 1: Timer B */ + T32A_TIMERC, /*!< 2: Timer C */ + T32A_TIMERMAX, +} t32_type_t; + +/** + * @enum t32_regnum_t + * @brief Use of Timer register number. + */ +typedef enum { + T32A_REG0 = 0, /*!< 0: Register 0 */ + T32A_REG1, /*!< 1: Register 1 */ + T32A_RELOAD, /*!< 2: Reload Register */ +} t32_regnum_t; +/** + * @enum t32_mode_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_MATCH = 0, /*!< 0: compare match detection 0 */ + T32A_OVERFLOW, /*!< 1: Overfloe detection */ + T32A_UNDERFLOW, /*!< 2: Underflow detection */ + T32A_CAPTURE0, /*!< 3: Capture 0 */ + T32A_CAPTURE1, /*!< 4: Capture 0 */ +} t32_mode_t; + +/** + * @enum t32_triger_t + * @brief Use of Timer register. + */ +typedef enum { + T32A_INTRG = 0, /*!< 0: internal triger */ + T32A_TIM_RISING_EDGE, /*!< 1: Same Channel other timer rising edge */ + T32A_TIM_TRAILING_EDGE, /*!< 2: Same Channel other timer trailing edge */ + T32A_EXTTRG_RISING_EDGE, /*!< 3: external triger rising edge */ + T32A_EXTTRG_TRAILING_EDGE, /*!< 4: external triger trailing edge */ +} t32_triger_t; +/** + * @} + */ /* End of group T32A_Exported_Typedef */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_Typedef T32A Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct t32a_mode_t + * @brief TimerA Mode Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t halt; /*!< T32A Debug HALT Control. + : Use @ref T32A_HALT */ + uint32_t mode; /*!< T32A 16bit/32bit MODE . + : Use @ref T32A_MODE32 */ +} t32a_mode_t; + +/*----------------------------------*/ +/** + * @struct t32a_runx_t + * @brief TimerA Run Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t runflg; /*!< TimerA Run Control Flag. + : Use @ref T32A_RUNFLGx */ + uint32_t sftstp; /*!< SW Counter STOP Control. + : Use @ref T32A_SFTSTPx */ + uint32_t sftsta; /*!< SW Counter START Control. + : Use @ref T32A_SFTSTAx */ + uint32_t run; /*!< TimerA Run Control. + : Use @ref T32A_RUNx */ +} t32a_runx_t; + +/*----------------------------------*/ +/** + * @struct t32a_crx_t + * @brief Counter Register Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prscl; /*!< T32A PRESCALER Control. + : Use @ref T32A_PRSCLx */ + uint32_t clk; /*!< T32A COLCK Control. + : Use @ref T32A_CLKx */ + uint32_t wbf; /*!< T32A Double Buffer Disable/Enable Control. + : Use @ref T32A_WBFx */ + uint32_t updn; /*!< T32A Counter Up/Down Control. + : Use @ref T32A_UPDNx */ + uint32_t reld; /*!< T32A Counter Reload Control. + : Use @ref T32A_RELDx */ + uint32_t stop; /*!< T32A Counter Stop Control. + : Use @ref T32A_STOPx */ + uint32_t start; /*!< T32A Counter Start Controlc. + : Use @ref T32A_STARTx */ +} t32a_crx_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx0_t + * @brief TimerA Output Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocr; /*!< T32AxOUTA Control. + : Use @ref T32A_OCRx */ +} t32a_outcrx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_outcrx1_t + * @brief T32AxOUTA Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ocrcap1; /*!< T32AxOUTA Control of T32AxCAPx1 T32AxRGx1. + : Use @ref T32A_OCRCAPx1 */ + uint32_t ocrcap0; /*!< T32AxOUTA Control of T32AxCAPx0 T32AxRGx1. + : Use @ref T32A_OCRCAPx0 */ + uint32_t ocrcmp1; /*!< T32AxOUTA Control of T32AxRGx1 Counter Value + : Use @ref T32A_OCRCMPx1 */ + uint32_t ocrcmp0; /*!< T32AxOUTA Control of T32AxRGx0 Counter Value + : Use @ref T32A_OCRCMPx0 */ +} t32a_outcrx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_capcrx_t + * @brief Capture Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capmx1; /*!< T32A Capture Control Register x1. + : Use @ref T32A_CAPMx1 */ + uint32_t capmx0; /*!< T32A Capture Control Register A0. + : Use @ref T32A_CAPMx0 */ +} t32a_capcrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx0_t + * @brief T32A Timer Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx0; /*!< T32A Timer Register x0. + : Use @ref T32A_RGx0 */ +} t32a_rgx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_rgx1_t + * @brief T32A Timer Register x1 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t rgx1; /*!< T32A Timer Register x1. + : Use @ref T32A_RGx1 */ +} t32a_rgx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_tmrx_t + * @brief T32A Counter Capture Register A Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tmrx; /*!< T32A Counter Capture Register x. + : Use @ref T32A_TMRx */ +} t32a_tmrx_t; + +/*----------------------------------*/ +/** + * @struct t32a_reldx_t + * @brief T32A Counter Reload Register Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reld; /*!< T32A Counter Reload Register. + : Use @ref T32A_RELD */ +} t32a_reldx_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx0_t + * @brief T32A Capture Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx0; /*!< T32A Capture Register x0. + : Use @ref T32A_CAPx0 */ +} t32a_capx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_capx1_t + * @brief T32A Capture Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t capx1; /*!< T32A Capture Register x1. + : Use @ref T32A_CAPx1 */ +} t32a_capx1_t; + +/*----------------------------------*/ +/** + * @struct t32a_imx_t + * @brief Interrupt mask register Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t imsterr; /*!< T32A State Transition Err Interrupt Request MASK (Only use Timer C). + : Use @ref T32A_IMSTERR */ + uint32_t imuf; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMUFx */ + uint32_t imof; /*!< T32A Underflow Interrupt Request MASK. + : Use @ref T32A_IMOFx */ + uint32_t imx1; /*!< T32A Match Up T32AxRGx1 Interrupt Request MASK. + : Use @ref T32A_IMx1 */ + uint32_t imx0; /*!< T32A Match Up T32AxRGx0 Interrupt Request MASK. + : Use @ref T32A_IMx0 */ +} t32a_imx_t; + +/*----------------------------------*/ +/** + * @struct t32a_stx_t + * @brief Status register structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intsterr; /*!< T32A State Transition Err Flag Status (Only use Timer C). + : Use @ref T32A_INTSTERR */ + uint32_t intuf; /*!< T32A Underflow Flag Status. + : Use @ref T32A_INTUFA */ + uint32_t intof; /*!< T32A Overflow Flag Status. + : Use @ref T32A_INTOFA */ + uint32_t intx1; /*!< T32A Match Up T32AxRGx1 Flag Status. + : Use @ref T32A_INTA1 */ + uint32_t intx0; /*!< T32A Match Up T32AxRGx0 Flag Status. + : Use @ref T32A_INTA0 */ +} t32a_stx_t; + +/*----------------------------------*/ +/** + * @struct t32a_dma_req_t + * @brief DMA Request register setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dmaenx2; /*!< T32A DMA Converter1 Request control. + : Use @ref T32A_DMAENx2 */ + uint32_t dmaenx1; /*!< T32A DMA InputCapture1 Request control. + : Use @ref T32A_DMAENx1 */ + uint32_t dmaenx0; /*!< T32A DMA InputCapture0 Request control. + : Use @ref T32A_DMAENx0 */ +} t32a_dma_req_t; + +/*----------------------------------*/ +/** + * @struct t32a_pulse_cr_t + * @brief Pulse Count Control register setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t pdn; /*!< Pulse Mode Count Down Control. + : Use @ref T32A_PDN */ + uint32_t pup; /*!< Pulse Mode Count UP Control. + : Use @ref T32A_PUP */ + uint32_t nf; /*!< Noise Filter control. + : Use @ref T32A_NF */ + uint32_t pdir; /*!< Phase 2 Pulse Direction control. + : Use @ref T32A_PDIR */ + uint32_t pmode; /*!< Pulse Count Mode control. + : Use @ref T32A_PMODE */ +} t32a_pulse_cr_t; + +/*----------------------------------*/ +/** + * @struct t32a_cpx0_t + * @brief T32A Compare Register x0 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t crgx0; /*!< T32A Compare Register x0. + : Use @ref T32A_CRGx0 */ +} t32a_cpx0_t; + +/*----------------------------------*/ +/** + * @struct t32a_cpx1_t + * @brief T32A Compare Register x1 Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t crgx1; /*!< T32A Compare Register x1. + : Use @ref T32A_CRGx1 */ +} t32a_cpx1_t; + +/** + * @struct t32a_initial_setting_t + * @brief Initial Timer setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + t32a_runx_t runx; /*!< Timer Run Control Setting */ + t32a_crx_t crx; /*!< Counter Register Control Setting */ + t32a_outcrx0_t outcrx0; /*!< Timer Output Control Setting */ + t32a_outcrx1_t outcrx1; /*!< T32AxOUTx Control Setting */ + t32a_capcrx_t capcrx; /*!< Capture Control Setting */ + t32a_rgx0_t rgx0; /*!< T32A Timer Register x0 Setting */ + t32a_rgx1_t rgx1; /*!< T32A Timer Register x1 Setting */ + t32a_tmrx_t tmrx; /*!< T32A Counter Capture Register Setting */ + t32a_reldx_t reldx; /*!< T32A Counter Reload Register Setting */ + t32a_capx0_t capx0; /*!< T32A Capture Register x0 Setting */ + t32a_capx1_t capx1; /*!< T32A Capture Register x1 Setting */ + t32a_imx_t imx; /*!< Interrupt mask register Setting */ + t32a_dma_req_t dma_req; /*!< DMA Request register Setting */ + t32a_pulse_cr_t pls_cr; /*!< Pulse Count Control Register Setting (Only use Timer C) */ + t32a_cpx0_t crgx0; /*!< T32A Compare Register x0 Setting */ + t32a_cpx1_t crgx1; /*!< T32A Compare Register x1 Setting */ + void (*handler_T)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Event handler. */ + void (*handler_TC0)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap0 Event handler. */ + void (*handler_TC1)(uint32_t id, uint32_t status, TXZ_Result result); /*!< Timer Cap1 Event handler. */ +} t32a_initial_setting_t; + +/** + * @struct t32a_initial_mode_t + * @brief Initial Mode setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + t32a_mode_t mode; /*!< Timer Mode Setting */ +} t32a_initial_mode_t; + + +/*----------------------------------*/ +/** + * @brief T32A handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct t32a_handle { + TSB_T32A_TypeDef *p_instance; /*!< Registers base address. */ + t32a_initial_mode_t init_mode; /*!< Timer Mode Initial Setting */ + t32a_initial_setting_t init[T32A_TIMERMAX]; /*!< Initial setting. */ +} t32a_t; + +/** @} */ +/* End of group T32A_Exported_Types */ +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Exported_functions T32A Exported Functions + * @{ + */ +TXZ_Result t32a_mode_init(t32a_t *p_obj); +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type); +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value); +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val); +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type); +void t32a_timer_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj); +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj); +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl); +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __T32A_H */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_tspi.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_tspi.h new file mode 100644 index 00000000000..182ec3bce7d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_tspi.h @@ -0,0 +1,1542 @@ +/** + ******************************************************************************* + * @file txzp_tspi.h + * @brief This file provides all the functions prototypes for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __TSPI_H +#define __TSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup TSPI TSPI + * @brief TSPI Driver. + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_define TSPI Exported Define + * @{ + */ +/** + * @defgroup TSPI_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define TSPI_NULL ((void *)0) +/** + * @} + */ /* End of group TSPI_NullPointer */ + +/** + * @defgroup TSPI_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define TSPI_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define TSPI_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group TSPI_ParameterResult */ + +/** + * @defgroup TSPI_Result Result + * @brief TSPI Result Macro Definition. + * @{ + */ +#define TSPI_RESULT_SUCCESS (0) /*!< Success */ +#define TSPI_RESULT_FAILURE (-1) /*!< Failure */ +/** + * @} + */ /* End of group TSPI_Result */ + +/** + * @defgroup TSPI_SW_Reset SW Reset + * @brief Software Rest Macro Definition. + * @{ + */ +#define TSPI_RESET10 ((uint32_t)0x00000080) /*!< RESET Pattarn 10 */ +#define TSPI_RESET01 ((uint32_t)0x00000040) /*!< RESET Pattarn 01 */ +/** + * @} + */ /* End of group TSPI_SW_Reset */ + + +/** + * @defgroup TSPI_Enable TSPI Enable/Disable Control + * @brief Enable/Disable TSPIE Macro Definition. + * @{ + */ +#define TSPI_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Enable */ + +/** + * @defgroup TSPI_Infinite_Transfer Infinite_Transfer + * @brief Enable/Disable INF Macro Definition. + * @{ + */ +#define TSPI_INF_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_INF_ENABLE ((uint32_t)0x00010000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Triger_Control Triger Control + * @brief Enable/Disable TRGEN Macro Definition. + * @{ + */ +#define TSPI_TRGEN_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRGEN_ENABLE ((uint32_t)0x00008000) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Control Transmission Control + * @brief Enable/Disable TRXE Macro Definition. + * @{ + */ +#define TSPI_TRXE_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TRXE_ENABLE ((uint32_t)0x00004000) /*!< Enable */ +#define TSPI_TRXE_DISABLE_MASK ((uint32_t)0xFFFFBFFF) /*!< Disable MASK*/ +/** + * @} + */ /* End of group TSPI_Transmission_Control */ + +/** + * @defgroup TSPI_Transmission_Mode Transmission Mode + * @brief TSPIIMS Mode Macro Definisiton. + * @{ + */ +#define TSPI_SPI_MODE ((uint32_t)0x00000000) /*!< TSPI MODE */ +#define TSPI_SIO_MODE ((uint32_t)0x00002000) /*!< SIO MODE */ +/** + * @} + */ /* End of group TSPI_Transmission_Mode */ + + +/** + * @defgroup TSPI_Operation_Select Operation Select + * @brief Master/Slave MSTR Operation Macro Definisiton. + * @{ + */ +#define TSPI_MASTER_OPERATION ((uint32_t)0x00001000) /*!< MASTER MODE */ +#define TSPI_SLAVE_OPERATION ((uint32_t)0x00000000) /*!< SLAVE MODE */ +/** + * @} + */ /* End of group TSPI_Operation_Select */ + + +/** + * @defgroup TSPI_Transfer_Mode Transfer Mode + * @brief Transfer Mode TMMD Macro Definisiton. + * @{ + */ +#define TSPI_TX_ONLY ((uint32_t)0x00000400) /*!< SEND ONLY */ +#define TSPI_RX_ONLY ((uint32_t)0x00000800) /*!< RECEIVE ONLY */ +#define TSPI_TWO_WAY ((uint32_t)0x00000C00) /*!< TWO WAY */ +#define TSPI_Transfer_Mode_MASK ((uint32_t)0x00000C00) /*!< Transfer Mode bit MASK */ +/** + * @} + */ /* End of group TSPI_Transfer_Mode */ + + +/** + * @defgroup TSPI_CSSEL_Select CSSEL Select + * @brief TSPIIxCS0/1/2/3 Select Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS0_ENABLE ((uint32_t)0x00000000) /*!< TSPIIxCS0 */ +#define TSPI_TSPIxCS1_ENABLE ((uint32_t)0x00000100) /*!< TSPIIxCS1 */ +#define TSPI_TSPIxCS2_ENABLE ((uint32_t)0x00000200) /*!< TSPIIxCS2 */ +#define TSPI_TSPIxCS3_ENABLE ((uint32_t)0x00000300) /*!< TSPIIxCS3 */ +/** + * @} + */ /* End of group TSPI_CSSEL_Select */ + +/** + * @defgroup TSPI_Transfer_Frame_Range Transfer Frame Range + * @brief Transfer Frame Range Macro Definisiton. + * @{ + */ +#define TSPI_TRANS_RANGE_CONTINUE ((uint32_t)0x00000000) /*!< Continue Transfer Frame :0 */ +#define TSPI_TRANS_RANGE_MAX ((uint32_t)0x000000FF) /*!< Maximum Transfer Frame Value :=255 */ +/** + * @} + */ /* End of group TSPI_Transfer_Frame_Range */ +/** + * @defgroup TSPI_IDLE_Output_value IDLE Output Value + * @brief IDLE time Output Value TIDLE Macro Definisiton. + * @{ + */ +#define TSPI_TIDLE_Hiz ((uint32_t)0x00000000) /*!< Hi-z */ +#define TSPI_TIDLE_LAST_DATA ((uint32_t)0x00400000) /*!< Last DATA */ +#define TSPI_TIDLE_LOW ((uint32_t)0x00800000) /*!< Low */ +#define TSPI_TIDLE_HI ((uint32_t)0x00C00000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_IDLE_Output_value */ + +/** + * @defgroup TSPI_RXDLY_value RXDLY Value + * @brief IDLE time Output Value TIDLE Macro Definisiton. + * @{ + */ +#define TSPI_RXDLY_FSYS_FSCK_2 ((uint32_t)0x00000000) /*!< fsys / fsck = 2 */ +#define TSPI_RXDLY_FSYS_FSCK_4 ((uint32_t)0x00010000) /*!< fsys / fsck = 4 */ +#define TSPI_RXDLY_FSYS_FSCK_6 ((uint32_t)0x00020000) /*!< fsys / fsck = 6 */ +#define TSPI_RXDLY_FSYS_FSCK_8 ((uint32_t)0x00030000) /*!< fsys / fsck = 8 */ +#define TSPI_RXDLY_FSYS_FSCK_10 ((uint32_t)0x00040000) /*!< fsys / fsck = 10 */ +#define TSPI_RXDLY_FSYS_FSCK_12 ((uint32_t)0x00050000) /*!< fsys / fsck = 12 */ +#define TSPI_RXDLY_FSYS_FSCK_14 ((uint32_t)0x00060000) /*!< fsys / fsck = 14 */ +#define TSPI_RXDLY_FSYS_FSCK_16 ((uint32_t)0x00070000) /*!< fsys / fsck >= 16 */ +#define TSPI_RXDLY_FSYS_FSCK_MASK ((uint32_t)0x00070000) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RXDLY_value*/ + + +/** +* @defgroup TSPI_Underrun_Output_value Underrun Occur Output Value +* @brief In case of Under Run Output Value TXDEMP Macro Definisiton. +* @{ +*/ +#define TSPI_TXDEMP_LOW ((uint32_t)0x00000000) /*!< Low */ +#define TSPI_TXDEMP_HI ((uint32_t)0x00200000) /*!< Hi */ +/** + * @} + */ /* End of group TSPI_Underrun_Output_value */ + + +/** + * @defgroup TSPI_TxFillLevel Tx Fill Level + * @brief Transmit Fill Level Macro Definisiton. + * @{ + */ +#define TSPI_TX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_FILL_LEVEL_1 ((uint32_t)0x00001000) /*!< 1 */ +#define TSPI_TX_FILL_LEVEL_2 ((uint32_t)0x00002000) /*!< 2 */ +#define TSPI_TX_FILL_LEVEL_3 ((uint32_t)0x00003000) /*!< 3 */ +#define TSPI_TX_FILL_LEVEL_4 ((uint32_t)0x00004000) /*!< 4 */ +#define TSPI_TX_FILL_LEVEL_5 ((uint32_t)0x00005000) /*!< 5 */ +#define TSPI_TX_FILL_LEVEL_6 ((uint32_t)0x00006000) /*!< 6 */ +#define TSPI_TX_FILL_LEVEL_7 ((uint32_t)0x00007000) /*!< 7 */ +#define TSPI_TX_FILL_LEVEL_MASK ((uint32_t)0x00007000) /*!< MASK */ +/*! + * @} + */ /* End of group TSPI_TxFillLevel */ + + +/** + * @defgroup TSPI_RxFillLevel Rx Fill Level + * @brief Receive Fill Level Macro Definisiton. + * @{ + */ +#define TSPI_RX_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 8 */ +#define TSPI_RX_FILL_LEVEL_1 ((uint32_t)0x00000100) /*!< 1 */ +#define TSPI_RX_FILL_LEVEL_2 ((uint32_t)0x00000200) /*!< 2 */ +#define TSPI_RX_FILL_LEVEL_3 ((uint32_t)0x00000300) /*!< 3 */ +#define TSPI_RX_FILL_LEVEL_4 ((uint32_t)0x00000400) /*!< 4 */ +#define TSPI_RX_FILL_LEVEL_5 ((uint32_t)0x00000500) /*!< 5 */ +#define TSPI_RX_FILL_LEVEL_6 ((uint32_t)0x00000600) /*!< 6 */ +#define TSPI_RX_FILL_LEVEL_7 ((uint32_t)0x00000700) /*!< 7 */ +#define TSPI_RX_FILL_LEVEL_MASK ((uint32_t)0x00000700) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_RxFillLevel */ + + +/** + * @defgroup TSPI_TxFIFOInterrupt Tx FIFO Interrpt + * @brief Enable/Disable Transmit FIFO Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterrupt */ + + +/** + * @defgroup TSPI_TxInterrupt Tx Interrpt + * @brief Enable/Disable Transmit Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxInterrupt */ + + +/** + * @defgroup TSPI_RxFIFOInterrupt Rx FIFO Interrpt + * @brief Enable/Disable Receive FIFO Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterrupt */ + + +/** + * @defgroup TSPI_RxInterrupt Rx Interrpt + * @brief Enable/Disable Receive Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxInterrupt */ + + +/** + * @defgroup TSPI_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ErrorInterrupt */ + + +/** + * @defgroup TSPI_TxDMAInterrupt Tx DMA Interrupt + * @brief Enable/Disable Transmit DMA Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_TX_DMA_INT_MASK ((uint32_t)0x00000002) /*!< Mask Data */ +#define TSPI_TX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_DMA_INT_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_TxDMAInterrupt */ + + +/** + * @defgroup TSPI_RxDMAInterrupt Rx DMA Interrupt + * @brief Enable/Disable Receive DMA Interrupt Macro Definisiton. + * @{ + */ +#define TSPI_RX_DMA_INT_MASK ((uint32_t)0x00000001) /*!< Mask Data */ +#define TSPI_RX_DMA_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_DMA_INT_ENABLE ((uint32_t)0x00000001) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_RxDMAInterrupt */ + + +/** + * @defgroup TSPI_Tx_Buffer_Clear Tx Buffer Clear + * @brief Tx Buffer Clear Macro Definisiton. + * @{ + */ +#define TSPI_TX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_TX_BUFF_CLR_DONE ((uint32_t)0x00000002) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Tx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Rx_Buffer_Clear Rx Buffer Clear + * @brief Rx Buffer Clear Macro Definisiton. + * @{ + */ +#define TSPI_RX_BUFF_CLR_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_RX_BUFF_CLR_DONE ((uint32_t)0x00000001) /*!< Clear */ +/** + * @} + */ /* End of group TSPI_Rx_Buffer_Clear */ + + +/** + * @defgroup TSPI_Baudrate_Clock Baudrate Input Clock + * @brief Baudrate Input Clock Macro Definisiton. + * @{ + */ +#define TSPI_BR_CLOCK_0 ((uint32_t)0x00000000) /*!< T0 */ +#define TSPI_BR_CLOCK_1 ((uint32_t)0x00000010) /*!< T1 */ +#define TSPI_BR_CLOCK_2 ((uint32_t)0x00000020) /*!< T2 */ +#define TSPI_BR_CLOCK_4 ((uint32_t)0x00000030) /*!< T4 */ +#define TSPI_BR_CLOCK_8 ((uint32_t)0x00000040) /*!< T8 */ +#define TSPI_BR_CLOCK_16 ((uint32_t)0x00000050) /*!< T16 */ +#define TSPI_BR_CLOCK_32 ((uint32_t)0x00000060) /*!< T32 */ +#define TSPI_BR_CLOCK_64 ((uint32_t)0x00000070) /*!< T64 */ +#define TSPI_BR_CLOCK_128 ((uint32_t)0x00000080) /*!< T128 */ +#define TSPI_BR_CLOCK_256 ((uint32_t)0x00000090) /*!< T256 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Clock */ + + +/** + * @defgroup TSPI_Baudrate_Divider Baudrate Divider + * @brief Baudrate IDivider Macro Definisiton. + * @{ + */ +#define TSPI_BR_DIVIDER_16 ((uint32_t)0x00000000) /*!< 1/16 */ +#define TSPI_BR_DIVIDER_1 ((uint32_t)0x00000001) /*!< 1/1 */ +#define TSPI_BR_DIVIDER_2 ((uint32_t)0x00000002) /*!< 1/2 */ +#define TSPI_BR_DIVIDER_3 ((uint32_t)0x00000003) /*!< 1/3 */ +#define TSPI_BR_DIVIDER_4 ((uint32_t)0x00000004) /*!< 1/4 */ +#define TSPI_BR_DIVIDER_5 ((uint32_t)0x00000005) /*!< 1/5 */ +#define TSPI_BR_DIVIDER_6 ((uint32_t)0x00000006) /*!< 1/6 */ +#define TSPI_BR_DIVIDER_7 ((uint32_t)0x00000007) /*!< 1/7 */ +#define TSPI_BR_DIVIDER_8 ((uint32_t)0x00000008) /*!< 1/8 */ +#define TSPI_BR_DIVIDER_9 ((uint32_t)0x00000009) /*!< 1/9 */ +#define TSPI_BR_DIVIDER_10 ((uint32_t)0x0000000a) /*!< 1/10 */ +#define TSPI_BR_DIVIDER_11 ((uint32_t)0x0000000b) /*!< 1/11 */ +#define TSPI_BR_DIVIDER_12 ((uint32_t)0x0000000c) /*!< 1/12 */ +#define TSPI_BR_DIVIDER_13 ((uint32_t)0x0000000d) /*!< 1/13 */ +#define TSPI_BR_DIVIDER_14 ((uint32_t)0x0000000e) /*!< 1/14 */ +#define TSPI_BR_DIVIDER_15 ((uint32_t)0x0000000f) /*!< 1/15 */ +/** + * @} + */ /* End of group TSPI_Baudrate_Divider */ + + +/** + * @defgroup TSPI_DataDirection Data Direction + * @brief Data Direction Macro Definisiton. + * @{ + */ +#define TSPI_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define TSPI_DATA_DIRECTION_MSB ((uint32_t)0x80000000) /*!< MSB first */ +/*! + * @} + */ /* End of group TSPI_DataDirection */ + + +/** + * @defgroup TSPI_DataLength Data Length + * @brief Data Length Macro Definisiton. + * @{ + */ +#define TSPI_DATA_LENGTH_8 ((uint32_t)0x08000000) /*!< 8 bit */ +#define TSPI_DATA_LENGTH_9 ((uint32_t)0x09000000) /*!< 9 bit */ +#define TSPI_DATA_LENGTH_10 ((uint32_t)0x0a000000) /*!< 10 bit */ +#define TSPI_DATA_LENGTH_11 ((uint32_t)0x0b000000) /*!< 11 bit */ +#define TSPI_DATA_LENGTH_12 ((uint32_t)0x0c000000) /*!< 12 bit */ +#define TSPI_DATA_LENGTH_13 ((uint32_t)0x0d000000) /*!< 13 bit */ +#define TSPI_DATA_LENGTH_14 ((uint32_t)0x0e000000) /*!< 14 bit */ +#define TSPI_DATA_LENGTH_15 ((uint32_t)0x0f000000) /*!< 15 bit */ +#define TSPI_DATA_LENGTH_16 ((uint32_t)0x10000000) /*!< 16 bit */ +#define TSPI_DATA_LENGTH_17 ((uint32_t)0x11000000) /*!< 17 bit */ +#define TSPI_DATA_LENGTH_18 ((uint32_t)0x12000000) /*!< 18 bit */ +#define TSPI_DATA_LENGTH_19 ((uint32_t)0x13000000) /*!< 19 bit */ +#define TSPI_DATA_LENGTH_20 ((uint32_t)0x14000000) /*!< 20 bit */ +#define TSPI_DATA_LENGTH_21 ((uint32_t)0x15000000) /*!< 21 bit */ +#define TSPI_DATA_LENGTH_22 ((uint32_t)0x16000000) /*!< 22 bit */ +#define TSPI_DATA_LENGTH_23 ((uint32_t)0x17000000) /*!< 23 bit */ +#define TSPI_DATA_LENGTH_24 ((uint32_t)0x18000000) /*!< 24 bit */ +#define TSPI_DATA_LENGTH_25 ((uint32_t)0x19000000) /*!< 25 bit */ +#define TSPI_DATA_LENGTH_26 ((uint32_t)0x1a000000) /*!< 26 bit */ +#define TSPI_DATA_LENGTH_27 ((uint32_t)0x1b000000) /*!< 27 bit */ +#define TSPI_DATA_LENGTH_28 ((uint32_t)0x1c000000) /*!< 28 bit */ +#define TSPI_DATA_LENGTH_29 ((uint32_t)0x1d000000) /*!< 29 bit */ +#define TSPI_DATA_LENGTH_30 ((uint32_t)0x1e000000) /*!< 30 bit */ +#define TSPI_DATA_LENGTH_31 ((uint32_t)0x1f000000) /*!< 31 bit */ +#define TSPI_DATA_LENGTH_32 ((uint32_t)0x20000000) /*!< 32 bit */ +#define TSPI_DATA_LENGTH_MASK ((uint32_t)0x3F000000) /*!< 32 bit */ +/** + * @} + */ /* End of group TSPI_DataLength */ + + +/** + * @defgroup TSPI_Frame_Interval_Time Frame Interval time + * @brief Frame Interval time Macro Definisiton. + * @{ + */ +#define TSPI_INTERVAL_TIME_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_INTERVAL_TIME_1 ((uint32_t)0x00100000) /*!< 1 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_2 ((uint32_t)0x00200000) /*!< 2 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_3 ((uint32_t)0x00300000) /*!< 3 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_4 ((uint32_t)0x00400000) /*!< 4 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_5 ((uint32_t)0x00500000) /*!< 5 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_6 ((uint32_t)0x00600000) /*!< 6 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_7 ((uint32_t)0x00700000) /*!< 7 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_8 ((uint32_t)0x00800000) /*!< 8 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_9 ((uint32_t)0x00900000) /*!< 9 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_10 ((uint32_t)0x00a00000) /*!< 10 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_11 ((uint32_t)0x00b00000) /*!< 11 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_12 ((uint32_t)0x00c00000) /*!< 12 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_13 ((uint32_t)0x00d00000) /*!< 13 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_14 ((uint32_t)0x00e00000) /*!< 14 x TSPIIxSCK */ +#define TSPI_INTERVAL_TIME_15 ((uint32_t)0x00f00000) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Frame_Interval_Time */ + + +/** + * @defgroup TSPI_TSPIxCS3_Polarity TSPIxCS3 Polarity + * @brief TSPIxCS3 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS3_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS3_POSITIVE ((uint32_t)0x00080000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS3_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS2_Polarity TSPIxCS2 Polarity + * @brief TSPIxCS2 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS2_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS2_POSITIVE ((uint32_t)0x00040000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS2_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS1_Polarity TSPIxCS1 Polarity + * @brief TSPIxCS1 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS1_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS1_POSITIVE ((uint32_t)0x00020000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS1_Polarity */ + + +/** + * @defgroup TSPI_TSPIxCS0_Polarity TSPIxCS0 Polarity + * @brief TSPIxCS0 Polarity Macro Definisiton. + * @{ + */ +#define TSPI_TSPIxCS0_NEGATIVE ((uint32_t)0x00000000) /*!< negative logic */ +#define TSPI_TSPIxCS0_POSITIVE ((uint32_t)0x00010000) /*!< positive logic */ +/** + * @} + */ /* End of group TSPI_TSPIxCS0_Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_Polarity Serial Clock Polarity + * @brief Serial Clock Polarity Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_1ST_EDGE ((uint32_t)0x00000000) /*!< 1st Edge Sampling */ +#define TSPI_SERIAL_CK_2ND_EDGE ((uint32_t)0x00008000) /*!< 2nd Edge Sampling */ +/** + * @} + */ /* End of group Serial Clock Polarity */ + + +/** + * @defgroup TSPI_Serial_Clock_IDLE_Polarity Serial Clock IDLE Polarity + * @brief Serial Clock IDLE Polarity Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_IDLE_LOW ((uint32_t)0x00000000) /*!< IDLE Term TSPII??SCK LOW */ +#define TSPI_SERIAL_CK_IDLE_HI ((uint32_t)0x00004000) /*!< IDLE Term TSPII??SCK HI */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_IDLE_Polarity */ + + +/** + * @defgroup TSPI_Minimum_IDLE_Time Minimum IDLE Time + * @brief Minimum IDLE Time Macro Definisiton. + * @{ + */ +#define TSPI_MIN_IDLE_TIME_1 ((uint32_t)0x00000400) /*!< 1 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_2 ((uint32_t)0x00000800) /*!< 2 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_3 ((uint32_t)0x00000c00) /*!< 3 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_4 ((uint32_t)0x00001000) /*!< 4 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_5 ((uint32_t)0x00001400) /*!< 5 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_6 ((uint32_t)0x00001800) /*!< 6 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_7 ((uint32_t)0x00001c00) /*!< 7 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_8 ((uint32_t)0x00002000) /*!< 8 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_9 ((uint32_t)0x00002400) /*!< 9 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_10 ((uint32_t)0x00002800) /*!< 10 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_11 ((uint32_t)0x00002C00) /*!< 11 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_12 ((uint32_t)0x00003000) /*!< 12 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_13 ((uint32_t)0x00003400) /*!< 13 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_14 ((uint32_t)0x00003800) /*!< 14 x TSPIIxSCK */ +#define TSPI_MIN_IDLE_TIME_15 ((uint32_t)0x00003C00) /*!< 15 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Minimum_IDLE_Time */ + + +/** + * @defgroup TSPI_Serial_Clock_Delay Serial Clock Delay + * @brief Serial Clock Delay Macro Definisiton. + * @{ + */ +#define TSPI_SERIAL_CK_DELAY_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_2 ((uint32_t)0x00000010) /*!< 2 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_3 ((uint32_t)0x00000020) /*!< 3 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_4 ((uint32_t)0x00000030) /*!< 4 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_5 ((uint32_t)0x00000040) /*!< 5 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_6 ((uint32_t)0x00000050) /*!< 6 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_7 ((uint32_t)0x00000060) /*!< 7 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_8 ((uint32_t)0x00000070) /*!< 8 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_9 ((uint32_t)0x00000080) /*!< 9 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_10 ((uint32_t)0x00000090) /*!< 10 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_11 ((uint32_t)0x000000a0) /*!< 11 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_12 ((uint32_t)0x000000b0) /*!< 12 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_13 ((uint32_t)0x000000c0) /*!< 13 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_14 ((uint32_t)0x000000d0) /*!< 14 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_15 ((uint32_t)0x000000e0) /*!< 15 x TSPIIxSCK */ +#define TSPI_SERIAL_CK_DELAY_16 ((uint32_t)0x000000f0) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Serial_Clock_Delay */ + + +/** + * @defgroup TSPI_Negate_Delay Negate Delay + * @brief Negate Delay Macro Definisiton. + * @{ + */ +#define TSPI_NEGATE_1 ((uint32_t)0x00000000) /*!< 1 x TSPIIxSCK */ +#define TSPI_NEGATE_2 ((uint32_t)0x00000001) /*!< 2 x TSPIIxSCK */ +#define TSPI_NEGATE_3 ((uint32_t)0x00000002) /*!< 3 x TSPIIxSCK */ +#define TSPI_NEGATE_4 ((uint32_t)0x00000003) /*!< 4 x TSPIIxSCK */ +#define TSPI_NEGATE_5 ((uint32_t)0x00000004) /*!< 5 x TSPIIxSCK */ +#define TSPI_NEGATE_6 ((uint32_t)0x00000005) /*!< 6 x TSPIIxSCK */ +#define TSPI_NEGATE_7 ((uint32_t)0x00000006) /*!< 7 x TSPIIxSCK */ +#define TSPI_NEGATE_8 ((uint32_t)0x00000007) /*!< 8 x TSPIIxSCK */ +#define TSPI_NEGATE_9 ((uint32_t)0x00000008) /*!< 9 x TSPIIxSCK */ +#define TSPI_NEGATE_10 ((uint32_t)0x00000009) /*!< 10 x TSPIIxSCK */ +#define TSPI_NEGATE_11 ((uint32_t)0x0000000a) /*!< 11 x TSPIIxSCK */ +#define TSPI_NEGATE_12 ((uint32_t)0x0000000b) /*!< 12 x TSPIIxSCK */ +#define TSPI_NEGATE_13 ((uint32_t)0x0000000c) /*!< 13 x TSPIIxSCK */ +#define TSPI_NEGATE_14 ((uint32_t)0x0000000d) /*!< 14 x TSPIIxSCK */ +#define TSPI_NEGATE_15 ((uint32_t)0x0000000e) /*!< 15 x TSPIIxSCK */ +#define TSPI_NEGATE_16 ((uint32_t)0x0000000f) /*!< 16 x TSPIIxSCK */ +/** + * @} + */ /* End of group TSPI_Negate_Delay */ + + +/** + * @defgroup TSPI_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define TSPI_PARITY_ENABLE ((uint32_t)0x00000002) /*!< Enable */ +/** + * @} + */ /* End of group TSPI_ParityEnable */ + + +/** + * @defgroup TSPI_ParityBit Parity Bit + * @brief Parity Bit Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define TSPI_PARITY_BIT_EVEN ((uint32_t)0x00000001) /*!< Even Parity */ +/** + * @} + */ /* End of group TSPI_ParityBit */ + +/** + * @defgroup TSPI_Sectcr0 Sect Bit + * @brief Sectcr0 Macro Definisiton. + * @{ + */ +#define TSPI_SECTCR0_SECT_FRAME_MODE ((uint32_t)0x00000000) /*!< Frame Mode */ +#define TSPI_SECTCR0_SECT_SECTOR_MODE ((uint32_t)0x00000001) /*!< Sector mode */ +/** + * @} + */ /* End of group TSPI_Sectcr0 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl3 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL3_0 ((uint32_t)0x00000000) /*!< Sectl3 Bit length 0 */ +#define TSPI_SECTCR1_SECTL3_1 ((uint32_t)0x01000000) /*!< Sectl3 Bit length 1 */ +#define TSPI_SECTCR1_SECTL3_2 ((uint32_t)0x02000000) /*!< Sectl3 Bit length 2 */ +#define TSPI_SECTCR1_SECTL3_3 ((uint32_t)0x03000000) /*!< Sectl3 Bit length 3 */ +#define TSPI_SECTCR1_SECTL3_4 ((uint32_t)0x04000000) /*!< Sectl3 Bit length 4 */ +#define TSPI_SECTCR1_SECTL3_5 ((uint32_t)0x05000000) /*!< Sectl3 Bit length 5 */ +#define TSPI_SECTCR1_SECTL3_6 ((uint32_t)0x06000000) /*!< Sectl3 Bit length 6 */ +#define TSPI_SECTCR1_SECTL3_7 ((uint32_t)0x07000000) /*!< Sectl3 Bit length 7 */ +#define TSPI_SECTCR1_SECTL3_8 ((uint32_t)0x08000000) /*!< Sectl3 Bit length 8 */ +#define TSPI_SECTCR1_SECTL3_9 ((uint32_t)0x09000000) /*!< Sectl3 Bit length 9 */ +#define TSPI_SECTCR1_SECTL3_10 ((uint32_t)0x0a000000) /*!< Sectl3 Bit length 10 */ +#define TSPI_SECTCR1_SECTL3_11 ((uint32_t)0x0b000000) /*!< Sectl3 Bit length 11 */ +#define TSPI_SECTCR1_SECTL3_12 ((uint32_t)0x0c000000) /*!< Sectl3 Bit length 12 */ +#define TSPI_SECTCR1_SECTL3_13 ((uint32_t)0x0d000000) /*!< Sectl3 Bit length 13 */ +#define TSPI_SECTCR1_SECTL3_14 ((uint32_t)0x0e000000) /*!< Sectl3 Bit length 14 */ +#define TSPI_SECTCR1_SECTL3_15 ((uint32_t)0x0f000000) /*!< Sectl3 Bit length 15 */ +#define TSPI_SECTCR1_SECTL3_16 ((uint32_t)0x10000000) /*!< Sectl3 Bit length 16 */ +#define TSPI_SECTCR1_SECTL3_17 ((uint32_t)0x11000000) /*!< Sectl3 Bit length 17 */ +#define TSPI_SECTCR1_SECTL3_18 ((uint32_t)0x12000000) /*!< Sectl3 Bit length 18 */ +#define TSPI_SECTCR1_SECTL3_19 ((uint32_t)0x13000000) /*!< Sectl3 Bit length 19 */ +#define TSPI_SECTCR1_SECTL3_20 ((uint32_t)0x14000000) /*!< Sectl3 Bit length 20 */ +#define TSPI_SECTCR1_SECTL3_21 ((uint32_t)0x15000000) /*!< Sectl3 Bit length 21 */ +#define TSPI_SECTCR1_SECTL3_22 ((uint32_t)0x16000000) /*!< Sectl3 Bit length 22 */ +#define TSPI_SECTCR1_SECTL3_23 ((uint32_t)0x17000000) /*!< Sectl3 Bit length 23 */ +#define TSPI_SECTCR1_SECTL3_24 ((uint32_t)0x18000000) /*!< Sectl3 Bit length 24 */ +#define TSPI_SECTCR1_SECTL3_25 ((uint32_t)0x19000000) /*!< Sectl3 Bit length 25 */ +#define TSPI_SECTCR1_SECTL3_26 ((uint32_t)0x1a000000) /*!< Sectl3 Bit length 26 */ +#define TSPI_SECTCR1_SECTL3_27 ((uint32_t)0x1b000000) /*!< Sectl3 Bit length 27 */ +#define TSPI_SECTCR1_SECTL3_28 ((uint32_t)0x1c000000) /*!< Sectl3 Bit length 28 */ +#define TSPI_SECTCR1_SECTL3_29 ((uint32_t)0x1d000000) /*!< Sectl3 Bit length 29 */ +#define TSPI_SECTCR1_SECTL3_30 ((uint32_t)0x1e000000) /*!< Sectl3 Bit length 30 */ +#define TSPI_SECTCR1_SECTL3_31 ((uint32_t)0x1f000000) /*!< Sectl3 Bit length 31 */ +#define TSPI_SECTCR1_SECTL3_32 ((uint32_t)0x20000000) /*!< Sectl3 Bit length 32 */ +#define TSPI_SECTCR1_SECTL3_MASK ((uint32_t)0x3f000000) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl3 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl2 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL2_0 ((uint32_t)0x00000000) /*!< Sectl2 Bit length 0 */ +#define TSPI_SECTCR1_SECTL2_1 ((uint32_t)0x00010000) /*!< Sectl2 Bit length 1 */ +#define TSPI_SECTCR1_SECTL2_2 ((uint32_t)0x00020000) /*!< Sectl2 Bit length 2 */ +#define TSPI_SECTCR1_SECTL2_3 ((uint32_t)0x00030000) /*!< Sectl2 Bit length 3 */ +#define TSPI_SECTCR1_SECTL2_4 ((uint32_t)0x00040000) /*!< Sectl2 Bit length 4 */ +#define TSPI_SECTCR1_SECTL2_5 ((uint32_t)0x00050000) /*!< Sectl2 Bit length 5 */ +#define TSPI_SECTCR1_SECTL2_6 ((uint32_t)0x00060000) /*!< Sectl2 Bit length 6 */ +#define TSPI_SECTCR1_SECTL2_7 ((uint32_t)0x00070000) /*!< Sectl2 Bit length 7 */ +#define TSPI_SECTCR1_SECTL2_8 ((uint32_t)0x00080000) /*!< Sectl2 Bit length 8 */ +#define TSPI_SECTCR1_SECTL2_9 ((uint32_t)0x00090000) /*!< Sectl2 Bit length 9 */ +#define TSPI_SECTCR1_SECTL2_10 ((uint32_t)0x000a0000) /*!< Sectl2 Bit length 10 */ +#define TSPI_SECTCR1_SECTL2_11 ((uint32_t)0x000b0000) /*!< Sectl2 Bit length 11 */ +#define TSPI_SECTCR1_SECTL2_12 ((uint32_t)0x000c0000) /*!< Sectl2 Bit length 12 */ +#define TSPI_SECTCR1_SECTL2_13 ((uint32_t)0x000d0000) /*!< Sectl2 Bit length 13 */ +#define TSPI_SECTCR1_SECTL2_14 ((uint32_t)0x000e0000) /*!< Sectl2 Bit length 14 */ +#define TSPI_SECTCR1_SECTL2_15 ((uint32_t)0x000f0000) /*!< Sectl2 Bit length 15 */ +#define TSPI_SECTCR1_SECTL2_16 ((uint32_t)0x00100000) /*!< Sectl2 Bit length 16 */ +#define TSPI_SECTCR1_SECTL2_17 ((uint32_t)0x00110000) /*!< Sectl2 Bit length 17 */ +#define TSPI_SECTCR1_SECTL2_18 ((uint32_t)0x00120000) /*!< Sectl2 Bit length 18 */ +#define TSPI_SECTCR1_SECTL2_19 ((uint32_t)0x00130000) /*!< Sectl2 Bit length 19 */ +#define TSPI_SECTCR1_SECTL2_20 ((uint32_t)0x00140000) /*!< Sectl2 Bit length 20 */ +#define TSPI_SECTCR1_SECTL2_21 ((uint32_t)0x00150000) /*!< Sectl2 Bit length 21 */ +#define TSPI_SECTCR1_SECTL2_22 ((uint32_t)0x00160000) /*!< Sectl2 Bit length 22 */ +#define TSPI_SECTCR1_SECTL2_23 ((uint32_t)0x00170000) /*!< Sectl2 Bit length 23 */ +#define TSPI_SECTCR1_SECTL2_24 ((uint32_t)0x00180000) /*!< Sectl2 Bit length 24 */ +#define TSPI_SECTCR1_SECTL2_25 ((uint32_t)0x00190000) /*!< Sectl2 Bit length 25 */ +#define TSPI_SECTCR1_SECTL2_26 ((uint32_t)0x001a0000) /*!< Sectl2 Bit length 26 */ +#define TSPI_SECTCR1_SECTL2_27 ((uint32_t)0x001b0000) /*!< Sectl2 Bit length 27 */ +#define TSPI_SECTCR1_SECTL2_28 ((uint32_t)0x001c0000) /*!< Sectl2 Bit length 28 */ +#define TSPI_SECTCR1_SECTL2_29 ((uint32_t)0x001d0000) /*!< Sectl2 Bit length 29 */ +#define TSPI_SECTCR1_SECTL2_30 ((uint32_t)0x001e0000) /*!< Sectl2 Bit length 30 */ +#define TSPI_SECTCR1_SECTL2_31 ((uint32_t)0x001f0000) /*!< Sectl2 Bit length 31 */ +#define TSPI_SECTCR1_SECTL2_32 ((uint32_t)0x00200000) /*!< Sectl2 Bit length 32 */ +#define TSPI_SECTCR1_SECTL2_MASK ((uint32_t)0x003f0000) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl2 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl1 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL1_1 ((uint32_t)0x00000100) /*!< Sectl1 Bit length 1 */ +#define TSPI_SECTCR1_SECTL1_2 ((uint32_t)0x00000200) /*!< Sectl1 Bit length 2 */ +#define TSPI_SECTCR1_SECTL1_3 ((uint32_t)0x00000300) /*!< Sectl1 Bit length 3 */ +#define TSPI_SECTCR1_SECTL1_4 ((uint32_t)0x00000400) /*!< Sectl1 Bit length 4 */ +#define TSPI_SECTCR1_SECTL1_5 ((uint32_t)0x00000500) /*!< Sectl1 Bit length 5 */ +#define TSPI_SECTCR1_SECTL1_6 ((uint32_t)0x00000600) /*!< Sectl1 Bit length 6 */ +#define TSPI_SECTCR1_SECTL1_7 ((uint32_t)0x00000700) /*!< Sectl1 Bit length 7 */ +#define TSPI_SECTCR1_SECTL1_8 ((uint32_t)0x00000800) /*!< Sectl1 Bit length 8 */ +#define TSPI_SECTCR1_SECTL1_9 ((uint32_t)0x00000900) /*!< Sectl1 Bit length 9 */ +#define TSPI_SECTCR1_SECTL1_10 ((uint32_t)0x00000a00) /*!< Sectl1 Bit length 10 */ +#define TSPI_SECTCR1_SECTL1_11 ((uint32_t)0x00000b00) /*!< Sectl1 Bit length 11 */ +#define TSPI_SECTCR1_SECTL1_12 ((uint32_t)0x00000c00) /*!< Sectl1 Bit length 12 */ +#define TSPI_SECTCR1_SECTL1_13 ((uint32_t)0x00000d00) /*!< Sectl1 Bit length 13 */ +#define TSPI_SECTCR1_SECTL1_14 ((uint32_t)0x00000e00) /*!< Sectl1 Bit length 14 */ +#define TSPI_SECTCR1_SECTL1_15 ((uint32_t)0x00000f00) /*!< Sectl1 Bit length 15 */ +#define TSPI_SECTCR1_SECTL1_16 ((uint32_t)0x00001000) /*!< Sectl1 Bit length 16 */ +#define TSPI_SECTCR1_SECTL1_17 ((uint32_t)0x00001100) /*!< Sectl1 Bit length 17 */ +#define TSPI_SECTCR1_SECTL1_18 ((uint32_t)0x00001200) /*!< Sectl1 Bit length 18 */ +#define TSPI_SECTCR1_SECTL1_19 ((uint32_t)0x00001300) /*!< Sectl1 Bit length 19 */ +#define TSPI_SECTCR1_SECTL1_20 ((uint32_t)0x00001400) /*!< Sectl1 Bit length 20 */ +#define TSPI_SECTCR1_SECTL1_21 ((uint32_t)0x00001500) /*!< Sectl1 Bit length 21 */ +#define TSPI_SECTCR1_SECTL1_22 ((uint32_t)0x00001600) /*!< Sectl1 Bit length 22 */ +#define TSPI_SECTCR1_SECTL1_23 ((uint32_t)0x00001700) /*!< Sectl1 Bit length 23 */ +#define TSPI_SECTCR1_SECTL1_24 ((uint32_t)0x00001800) /*!< Sectl1 Bit length 24 */ +#define TSPI_SECTCR1_SECTL1_25 ((uint32_t)0x00001900) /*!< Sectl1 Bit length 25 */ +#define TSPI_SECTCR1_SECTL1_26 ((uint32_t)0x00001a00) /*!< Sectl1 Bit length 26 */ +#define TSPI_SECTCR1_SECTL1_27 ((uint32_t)0x00001b00) /*!< Sectl1 Bit length 27 */ +#define TSPI_SECTCR1_SECTL1_28 ((uint32_t)0x00001c00) /*!< Sectl1 Bit length 28 */ +#define TSPI_SECTCR1_SECTL1_29 ((uint32_t)0x00001d00) /*!< Sectl1 Bit length 29 */ +#define TSPI_SECTCR1_SECTL1_30 ((uint32_t)0x00001e00) /*!< Sectl1 Bit length 30 */ +#define TSPI_SECTCR1_SECTL1_31 ((uint32_t)0x00001f00) /*!< Sectl1 Bit length 31 */ +#define TSPI_SECTCR1_SECTL1_32 ((uint32_t)0x00002000) /*!< Sectl1 Bit length 32 */ +#define TSPI_SECTCR1_SECTL1_MASK ((uint32_t)0x00003f00) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl1 */ + +/** +* @defgroup TSPI_Sectcr1 Sectl0 Bit length setting +* @brief Sectcr1 Macro Definisiton. +* @{ +*/ +#define TSPI_SECTCR1_SECTL0_1 ((uint32_t)0x00000001) /*!< Sectl0 Bit length 1 */ +#define TSPI_SECTCR1_SECTL0_2 ((uint32_t)0x00000002) /*!< Sectl0 Bit length 2 */ +#define TSPI_SECTCR1_SECTL0_3 ((uint32_t)0x00000003) /*!< Sectl0 Bit length 3 */ +#define TSPI_SECTCR1_SECTL0_4 ((uint32_t)0x00000004) /*!< Sectl0 Bit length 4 */ +#define TSPI_SECTCR1_SECTL0_5 ((uint32_t)0x00000005) /*!< Sectl0 Bit length 5 */ +#define TSPI_SECTCR1_SECTL0_6 ((uint32_t)0x00000006) /*!< Sectl0 Bit length 6 */ +#define TSPI_SECTCR1_SECTL0_7 ((uint32_t)0x00000007) /*!< Sectl0 Bit length 7 */ +#define TSPI_SECTCR1_SECTL0_8 ((uint32_t)0x00000008) /*!< Sectl0 Bit length 8 */ +#define TSPI_SECTCR1_SECTL0_9 ((uint32_t)0x00000009) /*!< Sectl0 Bit length 9 */ +#define TSPI_SECTCR1_SECTL0_10 ((uint32_t)0x0000000a) /*!< Sectl0 Bit length 10 */ +#define TSPI_SECTCR1_SECTL0_11 ((uint32_t)0x0000000b) /*!< Sectl0 Bit length 11 */ +#define TSPI_SECTCR1_SECTL0_12 ((uint32_t)0x0000000c) /*!< Sectl0 Bit length 12 */ +#define TSPI_SECTCR1_SECTL0_13 ((uint32_t)0x0000000d) /*!< Sectl0 Bit length 13 */ +#define TSPI_SECTCR1_SECTL0_14 ((uint32_t)0x0000000e) /*!< Sectl0 Bit length 14 */ +#define TSPI_SECTCR1_SECTL0_15 ((uint32_t)0x0000000f) /*!< Sectl0 Bit length 15 */ +#define TSPI_SECTCR1_SECTL0_16 ((uint32_t)0x00000010) /*!< Sectl0 Bit length 16 */ +#define TSPI_SECTCR1_SECTL0_17 ((uint32_t)0x00000011) /*!< Sectl0 Bit length 17 */ +#define TSPI_SECTCR1_SECTL0_18 ((uint32_t)0x00000012) /*!< Sectl0 Bit length 18 */ +#define TSPI_SECTCR1_SECTL0_19 ((uint32_t)0x00000013) /*!< Sectl0 Bit length 19 */ +#define TSPI_SECTCR1_SECTL0_20 ((uint32_t)0x00000014) /*!< Sectl0 Bit length 20 */ +#define TSPI_SECTCR1_SECTL0_21 ((uint32_t)0x00000015) /*!< Sectl0 Bit length 21 */ +#define TSPI_SECTCR1_SECTL0_22 ((uint32_t)0x00000016) /*!< Sectl0 Bit length 22 */ +#define TSPI_SECTCR1_SECTL0_23 ((uint32_t)0x00000017) /*!< Sectl0 Bit length 23 */ +#define TSPI_SECTCR1_SECTL0_24 ((uint32_t)0x00000018) /*!< Sectl0 Bit length 24 */ +#define TSPI_SECTCR1_SECTL0_25 ((uint32_t)0x00000019) /*!< Sectl0 Bit length 25 */ +#define TSPI_SECTCR1_SECTL0_26 ((uint32_t)0x0000001a) /*!< Sectl0 Bit length 26 */ +#define TSPI_SECTCR1_SECTL0_27 ((uint32_t)0x0000001b) /*!< Sectl0 Bit length 27 */ +#define TSPI_SECTCR1_SECTL0_28 ((uint32_t)0x0000001c) /*!< Sectl0 Bit length 28 */ +#define TSPI_SECTCR1_SECTL0_29 ((uint32_t)0x0000001d) /*!< Sectl0 Bit length 29 */ +#define TSPI_SECTCR1_SECTL0_30 ((uint32_t)0x0000001e) /*!< Sectl0 Bit length 30 */ +#define TSPI_SECTCR1_SECTL0_31 ((uint32_t)0x0000001f) /*!< Sectl0 Bit length 31 */ +#define TSPI_SECTCR1_SECTL0_32 ((uint32_t)0x00000020) /*!< Sectl0 Bit length 32 */ +#define TSPI_SECTCR1_SECTL0_MASK ((uint32_t)0x0000003f) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_Sectcr1 Sectl0 */ + +/** + * @defgroup TSPI_Status_Setting_flag Status Setting Flag + * @brief Enable/Disable Status Setting Flag Macro Definisiton. + * @{ + */ +#define TSPI_STATUS_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define TSPI_STATUS_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group TSPI_Status_Setting_flag */ + + +/** + * @defgroup TSPI_TxState Transmitting State Flag + * @brief Transmitting State Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_TX_FLAG_ACTIVE ((uint32_t)0x00800000) /*!< Active Sending Data */ +#define TSPI_TX_FLAG_MASK ((uint32_t)0x00800000) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_TxState */ + + +/** + * @defgroup TSPI_TxDone Transmitting Complete Flag + * @brief Transmitting Complete Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_DONE_FLAG ((uint32_t)0x00400000) /*!< Send Data Complete Flag */ +#define TSPI_TX_DONE ((uint32_t)0x00400000) /*!< Send Data Complete */ +#define TSPI_TX_DONE_CLR ((uint32_t)0x00400000) /*!< Send Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxDone */ + + +/** + * @defgroup TSPI_TxFIFOInterruptFlag Transmitting FIFO Interrpt Flag + * @brief Transmitting FIFO Interrpt Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_TX_FIFO_INT_ACTIVE ((uint32_t)0x00200000) /*!< Active Interrupt */ +#define TSPI_TX_FIFO_INT_CLR ((uint32_t)0x00200000) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_TxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_TxFIFOEmptyFlag Transmitting FIFO Empty Flag + * @brief Transmitting FIFO Empty Flag Macro Definisiton. + * @{ + */ +#define TSPI_TX_FIFO_NOT_EMP ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_TX_FIFO_EMP ((uint32_t)0x00100000) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_TxFIFOEmptyFlag */ + +/** + * @defgroup TSPI_TxReachFillLevel Current Transmitting FIFO Level + * @brief Current Transmitting FIFO Level Macro Definisiton. + * @{ + */ +#define TSPI_TX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_TX_REACH_FILL_LEVEL_1 ((uint32_t)0x00010000) /*!< 1 */ +#define TSPI_TX_REACH_FILL_LEVEL_2 ((uint32_t)0x00020000) /*!< 2 */ +#define TSPI_TX_REACH_FILL_LEVEL_3 ((uint32_t)0x00030000) /*!< 3 */ +#define TSPI_TX_REACH_FILL_LEVEL_4 ((uint32_t)0x00040000) /*!< 4 */ +#define TSPI_TX_REACH_FILL_LEVEL_5 ((uint32_t)0x00050000) /*!< 5 */ +#define TSPI_TX_REACH_FILL_LEVEL_6 ((uint32_t)0x00060000) /*!< 6 */ +#define TSPI_TX_REACH_FILL_LEVEL_7 ((uint32_t)0x00070000) /*!< 7 */ +#define TSPI_TX_REACH_FILL_LEVEL_MASK ((uint32_t)0x00070000) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_TxReachFillLevel */ + + +/** + * @defgroup TSPI_RxState Receive State Flag + * @brief Receive State Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FLAG_STOP ((uint32_t)0x00000000) /*!< Not Sending Data */ +#define TSPI_RX_FLAG_ACTIVE ((uint32_t)0x00000080) /*!< Active Sending Data */ +#define TSPI_RX_FLAG_MASK ((uint32_t)0x00000080) /*!< Active Flag Mask */ +/** + * @} + */ /* End of group TSPI_RxState */ + + +/** + * @defgroup TSPI_RxDone Receive Complete Flag + * @brief Receive Complete Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_DONE_FLAG ((uint32_t)0x00000040) /*!< Receive Data Complete Flag */ +#define TSPI_RX_DONE ((uint32_t)0x00000040) /*!< Send Data Complete */ +#define TSPI_RX_DONE_CLR ((uint32_t)0x00000040) /*!< Receive Data Complete Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxDone */ + + +/** + * @defgroup TSPI_RxFIFOInterruptFlag Receiving FIFO Interrpt Flag + * @brief Rx FIFO Interrpt Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_INT_STOP ((uint32_t)0x00000000) /*!< Not active Interrupt */ +#define TSPI_RX_FIFO_INT_ACTIVE ((uint32_t)0x00000020) /*!< Active Interrupt */ +#define TSPI_RX_FIFO_INT_CLR ((uint32_t)0x00000020) /*!< Interrupt Flag Clear */ +/** + * @} + */ /* End of group TSPI_RxFIFOInterruptFlag */ + +/** + * @defgroup TSPI_RxFIFOFullFlag Receiving FIFO Full Flag + * @brief Receiving FIFO Full Flag Macro Definisiton. + * @{ + */ +#define TSPI_RX_FIFO_NOT_FULL ((uint32_t)0x00000000) /*!< Remain Data in FIFO */ +#define TSPI_RX_FIFO_FULL ((uint32_t)0x00000010) /*!< FIFO is empty */ +/** + * @} + */ /* End of group TSPI_RxFIFOFullFlag */ + + +/** + * @defgroup TSPI_RxReachFillLevel Current Receive FIFO Level + * @brief Current Receive FIFO Level Macro Definisiton. + * @{ + */ +#define TSPI_RX_REACH_FILL_LEVEL_0 ((uint32_t)0x00000000) /*!< 0 */ +#define TSPI_RX_REACH_FILL_LEVEL_1 ((uint32_t)0x00000001) /*!< 1 */ +#define TSPI_RX_REACH_FILL_LEVEL_2 ((uint32_t)0x00000002) /*!< 2 */ +#define TSPI_RX_REACH_FILL_LEVEL_3 ((uint32_t)0x00000003) /*!< 3 */ +#define TSPI_RX_REACH_FILL_LEVEL_4 ((uint32_t)0x00000004) /*!< 4 */ +#define TSPI_RX_REACH_FILL_LEVEL_5 ((uint32_t)0x00000005) /*!< 5 */ +#define TSPI_RX_REACH_FILL_LEVEL_6 ((uint32_t)0x00000006) /*!< 6 */ +#define TSPI_RX_REACH_FILL_LEVEL_7 ((uint32_t)0x00000007) /*!< 7 */ +#define TSPI_RX_REACH_FILL_LEVEL_MASK ((uint32_t)0x0000000F) /*!< TX_REACH_FILL_LEVEL_MASK */ +/** + * @} + */ /* End of group TSPI_RxReachFillLevel */ + + +/** + * @defgroup TSPI_TRGErr Triger Error + * @brief Triger Error Macro Definisiton. + * @{ + */ +#define TSPI_TRGERR_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_TRGERR_ERR ((uint32_t)0x00000008) /*!< Error */ +#define TSPI_TRGERR_MASK ((uint32_t)0x00000008) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_TRGErr */ + +/** + * @defgroup TSPI_UnderrunErr Underrun Error + * @brief Underrun Error Macro Definisiton. + * @{ + */ +#define TSPI_UNDERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_UNDERRUN_ERR ((uint32_t)0x00000004) /*!< Error */ +#define TSPI_UNDERRUN_MASK ((uint32_t)0x00000004) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_UnderrunErr */ + +/** + * @defgroup TSPI_OverrunErr Overrun Error + * @brief Overrun Error Macro Definisiton. + * @{ + */ +#define TSPI_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_OVERRUN_ERR ((uint32_t)0x00000002) /*!< Error */ +#define TSPI_OVERRUN_MASK ((uint32_t)0x00000002) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_OverrunErr */ + + +/** + * @defgroup TSPI_ParityErr Parity Error + * @brief Parity Error Macro Definisiton. + * @{ + */ +#define TSPI_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define TSPI_PARITY_ERR ((uint32_t)0x00000001) /*!< Error */ +#define TSPI_PARITY_MASK ((uint32_t)0x00000001) /*!< MASK */ +/** + * @} + */ /* End of group TSPI_ParityErr */ + +/** +* @defgroup TSPI_Data_allign Data allign +* @brief Data allign Macro Definisiton. +* @{ +*/ +#define TSPI_DATA_ALLIGN_8 ((uint32_t)0x00000000) /*!< Data length byte */ +#define TSPI_DATA_ALLIGN_16 ((uint32_t)0x00000001) /*!< Data length half word */ +#define TSPI_DATA_ALLIGN_32 ((uint32_t)0x00000002) /*!< Data length word */ +/** + * @} + */ /* End of group TSPI_Data_allign */ + +/** +* @defgroup TSPI_FifoMax FIFO MAX +* @brief FIFO MAX LEVEL +* @{ +*/ +#define TSPI_FIFO_MAX ((uint32_t)0x00000008) /*!< Data length byte */ +/** + * @} + */ /* End of group TSPI_FifoMax */ + +/** +* @defgroup TSPI_ErrCode Error Code +* @brief Error Code Macro Definisiton. +* @{ +*/ +#define NOERROR ((uint32_t)0x00000000) /*!< no error */ +#define TIMEOUTERR ((uint32_t)0x00000001) /*!< transmit/receive timeout error */ +#define DATALENGTHERR ((uint32_t)0x00000002) /*!< frame length setting error */ +#define DATABUFEMPERR ((uint32_t)0x00000003) /*!< transmit data empty error */ +#define DATALACKERR ((uint32_t)0x00000004) /*!< transmit data insufficient error */ +#define FIFOFULLERR ((uint32_t)0x00000005) /*!< FIFO Full error */ +#define TRANSMITMODEERR ((uint32_t)0x00000006) /*!< transmit mode error */ +#define UNDERRUNERR ((uint32_t)0x00000007) /*!< transmit mode error */ +#define OVERRUNERR ((uint32_t)0x00000008) /*!< transmit mode error */ +#define PARITYERR ((uint32_t)0x00000009) /*!< transmit mode error */ +#define INITERR ((uint32_t)0x000000) /*!< transmit mode error */ +/** +* @} + */ /* End of group TSPI_ErrCode */ + +/** +* @defgroup TSPI_Buffer_Size Receive Buffer size +* @brief Error Code Macro Definisiton. +* @{ +*/ +#define BUFFSIZE ((uint32_t)0x000000010 /*!< Buffer Size */ +/** +* @} + */ /* End of group TSPI_Buffer_Size */ +/** + * @} + */ /* End of group TSPI_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/* No define */ +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_Typedef TSPI Exported Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @struct tspi_receive8_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive8_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive16_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive16_t; + +/** + * @struct tspi_receive32_t + * @brief Receive event information structure definenition. + * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} tspi_receive32_t; + +/*----------------------------------*/ +/** + * @struct tspi_receive_t + * @brief Receive event information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + tspi_receive8_t rx8; /*!< @ref tspi_receive8_t */ + tspi_receive16_t rx16; /*!< @ref tspi_receive16_t */ + tspi_receive32_t rx32; /*!< @ref tspi_receive16_t */ +} tspi_receive_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit8_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "8bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit8_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit16_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "9 - 16 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit16_t; +/*----------------------------------*/ +/** + * @struct tspi_transmit32_t + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "17 - 32 bit"( @ref TSPI_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} tspi_transmit32_t; + +/*----------------------------------*/ +/** + * @struct tspi_transmit_t + * @brief Transmit data information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + tspi_transmit8_t tx8; /*!< @ref tspi_transmit8_t */ + tspi_transmit16_t tx16; /*!< @ref tspi_transmit16_t */ + tspi_transmit32_t tx32; /*!< @ref tspi_transmit16_t */ +} tspi_transmit_t; + +/*----------------------------------*/ +/** + * @struct tspi_control1_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inf; /*!< INF Transmission Infinity Control. + : Use @ref TSPI_Infinity_Control */ + uint32_t trgen; /*!< TRGEN Transmission Triger Control. + : Use @ref TSPI_Triger_Control */ + uint32_t trxe; /*!< TRXE Transmission Control. + : Use @ref TSPI_Transmission_Control */ + uint32_t tspims; /*!< TSPI/SIO Transmission Mode. + : Use @ref TSPI_Transmission_Mode */ + uint32_t mstr; /*!< Master/Slave Operation Select. + : Use @ref TSPI_Operation_Select */ + uint32_t tmmd; /*!< Transfer Mode Select. + : Use @ref TSPI_Transfer_Mode */ + uint32_t cssel; /*!< CSSEL Select. + : Use @ref TSPI_CSSEL_Select */ + uint32_t fc; /*!< Transfer Frame Value. + : Range ( TSPI_TRANS_RANGE_CONTINUE <= N =< TSPI_TRANS_RANGE_MAX ) @ref TSPI_Transfer_Frame_Range */ +} tspi_control1_t; + +/*----------------------------------*/ +/** + * @struct tspi_control2_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tidle; /*!< IDLE Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t txdemp; /*!< Under Run Occur Output Value. + : Use @ref TSPI_IDLE_Output_value */ + uint32_t rxdly; /*!< Fsys Select. + : Use @ref TSPI_RXDLY_value */ + uint32_t til; /*!< Transmit Fill Level. + : Use @ref TSPI_TxFillLevel */ + uint32_t ril; /*!< Receive Fill Level. + : Use @ref TSPI_RxFillLevel */ + uint32_t inttxfe; /*!< Enable/Disable Transmit FIFO Interrupt. + : Use @ref TSPI_TxFIFOInterrupt */ + uint32_t inttxwe; /*!< Enable/Disable Transmit Interrupt. + : Use @ref TSPI_TxInterrupt */ + uint32_t intrxfe; /*!< Enable/Disable Receive FIFO Interrupt. + : Use @ref TSPI_RxFIFOInterrupt */ + uint32_t intrxwe; /*!< Enable/Disable Receive Interrupt. + : Use @ref TSPI_RxInterrupt */ + uint32_t interr; /*!< Enable/Disable Error Interrupt. + : Use @ref TSPI_ErrorInterrupt */ + uint32_t dmate; /*!< Enable/Disable Transmit DMA Interrupt. + : Use @ref TSPI_TxDMAInterrupt */ + uint32_t dmare; /*!< Enable/Disable Receive DMA Interrupt. + : Use @ref TSPI_RxDMAInterrupt */ +} tspi_control2_t; + +/*----------------------------------*/ +/** + * @struct tspi_control3_t + * @brief Control Setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tfempclr; /*!< Transmit Buffer Clear. + : Use @ref TSPI_Tx_Buffer_Clear */ + uint32_t rffllclr; /*!< Receive Buffer Clear. + : Use @ref TSPI_Rx_Buffer_Clear */ +} tspi_control3_t; + +/*----------------------------------*/ +/** + * @struct tspi_baudrate_t + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t brck; /*!< Baudrate Input Clock. + : Use @ref TSPI_Baudrate_Clock */ + uint32_t brs; /*!< Baudrate Divider. + : Use @ref TSPI_Baudrate_Divider */ +} tspi_baudrate_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr0_t + * @brief Format control0. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t dir; /*!< Data Direction. + : Use @ref TSPI_DataDirection */ + uint32_t fl; /*!< Data Length. + : Use @ref TSPI_DataLength */ + uint32_t fint; /*!< Frame Interval time. + : Use @ref TSPI_Frame_Interval_Time */ + uint32_t cs3pol; /*!< TSPIIxCS3 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS3_Polarity */ + uint32_t cs2pol; /*!< TSPIIxCS2 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS2_Polarity */ + uint32_t cs1pol; /*!< TSPIIxCS1 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS1_Polarity */ + uint32_t cs0pol; /*!< TSPIIxCS0 Polarity negative/positive. + : Use @ref TSPI_TSPIxCS0_Polarity */ + uint32_t ckpha; /*!< Serial Clock Polarity 1st/2nd edge. + : Use @ref TSPI_Serial_Clock_Polarity */ + uint32_t ckpol; /*!< Serial Clock IDLE Polarity Hi/Low. + : Use @ref TSPI_Serial_Clock_IDLE_Polarity */ + uint32_t csint; /*!< Minimum IDLE Time. + : Use @ref TSPI_Minimum_IDLE_Time */ + uint32_t cssckdl; /*!< Serial Clock Delay. + : Use @ref TSPI_Serial_Clock_Delay */ + uint32_t sckcsdl; /*!< Negate Delay. + : Use @ref TSPI_Negate_Delay */ +} tspi_fmtr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_fmtr1_t + * @brief Format control1. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t reserved; /*!< SIO Slave MOde. + : */ + uint32_t vpe; /*!< Enable/Disable Parity Function. + : Use @ref TSPI_ParityEnable */ + uint32_t vpm; /*!< Odd/Even Parity Bit. + : Use @ref TSPI_ParityBit */ +} tspi_fmtr1_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr0_t + * @brief Sector Mode Control0 setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sect; /*!< Sector Mode Setting Bit. + : Use @ref TSPI_Mode Setting Bit */ +} tspi_sectcr0_t; + +/*----------------------------------*/ +/** + * @struct tspi_sectcr1_t + * @brief Sector Mode Control0 setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t sectl3; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector3 Bit length setting */ + uint32_t sectl2; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector2 Bit length setting */ + uint32_t sectl1; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector1 Bit length setting */ + uint32_t sectl0; /*!< Sector3 Bit length setting + : Use @ref TSPI_Sector1 Bit length setting */ +} tspi_sectcr1_t; +/*----------------------------------*/ +/** + * @struct tspi_status_t + * @brief Status register. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t tspisue; /*!< Enable/Disable Status Setting Flag. + : Use @ref TSPI_Status_Setting_flag */ + uint32_t txrun; /*!< Stop/Active Tx Active Flag. + : Use @ref TSPI_TxState */ + uint32_t txend; /*!< Tx Data Send Complete Flag. + : Use @ref TSPI_TxDone */ + uint32_t inttxwf; /*!< Tx FIFO Interrpt Flag. + : Use @ref TSPI_TxFIFOInterruptFlag */ + uint32_t tfemp; /*!< Tx FIFO Empty Flag. + : Use @ref TSPI_TxFIFOEmptyFlag */ + uint32_t tlvll; /*!< Tx Reach Fill Level + : Use @ref TSPI_TxReachFillLevel */ + uint32_t rxrun; /*!< Stop/Active Rx Active Flag. + : Use @ref TSPI_RxState */ + uint32_t rxend; /*!< Rx Data Receive Complete Flag. + : Use @ref TSPI_RxDone */ + uint32_t intrxff; /*!< Rx FIFO Interrpt Flag + : Use @ref TSPI_RxFIFOInterruptFlag */ + uint32_t rffll; /*!< Rx FIFO Full Flag + : Use @ref TSPI_RxFIFOFullFlag */ + uint32_t rlvl; /*!< Rx Reach Fill Level + : Use @ref TSPI_RxReachFillLevel */ +} tspi_status_t; + +/*----------------------------------*/ +/** + * @struct tspi_error_t + * @brief Error flag. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t udrerr; /*!< Underrun Error. + : Use @ref TSPI_UnderrunErr */ + uint32_t ovrerr; /*!< Overrun Error. + : Use @ref TSPI_OverrunErr */ + uint32_t perr; /*!< Parity Error. + : Use @ref TSPI_ParityErr */ +} tspi_error_t; + + +/*----------------------------------*/ +/** + * @struct tspi_initial_setting_t + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + tspi_control1_t cnt1; /*!< Control1 setting. + : Use @ref tspi_control1_t */ + tspi_control2_t cnt2; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_control3_t cnt3; /*!< Control2 setting. + : Use @ref tspi_control2_t */ + tspi_baudrate_t brd; /*!< Baudrate setting. + : Use @ref tspi_baudrate_t */ + tspi_fmtr0_t fmr0; /*!< Format control0 setting. + : Use @ref tspi_fmtr0_t */ + tspi_fmtr1_t fmr1; /*!< Format control1 setting. + : Use @ref tspi_fmtr1_t */ + tspi_sectcr0_t sectcr0; /*!< Sector Mode Control0 setting. + : Use @ref tspi_sectcr0_t */ + tspi_sectcr1_t sectcr1; /*!< Sector Mode Control1 setting. + : Use @ref tspi_sectcr1_t */ +} tspi_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief TSPI handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct tspi_handle { + TSB_TSPI_TypeDef *p_instance; /*!< Registers base address. */ + tspi_initial_setting_t init; /*!< Initial setting. */ + uint32_t errcode; /*!< ErrorCode */ + /*------------------------------------------*/ + /*! + @brief Transmit Informatin. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmited data. */ + tspi_transmit_t info; /*!< Transmit Data Information. */ + uint8_t tx_allign; /*!< Transmit Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Informatin. + */ + /*------------------------------------------*/ + struct { + tspi_receive_t info; /*!< Receive Data Information. */ + uint8_t rx_allign; /*!< Receive Data length Information. */ + void (*handler)(uint32_t id, TXZ_Result result, tspi_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} tspi_t; +/** + * @} + */ /* End of group TSPI_Exported_Typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Exported_functions TSPI Exported Functions + * @{ + */ +TXZ_Result tspi_init(tspi_t *p_obj); +TXZ_Result tspi_deinit(tspi_t *p_obj); +TXZ_Result tspi_format(tspi_t *p_obj); +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout); +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info); +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info); +void tspi_irq_handler_transmit(tspi_t *p_obj); +void tspi_irq_handler_receive(tspi_t *p_obj); +void tspi_error_irq_handler(tspi_t *p_obj); +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status); +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error); +TXZ_Result tspi_error_clear(tspi_t *p_obj); +TXZ_Result tspi_discard_transmit(tspi_t *p_obj); +TXZ_Result tspi_discard_receive(tspi_t *p_obj); +/** + * @} + */ /* End of group TSPI_Exported_functions */ +/** + * @} + */ /* End of group TSPI */ +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __TSPI_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart.h new file mode 100644 index 00000000000..14e1ab5912d --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart.h @@ -0,0 +1,810 @@ +/** + ******************************************************************************* + * @file txzp_uart.h + * @brief This file provides all the functions prototypes for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_H +#define __UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @defgroup UART UART + * @brief UART Driver. + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/** + * @defgroup UART_FifoMax Max Num of FIFO + * @brief Max Num of Tx/Rx Fifo. + * @{ + */ +#define UART_TX_FIFO_MAX ((uint32_t)0x00000008) /*!< TX FIFO Max. */ +#define UART_RX_FIFO_MAX ((uint32_t)0x00000008) /*!< RX FIFO Max. */ +/** + * @} + */ /* End of group UART_FifoMax */ + +/** + * @defgroup UART_HalfClockSelect Half Clock Select + * @brief Output Terminal Select + * @{ + */ +#define UART_HALF_CLOCK_UTxTXDA ((uint32_t)0x00000000) /*!< Half Clock output terminal select UTxTXDA. */ +#define UART_HALF_CLOCK_UTxTXDB ((uint32_t)0x00040000) /*!< Half Clock output terminal select UTxTXDB. */ +/** + * @} + */ /* End of group UART_HalfClockSelect */ + +/** + * @defgroup UART_HalfClockMode Half Clock Mode + * @brief Half Clock Mode Setting. + * @{ + */ +#define UART_HALF_CLOCK_MODE_1 ((uint32_t)0x00000000) /*!< Half Clock 1 terminal Mode. */ +#define UART_HALF_CLOCK_MODE_2 ((uint32_t)0x00020000) /*!< Half Clock 2 terminal Mode. */ +/** + * @} + */ /* End of group UART_HalfClockMode */ + +/** + * @defgroup UART_HalfClockCTR Half Clock Mode Control + * @brief Half Clock Control. + * @{ + */ +#define UART_HALF_CLOCK_DISABLE ((uint32_t)0x00000000) /*!< Half Clock Mode Disable. */ +#define UART_HALF_CLOCK_ENABLE ((uint32_t)0x00010000) /*!< Half Clock Mode Enable. */ +/** + * @} + */ /* End of group UART_HalfClockCTR */ + +/** + * @defgroup UART_LoopBack Loop Back Function + * @brief Half Clock Control. + * @{ + */ +#define UART_LOOPBACK_DISABLE ((uint32_t)0x00000000) /*!< Loop Back Function Disable. */ +#define UART_LOOPBACK_ENABLE ((uint32_t)0x00008000) /*!< Loop Back Function Enable. */ +/** + * @} + */ /* End of group UART_LoopBack */ + + +/** + * @defgroup UART_NoiseFilter Noise Filter + * @brief Noise Filter Setting. + * @{ + */ +#define UART_NOISE_FILTER_NON ((uint32_t)0x00000000) /*!< No Filetering. */ +#define UART_NOISE_FILTER_2_T0 ((uint32_t)0x00001000) /*!< A signal below the 2/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_4_T0 ((uint32_t)0x00002000) /*!< A signal below the 4/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_8_T0 ((uint32_t)0x00003000) /*!< A signal below the 8/T0 is filtering as noise. */ +#define UART_NOISE_FILTER_2_CLOCK ((uint32_t)0x00004000) /*!< A signal below the 2/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_3_CLOCK ((uint32_t)0x00005000) /*!< A signal below the 3/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_4_CLOCK ((uint32_t)0x00006000) /*!< A signal below the 4/Clock is filtering as noise. */ +#define UART_NOISE_FILTER_5_CLOCK ((uint32_t)0x00007000) /*!< A signal below the 5/Clock is filtering as noise */ +/** + * @} + */ /* End of group UART_NoiseFilter */ + + +/** + * @defgroup UART_CTSHandshake CTS Handshake + * @brief Available CTS Handshake Macro Definisiton. + * @{ + */ +#define UART_CTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_CTS_ENABLE ((uint32_t)0x00000400) /*!< Available. */ +/** + * @} + */ /* End of group UART_CTSHandshake */ + + +/** + * @defgroup UART_RTSHandshake RTS Handshake + * @brief Available RTS Handshake Macro Definisiton. + * @{ + */ +#define UART_RTS_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RTS_ENABLE ((uint32_t)0x00000200) /*!< Available. */ +/** + * @} + */ /* End of group UART_RTSHandshake */ + + +/** + * @defgroup UART_DataComplementation Data Complementation + * @brief Enable/Disable Data Signal Complementation Macro Definisiton. + * @{ + */ +#define UART_DATA_COMPLEMENTION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DATA_COMPLEMENTION_ENABLE ((uint32_t)0x00000040) /*!< Enable */ +/** + * @} + */ /* End of group UART_DataComplementation */ + + +/** + * @defgroup UART_DataDirection Data Direction + * @brief Data Direction Macro Definisiton. + * @{ + */ +#define UART_DATA_DIRECTION_LSB ((uint32_t)0x00000000) /*!< LSB first */ +#define UART_DATA_DIRECTION_MSB ((uint32_t)0x00000020) /*!< MSB first */ +/*! + * @} + */ /* End of group UART_DataDirection */ + + +/** + * @defgroup UART_StopBit Stop Bit + * @brief Stop Bit Macro Definisiton. + * @{ + */ +#define UART_STOP_BIT_1 ((uint32_t)0x00000000) /*!< 1 bit */ +#define UART_STOP_BIT_2 ((uint32_t)0x00000010) /*!< 2 bit */ +/** + * @} + */ /* End of group UART_StopBit */ + + +/** + * @defgroup UART_ParityBit Parity Bit + * @brief Parity Bit Macro Definisiton. + * @{ + */ +#define UART_PARITY_BIT_ODD ((uint32_t)0x00000000) /*!< Odd Parity */ +#define UART_PARITY_BIT_EVEN ((uint32_t)0x00000008) /*!< Even Parity */ +/** + * @} + */ /* End of group UART_ParityBit */ + + +/** + * @defgroup UART_ParityEnable Parity Enable + * @brief Enable/Disable Parity Macro Definisiton. + * @{ + */ +#define UART_PARITY_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_PARITY_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ParityEnable */ + + +/** + * @defgroup UART_DataLength Data Length + * @brief Data Length Macro Definisiton. + * @{ + */ +#define UART_DATA_LENGTH_7 ((uint32_t)0x00000000) /*!< 7 bit */ +#define UART_DATA_LENGTH_8 ((uint32_t)0x00000001) /*!< 8 bit */ +#define UART_DATA_LENGTH_9 ((uint32_t)0x00000002) /*!< 9 bit */ +/** + * @} + */ /* End of group UART_DataLength */ + + +/** + * @defgroup UART_TxFillLevelRange Tx Fill Level Range + * @brief Transmit Fill Level Range Macro Definisiton. + * @brief Range of Value be set "(UART_TX_FILL_LEVEL_MIN <= Value <= UART_TX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_TX_FILL_RANGE_MIN ((uint32_t)0x00000000) /*!< Minimum Value :1 */ +#define UART_TX_FILL_RANGE_MAX ((uint32_t)0x00000007) /*!< Maximum Value :7 */ +/*! + * @} + */ /* End of group UART_TxFillLevelRange */ + + +/** + * @defgroup UART_RxFillLevelRange Rx Fill Level Range + * @brief Receive Fill Level Range Macro Definisiton. + * @brief Range of Value be set "(UART_RX_FILL_LEVEL_MIN <= Value <= UART_RX_FILL_LEVEL_MAX)". + * @{ + */ +#define UART_RX_FILL_RANGE_MIN ((uint32_t)0x00000001) /*!< Minimum Value :1 */ +#define UART_RX_FILL_RANGE_MAX ((uint32_t)0x00000008) /*!< Maximum Value :8 */ +/** + * @} + */ /* End of group UART_RxFillLevelRange */ + + +/** + * @defgroup UART_TxFIFOInterrupt Tx FIFO Interrpt + * @brief Available Transmit FIFO Interrupt Macro Definisiton. + * @{ + */ +#define UART_TX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_FIFO_INT_ENABLE ((uint32_t)0x00000080) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxFIFOInterrupt */ + + +/** + * @defgroup UART_TxInterrupt Tx Interrpt + * @brief Available Transmit Interrupt Macro Definisiton. + * @{ + */ +#define UART_TX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_TX_INT_ENABLE ((uint32_t)0x00000040) /*!< Available. */ +/** + * @} + */ /* End of group UART_TxInterrupt */ + + +/** + * @defgroup UART_RxFIFOInterrupt Rx FIFO Interrpt + * @brief Available Receive FIFO Interrupt Macro Definisiton. + * @{ + */ +#define UART_RX_FIFO_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_FIFO_INT_ENABLE ((uint32_t)0x00000020) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxFIFOInterrupt */ + + +/** + * @defgroup UART_RxInterrupt Rx Interrpt + * @brief Available Receive Interrupt Macro Definisiton. + * @{ + */ +#define UART_RX_INT_DISABLE ((uint32_t)0x00000000) /*!< Not Available. */ +#define UART_RX_INT_ENABLE ((uint32_t)0x00000010) /*!< Available. */ +/** + * @} + */ /* End of group UART_RxInterrupt */ + + +/** + * @defgroup UART_ErrorInterrupt Error Interrupt + * @brief Enable/Disable Error Interrupt Macro Definisiton. + * @{ + */ +#define UART_ERR_INT_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_ERR_INT_ENABLE ((uint32_t)0x00000004) /*!< Enable */ +/** + * @} + */ /* End of group UART_ErrorInterrupt */ + + +/** + * @defgroup UART_Prescaler Prescaler + * @brief Prescaler Macro Definisiton. + * @{ + */ +#define UART_PLESCALER_1 ((uint32_t)0x00000000) /*!< 1/1 */ +#define UART_PLESCALER_2 ((uint32_t)0x00000010) /*!< 1/2 */ +#define UART_PLESCALER_4 ((uint32_t)0x00000020) /*!< 1/4 */ +#define UART_PLESCALER_8 ((uint32_t)0x00000030) /*!< 1/8 */ +#define UART_PLESCALER_16 ((uint32_t)0x00000040) /*!< 1/16 */ +#define UART_PLESCALER_32 ((uint32_t)0x00000050) /*!< 1/32 */ +#define UART_PLESCALER_64 ((uint32_t)0x00000060) /*!< 1/64 */ +#define UART_PLESCALER_128 ((uint32_t)0x00000070) /*!< 1/128 */ +#define UART_PLESCALER_256 ((uint32_t)0x00000080) /*!< 1/256 */ +#define UART_PLESCALER_512 ((uint32_t)0x00000090) /*!< 1/512 */ +/** + * @} + */ /* End of group UART_Prescaler */ + + +/** + * @defgroup UART_Clock_Mask Clock Mask + * @brief Clock Mask Macro Definisiton. + * @{ + */ +#define UART_UARTxCLK_MASK ((uint32_t)0x00000000) /*!< [1:0] is always 0 */ +/** + * @} + */ /* End of group UART_Clock_Mask */ + + +/** + * @defgroup UART_Division Division + * @brief Enable/Disable Division Macro Definisiton. + * @{ + */ +#define UART_DIVISION_DISABLE ((uint32_t)0x00000000) /*!< Disable */ +#define UART_DIVISION_ENABLE ((uint32_t)0x00800000) /*!< Enable */ +/** + * @} + */ /* End of group UART_Division */ + + +/** + * @defgroup UART_RangeK Range K + * @brief Range of K Macro Definisiton. + * @brief Range of K be set "(UART_RANGE_K_MIN <= Value <= UART_RANGE_K_MAX)". + * @{ + */ +#define UART_RANGE_K_MIN ((uint32_t)0x00000000) /*!< Minimum Value :K=0 */ +#define UART_RANGE_K_MAX ((uint32_t)0x0000003F) /*!< Maximum Value :K=63 */ +/** + * @} + */ /* End of group UART_RangeK */ + + +/** + * @defgroup UART_RangeN Range N + * @brief Range of N Macro Definisiton. + * @brief Range of N be set "(UART_RANGE_N_MIN <= Value <= UART_RANGE_N_MAX)". + * @{ + */ +#define UART_RANGE_N_MIN ((uint32_t)0x00000001) /*!< Minimum Value :N=1 */ +#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF) /*!< Maximum Value :N=65535 */ +/** + * @} + */ /* End of group UART_RangeN */ + + +/** + * @defgroup UART_SettingEnable Setting Enable + * @brief Enable/Disable Setting Macro Definisiton. + * @{ + */ +#define UART_SETTING_MASK ((uint32_t)0x80000000) /*!< for Mask */ +#define UART_SETTING_ENABLE ((uint32_t)0x00000000) /*!< Setting Enable */ +#define UART_SETTING_DISABLE ((uint32_t)0x80000000) /*!< Setting Disable */ +/** + * @} + */ /* End of group UART_SettingEnable */ + + +/** + * @defgroup UART_TxState Tx State + * @brief Transmitting State Macro Definisiton. + * @{ + */ +#define UART_TX_STATE_MASK ((uint32_t)0x00008000) /*!< for Mask */ +#define UART_TX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_TX_STATE_RUN ((uint32_t)0x00008000) /*!< Run */ +/** + * @} + */ /* End of group UART_TxState */ + + +/** + * @defgroup UART_TxDone Transmitting Done + * @brief Transmitting Done Macro Definisiton. + * @{ + */ +#define UART_TX_MASK ((uint32_t)0x00004000) /*!< for Mask */ +#define UART_TX_DONE ((uint32_t)0x00004000) /*!< Transmitting Done */ +/** + * @} + */ /* End of group UART_TxDone */ + + +/** + * @defgroup UART_TxReachFillLevel Tx Reach Fill Level + * @brief Reach Transmitting Fill Level Macro Definisiton. + * @{ + */ +#define UART_TX_REACH_FILL_MASK ((uint32_t)0x00002000) /*!< for Mask */ +#define UART_TX_REACH_FILL_LEVEL ((uint32_t)0x00002000) /*!< Reach Transmitting Fill Level */ +/** + * @} + */ /* End of group UART_TxReachFillLevel */ + + +/** + * @defgroup UART_TxFifoLevel Tx FIFO Fill Level + * @brief Transmitting FIFO Fill Level Macro Definisiton. + * @{ + */ +#define UART_TX_FIFO_LEVEL_MASK ((uint32_t)0x00000F00) /*!< for Mask */ +/** + * @} + */ /* End of group UART_TxFifoLevel */ + + +/** + * @defgroup UART_RxState Rx State + * @brief Receive State Macro Definisiton. + * @{ + */ +#define UART_RX_STATE_MASK ((uint32_t)0x00000080) /*!< for Mask */ +#define UART_RX_STATE_SLEEP ((uint32_t)0x00000000) /*!< Sleep */ +#define UART_RX_STATE_RUN ((uint32_t)0x00000080) /*!< Run */ +/** + * @} + */ /* End of group UART_RxState */ + + +/** + * @defgroup UART_RxDone Rx Done + * @brief Receive Done Macro Definisiton. + * @{ + */ +#define UART_RX_MASK ((uint32_t)0x00000040) /*!< for Mask */ +#define UART_RX_DONE ((uint32_t)0x00000040) /*!< Receive Done */ +/** + * @} + */ /* End of group UART_RxDone */ + + +/** + * @defgroup UART_RxReachFillLevel Rx Reach Fill Level + * @brief Reach Receive Fill Level Macro Definisiton. + * @{ + */ +#define UART_RX_REACH_FILL_MASK ((uint32_t)0x00000020) /*!< for Mask */ +#define UART_RX_REACH_FILL_LEVEL ((uint32_t)0x00000020) /*!< Reach Receive Fill Level */ +/** + * @} + */ /* End of group UART_RxReachFillLevel */ + + +/** + * @defgroup UART_RxFifoLevel Rx FIFO Fill Level + * @brief Receive FIFO Fill Level Macro Definisiton. + * @{ + */ +#define UART_RX_FIFO_LEVEL_MASK ((uint32_t)0x0000000F) /*!< for Mask */ +/** + * @} + */ /* End of group UART_RxFifoLevel */ + + +/** + * @defgroup UART_TriggerErr Trigger Error + * @brief Trigger Error Macro Definisiton. + * @{ + */ +#define UART_TRIGGER_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_TRIGGER_ERR ((uint32_t)0x00000010) /*!< Error */ +/** + * @} + */ /* End of group UART_TxTriggerErr */ + + +/** + * @defgroup UART_OverrunErr Overrun Error + * @brief Overrun Error Macro Definisiton. + * @{ + */ +#define UART_OVERRUN_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_OVERRUN_ERR ((uint32_t)0x00000008) /*!< Error */ +/** + * @} + */ /* End of group UART_OverrunErr */ + + +/** + * @defgroup UART_ParityErr Parity Error + * @brief Parity Error Macro Definisiton. + * @{ + */ +#define UART_PARITY_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_PARITY_ERR ((uint32_t)0x00000004) /*!< Error */ +/** + * @} + */ /* End of group UART_ParityErr */ + + +/** + * @defgroup UART_FramingErr Framing Error + * @brief Framing Error Macro Definisiton. + * @{ + */ +#define UART_FRAMING_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_FRAMING_ERR ((uint32_t)0x00000002) /*!< Error */ +/** + * @} + */ /* End of group UART_FramingErr */ + + +/** + * @defgroup UART_BreakErr Break Error + * @brief Break Error Macro Definisiton. + * @{ + */ +#define UART_BREAK_NO_ERR ((uint32_t)0x00000000) /*!< No Error */ +#define UART_BREAK_ERR ((uint32_t)0x00000001) /*!< Error */ +/** + * @} + */ /* End of group UART_BreakErr */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_define UART Exported Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Exported_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_typedef UART Exported Typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief Receive event information structure definenition. + * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. + * @attention "num" must be over FIFO max num. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive8_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definenition. + * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to receive data. */ + uint32_t num; /*!< The number of receive data. */ +} uart_receive16_t; + +/*----------------------------------*/ +/** + * @brief Receive event information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + uart_receive8_t rx8; /*!< @ref uart_receive8_t */ + uart_receive16_t rx16; /*!< @ref uart_receive16_t */ +} uart_receive_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "7 or 8bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint8_t *p_data; /*!< The buffer to transmit data. */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit8_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definenition. + * @brief When data length definenition is "9bit"( @ref UART_DataLength ), use this. +*/ +/*----------------------------------*/ +typedef struct { + uint16_t *p_data; /*!< The buffer to transmit data. + Rransmit data valid range is ( 0x0000 <= range <= 0x01FF ) */ + uint32_t num; /*!< The number of transmit data. */ +} uart_transmit16_t; + +/*----------------------------------*/ +/** + * @brief Transmit data information structure definenition. +*/ +/*----------------------------------*/ +typedef union { + uart_transmit8_t tx8; /*!< @ref uart_transmit8_t */ + uart_transmit16_t tx16; /*!< @ref uart_transmit16_t */ +} uart_transmit_t; + +/*----------------------------------*/ +/** + * @brief Clock setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t prsel; /*!< Prescaler. + : Use @ref UART_Prescaler */ +} uart_clock_t; + +/*----------------------------------*/ +/** + * @brief Boudrate setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t ken; /*!< Enable/Disable Division Definisiton. + : Use @ref UART_Division */ + uint32_t brk; /*!< Division Value K. + : K Range ( UART_RANGE_K_MIN <= K =< UART_RANGE_K_MAX ) @ref UART_RangeK */ + uint32_t brn; /*!< Division Value N. + : N Range ( UART_RANGE_N_MIN <= N =< UART_RANGE_N_MAX ) @ref UART_RangeN */ +} uart_boudrate_t; + +/*----------------------------------*/ +/** + * @brief Transmit FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t inttx; /*!< Available Transmit FIFO Interrupt. + : Use @ref UART_TxFIFOInterrupt */ + uint32_t level; /*!< Transmit Fill Level. + : Range ( UART_TX_FILL_RANGE_MIN <= K =< UART_TX_FILL_RANGE_MAX ) @ref UART_TxFillLevelRange */ +} uart_tx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Receive FIFO setting. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t intrx; /*!< Available Receive FIFO Interrupt. + : Use @ref UART_RxFIFOInterrupt */ + uint32_t level; /*!< Receive Fill Level. + : Range ( UART_RX_FILL_RANGE_MIN <= K =< UART_RX_FILL_RANGE_MAX ) @ref UART_RxFillLevelRange */ +} uart_rx_fifo_t; + +/*----------------------------------*/ +/** + * @brief Initial setting structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + uint32_t id; /*!< ID: User value. */ + uart_clock_t clock; /*!< Clock setting. + : Use @ref uart_clock_t */ + uart_boudrate_t boudrate; /*!< Boudrate setting. + : Use @ref uart_boudrate_t */ + uint32_t inttx; /*!< Available Transmit Interrupt. + : Use @ref UART_TxInterrupt */ + uint32_t intrx; /*!< Available Receive Interrupt. + : Use @ref UART_RxInterrupt */ + uint32_t interr; /*!< Available Error Interrupt. + : Use @ref UART_ErrorInterrupt */ + uart_tx_fifo_t txfifo; /*!< Transmit FIFO setting. + : Use @ref uart_tx_fifo_t */ + uart_rx_fifo_t rxfifo; /*!< Receive FIFO setting. + : Use @ref uart_rx_fifo_t */ + uint32_t hct; /*!< Half Clock Terminal Select. + : Use @ref UART_HalfClockSelect */ + uint32_t hcm; /*!< Half Clock Mode Select. + : Use @ref UART_HalfClockMode */ + uint32_t hcc; /*!< Half Clock Control. + : Use @ref UART_HalfClockCTR */ + uint32_t lbc; /*!< Loop Back Control. + : Use @ref UART_LoopBack */ + uint32_t nf; /*!< UTxRXD Noise Filter. + : Use @ref UART_NoiseFilter */ + uint32_t ctse; /*!< Available CTS Handshake. + : Use @ref UART_CTSHandshake */ + uint32_t rtse; /*!< Available RTS Handshake. + : Use @ref UART_RTSHandshake */ + uint32_t iv; /*!< Data Signal Complementation. + : Use @ref UART_DataComplementation */ + uint32_t dir; /*!< Data Direction. + : Use @ref UART_DataDirection */ + uint32_t sblen; /*!< Stop Bit. + : Use @ref UART_StopBit */ + uint32_t even; /*!< Odd/Even Parity Bit. + : Use @ref UART_ParityBit */ + uint32_t pe; /*!< Enable/Disable Parity Bit. + : Use @ref UART_ParityEnable */ + uint32_t sm; /*!< Data Length. + : Use @ref UART_DataLength */ +} uart_initial_setting_t; + +/*----------------------------------*/ +/** + * @brief UART handle structure definenition. +*/ +/*----------------------------------*/ +typedef struct { + TSB_UART_TypeDef *p_instance; /*!< Registers base address. */ + uart_initial_setting_t init; /*!< Initial setting. */ + /*------------------------------------------*/ + /*! + @brief Transmit Informatin. + */ + /*------------------------------------------*/ + struct { + uint32_t rp; /*!< Num of transmited data. */ + uart_transmit_t info; /*!< Transmit Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result); /*!< Transmit Event handler. */ + } transmit; + /*------------------------------------------*/ + /*! + @brief Receive Informatin. + */ + /*------------------------------------------*/ + struct { + uart_receive_t info; /*!< Receive Data Information. */ + void (*handler)(uint32_t id, TXZ_Result result, uart_receive_t *p_info); /*!< Receive Event handler. */ + } receive; +} uart_t; + +/** + * @} + */ /* End of group UART_Exported_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Exported_functions UART Exported Functions + * @{ + */ +TXZ_Result uart_init(uart_t *p_obj); +TXZ_Result uart_deinit(uart_t *p_obj); +TXZ_Result uart_discard_transmit(uart_t *p_obj); +TXZ_Result uart_discard_receive(uart_t *p_obj); +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info); +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info); +void uart_transmit_irq_handler(uart_t *p_obj); +void uart_receive_irq_handler(uart_t *p_obj); +void uart_error_irq_handler(uart_t *p_obj); +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status); +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error); +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_setting); +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart_include.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart_include.h new file mode 100644 index 00000000000..5e18c322bf3 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/inc/txzp_uart_include.h @@ -0,0 +1,484 @@ +/** + ******************************************************************************* + * @file txzp_uart_include.h + * @brief This file provides internal common definition. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +/*------------------------------------------------------------------------------*/ +/* Define to prevent recursive inclusion */ +/*------------------------------------------------------------------------------*/ +#ifndef __UART_INCLUDE_H +#define __UART_INCLUDE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_driver_def.h" + +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/** + * @defgroup UART_NullPointer Null Pointer + * @brief Null Pointer. + * @{ + */ +#define UART_NULL ((void *)0) +/** + * @} + */ /* End of group UART_NullPointer */ + +/** + * @defgroup UART_ParameterResult Parameter Check Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define UART_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define UART_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of group UART_ParameterResult */ + +/** + * @defgroup UARTxSWRST UARTxSWRST Register + * @brief UARTxSWRST Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-8 | - | + * | 7 | SWRSTF | + * | 6:2 | - | + * | 1:0 | SWRST | + * @{ + */ +/* SWRSTF */ +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) /*!< SWRSTF :Mask. */ +#define UARTxSWRST_SWRSTF_IDLE ((uint32_t)0x00000000) /*!< SWRSTF :Not be "Software Reset". */ +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) /*!< SWRSTF :During "Software Reset". */ +/* SWRST */ +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) /*!< SWRST :"10" */ +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) /*!< SWRST :"01" */ +/** + * @} + */ /* End of group UARTxSWRST */ + +/** + * @defgroup UARTxCR0 UARTxCR0 Register + * @brief UARTxCR0 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | HBSST | + * | 17 | HBSMD | + * | 16 | HBSEN | + * | 15 | LPB | + * | 14-12 | NF[2:0] | + * | 11 | - | + * | 10 | CTSE | + * | 9 | RTSE | + * | 8 | WU | + * | 7 | - | + * | 6 | IV | + * | 5 | DIR | + * | 4 | SBLEN | + * | 3 | EVEN | + * | 2 | PE | + * | 1-0 | SM[1:0] | + * @{ + */ +/* HBSST */ +#define UARTxCR0_HBSST_MASK ((uint32_t)0x00040000) /*!< HBSST :Mask. */ +/* HBSMD */ +#define UARTxCR0_HBSMD_MASK ((uint32_t)0x00020000) /*!< HBSMD :Mask. */ +/* HBSEN */ +#define UARTxCR0_HBSEN_MASK ((uint32_t)0x00010000) /*!< HBSEN :Mask. */ +#define UARTxCR0_HBSEN_DISABLE ((uint32_t)0x00000000) /*!< HBSEN :Disable. */ +#define UARTxCR0_HBSEN_ENABLE ((uint32_t)0x00010000) /*!< HBSEN :Enable. */ +/* LPB */ +#define UARTxCR0_LPB_MASK ((uint32_t)0x00008000) /*!< LPB :Mask. */ +#define UARTxCR0_LPB_DISABLE ((uint32_t)0x00000000) /*!< LPB :Disable. */ +#define UARTxCR0_LPB_ENABLE ((uint32_t)0x00008000) /*!< LPB :Enable. */ +/* WU */ +#define UARTxCR0_WU_MASK ((uint32_t)0x00000100) /*!< WU :Mask. */ +#define UARTxCR0_WU_DISABLE ((uint32_t)0x00000000) /*!< WU :Disable. */ +#define UARTxCR0_WU_ENABLE ((uint32_t)0x00000100) /*!< WU :Enable. */ +/** + * @} + */ /* End of group UARTxCR0 */ + +/** + * @defgroup UARTxCR1 UARTxCR1 Register + * @brief UARTxCR1 Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-15 | - | + * | 14-12 | TIL[2:0] | + * | 11 | - | + * | 10-8 | RIL[2:0] | + * | 7 | INTTXFE | + * | 6 | INTTXWE | + * | 5 | INTRXFE | + * | 4 | INTRXWE | + * | 3 | - | + * | 2 | INTERR | + * | 1 | DMATE | + * | 0 | DMARE | + * @{ + */ +/* RIL */ +#define UARTxCR1_RIL_MASK ((uint32_t)0x00000700) /*!< RIL :Mask. */ +/* DMATE */ +#define UARTxCR1_DMATE_MASK ((uint32_t)0x00000002) /*!< DMATE :Mask. */ +#define UARTxCR1_DMATE_DISABLE ((uint32_t)0x00000000) /*!< DMATE :Disable. */ +#define UARTxCR1_DMATE_ENABLE ((uint32_t)0x00000002) /*!< DMATE :Enable. */ +/* DMARE */ +#define UARTxCR1_DMARE_MASK ((uint32_t)0x00000001) /*!< DMARE :Mask. */ +#define UARTxCR1_DMARE_DISABLE ((uint32_t)0x00000000) /*!< DMARE :Disable. */ +#define UARTxCR1_DMARE_ENABLE ((uint32_t)0x00000001) /*!< DMARE :Enable. */ +/** + * @} + */ /* End of group UARTxCR1 */ + +/** + * @defgroup UARTxTRANS UARTxTRANS Register + * @brief UARTxTRANS Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-4 | - | + * | 3 | BK | + * | 2 | TXTRG | + * | 1 | TXE | + * | 0 | RXE | + * @{ + */ +/* BK */ +#define UARTxTRANS_BK_MASK ((uint32_t)0x00000008) /*!< BK :Mask */ +#define UARTxTRANS_BK_STOP ((uint32_t)0x00000000) /*!< BK :Stop */ +#define UARTxTRANS_BK_SEND ((uint32_t)0x00000008) /*!< BK :Send */ +/* TXTRG */ +#define UARTxTRANS_TXTRG_MASK ((uint32_t)0x00000004) /*!< TXTRG :Mask */ +#define UARTxTRANS_TXTRG_DISABLE ((uint32_t)0x00000000) /*!< TXTRG :Disable */ +#define UARTxTRANS_TXTRG_ENABLE ((uint32_t)0x00000004) /*!< TXTRG :Enable */ +/* TXE */ +#define UARTxTRANS_TXE_MASK ((uint32_t)0x00000002) /*!< TXE :Mask */ +#define UARTxTRANS_TXE_DISABLE ((uint32_t)0x00000000) /*!< TXE :Disable */ +#define UARTxTRANS_TXE_ENABLE ((uint32_t)0x00000002) /*!< TXE :Enable */ +/* RXE */ +#define UARTxTRANS_RXE_MASK ((uint32_t)0x00000001) /*!< RXE :Mask */ +#define UARTxTRANS_RXE_DISABLE ((uint32_t)0x00000000) /*!< RXE :Disable */ +#define UARTxTRANS_RXE_ENABLE ((uint32_t)0x00000001) /*!< RXE :Enable */ +/* TXE,RXE */ +#define UARTxTRANS_TXE_RXE_MASK ((uint32_t)0x00000003) /*!< TXE/RXE:Mask */ +/** + * @} + */ /* End of group UARTxTRANS */ + +/** + * @defgroup UARTxDR UARTxDR Register + * @brief UARTxDR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-19 | - | + * | 18 | PERR | + * | 17 | FERR | + * | 16 | BERR | + * | 15:9 | - | + * | 8:0 | DR | + * @{ + */ +/* DR */ +#define UARTxDR_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 9bit */ +#define UARTxDR_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define UARTxDR_DR_7BIT_MASK ((uint32_t)0x0000007F) /*!< DR :Mask for 7bit */ +/** + * @} + */ /* End of group UARTxDR */ + +/** + * @defgroup UARTxSR UARTxSR Register + * @brief UARTxSR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31 | SUE | + * | 30:16 | - | + * | 15 | TXRUN | + * | 14 | TXEND | + * | 13 | TXFF | + * | 12 | - | + * | 11:8 | TLVL | + * | 7 | RXRUN | + * | 6 | RXEND | + * | 5 | RXFF | + * | 4 | - | + * | 3:0 | RLVL | + * @{ + */ +/* SUE */ +#define UARTxSR_SUE_MASK ((uint32_t)0x80000000) /*!< SUE :Mask. */ +/* TXEND */ +#define UARTxSR_TXEND_MASK ((uint32_t)0x00004000) /*!< TEXND :Mask. */ +#define UARTxSR_TXEND_R_END ((uint32_t)0x00004000) /*!< TXEND :[read] Transfer done. */ +#define UARTxSR_TXEND_W_CLEAR ((uint32_t)0x00004000) /*!< TXEND :[write] Clear Flag. */ +/* TXFF */ +#define UARTxSR_TXFF_MASK ((uint32_t)0x00002000) /*!< TXFF :Mask. */ +#define UARTxSR_TXFF_R_REACHED ((uint32_t)0x00002000) /*!< TXFF :[read] Reached the transfer level. */ +#define UARTxSR_TXFF_W_CLEAR ((uint32_t)0x00002000) /*!< TXFF :[write] Clear Flag. */ +/* TLVL */ +#define UARTxSR_TLVL_MASK ((uint32_t)0x00000F00) /*!< TLVL :Mask. */ +/* RXEND */ +#define UARTxSR_RXEND_MASK ((uint32_t)0x00000040) /*!< RXEND :Mask. */ +#define UARTxSR_RXEND_R_END ((uint32_t)0x00000040) /*!< RXEND :[read] Receive done. */ +#define UARTxSR_RXEND_W_CLEAR ((uint32_t)0x00000040) /*!< RXEND :[write] Clear Flag. */ +/* RXFF */ +#define UARTxSR_RXFF_MASK ((uint32_t)0x00000020) /*!< RXFF :Mask. */ +#define UARTxSR_RXFF_R_REACHED ((uint32_t)0x00000020) /*!< RXFF :[read] Receive done. */ +#define UARTxSR_RXFF_W_CLEAR ((uint32_t)0x00000020) /*!< RXFF :[write] Clear Flag. */ +/* RLVL */ +#define UARTxSR_RLVL_MASK ((uint32_t)0x0000000F) /*!< RLVL :Mask. */ +/** + * @} + */ /* End of group UARTxSR */ + +/** + * @defgroup UARTxFIFOCLR UARTxFIFOCLR Register + * @brief UARTxFIFOCLR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-2 | - | + * | 1 | TFCLR | + * | 0 | RFCLR | + * @{ + */ +/* TFCLR */ +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) /*!< TFCLR :Clear the transmit buff. */ +/* RFCLR */ +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) /*!< RFCLR :Clear the receive buff. */ +/** + * @} + */ /* End of group UARTxFIFOCLR */ + +/** + * @defgroup UARTxERR UARTxERR Register + * @brief UARTxERR Register Definition. + * @details Detail. + * | Bit | Bit Symbol | + * | :--- | :--- | + * | 31-5 | - | + * | 4 | TRGERR | + * | 3 | OVRERR | + * | 2 | PERR | + * | 1 | FERR | + * | 0 | BERR | + * @{ + */ +/* TRGERR */ +#define UARTxERR_TRGERR_MASK ((uint32_t)0x00000010) /*!< TRGERR :Mask. */ +#define UARTxERR_TRGERR_R_NO_ERR ((uint32_t)0x00000000) /*!< TRGERR :[read] No Error. */ +#define UARTxERR_TRGERR_R_ERR ((uint32_t)0x00000010) /*!< TRGERR :[read] Error. */ +#define UARTxERR_TRGERR_W_CLEAR ((uint32_t)0x00000010) /*!< TRGERR :[write] Clear Flag. */ +/* OVRERR */ +#define UARTxERR_OVRERR_MASK ((uint32_t)0x00000008) /*!< OVRERR :Mask. */ +#define UARTxERR_OVRERR_R_NO_ERR ((uint32_t)0x00000000) /*!< OVRERR :[read] No Error. */ +#define UARTxERR_OVRERR_R_ERR ((uint32_t)0x00000008) /*!< OVRERR :[read] Error. */ +#define UARTxERR_OVRERR_W_CLEAR ((uint32_t)0x00000008) /*!< OVRERR :[write] Clear Flag. */ +/* PERR */ +#define UARTxERR_PERR_MASK ((uint32_t)0x00000004) /*!< PERR :Mask. */ +#define UARTxERR_PERR_R_NO_ERR ((uint32_t)0x00000000) /*!< PERR :[read] No Error. */ +#define UARTxERR_PERR_R_ERR ((uint32_t)0x00000004) /*!< PERR :[read] Error. */ +#define UARTxERR_PERR_W_CLEAR ((uint32_t)0x00000004) /*!< PERR :[write] Clear Flag. */ +/* FERR */ +#define UARTxERR_FERR_MASK ((uint32_t)0x00000002) /*!< FERR :Mask. */ +#define UARTxERR_FERR_R_NO_ERR ((uint32_t)0x00000000) /*!< FERR :[read] No Error. */ +#define UARTxERR_FERR_R_ERR ((uint32_t)0x00000002) /*!< FERR :[read] Error. */ +#define UARTxERR_FERR_W_CLEAR ((uint32_t)0x00000002) /*!< FERR :[write] Clear Flag. */ +/* BERR */ +#define UARTxERR_BERR_MASK ((uint32_t)0x00000001) /*!< BERR :Mask. */ +#define UARTxERR_BERR_R_NO_ERR ((uint32_t)0x00000000) /*!< BERR :[read] No Error. */ +#define UARTxERR_BERR_R_ERR ((uint32_t)0x00000001) /*!< BERR :[read] Error. */ +#define UARTxERR_BERR_W_CLEAR ((uint32_t)0x00000001) /*!< BERR :[write] Clear Flag. */ +/** + * @} + */ /* End of group UARTxERR */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Inline Functions */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Private_fuctions + * @{ + */ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance); +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS TXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_TXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 1))) = 1; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Disable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 0; +#endif +} + +/*--------------------------------------------------*/ +/** + * @brief Enable UARTxTRANS RXE. + * @param p_instance: Instance address. + * @retval - + * @note Bitband Access + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_UARTxTRANS_RXE(TSB_UART_TypeDef *p_instance) +{ +#ifdef DEBUG + if ((uint32_t)p_instance >= (uint32_t)PERI_BASE) { + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; + } +#else + (*((__IO uint32_t *)BITBAND_PERI(&p_instance->TRANS, 0))) = 1; +#endif +} + + +/** + * @} + */ /* End of group UART_Private_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __UART_EX_H */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/rda_flash512ud32_b.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/rda_flash512ud32_b.c new file mode 100644 index 00000000000..7d22fb49d99 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/rda_flash512ud32_b.c @@ -0,0 +1,1568 @@ +/** + ******************************************************************************* + * @file rda_flash512ud32_b.c + * @brief This file provides API functions for FLASH rda.\n + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include +#include +#include "flash.h" +#include "TMPM4KNA.h" + +#if defined(__FLASH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup RDA_FLASH512UD32 RDA_FLASH512UD32 + * @{ + */ + + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_config RDA_FLASH512UD32 Private Config + * @{ + */ + + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_config */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_define RDA_FLASH512UD32 Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x80) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_MAX_DATA_PAGES (uint8_t)(0x21) /*!< Maxmum pages */ +#define FC_MAX_DATA_BLOCKS (uint8_t)(0x8) /*!< Maxmum blocks */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ +#define FC_BANK_USER_INFO (0x00000007UL) /*!< Bank Change User Information Area */ +#define FC_BANK_CODE_FLASH (0x00000000UL) /*!< Bank Change Code Flash */ +#define FC_BUFFER_DISABLE (0x00000007UL) /*!< Flash Buffer Disable nad Clear */ +#define FC_BUFFER_ENABLE (0x00000000UL) /*!< Flash Buffer Enable */ + +#define FC_PROTECT_ADDR (0x00002000UL) /*!< The lower address of protect command */ +#define FC_SWAP_ADDR (0x00003000UL) /*!< The lower address of swap command */ +#define FC_BUSY_MAX_WAIT (0x00001000UL) /*!< Busy wait count */ + +#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */ +#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */ +#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */ +#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */ +#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */ +#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */ +#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */ +#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */ +#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */ +#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */ + +/* FCSR0 register */ +#define FC_AREASEL_EXPECT_AREA0 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area0 */ +#define FC_AREASEL_EXPECT_AREA4 (uint32_t)(0x00000000UL) /*!< RW, Selects expect area4 */ +#define FC_AREASEL_AREA0 (uint32_t)(0x00000007UL) /*!< RW, Selects area0 */ +#define FC_AREASEL_AREA4 (uint32_t)(0x00070000UL) /*!< RW, Selects area4 */ +#define FC_AREASEL_MASK_AREA0 (uint32_t)(0xFF8F0FF8UL) /*!< RW, Selects area0 */ +#define FC_AREASEL_MASK_AREA4 (uint32_t)(0xFF880FFFUL) /*!< RW, Selects area4 */ +#define FC_AREASEL_WRITE_MODE (uint32_t)(0x04000000UL) /*!< R, Write Mode */ +#define FC_AREASEL4_WRITE_MODE (uint32_t)(0x40000000UL) /*!< R, Write Mode */ + +#define FC_SEC_MASK (uint32_t)(0x00000001UL) /*!< Flash security bit mask */ +#define FC_SEC_ENABLE (uint32_t)(0x00000001UL) /*!< Flash security enable */ + +static uint32_t fc_const_code_flash_address[FC_MAX_PAGES] = { + (0x5E000000UL), /*!< CODE FLASH Page0 */ + (0x5E001000UL), /*!< CODE FLASH Page1 */ + (0x5E002000UL), /*!< CODE FLASH Page2 */ + (0x5E003000UL), /*!< CODE FLASH Page3 */ + (0x5E004000UL), /*!< CODE FLASH Page4 */ + (0x5E005000UL), /*!< CODE FLASH Page5 */ + (0x5E006000UL), /*!< CODE FLASH Page6 */ + (0x5E007000UL), /*!< CODE FLASH Page7 */ + (0x5E008000UL), /*!< CODE FLASH Page8 */ + (0x5E009000UL), /*!< CODE FLASH Page9 */ + (0x5E00A000UL), /*!< CODE FLASH Page10 */ + (0x5E00B000UL), /*!< CODE FLASH Page11 */ + (0x5E00C000UL), /*!< CODE FLASH Page12 */ + (0x5E00D000UL), /*!< CODE FLASH Page13 */ + (0x5E00E000UL), /*!< CODE FLASH Page14 */ + (0x5E00F000UL), /*!< CODE FLASH Page15 */ + (0x5E010000UL), /*!< CODE FLASH Page16 */ + (0x5E011000UL), /*!< CODE FLASH Page17 */ + (0x5E012000UL), /*!< CODE FLASH Page18 */ + (0x5E013000UL), /*!< CODE FLASH Page19 */ + (0x5E014000UL), /*!< CODE FLASH Page20 */ + (0x5E015000UL), /*!< CODE FLASH Page21 */ + (0x5E016000UL), /*!< CODE FLASH Page22 */ + (0x5E017000UL), /*!< CODE FLASH Page23 */ + (0x5E018000UL), /*!< CODE FLASH Page24 */ + (0x5E019000UL), /*!< CODE FLASH Page25 */ + (0x5E01A000UL), /*!< CODE FLASH Page26 */ + (0x5E01B000UL), /*!< CODE FLASH Page27 */ + (0x5E01C000UL), /*!< CODE FLASH Page28 */ + (0x5E01D000UL), /*!< CODE FLASH Page29 */ + (0x5E01E000UL), /*!< CODE FLASH Page30 */ + (0x5E01F000UL) /*!< CODE FLASH Page31 */ +}; + +static uint32_t fc_const_code_flash_block_address[FC_MAX_BLOCKS] = { + (0x5E000000UL), /*!< CODE FLASH Block0 */ + (0x5E008000UL), /*!< CODE FLASH Block1 */ + (0x5E010000UL), /*!< CODE FLASH Block2 */ + (0x5E018000UL), /*!< CODE FLASH Block3 */ + (0x5E020000UL), /*!< CODE FLASH Block4 */ + (0x5E028000UL), /*!< CODE FLASH Block5 */ + (0x5E030000UL), /*!< CODE FLASH Block6 */ + (0x5E038000UL), /*!< CODE FLASH Block7 */ + (0x5E040000UL), /*!< CODE FLASH Block8 */ + (0x5E048000UL), /*!< CODE FLASH Block9 */ + (0x5E050000UL), /*!< CODE FLASH Block10 */ + (0x5E058000UL), /*!< CODE FLASH Block11 */ + (0x5E060000UL), /*!< CODE FLASH Block12 */ + (0x5E068000UL), /*!< CODE FLASH Block13 */ + (0x5E070000UL), /*!< CODE FLASH Block14 */ + (0x5E078000UL) /*!< CODE FLASH Block15 */ +}; + +static uint32_t fc_const_data_flash_address[FC_MAX_DATA_PAGES] = { + (0x30000000UL), /*!< DATA FLASH Page0 */ + (0x30000100UL), /*!< DATA FLASH Page1 */ + (0x30000200UL), /*!< DATA FLASH Page2 */ + (0x30000300UL), /*!< DATA FLASH Page3 */ + (0x30000400UL), /*!< DATA FLASH Page4 */ + (0x30000500UL), /*!< DATA FLASH Page5 */ + (0x30000600UL), /*!< DATA FLASH Page6 */ + (0x30000700UL), /*!< DATA FLASH Page7 */ + (0x30000800UL), /*!< DATA FLASH Page8 */ + (0x30000900UL), /*!< DATA FLASH Page9 */ + (0x30000A00UL), /*!< DATA FLASH Page10 */ + (0x30000B00UL), /*!< DATA FLASH Page11 */ + (0x30000C00UL), /*!< DATA FLASH Page12 */ + (0x30000D00UL), /*!< DATA FLASH Page13 */ + (0x30000E00UL), /*!< DATA FLASH Page14 */ + (0x30000F00UL), /*!< DATA FLASH Page15 */ + (0x30001000UL), /*!< DATA FLASH Page16 */ + (0x30001100UL), /*!< DATA FLASH Page17 */ + (0x30001200UL), /*!< DATA FLASH Page18 */ + (0x30001300UL), /*!< DATA FLASH Page19 */ + (0x30001400UL), /*!< DATA FLASH Page20 */ + (0x30001500UL), /*!< DATA FLASH Page21 */ + (0x30001600UL), /*!< DATA FLASH Page22 */ + (0x30001700UL), /*!< DATA FLASH Page23 */ + (0x30001800UL), /*!< DATA FLASH Page24 */ + (0x30001900UL), /*!< DATA FLASH Page25 */ + (0x30001A00UL), /*!< DATA FLASH Page26 */ + (0x30001B00UL), /*!< DATA FLASH Page27 */ + (0x30001C00UL), /*!< DATA FLASH Page28 */ + (0x30001D00UL), /*!< DATA FLASH Page29 */ + (0x30001E00UL), /*!< DATA FLASH Page30 */ + (0x30001F00UL), /*!< DATA FLASH Page31 */ + (0x30002000UL) /*!< DATA FLASH Page32 */ +}; + +static uint32_t fc_const_data_flash_block_address[FC_MAX_DATA_BLOCKS] = { + (0x30000000UL), /*!< DATA FLASH Block0 */ + (0x30001000UL), /*!< DATA FLASH Block1 */ + (0x30002000UL), /*!< DATA FLASH Block2 */ + (0x30003000UL), /*!< DATA FLASH Block3 */ + (0x30004000UL), /*!< DATA FLASH Block4 */ + (0x30005000UL), /*!< DATA FLASH Block5 */ + (0x30006000UL), /*!< DATA FLASH Block6 */ + (0x30007000UL) /*!< DATA FLASH Block7 */ +}; + +static uint32_t fc_const_data_flash_area_address[FC_MAX_AREAS] = { + (0x30000000UL) /*!< DATA FLASH AREA0 */ +}; + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_enum RDA_FLASH512UD32 Private Enum + * @{ + */ + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_enum */ + + +/*------------------------------------------------------------------------------*/ +/* Private Variables */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_variables RDA_FLASH512UD32 Private Variables + * @{ + */ + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_variables */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup RDA_FLASH512UD32_Private_functions RDA_FLASH512UD32 Private Functions + * @{ + */ +__STATIC_INLINE uint32_t fc_enable_areasel(void); +__STATIC_INLINE uint32_t fc_disable_areasel(void); +__STATIC_INLINE uint32_t fc_enable_areasel4(void); +__STATIC_INLINE uint32_t fc_disable_areasel4(void); + +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static uint32_t fc_write_data_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size); + +static void fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind); + +static uint32_t fc_get_status(fc_sr0_t status); +static uint32_t fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size); +static uint32_t fc_blank_check(uint32_t *address, uint32_t size); + +static void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size); + +static void fc_protect_program_command(uint32_t protect_bit, fc_protect_kind_t kind); +static void fc_protect_erase_command(void); + +static void fc_bank_change(uint32_t bank); + +__STATIC_INLINE uint32_t fc_protect_mask_set(uint32_t protect_bit, fc_protect_kind_t kind); + +/*--------------------------------------------------*/ +/** + * @brief Read clock set. + * @param - + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_read_clock_set(void) +{ + uint32_t regval = 0; + + SystemCoreClockUpdate(); + if (SystemCoreClock > SYSCORECLOCK_80M) { + regval = (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5)) { + /* no processing */ + } + } else { + regval = (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4)) { + /* no processing */ + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief fc fixed clock set. + * @param sysclock : system clock (Hz) + * @retval none. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_fixed_clock_set(uint32_t sysclock) +{ + uint32_t regval = 0; + + if (sysclock > SYSCORECLOCK_80M) { + regval = (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_5 | FC_ACCR_FCLC_5)) { + /* no processing */ + } + } else { + regval = (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4); + TSB_FC->KCR = FC_KCR_KEYCODE; + TSB_FC->FCACCR = regval; + while (TSB_FC->FCACCR != (uint32_t)(FC_ACCR_FDLC_4 | FC_ACCR_FCLC_4)) { + /* no processing */ + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Check FCSR0_RDYBSY. + * @param - + * @retval BUSY = 0 + * @note + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t Get_param_FC_RDYBSY(void) +{ + uint32_t retval = 0 ; + + retval = TSB_FC->SR0 & FCSR0_RDYBSY_MASK ; + + return retval ; +} +#if defined(_CC_ARM) +/*--------------------------------------------------*/ +/** + * @brief copy fc_func. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +void copy_fc_func(void) +{ + Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API); /* copy flash API to RAM */ + + return; +} + +/*--------------------------------------------------*/ +/** + * @brief copy user_data. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +void copy_user_data(char *data_a, char *data_b, uint32_t size) +{ + /* copy A to RAM */ + Copy_Routine(DEMO_A_RAM, (uint32_t *)data_a, size); + + /* copy B to RAM */ + Copy_Routine(DEMO_B_RAM, (uint32_t *)data_b, size); + + return; +} + +/*--------------------------------------------------*/ +/** + * @brief copy user_program. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +void copy_user_program(uint32_t size) +{ + /* copy A to RAM */ + Copy_Routine(DEMO_A_RAM, DEMO_A_FLASH, size); + + /* copy B to RAM */ + Copy_Routine(DEMO_B_RAM, DEMO_B_FLASH, size); + + return; +} + +/*--------------------------------------------------*/ +/** + * @brief rewrite_user_program. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +uint32_t rewrite_user_program(uint32_t size) +{ + uint32_t ret; + + ret = fc_write_code_flash(DEMO_B_RAM, DEMO_A_FLASH, size); + if (ret != TXZ_ERROR) { + ret = fc_write_code_flash(DEMO_A_RAM, DEMO_B_FLASH, size); + if (ret != TXZ_ERROR) { + ret = TXZ_SUCCESS; + } + } + + return (ret); +} + +#endif +/*--------------------------------------------------*/ +/** + * @brief Auto protect erase command of the code flash ROM. + * @param - + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function protect specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_protect_erase_code_flash(void) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + fc_protect_erase_command(); + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief fc_write_page_data_flash. + * @param - + * @retval - + * @note + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_write_page_data_flash(uint32_t page, uint32_t size) +{ + uint32_t ret; + uint8_t SetData[4], Data; + uint32_t i; + + Data = 0; + for (i = 0; i < size; i += 0x4U) { + SetData[0] = Data++; + SetData[1] = Data++; + SetData[2] = Data++; + SetData[3] = Data++; + + ret = fc_write_data_flash((uint32_t *)SetData, + (uint32_t *)(fc_const_data_flash_address[page] + i), + 0x4); + } + + return (ret); +} + +/*--------------------------------------------------*/ +/** + * @brief Auro page erase command of the user information area. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_user_information_area(uint32_t User_Information_Area) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + fc_bank_change(FC_BANK_USER_INFO); + + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)User_Information_Area, + FC_ERASE_KIND_PAGE); + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)User_Information_Area, FC_PAGE_SIZE) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + + fc_bank_change(FC_BANK_CODE_FLASH); + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Raed of the user information area. + * @param dst_address :destination address + * @param size :data size + * @retval - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +void fc_read_user_information_area(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + fc_bank_change(FC_BANK_USER_INFO); + + { + char *d = (char *)dst_address; + char *s = (char *)src_address; + int i; + for (i = 0; i < size; i++) { + *d++ = *s++; + } + } + + fc_bank_change(FC_BANK_CODE_FLASH); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the user information area. + * @param src_address :source address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_write_user_information_area(uint32_t *src_address, uint32_t size, uint32_t User_Information_Area) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + uint32_t i; + + fc_bank_change(FC_BANK_USER_INFO); + + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), + (uint32_t *)((uint32_t)User_Information_Area - FC_CODE_FLASH_ADDRESS_TOP + i), + (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, (uint32_t *)User_Information_Area, size); + + fc_bank_change(FC_BANK_CODE_FLASH); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_enable_areasel(void) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + + reg |= FC_AREASEL_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF0 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITE_MODE) == FC_AREASEL_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Enables the AREA4. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_enable_areasel4(void) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA4; + + reg |= FC_AREASEL_AREA4; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area4 */ + TSB_FC->AREASEL = reg; + + /* Confirms the FCAREASEL register the SSF4 was set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL4_WRITE_MODE) == FC_AREASEL4_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA0. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_disable_areasel(void) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = TSB_FC->AREASEL & FC_AREASEL_MASK_AREA0; + + reg |= FC_AREASEL_EXPECT_AREA0; + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->AREASEL = reg; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL_WRITE_MODE) != FC_AREASEL_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Disables the AREA4. + * @param - + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_disable_areasel4(void) +{ + uint32_t retval = TXZ_ERROR; + + + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area4 */ + TSB_FC->AREASEL = FC_AREASEL_EXPECT_AREA4; + + /* Confirms the SSF0 of the FCAREASEL register is not set. */ + while (1) { + uint32_t i = TSB_FC->AREASEL; + if ((i & FC_AREASEL4_WRITE_MODE) != FC_AREASEL4_WRITE_MODE) { + retval = TXZ_SUCCESS; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Writes data of the Flash ROM. + * @param src_address + * @param dst_address + * @param size + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_write_command(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval; + volatile uint32_t *addr1; + volatile uint32_t *addr2; + volatile uint32_t *addr3; + uint32_t *source = (uint32_t *) src_address; + + if ((uint32_t)dst_address >= 0x30000000) { + addr1 = (uint32_t *)((uint32_t)FC_CODE_DATA_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_DATA_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)dst_address); + /* Enables the AREA4. Write Mode. */ + retval = fc_enable_areasel4(); + } else { + addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + addr3 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + (uint32_t)dst_address); + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + } + + if (retval == TXZ_SUCCESS) { + uint32_t i; + + *addr1 = (0x000000AAUL); /* bus cycle 1 */ + *addr2 = (0x00000055UL); /* bus cycle 2 */ + if ((uint32_t)dst_address >= 0x30000000) { + *addr1 = (0x000000C0UL); /* bus cycle 3 */ + } else { + *addr1 = (0x000000A0UL); /* bus cycle 3 */ + } + for (i = (0UL); i < size; i += (0x4UL)) { + *addr3 = *source; + source++; + } + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {}; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {}; + } + + if ((uint32_t)addr1 > 0x5E000000) { + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } else { + /* Disables the AREA4. Read Mode. */ + retval = fc_disable_areasel4(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Verifies data of the Flash ROM. + * @param src_address :source address + * @param dst_address :destination address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_verify_check(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + char *s = (char *)src_address; + char *d = (char *)dst_address; + uint32_t i; + for (i = 0; i < size; i++) { + if (*s++ != *d++) { + return (TXZ_ERROR); + } + } + return (TXZ_SUCCESS); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto page erase command of the flash ROM. + * @param flash top address + * @param erase top address + * @param kind : Chip, Area, Block, Page, etc. + * @return - + * @note This function erases specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_erase_command(uint32_t *flash_top_address, uint32_t *erase_top_address, fc_erase_kind_t kind) +{ + uint32_t retval; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)flash_top_address + FC_CMD_BC2_ADDR); + volatile uint32_t *addr3 = (uint32_t *) erase_top_address; + + if ((uint32_t)addr1 > 0x5E000000) { + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + } else { + /* Enables the AREA4. Write Mode. */ + retval = fc_enable_areasel4(); + } + + if (retval == TXZ_SUCCESS) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = kind; + + /* Confirmation of the works start of ROM. */ + { + uint32_t busy_count = 0; + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + if (++busy_count > FC_BUSY_MAX_WAIT) { + break; + } + }; + } + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) { }; + } + if ((uint32_t)addr1 > 0x5E000000) { + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } else { + /* Disables the AREA4. Read Mode. */ + retval = fc_disable_areasel4(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Checks a blank of the Flash ROM every 4bytes. + * @param addrress + * @param size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_blank_check(uint32_t *address, uint32_t size) +{ + uint32_t retval = TXZ_SUCCESS; + uint32_t i; + + for (i = 0; i < (size / sizeof(uint32_t)); i++) { + uint32_t *addr = &address[i]; + if (*addr != FC_BRANK_VALUE) { + retval = TXZ_ERROR; + break; + } + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the status of the flash auto operation. + * @param status + * @return Result. + * @retval TXZ_BUSY : Busy. + * @retval TXZ_DONE : Done. + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_get_status(fc_sr0_t status) +{ + uint32_t retval; + uint32_t work32; + + /* Reads the FCSR0. Masks the other specfic status */ + work32 = TSB_FC->SR0 & (uint32_t)status; + + /* Confirms the specific status of the flash ROM */ + if (work32 == (uint32_t)status) { + retval = TXZ_DONE; + } else { + retval = TXZ_BUSY; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the code flash ROM. + * @param src_address :source address + * @param dst_address :destination address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the code Flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_write_code_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + uint32_t i; + /* Checks the code Flash ROM status */ + for (i = 0; i < size; i += (uint32_t)(0x10UL)) { + /* Writes 16bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), + (uint32_t *)((uint32_t)dst_address + i), + (uint32_t)(0x10UL)); + } + + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto page erase command of the code flash ROM. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_page_code_flash(fc_code_flash_page_number_t first_page, uint8_t num_of_pages) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_address[first_page], + FC_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief copy 32-bit data from source to dest + * @param the address of source and dast, the data size + * @retval None. + * @note - + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void Copy_Routine(uint32_t *dest, uint32_t *source, uint32_t size) +{ + uint32_t *dest_addr, *source_addr, tmpsize; + uint32_t i, tmps, tmpd, mask; + + dest_addr = dest; + source_addr = source; + + tmpsize = size >> 2U; + for (i = 0U; i < tmpsize; i++) { /* 32bits copy */ + *dest_addr = *source_addr; + dest_addr++; + source_addr++; + } + if (size & 0x00000003U) { /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */ + mask = 0xFFFFFF00U; + i = size & 0x00000003U; + tmps = *source_addr; + tmpd = *dest_addr; + while (i - 1U) { + mask = mask << 8U; + i--; + } + tmps = tmps & (~mask); + tmpd = tmpd & (mask); + *dest_addr = tmps + tmpd; /* 32bits copy, but only change the bytes need to be changed */ + } else { + /* Do nothing */ + } +} + +/*--------------------------------------------------*/ +/** + * @brief Auto page erase command of the data flash. + * @param first_page : The first page to erase + * @param num_of_pages : The number of pages to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified page of the data Flash and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_page_data_flash(fc_data_flash_page_number_t first_page, uint8_t num_of_pages) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the data Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum pages. */ + if ((first_page + num_of_pages) <= FC_MAX_DATA_PAGES) { + uint8_t i; + for (i = 0; i < num_of_pages; i++) { + /* Erases the specific page. */ + fc_erase_command((uint32_t *)FC_DATA_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_data_flash_address[first_page + i], + FC_ERASE_KIND_PAGE); + } + /* Checks a blank of the specific page. */ + if (fc_blank_check((uint32_t *)fc_const_data_flash_address[first_page], + FC_DATA_PAGE_SIZE * (uint32_t)num_of_pages) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto write command of the data flash. + * @param src_address :source address + * @param dst_address :destination address + * @param size :data size + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function writes 16bytes data to the DATA Flash. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static uint32_t fc_write_data_flash(uint32_t *src_address, uint32_t *dst_address, uint32_t size) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code DATA Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + uint32_t i; + /* Checks the DATA Flash status */ + for (i = 0; i < size; i += (uint32_t)(0x4UL)) { + /* Writes 4bytes data. */ + fc_write_command((uint32_t *)((uint32_t)src_address + i), + (uint32_t *)((uint32_t)dst_address + i), + (uint32_t)(0x4UL)); + } + /* Verifies user data and data of the Flash ROM. */ + retval = fc_verify_check(src_address, dst_address, size); + } else { + retval = TXZ_BUSY; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto block erase command of the data flash. + * @param first_block : The first block to erase + * @param num_of_block : The number of blocks to erase. + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified block of the data Flash and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_block_data_flash(fc_data_flash_block_number_t first_block, uint8_t num_of_block) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the data Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + if ((first_block + num_of_block) <= FC_MAX_DATA_BLOCKS) { + uint8_t i; + for (i = 0; i < num_of_block; i++) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_DATA_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_data_flash_block_address[first_block + i], + FC_ERASE_KIND_BLOCK); + } + /* Checks a blank of the specific block. */ + if (fc_blank_check((uint32_t *)fc_const_data_flash_block_address[first_block], + FC_DATA_BLOCK_SIZE * (uint32_t)num_of_block) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto area erase command of the data flash. + * @param area : The area block to erase + * @return Result. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note It works in the inner RAM. + * This function erases specified block of the data Flash and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_area_data_flash(fc_data_flash_area_number_t area) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the data Flash status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + if (area == 0) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_DATA_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_data_flash_area_address[area], + FC_ERASE_KIND_AREA); + /* Checks a blank of the specific block. */ + if (fc_blank_check((uint32_t *)fc_const_data_flash_area_address[area], FC_DATA_AREA_SIZE) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto protect page program command of the code flash ROM. + * @param page : The page to protect program + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function protect specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_protect_page_code_flash(fc_code_flash_page_number_t page) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + if (page <= FC_CODE_FLASH_PAGE7) { + fc_protect_program_command(page, FC_PROTECT_KIND_PAGE); + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto protect block program command of the code flash ROM. + * @param block : The block to protect program + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function protect specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_protect_block_code_flash(fc_code_flash_block_number_t block) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + /* Checks the number of maximum blocks. */ + if ((block >= FC_CODE_FLASH_BLOCK1) && (block <= FC_CODE_FLASH_BLOCK3)) { + fc_protect_program_command(block, FC_PROTECT_KIND_BLOCK); + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto ptotect bit program command of the flash ROM. + * @param protect_bit + * @param kind + * @return - + * @note This function protect specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_protect_program_command(uint32_t protect_bit, fc_protect_kind_t kind) +{ + uint32_t retval = TXZ_SUCCESS; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + volatile uint32_t *addr3; + + if (kind == FC_PROTECT_KIND_PAGE) { + if (protect_bit <= 7) { + addr3 = (uint32_t *)(FC_CODE_FLASH_ADDRESS_TOP + FC_PROTECT_ADDR + (protect_bit << 4)); + } else { + retval = TXZ_ERROR; + } + } else if (kind == FC_PROTECT_KIND_BLOCK) { + if ((protect_bit >= 1) && (protect_bit <= 3)) { + addr3 = (uint32_t *)(FC_CODE_FLASH_ADDRESS_TOP + FC_PROTECT_ADDR + 0x80 + ((protect_bit - 1) << 4)); + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + if (retval == TXZ_SUCCESS) { + retval = fc_protect_mask_set(protect_bit, kind); + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + + if (retval == TXZ_SUCCESS) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x0000009AUL); + *addr3 = (0x0000009AUL); + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {}; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {}; + } + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Auto ptotect bit erase command of the flash ROM. + * @param - + * @return - + * @note This function protect specified place of the flash ROM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_protect_erase_command(void) +{ + uint32_t retval = TXZ_SUCCESS; + volatile uint32_t *addr1 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC1_ADDR); + volatile uint32_t *addr2 = (uint32_t *)((uint32_t)FC_CODE_FLASH_ADDRESS_TOP + FC_CMD_BC2_ADDR); + volatile uint32_t *addr3 = (uint32_t *)(FC_CODE_FLASH_ADDRESS_TOP + FC_PROTECT_ADDR); + + { + /* Enables the AREA0. Write Mode. */ + retval = fc_enable_areasel(); + + if (retval == TXZ_SUCCESS) { + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr1 = (0x00000080UL); + *addr1 = (0x000000AAUL); + *addr2 = (0x00000055UL); + *addr3 = (0x00000060UL); + + /* Confirmation of the works start of ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) {}; + + /* Waits for a finish of the works in the code Flash ROM. */ + while (fc_get_status(FC_SR0_RDYBSY) == TXZ_BUSY) {}; + } + /* Disables the AREA0. Read Mode. */ + retval = fc_disable_areasel(); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Protect Mask Set. + * @param protect_bit + * @param kind + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function write the FCAREASEL regiset. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +__STATIC_INLINE uint32_t fc_protect_mask_set(uint32_t protect_bit, fc_protect_kind_t kind) +{ + uint32_t retval = TXZ_ERROR; + uint32_t reg = 0xFFFFFFFF; + + if (kind == FC_PROTECT_KIND_PAGE) { + reg = (TSB_FC->PMR0) | (1 << protect_bit); + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->PMR0 = reg; + + retval = TXZ_SUCCESS; + } else if (kind == FC_PROTECT_KIND_BLOCK) { + reg = (TSB_FC->PMR1) | (1 << protect_bit); + /* Writes the FCKER register the KEYCODE. */ + TSB_FC->KCR = FC_KCR_KEYCODE; + + /* Selects the area0 */ + TSB_FC->PMR1 = reg; + + retval = TXZ_SUCCESS; + } + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief Auto block erase command of the code flash ROM. + * @param first_block : The first block to erase + * @param num_of_block : The number of blocks to erase. + * @return Result. + * @retval TXZ_SUCCESS : Success. + * @retval TXZ_ERROR : Failure. + * @note It works in the inner RAM. + * This function erases specified block of the code Flash ROM and checks a blank. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +uint32_t fc_erase_block_code_flash(fc_code_flash_block_number_t first_block, uint8_t num_of_block) +{ + uint32_t retval = TXZ_SUCCESS; + + /* Checks the code Flash ROM status */ + if (fc_get_status(FC_SR0_RDYBSY) == TXZ_DONE) { + if ((first_block + num_of_block) <= FC_MAX_BLOCKS) { + uint8_t i; + for (i = 0; i < num_of_block; i++) { + /* Erases the specific block. */ + fc_erase_command((uint32_t *)FC_CODE_FLASH_ADDRESS_TOP, + (uint32_t *)fc_const_code_flash_block_address[first_block + i], + FC_ERASE_KIND_BLOCK); + } + /* Checks a blank of the specific block. */ + if (fc_blank_check((uint32_t *)fc_const_code_flash_block_address[first_block], FC_BLOCK_SIZE * (uint32_t)num_of_block) == TXZ_ERROR) { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + } else { + retval = TXZ_ERROR; + } + + return (retval); +} + +/*--------------------------------------------------*/ +/** + * @brief bank change. + * @param bank : FC_BANK_USER_INFO, FC_BANK_CODE_FLASH + * @return - + * @note It works in the inner RAM. + */ +/*--------------------------------------------------*/ +#if defined ( __GNUC__ ) /* GCC Compiler */ +__attribute__((section(".ram_func"))) +#endif +static void fc_bank_change(uint32_t bank) +{ + if (bank == FC_BANK_USER_INFO) { + /* Flash Buffer disable */ + TSB_FC->BUFDISCLR = FC_BUFFER_DISABLE; + while (TSB_FC->BUFDISCLR != FC_BUFFER_DISABLE); + /* change user information area */ + TSB_FC->BNKCR = FC_BANK_USER_INFO; + while (TSB_FC->BNKCR != FC_BANK_USER_INFO); + } else if (bank == FC_BANK_CODE_FLASH) { + /* change code flash */ + TSB_FC->BNKCR = FC_BANK_CODE_FLASH; + while (TSB_FC->BNKCR != FC_BANK_CODE_FLASH); + /* Flash Buffer enable */ + TSB_FC->BUFDISCLR = FC_BUFFER_ENABLE; + while (TSB_FC->BUFDISCLR != FC_BUFFER_ENABLE); + } else { + /* do nothing */ + } +} + +/*--------------------------------------------------*/ + + +/** + * @} + */ /* End of group RDA_FLASH512UD32_Private_functions */ + +/** + * @} + */ /* End of group RDA_FLASH512UD32 */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__FLASH_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c new file mode 100644 index 00000000000..6e12fe28786 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc.c @@ -0,0 +1,714 @@ +/** + ******************************************************************************* + * @file txzp_adc.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_adc_include.h" +#include "txzp_adc.h" + +#if defined(__ADC_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ +#define WAIT_UNIT_1US ((uint32_t)(1000000)) /*!< 1S-1us transfor unit. */ +#define WAIT_FORLOOP_STEPS ((uint32_t)(5)) /*!< for loop steps. */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_convert_time(uint32_t param); +__STATIC_INLINE int32_t check_param_rcut(uint32_t param); +#endif +static void clear_ch_instance_info(adc_ch_t *p_ch); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Convert time's parameter. + * @param param :Convert time's parameter + * @retval ADC_PARAM_OK :Valid + * @retval ADC_PARAM_NG :Invalid + * @note Macro definition is @ref ADC_CONVERT_TIME. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_convert_time(uint32_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_CONVERT_TIME_0_96_AVDD_4_5: + case ADC_CONVERT_TIME_0_91_AVDD_4_5: + case ADC_CONVERT_TIME_1_09_AVDD_4_5: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the AD RCUT's parameter. + * @param param :AD RCUT's parameter + * @retval ADC_PARAM_OK :Valid + * @retval ADC_PARAM_NG :Invalid + * @note Macro definition is @ref ADC_RCUT. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rcut(uint32_t param) +{ + int32_t result = ADC_PARAM_NG; + + switch (param) { + case ADC_RCUT_NORMAL: + case ADC_RCUT_LOW: + result = ADC_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +#endif + + +/*--------------------------------------------------*/ +/** + * @brief Channel Instance Information Clear. + * @param p_ch :Channel Instance Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +static void clear_ch_instance_info(adc_ch_t *p_ch) +{ + p_ch->p_tset = ADC_NULL; + p_ch->p_reg = ADC_NULL; + p_ch->init.type = ADC_CONVERSION_DISABLE; +} + +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the ADC object. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + * @attention After initialization, 3us of stabilization time is needed. + */ +/*--------------------------------------------------*/ +void wait_m(uint32_t count) +{ + uint32_t i, steps; + + /*-----------------------------------------*/ + /* step : 1000000us = fsys :1 */ + /* step = EOSC_SYS_CLOCK/1000000 */ + /*-----------------------------------------*/ + /* system core clock update */ + SystemCoreClockUpdate(); + steps = count * (SystemCoreClock / WAIT_UNIT_1US) / WAIT_FORLOOP_STEPS; + + for (i = 0; i < steps; ++i) { + __NOP(); + } +} +TXZ_Result adc_init(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter. */ + assert_param(check_param_convert_time(p_obj->init.convert_time)); + assert_param(check_param_rcut(p_obj->init.rcut)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Init Variable */ + /*------------------------------*/ + { + uint32_t i; + + for (i = 0; i < ADC_NUM_MAX; i++) { + clear_ch_instance_info(&p_obj->info.ch[i]); + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + + switch (p_obj->init.convert_time) { + case ADC_CONVERT_TIME_0_96_AVDD_4_5: + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON); + /*--- ADxCLK ---*/ + wait_m(3); + p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_96 | ADxCLK_VADCLK_4); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->EXAZSEL = 0; + p_obj->p_instance->MOD1 = ADxMOD1_TIME_0_96_AVDD_4_5; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADxMOD2; + break; + case ADC_CONVERT_TIME_0_91_AVDD_4_5: + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON); + /*--- ADxCLK ---*/ + wait_m(3); + p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_91_1_09 | ADxCLK_VADCLK_4); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->EXAZSEL = 0; + p_obj->p_instance->MOD1 = ADxMOD1_TIME_0_91_AVDD_4_5; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADxMOD2; + break; + case ADC_CONVERT_TIME_1_09_AVDD_4_5: + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (p_obj->init.rcut | ADxMOD0_DACON_ON); + /*--- ADxCLK ---*/ + wait_m(3); + p_obj->p_instance->CLK = (ADxCLK_EXAZ0_0_91_1_09 | ADxCLK_VADCLK_8); + /*--- ADxMOD1 ---*/ + p_obj->p_instance->EXAZSEL = 0; + p_obj->p_instance->MOD1 = ADxMOD1_TIME_1_09_AVDD_4_5; + /*--- ADxMOD2 ---*/ + p_obj->p_instance->MOD2 = ADxMOD2; + break; + default: + result = TXZ_ERROR; + /* no process */ + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the ADC object. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_deinit(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + { + uint32_t i; + adc_ch_t *p_ch; + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_deinit(p_ch) == TXZ_SUCCESS) { + clear_ch_instance_info(p_ch); + } + } + } + } + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxCMPEN ---*/ + p_obj->p_instance->CMPEN = (ADxCMPEN_CMP1EN_DISABLE | ADxCMPEN_CMP0EN_DISABLE); + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxMOD0 ---*/ + p_obj->p_instance->MOD0 = (ADxMOD0_RCUT_IREF_CUT | ADxMOD0_DACON_OFF); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief ADC Channel Setting. + * @param p_obj :ADC object. + * @param ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_setting :Channel Setting Source Address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_setting(adc_t *p_obj, uint32_t ch, adc_channel_setting_t *p_setting) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); + /* Check the parameter. */ + assert_param(check_param_channel(ch, ADC_NUM_MAX)); + assert_param(check_param_ain(p_setting->ain, ADC_AIN_RANGE_MIN, ADC_AIN_RANGE_MAX)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Channel Class Construct */ + /*------------------------------*/ + { + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + p_ch->p_tset = (__IO uint32_t *)(&p_obj->p_instance->TSET0 + ch); + p_ch->p_reg = (__I uint32_t *)(&p_obj->p_instance->REG0 + ch); + p_ch->init.interrupt = ADC_INT_DISABLE; + p_ch->init.type = ADC_CONVERSION_SGL; + p_ch->init.ain = p_setting->ain; + result = adc_ch_init(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief ADC Channel Clear. + * @param p_obj :ADC object. + * @param ch :Channel. Range is (value < ADC_NUM_MAX). + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_clear(adc_t *p_obj, uint32_t ch) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter. */ + assert_param(check_param_channel(ch, ADC_NUM_MAX)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Channel Class Destruct */ + /*------------------------------*/ + { + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_deinit(p_ch); + /* Init Variable */ + clear_ch_instance_info(p_ch); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get AD value. + * @param p_obj :ADC object. + * @param ch :Channel. Range is (value < ADC_NUM_MAX). + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result adc_channel_get_value(adc_t *p_obj, uint32_t ch, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_value)); + /* Check the parameter. */ + assert_param(check_param_channel(ch, ADC_NUM_MAX)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Get Value */ + /*------------------------------*/ + { + adc_ch_t *p_ch = &p_obj->info.ch[ch]; + + result = adc_ch_get_value(p_ch, p_value); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_start(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stop(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Conversion */ + /*------------------------------*/ + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); + /*------------------------------*/ + /* Wait Stop */ + /*------------------------------*/ + /*--- ADxST ---*/ + /* When all convetion stop, ADxST is set "0". */ + while (p_obj->p_instance->ST != 0) { + /* no processing */ + } + /*------------------------------*/ + /* Dummy Read */ + /*------------------------------*/ + /* Read is needed before the next convertion. */ + { + uint32_t i; + adc_ch_t *p_ch; + uint32_t value; + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type == ADC_CONVERSION_DISABLE) { + if (adc_ch_get_value(p_ch, &value) != TXZ_SUCCESS) { + /* no processing */ + } + } + } + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start non-blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_startIt(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Interrupt Setting */ + /*------------------------------*/ + { + uint32_t i; + adc_ch_t *p_ch; + adc_ch_t *p_chInt = ADC_NULL; + + for (i = 0; i < ADC_NUM_MAX; i++) { + p_ch = &p_obj->info.ch[i]; + if (p_ch->init.type != ADC_CONVERSION_DISABLE) { + if (adc_ch_int_disable(p_ch) != TXZ_SUCCESS) { + result = TXZ_ERROR; + } + p_chInt = p_ch; + } + } + /* Last Channel Number: Enable Interrupt */ + if (p_chInt != ADC_NULL) { + if (adc_ch_int_enable(p_chInt) != TXZ_SUCCESS) { + result = TXZ_ERROR; + } + } + } + /*------------------------------*/ + /* Enable Conversion */ + /*------------------------------*/ + /*--- ADxCR1 ---*/ + p_obj->p_instance->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE | ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE); + /*--- ADxCR0 ---*/ + p_obj->p_instance->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Stop non-blocking single conversion. + * @param p_obj :ADC object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_stopIt(adc_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Stop Conversion */ + /*------------------------------*/ + result = adc_stop(p_obj); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for single conversion done. + * @param p_obj :ADC object. + * @retval - + * @note Call by Single Conversion Done IRQ Handler. + */ +/*--------------------------------------------------*/ +void adc_irq_handler(adc_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->handler != ADC_NULL) { + p_obj->handler(p_obj->init.id, TXZ_SUCCESS); + } +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c new file mode 100644 index 00000000000..f2c020d0b32 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_adc_ch.c @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file txzp_adc_ch.c + * @brief This file provides API functions for ADC driver. \n + * Channel Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_adc_include.h" +#include "txzp_adc_ch.h" + +#if defined(__ADC_CH_H) +/** + * @addtogroup Periph_Driver Peripheral Driver + * @{ + */ + +/** + * @addtogroup ADC + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_define ADC Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_typedef ADC Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group ADC_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup ADC_Private_fuctions ADC Private Fuctions + * @{ + */ +#ifdef DEBUG +/* no define */ +#endif +__STATIC_INLINE uint32_t get_conversion_data(uint32_t reg); + +#ifdef DEBUG +/* no define */ +#endif +/*--------------------------------------------------*/ +/** + * @brief Get convertion data from ADxREGn. + * @param reg : ADxREGn data. + * @retval Convertion data. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t get_conversion_data(uint32_t reg) +{ + uint32_t result = (uint32_t)((reg & ADxREGn_ADRn_MASK) >> 4); + + return (result); +} +/** + * @} + */ /* End of group ADC_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup ADC_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the ADC Channel object. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_init(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg)); + /* Check the parameter. */ + /* No check */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + /*--- ADxTSET ---*/ + *p_obj->p_tset = (p_obj->init.interrupt | p_obj->init.type | p_obj->init.ain); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the ADC Channel object. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_deinit(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + *p_obj->p_tset = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_DISABLE | 0); + /*--- ADxREGx ---*/ + /* Read is needed before the next convertion. */ + { + volatile uint32_t reg; + reg = *p_obj->p_reg; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Enable Interrupt. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_enable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg)); + /* Check the parameter. */ + /* No check */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_ENABLE); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable Interrupt. + * @param p_obj :ADC Channel object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has stoped. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_int_disable(adc_ch_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_tset)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_reg)); + /* Check the parameter. */ + /* No check */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- ADxTSET ---*/ + { + uint32_t tset = (*p_obj->p_tset & ~ADxTSETn_ENINT_MASK); + + *p_obj->p_tset = (tset | ADxTSETn_ENINT_DISABLE); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get conversion value. + * @param p_obj :ADC Channel object. + * @param p_value :AD value. Destination address. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @pre Conversion has done. + */ +/*--------------------------------------------------*/ +TXZ_Result adc_ch_get_value(adc_ch_t *p_obj, uint32_t *p_value) +{ + TXZ_Result result = TXZ_ERROR; + uint32_t reg = *p_obj->p_reg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the ADC_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Check Result */ + /*------------------------------*/ + if ((reg & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) { + *p_value = get_conversion_data(reg); + result = TXZ_SUCCESS; + } + + return (result); +} +/** + * @} + */ /* End of group ADC_Exported_functions */ + +/** + * @} + */ /* End of group ADC */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__ADC_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_cg.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_cg.c new file mode 100644 index 00000000000..d24ed481109 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_cg.c @@ -0,0 +1,287 @@ +/** + ******************************************************************************* + * @file txzp_cg.c + * @brief This file provides API functions for CG driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_cg.h" + +#if defined(__CG_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup CG + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +/* no define */ +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ +#define CG_FSYS_MASK ((uint32_t)0x00070000) /*!< CG FSYS mask */ + +#define CG_FSYS_1 ((uint32_t)0x00000000) /*!< CG fc register value */ +#define CG_FSYS_2 ((uint32_t)0x00010000) /*!< CG fc/2 register value */ +#define CG_FSYS_4 ((uint32_t)0x00020000) /*!< CG fc/4 register value */ +#define CG_FSYS_8 ((uint32_t)0x00030000) /*!< CG fc/8 register value */ +#define CG_FSYS_16 ((uint32_t)0x00040000) /*!< CG fc/16 register value */ + +#define CG_FSYS_1_MUL ((uint32_t)0x00000001) /*!< CG fc multiplication value */ +#define CG_FSYS_2_MUL ((uint32_t)0x00000002) /*!< CG fc/2 multiplication value */ +#define CG_FSYS_4_MUL ((uint32_t)0x00000004) /*!< CG fc/4 multiplication value */ +#define CG_FSYS_8_MUL ((uint32_t)0x00000008) /*!< CG fc/8 multiplication value */ +#define CG_FSYS_16_MUL ((uint32_t)0x00000010) /*!< CG fc/16 multiplication value */ + +#define CG_PRCKST_MASK ((uint32_t)0x0F000000) /*!< CG PRCKST mask */ + +#define CG_PRCKST_1 ((uint32_t)0x00000000) /*!< CG T0 fc register status */ +#define CG_PRCKST_2 ((uint32_t)0x01000000) /*!< CG T0 fc/2 register status */ +#define CG_PRCKST_4 ((uint32_t)0x02000000) /*!< CG T0 fc/4 register status */ +#define CG_PRCKST_8 ((uint32_t)0x03000000) /*!< CG T0 fc/8 register status */ +#define CG_PRCKST_16 ((uint32_t)0x04000000) /*!< CG T0 fc/16 register status */ +#define CG_PRCKST_32 ((uint32_t)0x05000000) /*!< CG T0 fc/32 register status */ +#define CG_PRCKST_64 ((uint32_t)0x06000000) /*!< CG T0 fc/64 register status */ +#define CG_PRCKST_128 ((uint32_t)0x07000000) /*!< CG T0 fc/128 register status */ +#define CG_PRCKST_256 ((uint32_t)0x08000000) /*!< CG T0 fc/256 register status */ +#define CG_PRCKST_512 ((uint32_t)0x09000000) /*!< CG T0 fc/512 register status */ + +#define CG_PRCK_1_DIV ((uint32_t)0x00000001) /*!< CG T0 fc division value */ +#define CG_PRCK_2_DIV ((uint32_t)0x00000002) /*!< CG T0 fc/2 division value */ +#define CG_PRCK_4_DIV ((uint32_t)0x00000004) /*!< CG T0 fc/4 division value */ +#define CG_PRCK_8_DIV ((uint32_t)0x00000008) /*!< CG T0 fc/8 division value */ +#define CG_PRCK_16_DIV ((uint32_t)0x00000010) /*!< CG T0 fc/16 division value */ +#define CG_PRCK_32_DIV ((uint32_t)0x00000020) /*!< CG T0 fc/32 division value */ +#define CG_PRCK_64_DIV ((uint32_t)0x00000040) /*!< CG T0 fc/64 division value */ +#define CG_PRCK_128_DIV ((uint32_t)0x00000080) /*!< CG T0 fc/128 division value */ +#define CG_PRCK_256_DIV ((uint32_t)0x00000100) /*!< CG T0 fc/256 division value */ +#define CG_PRCK_512_DIV ((uint32_t)0x00000200) /*!< CG T0 fc/512 division value */ + + +#define CG_MCKSELPST_MASK ((uint32_t)0xC0000000) /*!< CG MCKSEL mask */ + +#define CG_MCKSELPST_1 ((uint32_t)0x00000000) /*!< CG T0 fc/PRCK value */ +#define CG_MCKSELPST_2 ((uint32_t)0x40000000) /*!< CG T0 fc/PRCK/2 value */ +#define CG_MCKSELPST_4 ((uint32_t)0x80000000) /*!< CG T0 fc/PRCK/4 value */ + +#define CG_FSYSM_1_DIV ((uint32_t)0x00000001) /*!< CG fsysm T0 division value */ +#define CG_FSYSM_2_DIV ((uint32_t)0x00000002) /*!< CG fsysm T0/2 division value */ +#define CG_FSYSM_4_DIV ((uint32_t)0x00000004) /*!< CG fsysm T0/4 division value */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_define CG Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_typedef CG Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Private_fuctions CG Private Fuctions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group CG_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup CG_Exported_functions CG Exported Functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Update Middle PrescalerClock according register values. + * @param p_obj :CG object. + * @retval Middle PrescalerClock Frequency. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint32_t cg_get_mphyt0(cg_t *p_obj) +{ + uint32_t result = 0U; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the CG_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + /* System core clock update */ + SystemCoreClockUpdate(); + + /* Get Gear status. */ + switch (p_obj->p_instance->SYSCR & CG_FSYS_MASK) { + case CG_FSYS_1: /* Gear -> fc */ + result = SystemCoreClock * CG_FSYS_1_MUL; + break; + case CG_FSYS_2: /* Gear -> fc/2 */ + result = SystemCoreClock * CG_FSYS_2_MUL; + break; + case CG_FSYS_4: /* Gear -> fc/4 */ + result = SystemCoreClock * CG_FSYS_4_MUL; + break; + case CG_FSYS_8: /* Gear -> fc/8 */ + result = SystemCoreClock * CG_FSYS_8_MUL; + break; + case CG_FSYS_16: /* Gear -> fc/16 */ + result = SystemCoreClock * CG_FSYS_16_MUL; + break; + default: + result = 0U; + break; + } + switch (p_obj->p_instance->SYSCR & CG_PRCKST_MASK) { + case CG_PRCKST_1: /* T0 -> fc */ + result /= CG_PRCK_1_DIV; + break; + case CG_PRCKST_2: /* T0 -> fc/2 */ + result /= CG_PRCK_2_DIV; + break; + case CG_PRCKST_4: /* T0 -> fc/4 */ + result /= CG_PRCK_4_DIV; + break; + case CG_PRCKST_8: /* T0 -> fc/8 */ + result /= CG_PRCK_8_DIV; + break; + case CG_PRCKST_16: /* T0 -> fc/16 */ + result /= CG_PRCK_16_DIV; + break; + case CG_PRCKST_32: /* T0 -> fc/32 */ + result /= CG_PRCK_32_DIV; + break; + case CG_PRCKST_64: /* T0 -> fc/64 */ + result /= CG_PRCK_64_DIV; + break; + case CG_PRCKST_128: /* T0 -> fc/128 */ + result /= CG_PRCK_128_DIV; + break; + case CG_PRCKST_256: /* T0 -> fc/256 */ + result /= CG_PRCK_256_DIV; + break; + case CG_PRCKST_512: /* T0 -> fc/512 */ + result /= CG_PRCK_512_DIV; + break; + default: + result = 0U; + break; + } + + switch (p_obj->p_instance->SYSCR & CG_MCKSELPST_MASK) { + case CG_MCKSELPST_1: /* T0 -> fc/PRCK */ + result /= CG_FSYSM_1_DIV; + break; + case CG_MCKSELPST_2: /* T0 -> fc/PRCK/2 */ + result /= CG_FSYSM_2_DIV; + break; + case CG_MCKSELPST_4: /* T0 -> fc/PRCK/4 */ + result /= CG_FSYSM_4_DIV; + break; + default: + result = 0U; + break; + } + return (result); +} + +/** + * @} + */ /* End of group CG_Exported_functions */ + +/** + * @} + */ /* End of group CG */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__CG_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_gpio.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_gpio.c new file mode 100644 index 00000000000..8c385e9e03f --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_gpio.c @@ -0,0 +1,1813 @@ +/** + ******************************************************************************* + * @file txzp_gpio.c + * @brief This file provides API functions for GPIO driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ + +#include "txzp_gpio.h" + +#if defined(__GPIO_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup GPIO + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name Bit Operation Macro + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PORT_BASE (0x400E0000UL) /*!< Port Register Base Adress */ +#define BITBAND_PORT_OFFSET (0x0000100UL) /*!< Port Register Offset Value */ +#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) /*!< Operational target Port Adress */ +#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) /*!< Operational target Control Register Adress */ +#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)(base)) |= (uint32_t)(0x0000001UL<< (bitnum))) /*!< Target Pin Bit set */ +#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)(base)) &= ~((uint32_t)(0x0000001UL<< (bitnum)))) /*!< Target Pin Bit clear */ +#define BITBAND_PORT_READ(val, base, bitnum) ((val) = ((*((__IO uint32_t *)(base)) & (uint32_t)((0x0000001UL)<< (bitnum))) >> (bitnum))) /*!< Target Pin Bit read */ +/** + * @} + */ /* End of Bit Operation Macro */ +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_define GPIO Private Define + * @{ + */ + +#define GPIO_THRESHOLD 12 +#define GPIO_OFFSET 3 + +/** + * @} + */ /* End of group GPIO_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_typedef GPIO Private Typedef + * @{ + */ + +/*! + * @brief Pin Exist Table + * @details Bit0 :GPIO_Mode_DATA + * @details Bit1 :GPIO_Mode_CR + * @details Bit2 :GPIO_Mode_FR1 + * @details Bit3 :GPIO_Mode_FR2 + + * @details Bit4 :GPIO_Mode_FR3 + * @details Bit5 :GPIO_Mode_FR4 + * @details Bit6 :GPIO_Mode_FR5 + * @details Bit7 :GPIO_Mode_FR6 + + * @details Bit8 :GPIO_Mode_FR7 + * @details Bit9 :GPIO_Mode_OD + * @details Bit10 :GPIO_Mode_PUP + * @details Bit11 :GPIO_Mode_PDN + + * @details Bit12 :GPIO_Mode_IE + */ + +static uint16_t PinExistTbl[GPIO_GROUP_Max][GPIO_PORT_Max] = { + /* Port-0 Port-1 Port-2 Port-3 Port-4 Port-5 Port-6 Port-7 */ + { 0x1E27, 0x1E27, 0x1FE7, 0x1F67, 0x1F27, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_A */ + { 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E23, 0x1E63 }, /** GPIO_PORT_B */ + { 0x1EFF, 0x1EFF, 0x1FD3, 0x1F53, 0x1E1F, 0x1E1F, 0x1ED3, 0x1E53 }, /** GPIO_PORT_C */ + { 0x1E23, 0x1E23, 0x1E67, 0x1EFF, 0x1EBB, 0x1EA3, 0x0000, 0x0000 }, /** GPIO_PORT_D */ + { 0x1E83, 0x1EE3, 0x1EE3, 0x1EE3, 0x1EA3, 0x1EA3, 0x1EA3, 0x1F83 }, /** GPIO_PORT_E */ + { 0x1F6F, 0x1F6F, 0x1F63, 0x1FEF, 0x1FFF, 0x1FF3, 0x1F3F, 0x1F3F }, /** GPIO_PORT_F */ + { 0x1E63, 0x1E67, 0x1E67, 0x1E27, 0x1E27, 0x1E27, 0x1E07, 0x0000 }, /** GPIO_PORT_G */ + { 0x1803, 0x1803, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_H */ + { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x0000, 0x0000 }, /** GPIO_PORT_J */ + { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_K */ + { 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03, 0x1E03 }, /** GPIO_PORT_L */ + { 0x1E03, 0x1E03, 0x1E03, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_M */ + { 0x1FFF, 0x1FFF, 0x1EE7, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_N */ + { 0x1FBF, 0x1FFF, 0x1EE3, 0x1EE7, 0x1EE7, 0x1EEF, 0x1ECF, 0x1F83 }, /** GPIO_PORT_U */ + { 0x1E2B, 0x1E0F, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, /** GPIO_PORT_V */ +}; + +/** + * @} + */ /* End of group GPIO_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup GPIO_Private_fuctions GPIO Private Fuctions + * @{ + */ + +#ifdef DEBUG +__INLINE static int32_t check_param_port_num(uint32_t param); +__INLINE static int32_t check_param_port_mode(uint32_t param); +#endif +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Port Number. + * @param param :Port Number parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref gpio_num_t +*/ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_port_num(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case GPIO_PORT_0: + case GPIO_PORT_1: + case GPIO_PORT_2: + case GPIO_PORT_3: + case GPIO_PORT_4: + case GPIO_PORT_5: + case GPIO_PORT_6: + case GPIO_PORT_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Port Mode. + * @param param :Port Mode parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref gpio_mode_t +*/ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_port_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case GPIO_Mode_DATA: + case GPIO_Mode_CR: + case GPIO_Mode_FR1: + case GPIO_Mode_FR2: + case GPIO_Mode_FR3: + case GPIO_Mode_FR4: + case GPIO_Mode_FR5: + case GPIO_Mode_FR6: + case GPIO_Mode_FR7: + case GPIO_Mode_OD: + case GPIO_Mode_PUP: + case GPIO_Mode_PDN: + case GPIO_Mode_IE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/*! + * @fn static int32_t check_param_pin_exist(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) + * @brief Check the Pin Exist. + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] num :GPIO Port Number. : Use @ref gpio_num_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + */ +/*--------------------------------------------------*/ + +static uint8_t change_mode_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_Mode_DATA) { + retVal = 0; + } else if (mode == GPIO_Mode_CR) { + retVal = 1; + } else if (mode == GPIO_Mode_FR1) { + retVal = 2; + } else if (mode == GPIO_Mode_FR2) { + retVal = 3; + } else if (mode == GPIO_Mode_FR3) { + retVal = 4; + } else if (mode == GPIO_Mode_FR4) { + retVal = 5; + } else if (mode == GPIO_Mode_FR5) { + retVal = 6; + } else if (mode == GPIO_Mode_FR6) { + retVal = 7; + } else if (mode == GPIO_Mode_FR7) { + retVal = 8; + } else if (mode == GPIO_Mode_OD) { + retVal = 9; + } else if (mode == GPIO_Mode_PUP) { + retVal = 10; + } else if (mode == GPIO_Mode_PDN) { + retVal = 11; + } else if (mode == GPIO_Mode_IE) { + retVal = 12; + } else { + retVal = 13; + } + + return retVal; +} + +static uint8_t change_func_to_num(uint32_t mode) +{ + uint8_t retVal = 0; + + if (mode == GPIO_FR_1) { + retVal = 2; + } else if (mode == GPIO_FR_2) { + retVal = 3; + } else if (mode == GPIO_FR_3) { + retVal = 4; + } else if (mode == GPIO_FR_4) { + retVal = 5; + } else if (mode == GPIO_FR_5) { + retVal = 6; + } else if (mode == GPIO_FR_6) { + retVal = 7; + } else if (mode == GPIO_FR_7) { + retVal = 8; + } else if (mode == GPIO_FR_NA) { + retVal = 1; + } else if (mode == 0) { + retVal = 1; + } else { + retVal = 13; + } + + return retVal; +} + +static int32_t check_param_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgmode; + uint16_t tmp; + + chgmode = change_mode_to_num(mode); + if ((chgmode < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgmode) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +static int32_t check_param_func_pin_exist(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode) +{ + int32_t result = PARAM_NG; + uint8_t chgfunc; + uint16_t tmp; + + chgfunc = change_func_to_num(mode); + /* param check skip if func is INPUT or OUTPUT */ + if (chgfunc == 1) { + return (PARAM_OK); + } + if ((chgfunc < 13) && (group < GPIO_GROUP_Max) && (num < GPIO_PORT_Max)) { + tmp = (PinExistTbl[group][num] >> chgfunc) & 0x01; + result = PARAM_OK; + if (tmp == 0) { + result = PARAM_NG; + } + } else { + result = PARAM_NG; + } + + return (result); +} +/** + * @} + */ /* End of group GPIO_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup GPIO_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result _gpio_init(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + switch (group) { + case GPIO_PORT_A: + p_obj->p_pa_instance->DATA = 0x00; + p_obj->p_pa_instance->CR = 0x00; + p_obj->p_pa_instance->FR1 = 0x00; + p_obj->p_pa_instance->FR4 = 0x00; + p_obj->p_pa_instance->FR5 = 0x00; + p_obj->p_pa_instance->FR6 = 0x00; + p_obj->p_pa_instance->FR7 = 0x00; + p_obj->p_pa_instance->OD = 0x00; + p_obj->p_pa_instance->PUP = 0x00; + p_obj->p_pa_instance->PDN = 0x00; + p_obj->p_pa_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA00 = 1U; + break; + case GPIO_PORT_B: + p_obj->p_pb_instance->DATA = 0x00; + p_obj->p_pb_instance->CR = 0x00; + p_obj->p_pb_instance->FR4 = 0x00; + p_obj->p_pb_instance->OD = 0x00; + p_obj->p_pb_instance->PUP = 0x00; + p_obj->p_pb_instance->PDN = 0x00; + p_obj->p_pb_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA01 = 1U; + break; + case GPIO_PORT_C: + p_obj->p_pc_instance->DATA = 0x00; + p_obj->p_pc_instance->CR = 0x00; + p_obj->p_pc_instance->FR1 = 0x00; + p_obj->p_pc_instance->FR2 = 0x00; + p_obj->p_pc_instance->FR3 = 0x00; + p_obj->p_pc_instance->FR4 = 0x00; + p_obj->p_pc_instance->FR5 = 0x00; + p_obj->p_pc_instance->FR6 = 0x00; + p_obj->p_pc_instance->FR7 = 0x00; + p_obj->p_pc_instance->OD = 0x00; + p_obj->p_pc_instance->PUP = 0x00; + p_obj->p_pc_instance->PDN = 0x00; + p_obj->p_pc_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA02 = 1U; + break; + case GPIO_PORT_D: + p_obj->p_pd_instance->DATA = 0x00; + p_obj->p_pd_instance->CR = 0x00; + p_obj->p_pd_instance->FR1 = 0x00; + p_obj->p_pd_instance->FR2 = 0x00; + p_obj->p_pd_instance->FR3 = 0x00; + p_obj->p_pd_instance->FR4 = 0x00; + p_obj->p_pd_instance->FR5 = 0x00; + p_obj->p_pd_instance->FR6 = 0x00; + p_obj->p_pd_instance->OD = 0x00; + p_obj->p_pd_instance->PUP = 0x00; + p_obj->p_pd_instance->PDN = 0x00; + p_obj->p_pd_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA03 = 1U; + break; + case GPIO_PORT_E: + p_obj->p_pe_instance->DATA = 0x00; + p_obj->p_pe_instance->CR = 0x00; + p_obj->p_pe_instance->FR4 = 0x00; + p_obj->p_pe_instance->FR5 = 0x00; + p_obj->p_pe_instance->FR6 = 0x00; + p_obj->p_pe_instance->FR7 = 0x00; + p_obj->p_pe_instance->OD = 0x00; + p_obj->p_pe_instance->PUP = 0x00; + p_obj->p_pe_instance->PDN = 0x00; + p_obj->p_pe_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA04 = 1U; + break; + case GPIO_PORT_F: + p_obj->p_pf_instance->DATA = 0x00; + p_obj->p_pf_instance->CR = 0x00; + p_obj->p_pf_instance->FR1 = 0x00; + p_obj->p_pf_instance->FR2 = 0x00; + p_obj->p_pf_instance->FR3 = 0x00; + p_obj->p_pf_instance->FR4 = 0x00; + p_obj->p_pf_instance->FR5 = 0x00; + p_obj->p_pf_instance->FR6 = 0x00; + p_obj->p_pf_instance->FR7 = 0x00; + p_obj->p_pf_instance->OD = 0x00; + p_obj->p_pf_instance->PUP = 0x00; + p_obj->p_pf_instance->PDN = 0x00; + p_obj->p_pf_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA05 = 1U; + break; + case GPIO_PORT_G: + p_obj->p_pg_instance->DATA = 0x00; + p_obj->p_pg_instance->CR = 0x00; + p_obj->p_pg_instance->FR1 = 0x00; + p_obj->p_pg_instance->FR4 = 0x00; + p_obj->p_pg_instance->FR5 = 0x00; + p_obj->p_pg_instance->OD = 0x00; + p_obj->p_pg_instance->PUP = 0x00; + p_obj->p_pg_instance->PDN = 0x00; + p_obj->p_pg_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA06 = 1U; + break; + case GPIO_PORT_H: + p_obj->p_ph_instance->DATA = 0x00; + p_obj->p_ph_instance->PDN = 0x00; + p_obj->p_ph_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA07 = 1U; + break; + case GPIO_PORT_J: + p_obj->p_pj_instance->DATA = 0x00; + p_obj->p_pj_instance->CR = 0x00; + p_obj->p_pj_instance->OD = 0x00; + p_obj->p_pj_instance->PUP = 0x00; + p_obj->p_pj_instance->PDN = 0x00; + p_obj->p_pj_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA08 = 1U; + break; + case GPIO_PORT_K: + p_obj->p_pk_instance->DATA = 0x00; + p_obj->p_pk_instance->CR = 0x06; + p_obj->p_pk_instance->OD = 0x00; + p_obj->p_pk_instance->PUP = 0x15; + p_obj->p_pk_instance->PDN = 0x08; + p_obj->p_pk_instance->IE = 0x1D; + TSB_CG_FSYSMENA_IPMENA09 = 1U; + break; + case GPIO_PORT_L: + p_obj->p_pl_instance->DATA = 0x00; + p_obj->p_pl_instance->CR = 0x00; + p_obj->p_pl_instance->OD = 0x00; + p_obj->p_pl_instance->PUP = 0x00; + p_obj->p_pl_instance->PDN = 0x00; + p_obj->p_pl_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA10 = 1U; + break; + case GPIO_PORT_M: + p_obj->p_pm_instance->DATA = 0x00; + p_obj->p_pm_instance->CR = 0x00; + p_obj->p_pm_instance->OD = 0x00; + p_obj->p_pm_instance->PUP = 0x00; + p_obj->p_pm_instance->PDN = 0x00; + p_obj->p_pm_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA11 = 1U; + break; + case GPIO_PORT_N: + p_obj->p_pn_instance->DATA = 0x00; + p_obj->p_pn_instance->CR = 0x00; + p_obj->p_pn_instance->FR1 = 0x00; + p_obj->p_pn_instance->FR2 = 0x00; + p_obj->p_pn_instance->FR3 = 0x00; + p_obj->p_pn_instance->FR4 = 0x00; + p_obj->p_pn_instance->FR5 = 0x00; + p_obj->p_pn_instance->FR6 = 0x00; + p_obj->p_pn_instance->FR7 = 0x00; + p_obj->p_pn_instance->OD = 0x00; + p_obj->p_pn_instance->PUP = 0x00; + p_obj->p_pn_instance->PDN = 0x00; + p_obj->p_pn_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA12 = 1U; + break; + case GPIO_PORT_U: + p_obj->p_pu_instance->DATA = 0x00; + p_obj->p_pu_instance->CR = 0x00; + p_obj->p_pu_instance->FR1 = 0x00; + p_obj->p_pu_instance->FR2 = 0x00; + p_obj->p_pu_instance->FR3 = 0x00; + p_obj->p_pu_instance->FR4 = 0x00; + p_obj->p_pu_instance->FR5 = 0x00; + p_obj->p_pu_instance->FR6 = 0x00; + p_obj->p_pu_instance->FR7 = 0x00; + p_obj->p_pu_instance->OD = 0x00; + p_obj->p_pu_instance->PUP = 0x00; + p_obj->p_pu_instance->PDN = 0x00; + p_obj->p_pu_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA16 = 1U; + break; + case GPIO_PORT_V: + p_obj->p_pv_instance->DATA = 0x00; + p_obj->p_pv_instance->CR = 0x00; + p_obj->p_pv_instance->FR1 = 0x00; + p_obj->p_pv_instance->FR2 = 0x00; + p_obj->p_pv_instance->FR4 = 0x00; + p_obj->p_pv_instance->OD = 0x00; + p_obj->p_pv_instance->PUP = 0x00; + p_obj->p_pv_instance->PDN = 0x00; + p_obj->p_pv_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA17 = 1U; + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the GPIO object. + * @param p_obj :GPIO object. + * @param group :GPIO Port Group.: Use @ref gpio_gr_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_deinit(_gpio_t *p_obj, uint32_t group) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (group) { + case GPIO_PORT_A: + p_obj->p_pa_instance->DATA = 0x00; + p_obj->p_pa_instance->CR = 0x00; + p_obj->p_pa_instance->FR1 = 0x00; + p_obj->p_pa_instance->FR4 = 0x00; + p_obj->p_pa_instance->FR5 = 0x00; + p_obj->p_pa_instance->FR6 = 0x00; + p_obj->p_pa_instance->FR7 = 0x00; + p_obj->p_pa_instance->OD = 0x00; + p_obj->p_pa_instance->PUP = 0x00; + p_obj->p_pa_instance->PDN = 0x00; + p_obj->p_pa_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA00 = 0U; + break; + case GPIO_PORT_B: + p_obj->p_pb_instance->DATA = 0x00; + p_obj->p_pb_instance->CR = 0x00; + p_obj->p_pb_instance->FR4 = 0x00; + p_obj->p_pb_instance->OD = 0x00; + p_obj->p_pb_instance->PUP = 0x00; + p_obj->p_pb_instance->PDN = 0x00; + p_obj->p_pb_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA01 = 0U; + break; + case GPIO_PORT_C: + p_obj->p_pc_instance->DATA = 0x00; + p_obj->p_pc_instance->CR = 0x00; + p_obj->p_pc_instance->FR1 = 0x00; + p_obj->p_pc_instance->FR2 = 0x00; + p_obj->p_pc_instance->FR3 = 0x00; + p_obj->p_pc_instance->FR4 = 0x00; + p_obj->p_pc_instance->FR5 = 0x00; + p_obj->p_pc_instance->FR6 = 0x00; + p_obj->p_pc_instance->FR7 = 0x00; + p_obj->p_pc_instance->OD = 0x00; + p_obj->p_pc_instance->PUP = 0x00; + p_obj->p_pc_instance->PDN = 0x00; + p_obj->p_pc_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA02 = 0U; + break; + case GPIO_PORT_D: + p_obj->p_pd_instance->DATA = 0x00; + p_obj->p_pd_instance->CR = 0x00; + p_obj->p_pd_instance->FR1 = 0x00; + p_obj->p_pd_instance->FR2 = 0x00; + p_obj->p_pd_instance->FR3 = 0x00; + p_obj->p_pd_instance->FR4 = 0x00; + p_obj->p_pd_instance->FR5 = 0x00; + p_obj->p_pd_instance->FR6 = 0x00; + p_obj->p_pd_instance->OD = 0x00; + p_obj->p_pd_instance->PUP = 0x00; + p_obj->p_pd_instance->PDN = 0x00; + p_obj->p_pd_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA03 = 0U; + break; + case GPIO_PORT_E: + p_obj->p_pe_instance->DATA = 0x00; + p_obj->p_pe_instance->CR = 0x00; + p_obj->p_pe_instance->FR4 = 0x00; + p_obj->p_pe_instance->FR5 = 0x00; + p_obj->p_pe_instance->FR6 = 0x00; + p_obj->p_pe_instance->FR7 = 0x00; + p_obj->p_pe_instance->OD = 0x00; + p_obj->p_pe_instance->PUP = 0x00; + p_obj->p_pe_instance->PDN = 0x00; + p_obj->p_pe_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA04 = 0U; + break; + case GPIO_PORT_F: + p_obj->p_pf_instance->DATA = 0x00; + p_obj->p_pf_instance->CR = 0x00; + p_obj->p_pf_instance->FR1 = 0x00; + p_obj->p_pf_instance->FR2 = 0x00; + p_obj->p_pf_instance->FR3 = 0x00; + p_obj->p_pf_instance->FR4 = 0x00; + p_obj->p_pf_instance->FR5 = 0x00; + p_obj->p_pf_instance->FR6 = 0x00; + p_obj->p_pf_instance->FR7 = 0x00; + p_obj->p_pf_instance->OD = 0x00; + p_obj->p_pf_instance->PUP = 0x00; + p_obj->p_pf_instance->PDN = 0x00; + p_obj->p_pf_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA05 = 0U; + break; + case GPIO_PORT_G: + p_obj->p_pg_instance->DATA = 0x00; + p_obj->p_pg_instance->CR = 0x00; + p_obj->p_pg_instance->FR1 = 0x00; + p_obj->p_pg_instance->FR4 = 0x00; + p_obj->p_pg_instance->FR5 = 0x00; + p_obj->p_pg_instance->OD = 0x00; + p_obj->p_pg_instance->PUP = 0x00; + p_obj->p_pg_instance->PDN = 0x00; + p_obj->p_pg_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA06 = 0U; + break; + case GPIO_PORT_H: + p_obj->p_ph_instance->DATA = 0x00; + p_obj->p_ph_instance->PDN = 0x00; + p_obj->p_ph_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA07 = 0U; + break; + case GPIO_PORT_J: + p_obj->p_pj_instance->DATA = 0x00; + p_obj->p_pj_instance->CR = 0x00; + p_obj->p_pj_instance->OD = 0x00; + p_obj->p_pj_instance->PUP = 0x00; + p_obj->p_pj_instance->PDN = 0x00; + p_obj->p_pj_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA08 = 0U; + break; + case GPIO_PORT_K: + p_obj->p_pk_instance->DATA = 0x00; + p_obj->p_pk_instance->CR = 0x06; + p_obj->p_pk_instance->OD = 0x00; + p_obj->p_pk_instance->PUP = 0x15; + p_obj->p_pk_instance->PDN = 0x08; + p_obj->p_pk_instance->IE = 0x1D; + TSB_CG_FSYSMENA_IPMENA09 = 0U; + break; + case GPIO_PORT_L: + p_obj->p_pl_instance->DATA = 0x00; + p_obj->p_pl_instance->CR = 0x00; + p_obj->p_pl_instance->OD = 0x00; + p_obj->p_pl_instance->PUP = 0x00; + p_obj->p_pl_instance->PDN = 0x00; + p_obj->p_pl_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA10 = 0U; + break; + case GPIO_PORT_M: + p_obj->p_pm_instance->DATA = 0x00; + p_obj->p_pm_instance->CR = 0x00; + p_obj->p_pm_instance->OD = 0x00; + p_obj->p_pm_instance->PUP = 0x00; + p_obj->p_pm_instance->PDN = 0x00; + p_obj->p_pm_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA11 = 0U; + break; + case GPIO_PORT_N: + p_obj->p_pn_instance->DATA = 0x00; + p_obj->p_pn_instance->CR = 0x00; + p_obj->p_pn_instance->FR1 = 0x00; + p_obj->p_pn_instance->FR2 = 0x00; + p_obj->p_pn_instance->FR3 = 0x00; + p_obj->p_pn_instance->FR4 = 0x00; + p_obj->p_pn_instance->FR5 = 0x00; + p_obj->p_pn_instance->FR6 = 0x00; + p_obj->p_pn_instance->FR7 = 0x00; + p_obj->p_pn_instance->OD = 0x00; + p_obj->p_pn_instance->PUP = 0x00; + p_obj->p_pn_instance->PDN = 0x00; + p_obj->p_pn_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA12 = 0U; + break; + case GPIO_PORT_U: + p_obj->p_pu_instance->DATA = 0x00; + p_obj->p_pu_instance->CR = 0x00; + p_obj->p_pu_instance->FR1 = 0x00; + p_obj->p_pu_instance->FR2 = 0x00; + p_obj->p_pu_instance->FR3 = 0x00; + p_obj->p_pu_instance->FR4 = 0x00; + p_obj->p_pu_instance->FR5 = 0x00; + p_obj->p_pu_instance->FR6 = 0x00; + p_obj->p_pu_instance->FR7 = 0x00; + p_obj->p_pu_instance->OD = 0x00; + p_obj->p_pu_instance->PUP = 0x00; + p_obj->p_pu_instance->PDN = 0x00; + p_obj->p_pu_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA16 = 0U; + break; + case GPIO_PORT_V: + p_obj->p_pv_instance->DATA = 0x00; + p_obj->p_pv_instance->CR = 0x00; + p_obj->p_pv_instance->FR1 = 0x00; + p_obj->p_pv_instance->FR2 = 0x00; + p_obj->p_pv_instance->FR4 = 0x00; + p_obj->p_pv_instance->OD = 0x00; + p_obj->p_pv_instance->PUP = 0x00; + p_obj->p_pv_instance->PDN = 0x00; + p_obj->p_pv_instance->IE = 0x00; + TSB_CG_FSYSMENA_IPMENA17 = 0U; + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Port Mode Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param val :value + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t i; + int32_t param_result = PARAM_NG; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_mode(mode); + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(&p_obj)); +#endif + + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = check_param_pin_exist(p_obj, group, (uint32_t)i, mode); + if (param_result == PARAM_OK) { + break; + } else { + result = TXZ_ERROR; + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + return (result); + } + + switch (group) { + case GPIO_PORT_A: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pa_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pa_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pa_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pa_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pa_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pa_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pa_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pa_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pa_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pa_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pa_instance->IE = val; + } + break; + case GPIO_PORT_B: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pb_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pb_instance->CR = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pb_instance->FR4 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pb_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pb_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pb_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pb_instance->IE = val; + } + break; + case GPIO_PORT_C: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pc_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pc_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pc_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pc_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pc_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pc_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pc_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pc_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pc_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pc_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pc_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pc_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pc_instance->IE = val; + } + break; + case GPIO_PORT_D: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pd_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pd_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pd_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pd_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pd_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pd_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pd_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pd_instance->FR6 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pd_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pd_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pd_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pd_instance->IE = val; + } + break; + case GPIO_PORT_E: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pe_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pe_instance->CR = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pe_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pe_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pe_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pe_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pe_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pe_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pe_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pe_instance->IE = val; + } + break; + case GPIO_PORT_F: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pf_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pf_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pf_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pf_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pf_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pf_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pf_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pf_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pf_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pf_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pf_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pf_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pf_instance->IE = val; + } + break; + case GPIO_PORT_G: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pg_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pg_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pg_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pg_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pg_instance->FR5 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pg_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pg_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pg_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pg_instance->IE = val; + } + break; + case GPIO_PORT_H: + if (mode == GPIO_Mode_DATA) { + p_obj->p_ph_instance->DATA = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_ph_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_ph_instance->IE = val; + } + break; + case GPIO_PORT_J: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pj_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pj_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pj_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pj_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pj_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pj_instance->IE = val; + } + break; + case GPIO_PORT_K: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pk_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pk_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pk_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pk_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pk_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pk_instance->IE = val; + } + break; + case GPIO_PORT_L: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pl_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pl_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pl_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pl_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pl_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pl_instance->IE = val; + } + break; + case GPIO_PORT_M: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pm_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pm_instance->CR = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pm_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pm_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pm_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pm_instance->IE = val; + } + break; + case GPIO_PORT_N: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pn_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pn_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pn_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pn_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pn_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pn_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pn_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pn_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pn_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pn_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pn_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pn_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pn_instance->IE = val; + } + break; + case GPIO_PORT_U: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pu_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pu_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pu_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pu_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR3) { + p_obj->p_pu_instance->FR3 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pu_instance->FR4 = val; + } else if (mode == GPIO_Mode_FR5) { + p_obj->p_pu_instance->FR5 = val; + } else if (mode == GPIO_Mode_FR6) { + p_obj->p_pu_instance->FR6 = val; + } else if (mode == GPIO_Mode_FR7) { + p_obj->p_pu_instance->FR7 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pu_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pu_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pu_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pu_instance->IE = val; + } + break; + case GPIO_PORT_V: + if (mode == GPIO_Mode_DATA) { + p_obj->p_pv_instance->DATA = val; + } else if (mode == GPIO_Mode_CR) { + p_obj->p_pv_instance->CR = val; + } else if (mode == GPIO_Mode_FR1) { + p_obj->p_pv_instance->FR1 = val; + } else if (mode == GPIO_Mode_FR2) { + p_obj->p_pv_instance->FR2 = val; + } else if (mode == GPIO_Mode_FR4) { + p_obj->p_pv_instance->FR4 = val; + } else if (mode == GPIO_Mode_OD) { + p_obj->p_pv_instance->OD = val; + } else if (mode == GPIO_Mode_PUP) { + p_obj->p_pv_instance->PUP = val; + } else if (mode == GPIO_Mode_PDN) { + p_obj->p_pv_instance->PDN = val; + } else if (mode == GPIO_Mode_IE) { + p_obj->p_pv_instance->IE = val; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result gpio_read_mode(gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) + * @brief Port Mode Read + * @param[in] p_obj :GPIO object. + * @param[in] group :GPIO Port Group. : Use @ref gpio_gr_t + * @param[in] mode :GPIO Port Mode. : Use @ref gpio_num_t + * @param[out] val :value store address + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_mode(_gpio_t *p_obj, uint32_t group, uint32_t mode, uint32_t *val) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + uint32_t i; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_mode(mode); + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + /* Check the parameters, the NULL of address */ + for (i = GPIO_PORT_0; i < GPIO_PORT_Max; i++) { + param_result = (int32_t)check_param_pin_exist(p_obj, group, i, mode); + if (param_result == PARAM_OK) { + break; + } else { + /* No Process */ + } + } + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + return (result); + } + + switch (group) { + case GPIO_PORT_A: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pa_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pa_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pa_instance->FR1 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pa_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pa_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pa_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pa_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pa_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pa_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pa_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pa_instance->IE ; + } + break; + case GPIO_PORT_B: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pb_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pb_instance->CR ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pb_instance->FR4 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pb_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pb_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pb_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pb_instance->IE ; + } + break; + case GPIO_PORT_C: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pc_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pc_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pc_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pc_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pc_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pc_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pc_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pc_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pc_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pc_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pc_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pc_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pc_instance->IE ; + } + break; + case GPIO_PORT_D: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pd_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pd_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pd_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pd_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pd_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pd_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pd_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pd_instance->FR6 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pd_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pd_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pd_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pd_instance->IE ; + } + break; + case GPIO_PORT_E: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pe_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pe_instance->CR ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pe_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pe_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pe_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pe_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pe_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pe_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pe_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pe_instance->IE ; + } + break; + case GPIO_PORT_F: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pf_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pf_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pf_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pf_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pf_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pf_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pf_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pf_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pf_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pf_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pf_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pf_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pf_instance->IE ; + } + break; + case GPIO_PORT_G: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pg_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pg_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pg_instance->FR1 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pg_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pg_instance->FR5 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pg_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pg_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pg_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pg_instance->IE; + } + break; + case GPIO_PORT_H: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_ph_instance->DATA; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_ph_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_ph_instance->IE ; + } + break; + case GPIO_PORT_J: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pj_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pj_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pj_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pj_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pj_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pj_instance->IE ; + } + break; + case GPIO_PORT_K: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pk_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pk_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pk_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pk_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pk_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pk_instance->IE ; + } + break; + case GPIO_PORT_L: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pl_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pl_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pl_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pl_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pl_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pl_instance->IE ; + } + break; + case GPIO_PORT_M: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pm_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pm_instance->CR ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pm_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pm_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pm_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pm_instance->IE ; + } + break; + case GPIO_PORT_N: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pn_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pn_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pn_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pn_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pn_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pn_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pn_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pn_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pn_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pn_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pn_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pn_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pn_instance->IE ; + } + break; + case GPIO_PORT_U: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pu_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pu_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pu_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pu_instance->FR2 ; + } else if (mode == GPIO_Mode_FR3) { + *val = p_obj->p_pu_instance->FR3 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pu_instance->FR4 ; + } else if (mode == GPIO_Mode_FR5) { + *val = p_obj->p_pu_instance->FR5 ; + } else if (mode == GPIO_Mode_FR6) { + *val = p_obj->p_pu_instance->FR6 ; + } else if (mode == GPIO_Mode_FR7) { + *val = p_obj->p_pu_instance->FR7 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pu_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pu_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pu_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pu_instance->IE ; + } + break; + case GPIO_PORT_V: + if (mode == GPIO_Mode_DATA) { + *val = p_obj->p_pv_instance->DATA; + } else if (mode == GPIO_Mode_CR) { + *val = p_obj->p_pv_instance->CR ; + } else if (mode == GPIO_Mode_FR1) { + *val = p_obj->p_pv_instance->FR1 ; + } else if (mode == GPIO_Mode_FR2) { + *val = p_obj->p_pv_instance->FR2 ; + } else if (mode == GPIO_Mode_FR4) { + *val = p_obj->p_pv_instance->FR4 ; + } else if (mode == GPIO_Mode_OD) { + *val = p_obj->p_pv_instance->OD ; + } else if (mode == GPIO_Mode_PUP) { + *val = p_obj->p_pv_instance->PUP ; + } else if (mode == GPIO_Mode_PDN) { + *val = p_obj->p_pv_instance->PDN ; + } else if (mode == GPIO_Mode_IE) { + *val = p_obj->p_pv_instance->IE ; + } + break; + default: + result = TXZ_ERROR; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Port Function switching + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param func :GPIO Portxx Func. : Use @ref gpio_pa0_func_t - @ref gpio_pl4_func_t + * @param inout :GPIO bit Value.: Use @ref gpio_pinstate_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_func(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t func, uint32_t inout) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t param_result = PARAM_NG; + uint32_t port_base; + uint32_t mode_base; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + param_result = check_param_func_pin_exist(p_obj, group, num, func); + if (((void *)(p_obj) == (void *)0) || (param_result == PARAM_NG)) { + result = TXZ_ERROR; + return (result); + } + + if (group > GPIO_THRESHOLD) { + group += GPIO_OFFSET; + } + + port_base = BITBAND_PORT_BASE(group); + + /* Initialization PxFR OFF */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_CLR(mode_base, num); + + /* Initialize Input */ + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + + switch (func) { + case 0: + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 1: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 2: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 3: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 4: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 5: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 6: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + case 7: + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7); + BITBAND_PORT_SET(mode_base, num); + if (inout == GPIO_PIN_OUTPUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_CLR(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } else if (inout == GPIO_PIN_INOUT) { + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE); + BITBAND_PORT_SET(mode_base, num); + mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR); + BITBAND_PORT_SET(mode_base, num); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Port Bit Write + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param val :GPIO Pin Reset/Set. : Use @ref gpio_pinstate_t + * @retval GPIO_RESULT_SUCCESS :Success. + * @retval GPIO_RESULT_FAILURE :Failure. + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_write_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, uint32_t val) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_num(num); + check_param_port_mode(mode); +#endif + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + return (result); + } + if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + return (result); + } + + if (group > GPIO_THRESHOLD) { + group += GPIO_OFFSET; + } + + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + if (val == GPIO_PIN_SET) { + BITBAND_PORT_SET(base, num); + } else { + BITBAND_PORT_CLR(base, num); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @fn TXZ_Result gpio_read_bit(gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) + * @brief Port Bit Read + * @param p_obj :GPIO object. + * @param group :GPIO Port Group. : Use @ref gpio_gr_t + * @param num :GPIO Port Number. : Use @ref gpio_num_t + * @param mode :GPIO Port Mode. : Use @ref gpio_mode_t + * @param[out] *pinstate : store Value of GPIO BitPin. : Use @ref gpio_pinstate_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, no processing.: Use @ref gpio_pinstate_t + */ +/*--------------------------------------------------*/ +TXZ_Result gpio_read_bit(_gpio_t *p_obj, uint32_t group, uint32_t num, uint32_t mode, gpio_pinstate_t *pinstate) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t base; + uint32_t val; +#ifdef DEBUG + /* Check the parameters */ + check_param_port_num(num); + check_param_port_mode(mode); +#endif + if ((void *)(p_obj) == (void *)0) { + result = TXZ_ERROR; + return (result); + } + if (check_param_pin_exist(p_obj, group, num, mode) == PARAM_NG) { + result = TXZ_ERROR; + return (result); + } + + if (group > GPIO_THRESHOLD) { + group += GPIO_OFFSET; + } + + base = BITBAND_PORT_BASE(group); + base = BITBAND_PORT_MODE_BASE(base, mode); + BITBAND_PORT_READ(val, base, num); + if (val == GPIO_PIN_RESET) { + *pinstate = GPIO_PIN_RESET; + } else if (val == GPIO_PIN_SET) { + *pinstate = GPIO_PIN_SET; + } else { + result = TXZ_ERROR; + } + + return result; +} + +/** + * @} + */ /* End of group GPIO_Exported_functions */ + +/** + * @} + */ /* End of group GPIO */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__GPIO_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c.c new file mode 100644 index 00000000000..1874ede5986 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c.c @@ -0,0 +1,414 @@ +/** + ******************************************************************************* + * @file txzp_i2c.c + * @brief This file provides API functions for I2C Class. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_i2c.h" + +#if defined(__I2C_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief SCK Divider value table. + * @details SCK = b000 - b111. + * @note NFSEL=0 (Digital Setting) Divider value. +*/ +/*----------------------------------*/ +static const uint32_t I2C_SCK_DIVIDER_TBL[8] = { 20, 24, 32, 48, 80, 144, 272, 528 }; +static const uint32_t I2C_SCK_LOW_MUL_TBL[8] = { 12, 14, 18, 26, 42, 74, 138, 266 }; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Initializing I2C Regester + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + p_obj->p_instance->CR2 = I2CxCR2_I2CM_ENABLE; + p_obj->p_instance->OP = I2CxOP_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->AR = I2CxAR_INIT; + p_obj->p_instance->AR2 = I2CxAR2_INIT; + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); + p_obj->p_instance->IE = I2CxIE_CLEAR; +} + +/*--------------------------------------------------*/ +/** + * @brief Generate start condition + * @param p_obj :I2C object. + * @param data :Slave address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_start_condition(I2C_t *p_obj, uint32_t data) +{ + __IO uint32_t opreg; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + opreg = p_obj->p_instance->OP; + opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN); + if (I2C_master(p_obj)) { + if ((p_obj->p_instance->SR & I2CxSR_BB)) { + opreg |= I2CxOP_SREN; + } + } + p_obj->p_instance->CR1 = (I2CxCR1_ACK | I2CxCR1_NOACK | p_obj->init.clock.sck); + p_obj->p_instance->OP = opreg; + p_obj->p_instance->DBR = (data & I2CxDBR_DB_MASK); + p_obj->p_instance->CR2 = I2CxCR2_START_CONDITION; +} + +/*--------------------------------------------------*/ +/** + * @brief Return the I2c clock setting + * @param p_obj :I2C object. + * @param frequency :Maximum frequency. + * @param fsys :SystemCoreClock. + * @param p_setting :Clock data pointer. + * @retval Non-zero :Scl frequency. + * @retval 0 :Error. + * @note - + */ +/*--------------------------------------------------*/ +uint32_t I2C_get_clock_setting(I2C_t *p_obj, uint32_t frequency, uint32_t fsys, I2C_clock_setting_t *p_setting) +{ + uint32_t result = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_setting)); +#endif /* #ifdef DEBUG */ + + if (frequency <= 1000000) { + uint64_t sck, tmp_sck; + uint64_t prsck, tmp_prsck; + uint64_t fscl, tmp_fscl; + uint64_t fx; + uint64_t max_fx, min_fx; + uint64_t low_width, low_width_min; + + sck = tmp_sck = 0; + prsck = tmp_prsck = 1; + fscl = tmp_fscl = 0; + + if (frequency <= 400000) { + max_fx = 11428572U; /* Tpresck: 87.5ns 1/87.5 = 0.0114285714 */ + min_fx = 6666666U; /* Tpresck:150.0ns 1/150 = 0.0066666667 */ + low_width_min = 1600; + } else { + max_fx = 26666667U; /* Tpresck:37.5ns 1/37.5 = 0.0266666667 */ + min_fx = 15384615U; /* Tpresck:65.0ns 1/65 = 0.0153846154 */ + low_width_min = 675; + } + for (prsck = 1; prsck <= 32; prsck++) { + fx = ((uint64_t)fsys / prsck); + + if ((fx < max_fx) && (fx >= min_fx)) { + for (sck = 0; sck <= 7; sck++) { + low_width = (uint64_t)(1000000000 * prsck * I2C_SCK_LOW_MUL_TBL[sck]) / fsys; + if (low_width < low_width_min) { + continue; + } + fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]); + + if ((fscl <= frequency) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + tmp_sck = sck; + tmp_prsck = (prsck < 32) ? prsck : 0; + } + } + } + } + result = (uint32_t)tmp_fscl; + p_setting->sck = (uint32_t)tmp_sck; + p_setting->prsck = (tmp_prsck < 32) ? (uint32_t)tmp_prsck : 0; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Slave mode setting. + * @param p_obj :I2C object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2C_slave_init(I2C_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->OP = I2CxOP_SLAVE_INIT; + p_obj->p_instance->CR1 = (I2CxCR1_ACK | p_obj->init.clock.sck); + p_obj->p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->p_instance->CR2 = I2CxCR2_INIT; + p_obj->p_instance->PRS = (I2CxPRS_PRCK & p_obj->init.clock.prsck); +} +#if defined(I2CSxWUP_EN) +/*--------------------------------------------------*/ +/** + * @brief I2C Wakeup Control setting. + * @param p_obj :I2CS object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_init(I2CS_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->WUPCR1 = (p_obj->init.wup.sgcdi | p_obj->init.wup.ack | p_obj->init.wup.reset | p_obj->init.wup.intend); +} + +/*--------------------------------------------------*/ +/** + * @brief Primary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Primary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Primary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->WUPCR2 = (0x0000000E & adr); +} + +/*--------------------------------------------------*/ +/** + * @brief Secondary Slave Address setting. + * @param p_obj :I2CS object. + * @param addr :Secondary Slave Address. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void I2CS_Secondary_slave_adr_set(I2CS_t *p_obj, uint32_t adr) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + p_obj->p_instance->WUPCR3 = (0x0000000E & adr); + p_obj->p_instance->WUPCR3 |= 0x00000001; /* WUPSA2EN: Secondary Slave Address Use Setting */ +} +#endif +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c_api.c new file mode 100644 index 00000000000..2e3c4b35f93 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_i2c_api.c @@ -0,0 +1,1381 @@ +/** + ******************************************************************************* + * @file txzp_i2c_api.c + * @brief This file provides API functions for BSP I2C driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_i2c_api.h" + +#if defined(__I2C_API_H) + +/** + * @addtogroup Example + * @{ + */ + +/** + * @addtogroup UTILITIES + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_macro + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_macro */ + +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define I2C_PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define I2C_PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name timeout + * @brief This timeouts are not based on accurate values, this just guarantee that + the application will not remain stuck if the I2C communication is corrupted. + * @{ + */ +#define I2C_TIMEOUT (100000) /*>! fail safe. */ + +/** + * @} + */ /* End of name timeout */ + +#define I2CxSR_AL ((uint32_t)0x00000008) /*!< AL */ +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +#define I2C_CH0 (0) /*!< I2C Channel 0. */ +#define I2C_CH1 (1) /*!< I2C Channel 1. */ +#define I2C_CH2 (2) /*!< I2C Channel 2. */ +#define I2C_CH3 (3) /*!< I2C Channel 3. */ +#define I2C_CH4 (4) /*!< I2C Channel 3. */ +#define I2C_CH_NUM (5) /*!< Number of I2C Channel. */ + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_define + * @{ + */ +/*----------------------------------*/ +/** + * @brief Transfer State. +*/ +/*----------------------------------*/ +enum { + I2C_TRANSFER_STATE_IDLE = 0U, /*!< Idle. */ + I2C_TRANSFER_STATE_BUSY /*!< Busy. */ +} TransferState; + +/** + * @} + */ /* End of group UTILITIES_Private_define */ + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_typedef + * @{ + */ + +/*----------------------------------*/ +/** + * @brief For IRQn_Type number definition. +*/ +/*----------------------------------*/ +typedef struct { + IRQn_Type i2c; + IRQn_Type al; + IRQn_Type bf; + IRQn_Type na; +} i2c_irq_t; + +/** + * @} + */ /* End of group UTILITIES_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_variables + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UTILITIES_Private_variables */ + +/*------------------------------------------------------------------------------*/ +/* Const Table */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_const + * @{ + */ +/*----------------------------------*/ +/** + * @brief Channel 0 IRQn_Type number table. +*/ +/*----------------------------------*/ +static const i2c_irq_t I2C_CH0_IRQN_TBL[1] = { + { INTI2C0NST_IRQn, INTI2C0ATX_IRQn, INTI2C0BRX_IRQn, INTI2C0NA_IRQn } +}; + +/** + * @} + */ /* End of group UTILITIES_Private_const */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Private_functions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn); +__STATIC_INLINE int32_t check_param_address(int32_t address); +#endif +__STATIC_INLINE void enable_irq(uint32_t irqn); +__STATIC_INLINE void disable_irq(uint32_t irqn); +__STATIC_INLINE void clear_irq(uint32_t irqn); +__STATIC_INLINE void set_port_ch0(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch1(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch2(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch3(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE void set_port_ch4(i2c_port_t sda, i2c_port_t scl); +__STATIC_INLINE uint32_t set_i2c(uint8_t ch, uint32_t *p_irqn); +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj); +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj); +static void i2c_irq_handler(_i2c_t *p_obj); +static void i2c_slave_irq_handler(_i2c_t *p_obj); + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Compare the IRQn's parameter. + * @param irqn :I2C IRQn List. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note -. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_irqn(uint32_t irqn) +{ + int32_t result = I2C_PARAM_NG; + + if (irqn == (uint32_t)&I2C_CH0_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH1_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH2_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH3_IRQN_TBL) { + result = I2C_PARAM_OK; + } + if (irqn == (uint32_t)&I2C_CH4_IRQN_TBL) { + result = I2C_PARAM_OK; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Compare the Slave address's parameter. + * @param address :Address. + * @retval I2C_PARAM_OK :Available. + * @retval I2C_PARAM_NG :Not Available. + * @note Here, 10bit address has not supported. + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_address(int32_t address) +{ + int32_t result = I2C_PARAM_NG; + + if ((address >= 0) && (address <= 255)) { + result = I2C_PARAM_OK; + } + return (result); +} +#endif + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void enable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_EnableIRQ(p_irqn->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void disable_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_DisableIRQ(p_irqn->i2c); + NVIC_DisableIRQ(p_irqn->al); + NVIC_DisableIRQ(p_irqn->bf); + NVIC_DisableIRQ(p_irqn->na); +} + +/*--------------------------------------------------*/ +/** + * @brief ClearPending I2C IRQ + * @param irqn :I2C IRQn List. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void clear_irq(uint32_t irqn) +{ + i2c_irq_t *p_irqn = (i2c_irq_t *)irqn; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(check_param_irqn(irqn)); +#endif /* #ifdef DEBUG */ + NVIC_ClearPendingIRQ(p_irqn->i2c); + NVIC_ClearPendingIRQ(p_irqn->al); + NVIC_ClearPendingIRQ(p_irqn->bf); + NVIC_ClearPendingIRQ(p_irqn->na); +} +/*--------------------------------------------------*/ +/** + * @brief Reset Asynch Transfer + * @param p_obj :i2c object + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE void reset_asynch(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); + I2C_disable_interrupt(&p_obj->i2c); +} + +__STATIC_INLINE int32_t I2C_status_arbitration(I2C_t *p_obj) +{ +#ifdef DEBUG + if ((p_obj != I2C_NULL) && (p_obj->p_instance != I2C_NULL)) { + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); + } + return (0); +#else + return ((p_obj->p_instance->SR & I2CxSR_AL) == I2CxSR_AL); +#endif +} +/*--------------------------------------------------*/ +/** + * @brief Waiting i2c status + * @param p_obj :i2c object + * @retval 0 :Success. + * @retval -1 :Failure. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t wait_status(_i2c_t *p_obj) +{ + int32_t timeout; + + timeout = I2C_TIMEOUT; + while (!I2C_int_status(&p_obj->i2c)) { + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + return (-5); + } + if ((timeout--) == 0) { + return (-1); + } + } + if (I2C_status_arbitration(&p_obj->i2c)) { + volatile uint32_t dummy = 0; + dummy = I2C_read_data(&p_obj->i2c); + return (-5); + } + return (0); +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((!I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + if (I2C_transmitter(&p_obj->i2c)) { + int32_t start = I2C_restart(&p_obj->i2c); + + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else if (p_obj->rx_buff.length != 0) { + I2C_start_condition(&p_obj->i2c, (p_obj->info.asynch.address | 1U)); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else if (p_obj->rx_buff.length != 0) { + if (p_obj->tx_buff.pos == 0) { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + p_obj->info.asynch.event = (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } else { + int32_t start = I2C_restart(&p_obj->i2c); + + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + if (p_obj->info.asynch.stop) { + I2C_stop_condition(&p_obj->i2c); + } + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + } +} + +/*--------------------------------------------------*/ +/** + * @brief I2C Transfer handler + * @param p_obj :i2c object. + * @retval - + * @note Called by i2c_slave_irq_handler_asynch_t. + */ +/*--------------------------------------------------*/ +static void i2c_slave_irq_handler(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + + if ((I2C_master(&p_obj->i2c)) || (p_obj->info.asynch.state != I2C_TRANSFER_STATE_BUSY)) { + p_obj->info.asynch.event = I2C_EVENT_ERROR; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } else { + int32_t start = I2C_slave_detected(&p_obj->i2c); + if (start) { + uint8_t sa = (uint8_t)I2C_read_data(&p_obj->i2c); + } + if (I2C_transmitter(&p_obj->i2c)) { + if (!I2C_get_ack(&p_obj->i2c)) { + if (p_obj->tx_buff.pos < p_obj->tx_buff.length) { + I2C_write_data(&p_obj->i2c, (uint32_t)p_obj->tx_buff.p_buffer[p_obj->tx_buff.pos++]); + } else { + /* dummy, wait nack */ + I2C_write_data(&p_obj->i2c, 0); + } + } else { + /* error event not be set */ + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } else { + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + if (!start) { + p_obj->rx_buff.p_buffer[p_obj->rx_buff.pos++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + } + if (p_obj->rx_buff.pos < p_obj->rx_buff.length) { + I2C_set_ack(&p_obj->i2c, ((p_obj->rx_buff.pos < (p_obj->rx_buff.length - 1) ? 0 : 1))); + I2C_write_data(&p_obj->i2c, 0); + } else { + p_obj->info.asynch.event = I2C_EVENT_TRANSFER_COMPLETE; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + } + } + } + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + reset_asynch(p_obj); + I2C_slave_init(&p_obj->i2c); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Enable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_enable_irq(_i2c_t *p_obj) +{ + enable_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Disable I2C IRQ + * @param p_obj :i2c object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void i2c_disable_irq(_i2c_t *p_obj) +{ + disable_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UTILITIES_Exported_functions + * @{ + */ + +/*--------------------------------------------------*/ +/** + * @brief Reset I2C peripheral + * @param p_obj :i2c object. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_reset_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + /* Software reset */ + I2C_reset(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure the I2C frequency + * @param p_obj :i2c object. + * @param hz :frequency in Hz. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_frequency_t(_i2c_t *p_obj, int32_t hz) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_port_high(&p_obj->i2c)) { + uint32_t fval; + + SystemCoreClockUpdate(); + + fval = I2C_get_clock_setting(&p_obj->i2c, (uint32_t)hz, SystemCoreClock, &p_obj->i2c.init.clock); + if (fval != 0) { + //I2C_init(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + p_obj->info.asynch.address = 0; + p_obj->info.asynch.stop = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + p_obj->info.asynch.event = 0; + p_obj->tx_buff.p_buffer = I2C_NULL; + p_obj->tx_buff.length = 0; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = I2C_NULL; + p_obj->rx_buff.length = 0; + p_obj->rx_buff.pos = 0; + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check bus free on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_check_bus_free_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.bus_free = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a start condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure.(now, not use) + * @note Start condition is not generate yet, after this function returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_start_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + p_obj->info.start = 1; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Creates a stop condition on the I2C bus. + * @param p_obj :i2c object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_stop_t(_i2c_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_stop_condition(&p_obj->i2c); + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + result = TXZ_ERROR; + break; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Address of Read data. + * @param length :Number of the bytes to read. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of read bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_read_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (length > 0) { + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, (int32_t)((uint32_t)address | 1U)); + if (result == I2C_ACK) { + /* Read all bytes */ + while (count < length) { + int32_t data = i2c_byte_read_t(p_obj, ((count < (length - 1)) ? 0 : 1)); + if (data < 0) { + result = data; + break; + } + p_data[count++] = (uint8_t)data; + } + result = count; + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1) ;//I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data + * @param p_obj :i2c object. + * @param address :Slave address(7-bit) and last bit is 0. + * @param p_data :Destination address of Write data. + * @param length :Number of the bytes to write. + * @param stop :Stop to be generated after the transfer is done. + * @retval Number of write bytes. + * @note Master and blocking function. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_write_t(_i2c_t *p_obj, int32_t address, uint8_t *p_data, int32_t length, int32_t stop) +{ + int32_t result = 0; + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + /* Start Condition */ + if (i2c_start_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + result = i2c_byte_write_t(p_obj, address); + if (result == I2C_ACK) { + /* Write all bytes */ + while (count < length) { + int32_t data = i2c_byte_write_t(p_obj, (int32_t)p_data[count++]); + if (data < I2C_ACK) { + result = data; + break; + } + } + if (result >= 0) { + result = count; + } + } else if (result == I2C_ERROR_ARBITRATION) { + } else if (result == (-2)) { //I2C_ERROR_BUS_BUSY + } else { + stop = 1; + result = (-1); //I2C_ERROR_NO_SLAVE; + } + /* Stop Condition */ + if (stop) { + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Read one byte + * @param p_obj :i2c object. + * @param last :last acknowledge. + * @retval The read byte (but -1 is timout error). + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_read_t(_i2c_t *p_obj, int32_t last) +{ + int32_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, last); + I2C_write_data(&p_obj->i2c, 0); + result = wait_status(p_obj); + if (result < 0) { + // result = -1; + } else { + result = (int32_t)I2C_read_data(&p_obj->i2c); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Write one byte + * @param p_obj :i2c object. + * @param data :Write data. + * @retval 0 :NACK was received. + * @retval 1 :ACK was received. + * @retval -1 :Timout error. + * @note Macro definition of return values is @ref I2C_ACK. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_byte_write_t(_i2c_t *p_obj, int32_t data) +{ + int32_t result; + int32_t timeout; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + I2C_clear_int_status(&p_obj->i2c); + if (p_obj->info.start == 1) { + p_obj->info.start = 0; + if (p_obj->info.bus_free == 1) { + timeout = I2C_TIMEOUT; + while (i2c_active_t(p_obj)) { + if ((timeout--) == 0) { + p_obj->info.bus_free = 0; + return (-1); + } + } + } + /* Start Condition */ + I2C_start_condition(&p_obj->i2c, (uint32_t)data); + if ((p_obj->info.bus_free == 1) && (!I2C_master(&p_obj->i2c))) { + p_obj->i2c.p_instance->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR); + p_obj->info.bus_free = 0; + if (I2C_status_arbitration(&p_obj->i2c)) { + return (-5); + } + return (-2); + } + } else { + I2C_write_data(&p_obj->i2c, (uint32_t)data); + } + p_obj->info.bus_free = 0; + result = wait_status(p_obj); + if (result < 0) { + return (result); + } + if (!I2C_get_ack(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Attempts to determine if the I2C bus is already in use + * @param p_obj :i2c object. + * @retval 0 :Non-active. + * @retval 1 :Active. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +uint8_t i2c_active_t(_i2c_t *p_obj) +{ + uint8_t result; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_status_busy(&p_obj->i2c)) { + result = 1; + } else { + result = 0; + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @param address :Slave address(7-bit) and last bit is 0. + * @param stop :Stop to be generated after the transfer is done. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Master and non-blocking function. + * @note Events of this function will be notified on i2c_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length, int32_t address, int32_t stop) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address(address)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = (uint32_t)address; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = (uint32_t)stop; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + if ((tx_length == 0) && (rx_length != 0)) { + I2C_start_condition(&p_obj->i2c, (uint32_t)((uint32_t)address | 1U)); + } else { + I2C_start_condition(&p_obj->i2c, (uint32_t)address); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note After error event occurred on i2c_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + if (i2c_stop_t(p_obj) == TXZ_SUCCESS) { + /* no processing */ + } + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C as slave or master. + * @param p_obj :i2c object. + * @param enable_slave :Enable slave mode. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_mode_t(_i2c_t *p_obj, int32_t enable_slave) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + disable_irq(p_obj->info.irqn); + + if (enable_slave) { + I2C_slave_init(&p_obj->i2c); + } else { + /* Slave Disable Settings. */ + i2c_reset_t(p_obj); + I2C_init(&p_obj->i2c); + } + p_obj->info.bus_free = 0; + p_obj->info.start = 0; + I2C_clear_int_status(&p_obj->i2c); +} + +/*--------------------------------------------------*/ +/** + * @brief Check to see if the I2C slave has been addressed. + * @param p_obj :i2c object. + * @retval I2C_NO_DATA :The slave has not been addressed. + * @retval I2C_READ_ADDRESSED :Read addresses. + * @retval I2C_WRITE_GENERAL :Write to all slaves(now, not support). + * @retval I2C_WRITE_ADDRESSED :Write addressed. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_receive_t(_i2c_t *p_obj) +{ + int32_t result = I2C_NO_DATA; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (I2C_slave_detected(&p_obj->i2c)) { + uint32_t sa = I2C_read_data(&p_obj->i2c); + + if (!I2C_transmitter(&p_obj->i2c)) { + result = I2C_WRITE_ADDRESSED; + } else { + result = I2C_READ_ADDRESSED; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking reading data. + * @param p_obj :i2c object. + * @param p_data :Destination address of read data. + * @param length :Number of bytes to read. + * @retval Number of read bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_read_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Read all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_set_ack(&p_obj->i2c, ((count < (length - 1)) ? 0 : 1)); + I2C_write_data(&p_obj->i2c, 0); + if (wait_status(p_obj) < 0) { + break; + } + if (I2C_slave_detected(&p_obj->i2c)) { + return (count); + } + p_data[count++] = (uint8_t)I2C_read_data(&p_obj->i2c); + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Blocking sending data. + * @param p_obj :i2c object. + * @param p_data :Source address of write data. + * @param length :Number of bytes to write. + * @retval Number of written bytes. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +int32_t i2c_slave_write_t(_i2c_t *p_obj, uint8_t *p_data, int32_t length) +{ + int32_t count = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_data)); +#endif /* #ifdef DEBUG */ + + /* Write all bytes */ + while (count < length) { + I2C_clear_int_status(&p_obj->i2c); + I2C_write_data(&p_obj->i2c, (uint32_t)p_data[count++]); + if (wait_status(p_obj) < 0) { + break; + } + if (!I2C_get_ack(&p_obj->i2c)) { + /* continue */ + } else { + break; + } + } + I2C_slave_init(&p_obj->i2c); + return (count); +} + +/*--------------------------------------------------*/ +/** + * @brief Configure I2C slave address. + * @param p_obj :i2c object. + * @param address :Address to be set. + * @retval - + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_address_t(_i2c_t *p_obj, uint32_t address) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(check_param_address((int32_t)address)); +#endif /* #ifdef DEBUG */ + + I2C_set_address(&p_obj->i2c, address); +} + + +/*--------------------------------------------------*/ +/** + * @brief Start I2C asynchronous transfer + * @param p_obj :i2c object. + * @param p_tx :Buffer of write data. + * @param tx_length :Length of write data. + * @param p_rx :Buffer of read data. + * @param rx_length :Length of read data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Slave and non-blocking function. + * @note Events of this function will be notified on i2c_slave_irq_handler_asynch_t. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result i2c_slave_transfer_asynch_t(_i2c_t *p_obj, uint8_t *p_tx, int32_t tx_length, uint8_t *p_rx, int32_t rx_length) +{ + TXZ_Result result = TXZ_ERROR; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + if (p_obj->info.asynch.state == I2C_TRANSFER_STATE_IDLE) { + if (((p_tx != I2C_NULL) && (tx_length > 0)) || ((p_rx != I2C_NULL) && (rx_length > 0))) { + reset_asynch(p_obj); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); + p_obj->info.asynch.address = 0; + p_obj->info.asynch.event = 0; + p_obj->info.asynch.stop = 0; + p_obj->tx_buff.p_buffer = p_tx; + p_obj->tx_buff.length = (uint32_t)tx_length; + p_obj->tx_buff.pos = 0; + p_obj->rx_buff.p_buffer = p_rx; + p_obj->rx_buff.length = (uint32_t)rx_length; + p_obj->rx_buff.pos = 0; + p_obj->info.asynch.state = I2C_TRANSFER_STATE_BUSY; + I2C_enable_interrupt(&p_obj->i2c); + enable_irq(p_obj->info.irqn); + result = TXZ_SUCCESS; + } + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief The asynchronous IRQ handler + * @param p_obj :i2c object. + * @retval zero :Transfer in progress. + * @retval non-zero :Event information. + * @note Macro definition of return values is @ref I2C_Events. + * @attention This function should be implement as INTI2Cx_IRQHandler. + */ +/*--------------------------------------------------*/ +uint32_t i2c_slave_irq_handler_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + i2c_slave_irq_handler(p_obj); + + return (p_obj->info.asynch.event & I2C_EVENT_ALL); +} + +/*--------------------------------------------------*/ +/** + * @brief Abort asynchronous transfer + * @param p_obj :i2c object. + * @retval - + * @note For a non-blocking function. + * @note After error event occurred on i2c_slave_irq_handler_asynch_t, + * @note call this function and clear error status. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void i2c_slave_abort_asynch_t(_i2c_t *p_obj) +{ + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif /* #ifdef DEBUG */ + + reset_asynch(p_obj); + p_obj->info.asynch.state = I2C_TRANSFER_STATE_IDLE; + I2C_slave_init(&p_obj->i2c); + I2C_clear_int_status(&p_obj->i2c); + clear_irq(p_obj->info.irqn); +} + +/** + * @} + */ /* End of group UTILITIES_Exported_functions */ + +/** + * @} + */ /* End of group UTILITIES */ + +/** + * @} + */ /* End of group Example */ + +#endif /* defined(__I2C_API_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_t32a.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_t32a.c new file mode 100644 index 00000000000..2cd5fd8c0f0 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_t32a.c @@ -0,0 +1,2004 @@ +/** + ******************************************************************************* + * @file txzp_t32a.c + * @brief This file provides API functions for T32A driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_t32a.h" + +#if defined(__T32A_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup T32A + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ +/** + * @} + */ /* End of group T32A_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_define T32A Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_typedef T32A Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Member */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Private_member T32A Private Member + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group T32A_Private_member */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup T32A_Private_fuctions TSPI Private Fuctions + * @{ + */ +#ifdef DEBUG +__INLINE static int32_t check_param_mode_halt(uint32_t param); +__INLINE static int32_t check_param_mode_mode32(uint32_t param); +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param); +__INLINE static int32_t check_param_runx_sftstax(uint32_t param); +__INLINE static int32_t check_param_runx_runx(uint32_t param); +__INLINE static int32_t check_param_crx_prsclx(uint32_t param); +__INLINE static int32_t check_param_crx_clkx(uint32_t param); +__INLINE static int32_t check_param_crx_wbfx(uint32_t param); +__INLINE static int32_t check_param_crx_updnx(uint32_t param); +__INLINE static int32_t check_param_crx_reldx(uint32_t param); +__INLINE static int32_t check_param_crx_stopx(uint32_t param); +__INLINE static int32_t check_param_crx_startx(uint32_t param); +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param); +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param); +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param); +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param); +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param); +__INLINE static int32_t check_param_reldx_reld(uint32_t param); +__INLINE static int32_t check_param_imx_imsterr(uint32_t param); +__INLINE static int32_t check_param_imx_imufx(uint32_t param); +__INLINE static int32_t check_param_imx_imofx(uint32_t param); +__INLINE static int32_t check_param_imx_imx1(uint32_t param); +__INLINE static int32_t check_param_imx_imx0(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param); +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param); +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param); +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param); +#endif + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Mode HALT's parameter. + * @param param :Mode HALT's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_HALT + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_halt(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DBG_HALT_RUN: + case T32A_DBG_HALT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Mode mode32's parameter. + * @param param :Mode mode32's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_MODE32 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_mode_mode32(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_MODE_16: + case T32A_MODE_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW Counter STOP Control's parameter. + * @param param :SW Counter STOP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstpx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_STOP: + case T32A_COUNT_STOP: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the SW START Control's parameter. + * @param param :SW START Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_SFTSTAx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_sftstax(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_DONT_START: + case T32A_COUNT_START: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A RUN Disable/Enable Control's parameter. + * @param param :T32A RUN Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_runx_runx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RUN_DISABLE: + case T32A_RUN_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PRSCLx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_prsclx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PRSCLx_1: + case T32A_PRSCLx_2: + case T32A_PRSCLx_8: + case T32A_PRSCLx_32: + case T32A_PRSCLx_128: + case T32A_PRSCLx_256: + case T32A_PRSCLx_512: + case T32A_PRSCLx_1024: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A PRESCALER Control's parameter. + * @param param :T32A PRESCALER Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CLKx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_clkx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CLKx_PRSCLx: + case T32A_CLKx_INTRG: + case T32A_CLKx_TIM_RISING_EDGE: + case T32A_CLKx_TIM_TRAILING_EDGE: + case T32A_CLKx_EXTTRG_RISING_EDGE: + case T32A_CLKx_EXTTRG_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Double Buffer Disable/Enable Control's parameter. + * @param param :Double Buffer Disable/Enable Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_WBFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_wbfx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_WBF_DISABLE: + case T32A_WBF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Up/Down Control's parameter. + * @param param :T32A Counter Up/Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_UPDNx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_updnx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_COUNT_UP: + case T32A_COUNT_DOWN: + case T32A_COUNT_UPDOWN: + case T32A_COUNT_PLS: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Control's parameter. + * @param param :T32A Counter Reload Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELDx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_reldx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_RELOAD_NON: + case T32A_RELOAD_INTRG: + case T32A_RELOAD_EXTTRG_RISING_EDGE: + case T32A_RELOAD_EXTTRG_TRAILING_EDGE: + case T32A_RELOAD_TIM_RISING_EDGE: + case T32A_RELOAD_TIM_TRAILING_EDGE: + case T32A_RELOAD_SYNC: + case T32A_RELOAD_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Stop Control's parameter. + * @param param :T32A Counter Stop Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STOPx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_stopx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_STOP_NON: + case T32A_STOP_INTRG: + case T32A_STOP_EXTTRG_RISING_EDGE: + case T32A_STOP_EXTTRG_TRAILING_EDGE: + case T32A_STOP_TIM_RISING_EDGE: + case T32A_STOP_TIM_TRAILING_EDGE: + case T32A_STOP_SYNC: + case T32A_STOP_TREGx: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Start Control's parameter. + * @param param :T32A Counter Start Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_STARTx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_crx_startx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_START_NON: + case T32A_START_INTRG: + case T32A_START_EXTTRG_RISING_EDGE: + case T32A_START_EXTTRG_TRAILING_EDGE: + case T32A_START_TIM_RISING_EDGE: + case T32A_START_TIM_TRAILING_EDGE: + case T32A_START_SYNC: + result = PARAM_OK; + break; + case T32A_START_Rsvd: + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control's parameter. + * @param param :T32AxOUTA Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx0_ocrx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCR_DISABLE: + case T32A_OCR_SET: + case T32A_OCR_CLR: + case T32A_OCR_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx1 T32AxRGx1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx1_DISABLE: + case T32A_OCRCAPx1_SET: + case T32A_OCRCAPx1_CLR: + case T32A_OCRCAPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter. + * @param param :T32AxOUTA Control of T32AxCAPx0 T32AxRGx0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCAPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcapx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCAPx0_DISABLE: + case T32A_OCRCAPx0_SET: + case T32A_OCRCAPx0_CLR: + case T32A_OCRCAPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx1_DISABLE: + case T32A_OCRCMPx1_SET: + case T32A_OCRCMPx1_CLR: + case T32A_OCRCMPx1_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32AxOUTA Control of T32AxRGx1 Counter Value's parameter. + * @param param :T32AxOUTA Control of T32AxRGx1 Counter Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_OCRCMPx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_outcrx1_ocrcmpx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_OCRCMPx0_DISABLE: + case T32A_OCRCMPx0_SET: + case T32A_OCRCMPx0_CLR: + case T32A_OCRCMPx0_INVERSION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A1's parameter. + * @param param :T32A Capture Control Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx1_DISABLE: + case T32A_CAPMx1_INTRG: + case T32A_CAPMx1_INx0_RISING_EDGE: + case T32A_CAPMx1_INx0_TRAILING_EDGE: + case T32A_CAPMx1_INx1_RISING_EDGE: + case T32A_CAPMx1_INx1_TRAILING_EDGE: + case T32A_CAPMx1_TIM_RISING_EDGE: + case T32A_CAPMx1_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Capture Control Register A0's parameter. + * @param param :T32A Capture Control Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_CAPMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_capcrx_capmx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_CAPMx0_DISABLE: + case T32A_CAPMx0_INTRG: + case T32A_CAPMx0_INx0_RISING_EDGE: + case T32A_CAPMx0_INx0_TRAILING_EDGE: + case T32A_CAPMx0_INx1_RISING_EDGE: + case T32A_CAPMx0_INx1_TRAILING_EDGE: + case T32A_CAPMx0_TIM_RISING_EDGE: + case T32A_CAPMx0_TIM_TRAILING_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A0's parameter. + * @param param :T32A Timer Register A0's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx0_rgx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx0_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Timer Register A1's parameter. + * @param param :T32A Timer Register A1's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RGx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rgx1_rgx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RGx1_MASK) { + result = PARAM_OK; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Counter Reload Register A's parameter. + * @param param :T32A Counter Reload Register A's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_RELD + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_reldx_reld(uint32_t param) +{ + int32_t result = PARAM_NG; + + if (param <= T32A_RELDx_MASK) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Statuserr Interrupt Request MASK's parameter. + * @param param :T32A Statuserr Interrupt Request MASK's parameter. + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMSTEER + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imsterr(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMSTERR_MASK_NOREQ: + case T32A_IMSTERR_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMUFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imufx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Overflow Interrupt Request MASK's parameter. + * @param param :T32A Overflow Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMOFx + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imofx(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMOFx_MASK_NOREQ: + case T32A_IMOFx_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx1 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx1_MASK_NOREQ: + case T32A_IMx1_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter. + * @param param :T32A Match Up T32AxRGx0 Interrupt Request MASK's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_IMx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_imx_imx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_IMx0_MASK_NOREQ: + case T32A_IMx0_MASK_REQ: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA Converter1 Request control's parameter. + * @param param :T32A DMA Converter1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx2 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx2(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx2_DISABLE: + case T32A_DMAENx2_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture1 Request control's parameter. + * @param param :T32A DMA InputCapture1 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx1 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx1(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx1_DISABLE: + case T32A_DMAENx1_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A DMA InputCapture0 Request control's parameter. + * @param param :T32A DMA InputCapture0 Request control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_DMAENx0 + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_dma_req_dmaenx0(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_DMAENx0_DISABLE: + case T32A_DMAENx0_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count Down Control's parameter. + * @param param :T32A Pulse Mode Count Down Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDN + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdn(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDN_NON0: + case T32A_PDN_NON1: + case T32A_PDN_INC0_RISING_EDGE: + case T32A_PDN_INC0_TRAILING_EDGE: + case T32A_PDN_INC1_RISING_EDGE: + case T32A_PDN_INC1_TRAILING_EDGE: + case T32A_PDN_INC0_BOTH_EDGE: + case T32A_PDN_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Mode Count UP Control's parameter. + * @param param :T32A Pulse Mode Count UP Control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PUP + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pup(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PUP_NON0: + case T32A_PUP_NON1: + case T32A_PUP_INC0_RISING_EDGE: + case T32A_PUP_INC0_TRAILING_EDGE: + case T32A_PUP_INC1_RISING_EDGE: + case T32A_PUP_INC1_TRAILING_EDGE: + case T32A_PUP_INC0_BOTH_EDGE: + case T32A_PUP_INC1_BOTH_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Noise Filter control's parameter. + * @param param :T32A Noise Filter control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_NF + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_nf(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_NF_NON: + case T32A_NF_2: + case T32A_NF_4: + case T32A_NF_8: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Phase 2 Pulse Direction control's parameter. + * @param param :T32A Phase 2 Pulse Direction control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PDIR + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pdir(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PDIR_FORWARD: + case T32A_PDIR_BACKWARD: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the T32A Pulse Count Mode control's parameter. + * @param param :T32A Pulse Count Mode control's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref T32A_PMODE + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_pls_cr_pmode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case T32A_PMODE_PHASE_2: + case T32A_PMODE_PHASE_1: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + + + +#endif +/** + * @} + */ /* End of group T32A_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup T32A_Exported_functions + + */ +/*--------------------------------------------------*/ +/** + * @brief Mode Initialize the T32A object. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_mode_init(t32a_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); +#endif /* DEBUG */ + /* Timer Mode Set */ + p_obj->p_instance->MOD = 0; + p_obj->p_instance->MOD = (p_obj->init_mode.mode.halt | p_obj->init_mode.mode.mode); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Initialize the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_init(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + /* Check the parameter of TimerA Mode Set */ + check_param_mode_halt(p_obj->init_mode.mode.halt); + check_param_mode_mode32(p_obj->init_mode.mode.mode); + /* Check the parameter of TimerA Run Control Set */ + check_param_runx_sftstpx(p_obj->init[type].runx.sftstp); + check_param_runx_sftstax(p_obj->init[type].runx.sftsta); + check_param_runx_runx(p_obj->init[type].runx.run); + /* Check the parameter of Counter Register Control Set */ + check_param_crx_prsclx(p_obj->init[type].crx.prscl); + check_param_crx_clkx(p_obj->init[type].crx.clk); + check_param_crx_wbfx(p_obj->init[type].crx.wbf); + check_param_crx_updnx(p_obj->init[type].crx.updn); + check_param_crx_reldx(p_obj->init[type].crx.reld); + check_param_crx_stopx(p_obj->init[type].crx.stop); + check_param_crx_startx(p_obj->init[type].crx.start); + /* Check the parameter of TimerA Output Control Set */ + check_param_outcrx0_ocrx(p_obj->init[type].outcrx0.ocr); + /* Check the parameter of T32AxOUTA Control Set */ + check_param_outcrx1_ocrcapx1(p_obj->init[type].outcrx1.ocrcap1); + check_param_outcrx1_ocrcapx0(p_obj->init[type].outcrx1.ocrcap0); + check_param_outcrx1_ocrcmpx1(p_obj->init[type].outcrx1.ocrcmp1); + check_param_outcrx1_ocrcmpx0(p_obj->init[type].outcrx1.ocrcmp0); + /* Check the parameter of Capture Control Set */ + check_param_capcrx_capmx1(p_obj->init[type].capcrx.capmx1); + check_param_capcrx_capmx0(p_obj->init[type].capcrx.capmx0); + /* Check the parameter of T32A Timer Register 0 Set */ + check_param_rgx0_rgx0(p_obj->init[type].rgx0.rgx0); + /* Check the parameter of T32A Timer Register 1 Set */ + check_param_rgx1_rgx1(p_obj->init[type].rgx1.rgx1); + /* Check the parameter of T32A Counter Reload Register Set */ + check_param_reldx_reld(p_obj->init[type].reldx.reld); + /* Check the parameter of Interrupt mask register Set */ + check_param_imx_imsterr(p_obj->init[type].imx.imsterr); + check_param_imx_imufx(p_obj->init[type].imx.imuf); + check_param_imx_imofx(p_obj->init[type].imx.imof); + check_param_imx_imx1(p_obj->init[type].imx.imx1); + check_param_imx_imx0(p_obj->init[type].imx.imx0); + /* Check the parameter of DMA Request register Set */ + check_param_dma_req_dmaenx2(p_obj->init[type].dma_req.dmaenx2); + check_param_dma_req_dmaenx1(p_obj->init[type].dma_req.dmaenx1); + check_param_dma_req_dmaenx0(p_obj->init[type].dma_req.dmaenx0); +#endif + + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerA Run Control Disable */ + p_obj->p_instance->RUNA = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRA = 0; + p_obj->p_instance->CRA = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerA Output Control Set */ + p_obj->p_instance->OUTCRA0 = 0; + p_obj->p_instance->OUTCRA0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTA Control Set */ + p_obj->p_instance->OUTCRA1 = 0; + p_obj->p_instance->OUTCRA1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register A0 Set */ + p_obj->p_instance->RGA0 = 0; + p_obj->p_instance->RGA0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register A1 Set */ + p_obj->p_instance->RGA1 = 0; + p_obj->p_instance->RGA1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDA = 0; + p_obj->p_instance->RELDA = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRA = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMA = 0; + p_obj->p_instance->IMA = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAA = 0; + p_obj->p_instance->DMAA = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerA Run Control Set */ + p_obj->p_instance->RUNA = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERB: + /* Timer B */ + if (p_obj->init_mode.mode.mode != T32A_MODE_16) { + result = TXZ_ERROR; + return (result); + } + /* TimerB Run Control Disable */ + p_obj->p_instance->RUNB = 0; + /* Counter Register Control Set */ + p_obj->p_instance->CRB = 0; + p_obj->p_instance->CRB = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerB Output Control Set */ + p_obj->p_instance->OUTCRB0 = 0; + p_obj->p_instance->OUTCRB0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTB Control Set */ + p_obj->p_instance->OUTCRB1 = 0; + p_obj->p_instance->OUTCRB1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register B0 Set */ + p_obj->p_instance->RGB0 = 0; + p_obj->p_instance->RGB0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register B1 Set */ + p_obj->p_instance->RGB1 = 0; + p_obj->p_instance->RGB1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDB = 0; + p_obj->p_instance->RELDB = p_obj->init[type].reldx.reld; + /* TimerB Capture Control Set */ + p_obj->p_instance->CAPCRB = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMB = 0; + p_obj->p_instance->IMB = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAB = 0; + p_obj->p_instance->DMAB = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* TimerB Run Control Set */ + p_obj->p_instance->RUNB = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + case T32A_TIMERC: + /* Timer C */ + if (p_obj->init_mode.mode.mode != T32A_MODE_32) { + result = TXZ_ERROR; + return (result); + } + /* TimerC Run Control Disable */ + p_obj->p_instance->RUNC = 0; +#ifdef DEBUG + /* Pulse Count Control register Set */ + check_param_pls_cr_pdn(p_obj->init[type].pls_cr.pdn); + check_param_pls_cr_pup(p_obj->init[type].pls_cr.pup); + check_param_pls_cr_nf(p_obj->init[type].pls_cr.nf); + check_param_pls_cr_pdir(p_obj->init[type].pls_cr.pdir); + check_param_pls_cr_pmode(p_obj->init[type].pls_cr.pmode); +#endif + /* Counter Register Control Set */ + p_obj->p_instance->CRC = 0; + p_obj->p_instance->CRC = (p_obj->init[type].crx.prscl | p_obj->init[type].crx.clk | p_obj->init[type].crx.wbf | p_obj->init[type].crx.updn | \ + p_obj->init[type].crx.reld | p_obj->init[type].crx.stop | p_obj->init[type].crx.start); + /* TimerC Output Control Set */ + p_obj->p_instance->OUTCRC0 = 0; + p_obj->p_instance->OUTCRC0 = p_obj->init[type].outcrx0.ocr; + /* T32AxOUTC Control Set */ + p_obj->p_instance->OUTCRC1 = 0; + p_obj->p_instance->OUTCRC1 = (p_obj->init[type].outcrx1.ocrcap1 | p_obj->init[type].outcrx1.ocrcap0 | p_obj->init[type].outcrx1.ocrcmp1 | \ + p_obj->init[type].outcrx1.ocrcmp0); + /* T32A Timer Register C0 Set */ + p_obj->p_instance->RGC0 = 0; + p_obj->p_instance->RGC0 = p_obj->init[type].rgx0.rgx0; + /* T32A Timer Register C1 Set */ + p_obj->p_instance->RGC1 = 0; + p_obj->p_instance->RGC1 = p_obj->init[type].rgx1.rgx1; + /* T32A Counter Reload Register Set */ + p_obj->p_instance->RELDC = 0; + p_obj->p_instance->RELDC = p_obj->init[type].reldx.reld; + /* TimerC Capture Control Set */ + p_obj->p_instance->CAPCRC = (p_obj->init[type].capcrx.capmx0 | p_obj->init[type].capcrx.capmx1); + /* Interrupt mask register Set */ + p_obj->p_instance->IMC = 0; + p_obj->p_instance->IMC = (p_obj->init[type].imx.imuf | p_obj->init[type].imx.imof | p_obj->init[type].imx.imx1 | \ + p_obj->init[type].imx.imx0); + /* DMA Request register Set */ + p_obj->p_instance->DMAC = 0; + p_obj->p_instance->DMAC = (p_obj->init[type].dma_req.dmaenx2 | p_obj->init[type].dma_req.dmaenx1 | p_obj->init[type].dma_req.dmaenx0); + /* Pulse Count Control register Set */ + p_obj->p_instance->PLSCR = 0; + p_obj->p_instance->PLSCR = (p_obj->init[type].pls_cr.pdn | p_obj->init[type].pls_cr.pup | p_obj->init[type].pls_cr.nf | \ + p_obj->init[type].pls_cr.pdir | p_obj->init[type].pls_cr.pmode); + /* TimerC Run Control Set */ + p_obj->p_instance->RUNC = (p_obj->init[type].runx.sftstp | p_obj->init[type].runx.sftsta | p_obj->init[type].runx.run); + break; + default: + result = TXZ_ERROR; + return (result); + } + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the T32A object. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_deinit(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* Timer C */ + /* Disable the selected T32A peripheral */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_startIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A RUN */ + p_obj->p_instance->RUNA |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer B RUN */ + p_obj->p_instance->RUNB |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C RUN */ + p_obj->p_instance->RUNC |= T32A_RUN_ENABLE; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_timer_stopIT(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A Stop */ + p_obj->p_instance->RUNA = T32A_RUN_DISABLE; + break; + case T32A_TIMERB: + /* Timer B Stop */ + p_obj->p_instance->RUNB = T32A_RUN_DISABLE; + break; + case T32A_TIMERC: + /* SW Counter Stop & Timer C Stop */ + p_obj->p_instance->RUNC = T32A_RUN_DISABLE; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Start in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_start(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + if (((p_obj->p_instance->RUNA) & T32A_RUNFLG_RUN) == 0) { + /* Timer A SW Counter start */ + p_obj->p_instance->RUNA |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERB: + if (((p_obj->p_instance->RUNB) & T32A_RUNFLG_RUN) == 0) { + /* Timer SW Counter start */ + p_obj->p_instance->RUNB |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + case T32A_TIMERC: + if (((p_obj->p_instance->RUNC) & T32A_RUNFLG_RUN) == 0) { + /* Timer C SW Counter start */ + p_obj->p_instance->RUNC |= T32A_COUNT_START; + } else { + result = TXZ_ERROR; + return (result); + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Stop in interrupt mode. + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_SWcounter_stop(t32a_t *p_obj, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* TimerA SW Counter Stop */ + p_obj->p_instance->RUNA = T32A_COUNT_STOP; + break; + case T32A_TIMERB: + /* Timer B SW Counter Stop */ + p_obj->p_instance->RUNB = T32A_COUNT_STOP; + break; + case T32A_TIMERC: + /* Timer C SW Counter Stop */ + p_obj->p_instance->RUNC = T32A_COUNT_STOP; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Setting + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param num :T32A Register Number. : Use @ref t32_regnum_t + * @param value :Setting Value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_reg_set(t32a_t *p_obj, uint32_t type, uint32_t num, uint32_t value) +{ + TXZ_Result result = TXZ_SUCCESS; +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + switch (type) { + case T32A_TIMERA: + /* Timer A */ + if (num == T32A_REG0) { + p_obj->p_instance->RGA0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGA1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDA = value; + } + break; + case T32A_TIMERB: + /* Timer B */ + if (num == T32A_REG0) { + p_obj->p_instance->RGB0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGB1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDB = value; + } + break; + case T32A_TIMERC: + /* Timer C */ + if (num == T32A_REG0) { + p_obj->p_instance->RGC0 = value; + } else if (num == T32A_REG1) { + p_obj->p_instance->RGC1 = value; + } else if (num == T32A_RELOAD) { + p_obj->p_instance->RELDC = value; + } + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Timer Register Value Read + * @param p_obj :T32A object. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @param p_val :Save area for register value. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_tmr_read(t32a_t *p_obj, uint32_t type, uint32_t *p_val) +{ + TXZ_Result result = TXZ_SUCCESS; + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_val = p_obj->p_instance->TMRA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_val = p_obj->p_instance->TMRB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_val = p_obj->p_instance->TMRC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-4 | - | - | + * | 3 | INTUFA | Under Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 2 | INTOFA | Over Flow Intterrupt. Use @ref T32A_INTOFx_FLG_MASK. | + * | 1 | INTx1 | Match up TimerRegister x1 Intterrupt. Use @ref T32A_INTx1_FLG_MASK. | + * | 0 | INTx0 | Match up TimerRegister x0 Intterrupt. Use @ref T32A_INTx0_FLG_MASK. | + * + * @param p_obj :T32A object. + * @param p_status :Save area for status. + * @param type :T32A Timer Type. : Use @ref t32_type_t + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_get_status(t32a_t *p_obj, uint32_t *p_status, uint32_t type) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + switch (type) { + case T32A_TIMERA: + /* Timer A */ + *p_status = p_obj->p_instance->STA; + break; + case T32A_TIMERB: + /* Timer B */ + *p_status = p_obj->p_instance->STB; + break; + case T32A_TIMERC: + /* Timer C */ + *p_status = p_obj->p_instance->STC; + break; + default: + result = TXZ_ERROR; + return (result); + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for Timer interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_T(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_T(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_T != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_T(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture0 Handler for Timer Capture0 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap0_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC0(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC0(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC0 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC0(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Timer Capture1 Handler for Timer Capture1 interrupt. + * @param p_obj :T32A object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note An initial value of default is set at the + reset status value. If needed, please + rewrite and use an initial value. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +void t32a_timer_cap1_IRQHandler(t32a_t *p_obj) +{ + uint32_t status_a, status_b, status_c; + /*------------------------------*/ + /* Get Status */ + /*------------------------------*/ + (void)t32a_get_status(p_obj, &status_a, T32A_TIMERA); + (void)t32a_get_status(p_obj, &status_b, T32A_TIMERB); + (void)t32a_get_status(p_obj, &status_c, T32A_TIMERC); + + if (status_a != 0) { + /*------------------------------*/ + /* Call Handler Timer A */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERA].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERA].handler_TC1(p_obj->init[T32A_TIMERA].id, status_a, TXZ_SUCCESS); + } + } + if (status_b != 0) { + /*------------------------------*/ + /* Call Handler Timer B */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERB].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERB].handler_TC1(p_obj->init[T32A_TIMERB].id, status_b, TXZ_SUCCESS); + } + } + if (status_c != 0) { + /*------------------------------*/ + /* Call Handler Timer C */ + /*------------------------------*/ + if (p_obj->init[T32A_TIMERC].handler_TC1 != T32A_NULL) { + /* Call the handler with Status Register Value & SUCCESS. */ + p_obj->init[T32A_TIMERC].handler_TC1(p_obj->init[T32A_TIMERC].id, status_c, TXZ_SUCCESS); + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Calculate timer value to set timer register. + * @param p_value: time value store pointer. + * @param time: The require period which the uint is us. + * @param prescaler: System Clock Freq + * @param prscl: Select the division for source clock @ref T32A_PRSCLx. + * @retval the value set to Tmrb timer register. + */ +/*--------------------------------------------------*/ +TXZ_Result t32a_Calculator(uint32_t *p_value, uint32_t time, uint32_t prescaler, uint32_t prscl) +{ + TXZ_Result result = TXZ_SUCCESS; + uint64_t denominator; + uint64_t numerator; + uint32_t div; + + /* div */ + switch (prscl) { + case T32A_PRSCLx_1: + div = 1; + break; + case T32A_PRSCLx_2: + div = 2; + break; + case T32A_PRSCLx_8: + div = 8; + break; + case T32A_PRSCLx_32: + div = 32; + break; + case T32A_PRSCLx_128: + div = 128; + break; + case T32A_PRSCLx_256: + div = 256; + break; + case T32A_PRSCLx_512: + div = 512; + break; + case T32A_PRSCLx_1024: + div = 1024; + break; + default: + div = 1; + break; + } + /*-----------------------------------------------*/ + /* "1"counter (s) = 1 / fs */ + /* "1"counter (s) = 1 / (prescaler / div) */ + /* "1"counter (us) = (10^6) / (prescaler / div) */ + /* "1"counter (us) = ((10^6) * div)/prescaler */ + /* "x"counter (us) = time */ + /*-----------------------------------------------*/ + /* x : time = 1 : ((10^6) * div)/prescaler */ + /*-----------------------------------------------*/ + /* x = time / (((10^6) * div)/prescaler) */ + /* = (prescaler * time) / ((10^6) * div) */ + /*-----------------------------------------------*/ + denominator = (uint64_t)((uint64_t)(prescaler) * (uint64_t)(time)); + numerator = (uint64_t)((uint64_t)(1000000) * (uint64_t)div); + denominator = (uint64_t)(denominator / numerator); + /* result */ + if ((denominator == (uint64_t)(0)) || (denominator > (uint64_t)(0xFFFF))) { + result = TXZ_ERROR; + } else { + *p_value = (uint32_t)denominator; + } + + return (result); +} + +/** + * @} + */ /* End of group T32A_Exported_functions */ + +/** + * @} + */ /* End of group T32A */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__T32A_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_tspi.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_tspi.c new file mode 100644 index 00000000000..63deabf5232 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_tspi.c @@ -0,0 +1,2645 @@ +/** + ******************************************************************************* + * @file txzp_tspi.c + * @brief This file provides API functions for TSPI driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_tspi.h" + +#if defined(__TSPI_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup TSPI + * @{ + */ + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ +/** + * @name TSPI NULL Pointer + * @brief Null Pointer for TSPI + * @{ + */ +#define TSPI_NULL ((void *)0) /*!< NULL pointer. */ +/** + * @} + */ /* End of name TSPI NULL Pointer */ + +/** + * @name Parameter Result + * @brief Whether the parameter is specified or not. + * @{ + */ +#define PARAM_OK ((int32_t)1) /*!< Parameter is valid(specified). */ +#define PARAM_NG ((int32_t)0) /*!< Parameter is invalid(not specified). */ +/** + * @} + */ /* End of name Parameter Result */ + +/** + * @name FIFO Max Num. + * @brief Transfer's/Receive's FIFO Max Num. + * @{ + */ +#define TRANSFER_FIFO_MAX_NUM ((uint32_t)8) /*!< Transfer's FIFO Max Num. */ +#define RECEIVE_FIFO_MAX_NUM ((uint32_t)8) /*!< Receive's FIFO Max Num. */ +/** + * @} + */ /* End of name FIFO Max Num */ + +/** + * @name TSPIxDR_MASK Macro Definition. + * @brief TSPIxDR_MASK Macro Definition. + * @{ + */ +/* DR */ +#define TSPI_DR_8BIT_MASK ((uint32_t)0x000000FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_9BIT_MASK ((uint32_t)0x000001FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_10BIT_MASK ((uint32_t)0x000003FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_11BIT_MASK ((uint32_t)0x000007FF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_12BIT_MASK ((uint32_t)0x00000FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_13BIT_MASK ((uint32_t)0x00001FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_14BIT_MASK ((uint32_t)0x00003FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_15BIT_MASK ((uint32_t)0x00007FFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_16BIT_MASK ((uint32_t)0x0000FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_17BIT_MASK ((uint32_t)0x0001FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_18BIT_MASK ((uint32_t)0x0003FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_19BIT_MASK ((uint32_t)0x0007FFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_20BIT_MASK ((uint32_t)0x000FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_21BIT_MASK ((uint32_t)0x001FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_22BIT_MASK ((uint32_t)0x003FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_23BIT_MASK ((uint32_t)0x007FFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_24BIT_MASK ((uint32_t)0x00FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_25BIT_MASK ((uint32_t)0x01FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_26BIT_MASK ((uint32_t)0x03FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_27BIT_MASK ((uint32_t)0x07FFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_28BIT_MASK ((uint32_t)0x0FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_29BIT_MASK ((uint32_t)0x1FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_30BIT_MASK ((uint32_t)0x3FFFFFFF) /*!< DR :Mask for 8bit */ +#define TSPI_DR_31BIT_MASK ((uint32_t)0x7FFFFFFF) /*!< DR :Mask for 8bit */ +/** + * @} + */ /* End of name TSPIxDR_MASK Macro Definition */ + +/** + * @name TSPI _DATA_LENGTH Macro Definition. + * @brief TSPI DATA LENGTH Macro Definition. + * @{ + */ +#define DATA_LENGTH_8 ((uint32_t)0x08) /*!< 8 bit */ +#define DATA_LENGTH_9 ((uint32_t)0x09) /*!< 9 bit */ +#define DATA_LENGTH_10 ((uint32_t)0x0a) /*!< 10 bit */ +#define DATA_LENGTH_11 ((uint32_t)0x0b) /*!< 11 bit */ +#define DATA_LENGTH_12 ((uint32_t)0x0c) /*!< 12 bit */ +#define DATA_LENGTH_13 ((uint32_t)0x0d) /*!< 13 bit */ +#define DATA_LENGTH_14 ((uint32_t)0x0e) /*!< 14 bit */ +#define DATA_LENGTH_15 ((uint32_t)0x0f) /*!< 15 bit */ +#define DATA_LENGTH_16 ((uint32_t)0x10) /*!< 16 bit */ +#define DATA_LENGTH_17 ((uint32_t)0x11) /*!< 17 bit */ +#define DATA_LENGTH_18 ((uint32_t)0x12) /*!< 18 bit */ +#define DATA_LENGTH_19 ((uint32_t)0x13) /*!< 19 bit */ +#define DATA_LENGTH_20 ((uint32_t)0x14) /*!< 20 bit */ +#define DATA_LENGTH_21 ((uint32_t)0x15) /*!< 21 bit */ +#define DATA_LENGTH_22 ((uint32_t)0x16) /*!< 22 bit */ +#define DATA_LENGTH_23 ((uint32_t)0x17) /*!< 23 bit */ +#define DATA_LENGTH_24 ((uint32_t)0x18) /*!< 24 bit */ +#define DATA_LENGTH_25 ((uint32_t)0x19) /*!< 25 bit */ +#define DATA_LENGTH_26 ((uint32_t)0x1a) /*!< 26 bit */ +#define DATA_LENGTH_27 ((uint32_t)0x1b) /*!< 27 bit */ +#define DATA_LENGTH_28 ((uint32_t)0x1c) /*!< 28 bit */ +#define DATA_LENGTH_29 ((uint32_t)0x1d) /*!< 29 bit */ +#define DATA_LENGTH_30 ((uint32_t)0x1e) /*!< 30 bit */ +#define DATA_LENGTH_31 ((uint32_t)0x1f) /*!< 31 bit */ +#define DATA_LENGTH_32 ((uint32_t)0x20) /*!< 32 bit */ +/** + * @} + */ /* End of name TSPI _DATA_LENGTH Macro Definition */ +/** + * @} + */ /* End of group TSPI_Private_typedef */ +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_define TSPI Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group TSPI_Private_define */ +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_typedef TSPI Private Typedef + * @{ + */ +/*----------------------------------*/ +/** + * @brief TSPI mask array. +*/ +/*----------------------------------*/ +static uint32_t mask[32] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + TSPI_DR_8BIT_MASK, + TSPI_DR_9BIT_MASK, + TSPI_DR_10BIT_MASK, + TSPI_DR_11BIT_MASK, + TSPI_DR_12BIT_MASK, + TSPI_DR_13BIT_MASK, + TSPI_DR_14BIT_MASK, + TSPI_DR_15BIT_MASK, + TSPI_DR_16BIT_MASK, + TSPI_DR_17BIT_MASK, + TSPI_DR_18BIT_MASK, + TSPI_DR_19BIT_MASK, + TSPI_DR_20BIT_MASK, + TSPI_DR_21BIT_MASK, + TSPI_DR_22BIT_MASK, + TSPI_DR_23BIT_MASK, + TSPI_DR_24BIT_MASK, + TSPI_DR_25BIT_MASK, + TSPI_DR_26BIT_MASK, + TSPI_DR_27BIT_MASK, + TSPI_DR_28BIT_MASK, + TSPI_DR_29BIT_MASK, + TSPI_DR_30BIT_MASK, + TSPI_DR_31BIT_MASK +}; + +/** + * @} + */ /* End of group TSPI_Private_typedef */ + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup TSPI_Private_fuctions TSPI Private Fuctions + * @{ + */ + +#ifdef DEBUG +__INLINE static int32_t check_param_frameinf_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_enable(uint32_t param); +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param); +__INLINE static int32_t check_param_transmit_master(uint32_t param); +__INLINE static int32_t check_param_transmit_mode(uint32_t param); +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param); +__INLINE static int32_t check_param_frame_range(uint32_t param); +__INLINE static int32_t check_param_idle_imp(uint32_t param); +__INLINE static int32_t check_param_underrun_imp(uint32_t param); +__INLINE static int32_t check_param_rxdly_value(uint32_t param); +__INLINE static int32_t check_param_tx_fill_level(uint32_t param); +__INLINE static int32_t check_param_rx_fill_level(uint32_t param); +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param); +__INLINE static int32_t check_param_err_int(uint32_t param); +__INLINE static int32_t check_param_tx_dma_int(uint32_t param); +__INLINE static int32_t check_param_rx_dma_int(uint32_t param); +__INLINE static int32_t check_param_input_clock(uint32_t param); +__INLINE static int32_t check_param_input_divider(uint32_t param); +__INLINE static int32_t check_param_data_direction(uint32_t param); +__INLINE static int32_t check_param_frame_length(uint32_t param); +__INLINE static int32_t check_param_frame_interval(uint32_t param); +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param); +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param); +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param); +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param); +__INLINE static int32_t check_param_min_idle_time(uint32_t param); +__INLINE static int32_t check_param_clock_delay(uint32_t param); +__INLINE static int32_t check_param_negate_delay(uint32_t param); +__INLINE static int32_t check_param_parity_enable(uint32_t param); +__INLINE static int32_t check_param_parity_bit(uint32_t param); +__INLINE static int32_t check_param_sect_mode(uint32_t param); +__INLINE static int32_t check_param_sectl0_value(uint32_t param); +__INLINE static int32_t check_param_sectl1_value(uint32_t param); +__INLINE static int32_t check_param_sectl2_value(uint32_t param); +__INLINE static int32_t check_param_sectl3_value(uint32_t param); +#endif + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit frame infinity Enable's parameter. + * @param param :Transmit frame infinity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Infinity_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frameinf_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INF_DISABLE: + case TSPI_INF_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Enable's parameter. + * @param param :Transmit Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Control + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TRXE_DISABLE: + case TSPI_TRXE_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Mode's parameter. + * @param param :Transmit Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transmission_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_tspi_sio(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SPI_MODE: + case TSPI_SIO_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Master/Slave parameter. + * @param param :Transmit Master/Slave parameter (Only support Master mode) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Operation_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_master(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MASTER_OPERATION: + case TSPI_SLAVE_OPERATION: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transfer Mode's parameter. + * @param param :Transfer Mode's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Mode + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TWO_WAY: + case TSPI_TX_ONLY: + case TSPI_RX_ONLY: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Sel Select's parameter. + * @param param :Transmit Sel Select's parameter (not support Two Way) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_CSSEL_Select + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_transmit_sel_select(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_ENABLE: + case TSPI_TSPIxCS1_ENABLE: + case TSPI_TSPIxCS2_ENABLE: + case TSPI_TSPIxCS3_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Transmit Frame Range's parameter. + * @param param :TransmitFrame Range's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Transfer_Frame_Range + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_range(uint32_t param) + +{ + int32_t result = PARAM_NG; + + if ((TSPI_TRANS_RANGE_CONTINUE == param) || (param <= TSPI_TRANS_RANGE_MAX)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the IDLE Output Value's parameter. + * @param param :IDLE Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_IDLE_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TIDLE_Hiz: + case TSPI_TIDLE_LAST_DATA: + case TSPI_TIDLE_LOW: + case TSPI_TIDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_underrun_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TXDEMP_LOW: + case TSPI_TXDEMP_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Underrun Occur Output Value's parameter. + * @param param :Underrun Occur Output Value's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Underrun_Output_value + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rxdly_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RXDLY_FSYS_FSCK_2: + case TSPI_RXDLY_FSYS_FSCK_4: + case TSPI_RXDLY_FSYS_FSCK_6: + case TSPI_RXDLY_FSYS_FSCK_8: + case TSPI_RXDLY_FSYS_FSCK_10: + case TSPI_RXDLY_FSYS_FSCK_12: + case TSPI_RXDLY_FSYS_FSCK_14: + case TSPI_RXDLY_FSYS_FSCK_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level's parameter. + * @param param :Tx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FILL_LEVEL_0: + case TSPI_TX_FILL_LEVEL_1: + case TSPI_TX_FILL_LEVEL_2: + case TSPI_TX_FILL_LEVEL_3: + case TSPI_TX_FILL_LEVEL_4: + case TSPI_TX_FILL_LEVEL_5: + case TSPI_TX_FILL_LEVEL_6: + case TSPI_TX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFillLevel + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fill_level(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FILL_LEVEL_0: + case TSPI_RX_FILL_LEVEL_1: + case TSPI_RX_FILL_LEVEL_2: + case TSPI_RX_FILL_LEVEL_3: + case TSPI_RX_FILL_LEVEL_4: + case TSPI_RX_FILL_LEVEL_5: + case TSPI_RX_FILL_LEVEL_6: + case TSPI_RX_FILL_LEVEL_7: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_FIFO_INT_DISABLE: + case TSPI_TX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_INT_DISABLE: + case TSPI_TX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxFIFOInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_FIFO_INT_DISABLE: + case TSPI_RX_FIFO_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_INT_DISABLE: + case TSPI_RX_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ErrorInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_err_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_ERR_INT_DISABLE: + case TSPI_ERR_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx DMA Interrupt's parameter. + * @param param :Tx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TX_DMA_INT_DISABLE: + case TSPI_TX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx DMA Interrupt's parameter. + * @param param :Rx DMA Interrupt's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_RxDMAInterrupt + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_rx_dma_int(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_RX_DMA_INT_DISABLE: + case TSPI_RX_DMA_INT_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Input Clock's parameter. + * @param param :Input Clock's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_clock(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_CLOCK_0: + case TSPI_BR_CLOCK_1: + case TSPI_BR_CLOCK_2: + case TSPI_BR_CLOCK_4: + case TSPI_BR_CLOCK_8: + case TSPI_BR_CLOCK_16: + case TSPI_BR_CLOCK_32: + case TSPI_BR_CLOCK_64: + case TSPI_BR_CLOCK_128: + case TSPI_BR_CLOCK_256: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Baudrate Divider's parameter. + * @param param :Baudrate Divider's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Baudrate_Clock + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_input_divider(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_BR_DIVIDER_16: + case TSPI_BR_DIVIDER_1: + case TSPI_BR_DIVIDER_2: + case TSPI_BR_DIVIDER_3: + case TSPI_BR_DIVIDER_4: + case TSPI_BR_DIVIDER_5: + case TSPI_BR_DIVIDER_6: + case TSPI_BR_DIVIDER_7: + case TSPI_BR_DIVIDER_8: + case TSPI_BR_DIVIDER_9: + case TSPI_BR_DIVIDER_10: + case TSPI_BR_DIVIDER_11: + case TSPI_BR_DIVIDER_12: + case TSPI_BR_DIVIDER_13: + case TSPI_BR_DIVIDER_14: + case TSPI_BR_DIVIDER_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataDirection"TSPI_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_DIRECTION_LSB: + case TSPI_DATA_DIRECTION_MSB: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter (Only support 8bit DATA) + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_DataLength"TSPI_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_length(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_DATA_LENGTH_8: + case TSPI_DATA_LENGTH_9: + case TSPI_DATA_LENGTH_10: + case TSPI_DATA_LENGTH_11: + case TSPI_DATA_LENGTH_12: + case TSPI_DATA_LENGTH_13: + case TSPI_DATA_LENGTH_14: + case TSPI_DATA_LENGTH_15: + case TSPI_DATA_LENGTH_16: + case TSPI_DATA_LENGTH_17: + case TSPI_DATA_LENGTH_18: + case TSPI_DATA_LENGTH_19: + case TSPI_DATA_LENGTH_20: + case TSPI_DATA_LENGTH_21: + case TSPI_DATA_LENGTH_22: + case TSPI_DATA_LENGTH_23: + case TSPI_DATA_LENGTH_24: + case TSPI_DATA_LENGTH_25: + case TSPI_DATA_LENGTH_26: + case TSPI_DATA_LENGTH_27: + case TSPI_DATA_LENGTH_28: + case TSPI_DATA_LENGTH_29: + case TSPI_DATA_LENGTH_30: + case TSPI_DATA_LENGTH_31: + case TSPI_DATA_LENGTH_32: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Frame Interval's parameter. + * @param param :Frame Interval's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Frame_Interval_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_frame_interval(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_INTERVAL_TIME_0: + case TSPI_INTERVAL_TIME_1: + case TSPI_INTERVAL_TIME_2: + case TSPI_INTERVAL_TIME_3: + case TSPI_INTERVAL_TIME_4: + case TSPI_INTERVAL_TIME_5: + case TSPI_INTERVAL_TIME_6: + case TSPI_INTERVAL_TIME_7: + case TSPI_INTERVAL_TIME_8: + case TSPI_INTERVAL_TIME_9: + case TSPI_INTERVAL_TIME_10: + case TSPI_INTERVAL_TIME_11: + case TSPI_INTERVAL_TIME_12: + case TSPI_INTERVAL_TIME_13: + case TSPI_INTERVAL_TIME_14: + case TSPI_INTERVAL_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS3 Polarity's parameter. + * @param param :TTSPIxCS3 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS3_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs3_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS3_NEGATIVE: + case TSPI_TSPIxCS3_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS2 Polarity's parameter. + * @param param :TTSPIxCS2 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS2_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs2_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS2_NEGATIVE: + case TSPI_TSPIxCS2_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS1 Polarity's parameter. + * @param param :TTSPIxCS1 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS1_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs1_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS1_NEGATIVE: + case TSPI_TSPIxCS1_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the TTSPIxCS0 Polarity's parameter. + * @param param :TTSPIxCS0 Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_TTSPIxCS0_Polarity. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_tspixcs0_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_TSPIxCS0_NEGATIVE: + case TSPI_TSPIxCS0_POSITIVE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Polarity's parameter. + * @param param :Serial Clock Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_edge_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_1ST_EDGE: + case TSPI_SERIAL_CK_2ND_EDGE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock IDLE Polarity's parameter. + * @param param :Serial Clock IDLE Polarity's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_IDLE_Polarity + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_idle_imp(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_IDLE_LOW: + case TSPI_SERIAL_CK_IDLE_HI: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Minimum IDLE Time's parameter. + * @param param :Minimum IDLE Time's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Minimum_IDLE_Time + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_min_idle_time(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_MIN_IDLE_TIME_1: + case TSPI_MIN_IDLE_TIME_2: + case TSPI_MIN_IDLE_TIME_3: + case TSPI_MIN_IDLE_TIME_4: + case TSPI_MIN_IDLE_TIME_5: + case TSPI_MIN_IDLE_TIME_6: + case TSPI_MIN_IDLE_TIME_7: + case TSPI_MIN_IDLE_TIME_8: + case TSPI_MIN_IDLE_TIME_9: + case TSPI_MIN_IDLE_TIME_10: + case TSPI_MIN_IDLE_TIME_11: + case TSPI_MIN_IDLE_TIME_12: + case TSPI_MIN_IDLE_TIME_13: + case TSPI_MIN_IDLE_TIME_14: + case TSPI_MIN_IDLE_TIME_15: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Serial Clock Delay's parameter. + * @param param :Serial Clock Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Serial_Clock_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_clock_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SERIAL_CK_DELAY_1: + case TSPI_SERIAL_CK_DELAY_2: + case TSPI_SERIAL_CK_DELAY_3: + case TSPI_SERIAL_CK_DELAY_4: + case TSPI_SERIAL_CK_DELAY_5: + case TSPI_SERIAL_CK_DELAY_6: + case TSPI_SERIAL_CK_DELAY_7: + case TSPI_SERIAL_CK_DELAY_8: + case TSPI_SERIAL_CK_DELAY_9: + case TSPI_SERIAL_CK_DELAY_10: + case TSPI_SERIAL_CK_DELAY_11: + case TSPI_SERIAL_CK_DELAY_12: + case TSPI_SERIAL_CK_DELAY_13: + case TSPI_SERIAL_CK_DELAY_14: + case TSPI_SERIAL_CK_DELAY_15: + case TSPI_SERIAL_CK_DELAY_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Negate Delay's parameter. + * @param param :Negate Delay's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_Negate_Delay + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_negate_delay(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_NEGATE_1: + case TSPI_NEGATE_2: + case TSPI_NEGATE_3: + case TSPI_NEGATE_4: + case TSPI_NEGATE_5: + case TSPI_NEGATE_6: + case TSPI_NEGATE_7: + case TSPI_NEGATE_8: + case TSPI_NEGATE_9: + case TSPI_NEGATE_10: + case TSPI_NEGATE_11: + case TSPI_NEGATE_12: + case TSPI_NEGATE_13: + case TSPI_NEGATE_14: + case TSPI_NEGATE_15: + case TSPI_NEGATE_16: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityEnable"TSPI_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_DISABLE: + case TSPI_PARITY_ENABLE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_ParityBit"TSPI_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_PARITY_BIT_ODD: + case TSPI_PARITY_BIT_EVEN: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sect Mode's parameter. + * @param param :Sect Mode's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_MODE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sect_mode(uint32_t param) +{ + int32_t result = PARAM_NG; + + switch (param) { + case TSPI_SECTCR0_SECT_FRAME_MODE: + case TSPI_SECTCR0_SECT_SECTOR_MODE: + result = PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl0 bit length's parameter. + * @param param :Sectl0 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl0_value(uint32_t param) +{ + int32_t result = PARAM_NG; + + /* 1~32:setting enable */ + if ((param >= TSPI_SECTCR1_SECTL0_1) && (param <= TSPI_SECTCR1_SECTL0_32)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl1 bit length's parameter. + * @param param :Sectl1 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl1_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl1_value = (param >> 8); + + /* 1~32:setting enable */ + if ((sectl1_value >= TSPI_SECTCR1_SECTL1_1) && (sectl1_value <= TSPI_SECTCR1_SECTL1_32)) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl2 bit length's parameter. + * @param param :Sectl2 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl2_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl2_value = (param >> 16); + + /* 0~32:setting enable */ + if (sectl2_value <= TSPI_SECTCR1_SECTL2_32) { + result = PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Sectl3 bit length's parameter. + * @param param :Sectl3 bit length's parameter + * @retval PARAM_OK :Valid + * @retval PARAM_NG :Invalid + * @note Macro definition is @ref TSPI_SECT_VALUE. + */ +/*--------------------------------------------------*/ +__INLINE static int32_t check_param_sectl3_value(uint32_t param) +{ + int32_t result = PARAM_NG; + uint32_t sectl3_value = (param >> 24); + + /* 0~32:setting enable */ + if (sectl3_value <= TSPI_SECTCR1_SECTL3_32) { + result = PARAM_OK; + } + + return (result); +} +#endif +/** + * @} + */ /* End of group TSPI_Private_functions */ + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup TSPI_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_init(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxCR1. */ + assert_param(check_param_frameinf_enable(p_obj->init.cnt1.inf)); + assert_param(check_param_transmit_enable(p_obj->init.cnt1.trxe)); + assert_param(check_param_transmit_tspi_sio(p_obj->init.cnt1.tspims)); + assert_param(check_param_transmit_master(p_obj->init.cnt1.mstr)); + assert_param(check_param_transmit_mode(p_obj->init.cnt1.tmmd)); + assert_param(check_param_transmit_sel_select(p_obj->init.cnt1.cssel)); + assert_param(check_param_frame_range(p_obj->init.cnt1.fc)); + /* Check the parameter of TTSPIxCR2 */ + assert_param(check_param_idle_imp(p_obj->init.cnt2.tidle)); + assert_param(check_param_underrun_imp(p_obj->init.cnt2.txdemp)); + assert_param(check_param_rxdly_value(p_obj->init.cnt2.rxdly)); + assert_param(check_param_tx_fill_level(p_obj->init.cnt2.til)); + assert_param(check_param_rx_fill_level(p_obj->init.cnt2.ril)); + assert_param(check_param_tx_int(p_obj->init.cnt2.inttxwe)); + assert_param(check_param_rx_int(p_obj->init.cnt2.intrxwe)); + assert_param(check_param_tx_fifo_int(p_obj->init.cnt2.inttxfe)); + assert_param(check_param_rx_fifo_int(p_obj->init.cnt2.intrxfe)); + assert_param(check_param_err_int(p_obj->init.cnt2.interr)); + assert_param(check_param_tx_dma_int(p_obj->init.cnt2.dmate)); + assert_param(check_param_rx_dma_int(p_obj->init.cnt2.dmare)); + /* Check the parameter of TTSPIxBR */ + assert_param(check_param_input_clock(p_obj->init.brd.brck)); + assert_param(check_param_input_divider(p_obj->init.brd.brs)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); + /* Check the parameter of TSPISECTCR0 */ + assert_param(check_param_sect_mode(p_obj->init.sectcr0.sect)); + /* Check the parameter of TSPISECTCR1 */ + assert_param(check_param_sectl0_value(p_obj->init.sectcr1.sectl0)); + assert_param(check_param_sectl1_value(p_obj->init.sectcr1.sectl1)); + assert_param(check_param_sectl2_value(p_obj->init.sectcr1.sectl2)); + assert_param(check_param_sectl3_value(p_obj->init.sectcr1.sectl3)); +#endif + + + /* TSPI Software Reset */ + p_obj->p_instance->CR0 = TSPI_ENABLE; + p_obj->p_instance->CR0 = (TSPI_RESET10 | TSPI_ENABLE); + p_obj->p_instance->CR0 = (TSPI_RESET01 | TSPI_ENABLE); + + /* Wait for 2 clocks of reset completion */ + __NOP(); + __NOP(); + + /* Control1 Register1 Set*/ + p_obj->p_instance->CR1 = 0x00001C01U; + p_obj->p_instance->CR1 = (p_obj->init.cnt1.cssel | p_obj->init.cnt1.fc | p_obj->init.cnt1.mstr | p_obj->init.cnt1.tmmd | \ + p_obj->init.cnt1.trxe | p_obj->init.cnt1.tspims | p_obj->init.cnt1.trgen | p_obj->init.cnt1.inf); + /* Control2 Register Set */ + p_obj->p_instance->CR2 = 0x00E10100U; + p_obj->p_instance->CR2 = (p_obj->init.cnt2.tidle | p_obj->init.cnt2.txdemp | p_obj->init.cnt2.rxdly | p_obj->init.cnt2.til | \ + p_obj->init.cnt2.ril | p_obj->init.cnt2.inttxfe | p_obj->init.cnt2.intrxfe | p_obj->init.cnt2.inttxwe | \ + p_obj->init.cnt2.intrxwe | p_obj->init.cnt2.interr | p_obj->init.cnt2.dmate | p_obj->init.cnt2.dmare); + + /* Control3 Register is FIFO clear, do nothing */ + + /* Baudrate Register Set */ + p_obj->p_instance->BR = 0U; + p_obj->p_instance->BR = (p_obj->init.brd.brck | p_obj->init.brd.brs); + + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = 0x8800C400U; + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = 0U; + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + + /* Sect control0 Register Set*/ + p_obj->p_instance->SECTCR0 = 0U; + p_obj->p_instance->SECTCR0 = p_obj->init.sectcr0.sect; + + /* Sect control1 Register Set*/ + p_obj->p_instance->SECTCR1 = 0x00000101U; + p_obj->p_instance->SECTCR1 = (p_obj->init.sectcr1.sectl3 | p_obj->init.sectcr1.sectl2 | p_obj->init.sectcr1.sectl1 | p_obj->init.sectcr1.sectl0); + + /* not created */ + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the TSPI object. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_deinit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Disable the selected TSPI peripheral */ + p_obj->p_instance->CR0 |= TSPI_DISABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data.. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_write(tspi_t *p_obj, tspi_transmit_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + + /* Transmit data check*/ + if ((p_info->tx8.p_data == TSPI_NULL) || (p_info->tx8.num == 0)) { + p_obj->errcode = DATABUFEMPERR; + result = TXZ_ERROR; + return (result); + } + + /* FIFO Cear */ + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->transmit.tx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + /* Transmit Data write to D ata Register */ + while (p_info->tx8.num > 0) { + /* Check the current fill level */ + if (((p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK) >> 16) <= 7) { + *((__IO uint8_t *)&p_obj->p_instance->DR) = ((*p_info->tx8.p_data++) & (uint8_t)TSPI_DR_8BIT_MASK); + p_info->tx8.num--; + /* check complete transmit */ + if ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } else { + /* Enable TSPI Transmission Control */ + if (p_info->tx8.num == 0) { + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + return (result); + } else { + /* Next transmit data sending */ + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + } + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + + } + /* check complete transmit */ + while ((p_obj->p_instance->SR & TSPI_TX_DONE_FLAG) != TSPI_TX_DONE) { + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + /* Check Error Flag */ + (void)tspi_get_error(p_obj, &err); + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + + if (p_obj->errcode == NOERROR) { + //p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @param timeout :Timeout duration. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_info is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_read(tspi_t *p_obj, tspi_receive_t *p_info, uint32_t timeout) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t err = 0; + uint32_t length = 0; + uint32_t count = 0; + uint32_t index = 0; +// uint32_t level = 0; + + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + p_obj->errcode = NOERROR; + + /* Check the Transfer Mode setting */ + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_TX_ONLY) { + p_obj->errcode = TRANSMITMODEERR; + result = TXZ_ERROR; + return (result); + } + if ((p_obj->p_instance->CR1 & TSPI_Transfer_Mode_MASK) == TSPI_RX_ONLY) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + } + + /* Transmit data check*/ + if ((p_info->rx8.p_data == TSPI_NULL) || (p_info->rx8.num == 0)) { + result = TXZ_ERROR; + return (result); + } + count = p_info->rx8.num; + + /* Check the Frame length setting */ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /* Blocking Communication support frame length 8bit (1 byte) only */ + if (length == (TSPI_DATA_LENGTH_8 >> 24)) { + p_obj->receive.rx_allign = TSPI_DATA_ALLIGN_8; + } else { + p_obj->errcode = DATALENGTHERR; + result = TXZ_ERROR; + return (result); + } + + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + while (timeout > 0) { + /* Wait until Receive Complete Flag is set to receive data */ + if ((p_obj->p_instance->SR & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) { + while (count > 0) { + /* Check the remain data exist */ + if ((p_obj->p_instance->SR & TSPI_RX_REACH_FILL_LEVEL_MASK) != 0) { + p_info->rx8.p_data[index] = (*((__IO uint8_t *)&p_obj->p_instance->DR) & (uint8_t)TSPI_DR_8BIT_MASK); + count--; + index++; + } else { + p_obj->errcode = FIFOFULLERR; + timeout--; + if (timeout == 0) { + p_obj->errcode = TIMEOUTERR; + result = TXZ_ERROR; + return (result); + } + } + } + /* Receive Complete Flag is clear */ + p_obj->p_instance->SR |= TSPI_RX_DONE_CLR; + /* FIFO Cear */ + p_obj->p_instance->CR2 |= TSPI_RX_BUFF_CLR_DONE; + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + return (result); + } else { + timeout--; + } + } + /* Timeout management */ + p_obj->errcode = TIMEOUTERR; + + /* Check Error Flag set */ + (void)tspi_get_error(p_obj, &err); + if (((err) & TSPI_UNDERRUN_ERR) == TSPI_UNDERRUN_ERR) { + p_obj->errcode = UNDERRUNERR; + } else if (((err) & TSPI_OVERRUN_ERR) == TSPI_OVERRUN_ERR) { + p_obj->errcode = OVERRUNERR; + } else if (((err) & TSPI_PARITY_ERR) == TSPI_PARITY_ERR) { + p_obj->errcode = PARITYERR; + } + + result = TXZ_ERROR; + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of transmit data. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_transfer(tspi_t *p_obj, tspi_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx32.p_data)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + p_obj->p_instance->SR |= TSPI_TX_DONE_CLR; + p_obj->p_instance->CR3 |= TSPI_TX_BUFF_CLR_DONE; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + p_obj->transmit.tx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + p_obj->transmit.tx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->transmit.info.tx32.p_data = p_info->tx32.p_data; + p_obj->transmit.info.tx32.num = p_info->tx32.num; + p_obj->transmit.tx_allign = 32; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /* transmit data length set */ + + /*--- TSPIxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + __IO uint32_t tlvl = (p_obj->p_instance->SR & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Empty FIFO Num */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + /*--- TSPIxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + return (result); +} + + + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :TSPI object. + * @param p_info :The information of receive buffer. + * @retval SUCCESS :Success. + * @retval FAILURE :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref TSPI_TxReachFillLevel) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_master_receive(tspi_t *p_obj, tspi_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t length = 0; + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.fmr0.fl == TSPI_DATA_LENGTH_8) { + /* 8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + } else if ((p_obj->init.fmr0.fl > TSPI_DATA_LENGTH_8) && (p_obj->init.fmr0.fl < TSPI_DATA_LENGTH_17)) { + /* 9 - 16 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + } else { + /* 17 - 32 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx32.p_data)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + //p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + p_obj->receive.rx_allign = 8; + + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.info.rx32.p_data = p_info->rx32.p_data; + p_obj->receive.info.rx32.num = p_info->rx32.num; + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_transmit(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + //p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_TX_FIFO_INT_CLR); + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24U); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + /* Check the transmit's end flag. */ + if (((status & TSPI_TX_DONE_FLAG) == TSPI_TX_DONE) || + ((status & TSPI_TX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.til)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + __IO uint32_t tlvl = (status & TSPI_TX_REACH_FILL_LEVEL_MASK); + tlvl >>= 8; + /* FIFO Max = TRANSFER_FIFO_MAX_NUM */ + if (tlvl > TRANSFER_FIFO_MAX_NUM) { + tlvl = TRANSFER_FIFO_MAX_NUM; + } + /* Get the empty num in FIFO. */ + { + __IO uint32_t work = tlvl; + tlvl = (TRANSFER_FIFO_MAX_NUM - work); + } + if (tlvl == TRANSFER_FIFO_MAX_NUM) { + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->transmit.tx_allign = 8; + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->transmit.tx_allign = 16; + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } else { + /* 17 - 32 bit */ + p_obj->transmit.tx_allign = 32; + if (p_obj->transmit.info.tx32.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->transmit.tx_allign) { + case 8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & (uint8_t)TSPI_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 16: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case 32: + if (p_obj->transmit.info.tx32.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx32.p_data + p_obj->transmit.rp) & mask[length]); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } +#if 0 + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; +#endif + } + } +} +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_irq_handler_receive(tspi_t *p_obj) +{ + __IO uint32_t status; + + uint32_t length = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current TSPIxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + //p_obj->p_instance->SR = (TSPI_RX_DONE_CLR | TSPI_RX_FIFO_INT_CLR); + /*------------------------------*/ + /* Data length setting */ + /*------------------------------*/ + length = ((p_obj->p_instance->FMTR0 & TSPI_DATA_LENGTH_MASK) >> 24); + if (length == DATA_LENGTH_8) { + /* 8 bit */ + p_obj->receive.rx_allign = 8; + } else if ((length > DATA_LENGTH_8) && (length < DATA_LENGTH_17)) { + /* 9 - 16 bit */ + p_obj->receive.rx_allign = 16; + } else { + /* 17 - 32 bit */ + p_obj->receive.rx_allign = 32; + } + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + /* Check the receive's end flag. */ + if (((status & TSPI_RX_DONE_FLAG) == TSPI_RX_DONE) || + ((status & TSPI_RX_REACH_FILL_LEVEL_MASK) == p_obj->init.cnt2.ril)) { + /* Read FIFO fill level. */ + __IO uint32_t rlvl = (status & TSPI_RX_REACH_FILL_LEVEL_MASK); + //__IO uint32_t rlvl = 7; + /* FIFO Max = RECEIVE_FIFO_MAX_NUM */ + if (rlvl > RECEIVE_FIFO_MAX_NUM) { + rlvl = RECEIVE_FIFO_MAX_NUM; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->receive.rx_allign) { + case 8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & (uint8_t)TSPI_DR_8BIT_MASK); + break; + case 16: + *(p_obj->receive.info.rx16.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + case 32: + *(p_obj->receive.info.rx32.p_data + i) = (uint8_t)(p_obj->p_instance->DR & mask[length]); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + tspi_receive_t param; + + switch (p_obj->receive.rx_allign) { + case 8: + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + break; + case 16: + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + break; + case 32: + param.rx32.p_data = p_obj->receive.info.rx32.p_data; + param.rx32.num = rlvl; + break; + default: + /* no process */ + break; + } + /* Call the receive handler with SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :TSPI object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void tspi_error_irq_handler(tspi_t *p_obj) +{ + __IO uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current TSPIxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- TSPIxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & TSPI_TRGERR_MASK) == TSPI_TRGERR_ERR) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != TSPI_NULL) { + /* Call the transmit handler with FAILURE. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* UNDERERR */ + if ((error & TSPI_UNDERRUN_MASK) == TSPI_UNDERRUN_ERR) { + err = TXZ_ERROR; + } + /* OVRERR */ + if ((error & TSPI_OVERRUN_MASK) == TSPI_OVERRUN_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & TSPI_PARITY_MASK) == TSPI_PARITY_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=0). */ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != TSPI_NULL) { + /* Call the receive handler with FAILURE. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, TSPI_NULL); + } + } + } +} + + +/*--------------------------------------------------*/ +/** + * @brief Data Format setting + * @param p_obj :TSPI object. + * @retval - + * @note When p_obj is NULL, no processing. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_format(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + /* Check the parameter of TTSPIxFMTR0 */ + assert_param(check_param_data_direction(p_obj->init.fmr0.dir)); + assert_param(check_param_frame_length(p_obj->init.fmr0.fl)); + assert_param(check_param_frame_interval(p_obj->init.fmr0.fint)); + assert_param(check_param_tspixcs3_imp(p_obj->init.fmr0.cs3pol)); + assert_param(check_param_tspixcs2_imp(p_obj->init.fmr0.cs2pol)); + assert_param(check_param_tspixcs1_imp(p_obj->init.fmr0.cs1pol)); + assert_param(check_param_tspixcs0_imp(p_obj->init.fmr0.cs0pol)); + assert_param(check_param_clock_edge_imp(p_obj->init.fmr0.ckpha)); + assert_param(check_param_clock_idle_imp(p_obj->init.fmr0.ckpol)); + assert_param(check_param_min_idle_time(p_obj->init.fmr0.csint)); + assert_param(check_param_clock_delay(p_obj->init.fmr0.cssckdl)); + assert_param(check_param_negate_delay(p_obj->init.fmr0.sckcsdl)); + /* Check the parameter of TTSPIxFMTR1 */ + assert_param(check_param_parity_enable(p_obj->init.fmr1.vpe)); + assert_param(check_param_parity_bit(p_obj->init.fmr1.vpm)); +#endif + + + /* Format control1 Register Set*/ + p_obj->p_instance->FMTR1 = (p_obj->init.fmr1.vpm | p_obj->init.fmr1.vpe); + /* Format control0 Register Set */ + p_obj->p_instance->FMTR0 = (p_obj->init.fmr0.ckpha | p_obj->init.fmr0.ckpol | p_obj->init.fmr0.cs0pol | p_obj->init.fmr0.cs1pol | \ + p_obj->init.fmr0.cs2pol | p_obj->init.fmr0.cs3pol | p_obj->init.fmr0.csint | p_obj->init.fmr0.cssckdl | \ + p_obj->init.fmr0.dir | p_obj->init.fmr0.fint | p_obj->init.fmr0.fl | p_obj->init.fmr0.sckcsdl); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref TSPI_Status_Setting_flag. | + * | 30-24 | - | - | + * | 23 | TXRUN | Transmitting State Flag. Use @ref TSPI_TxState. | + * | 22 | TXEND | Transmitting Done Flag. Use @ref TSPI_TxDone. | + * | 21 | INTTXWF | Transmitting FIFO Interrpt Flag. Use @ref TSPI_TxFIFOInterruptFlag. | + * | 20 | TFEMP | Transmitting FIFO Empty Flag. Use @ref TSPI_TxFIFOEmptyFlag. | + * | 19-16 | TLVL | Current Transmitting FIFO Level. @ref TSPI_TxReachFillLevel. | + * | 15-8 | - | - | + * | 7 | RXRUN | Receive State Flag. Use @ref TSPI_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref TSPI_RxDone. | + * | 5 | INTRXFF | Receiving FIFO Interrpt Flag. Use @ref TSPI_RxFIFOInterruptFlag. | + * | 4 | RXFLL | Receiving FIFO Full Flag. Use @ref TSPI_RxFIFOFullFlag | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref TSPI_RxFIFOFullFlag | + * + * @param p_obj :TSPI object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_status is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_status(tspi_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI state */ + *p_status = p_obj->p_instance->SR; + if (p_status != TSPI_NULL) { + return (result); + } else { + result = TXZ_ERROR; + return (result); + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_get_error(tspi_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + + /* Return TSPI ERROR */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Error information clear. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-3 | - | - | + * | 3 | TRGERR | Trigger Error. Use @ref TSPI_TRGErr. | + * | 2 | UDRERR | Overrun Error. Use @ref TSPI_UnderrunErr. | + * | 1 | OVRERR | Overrun Error. Use @ref TSPI_OverrunErr. | + * | 0 | PERR | Parity Error. Use @ref TSPI_ParityErr. | + * + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note When p_obj is NULL, "Failure" is returned. + * @note When p_error is NULL, "Failure" is returned. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_error_clear(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + /* Check the parameters */ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); +#endif + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_transmit(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :TSPI object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result tspi_discard_receive(tspi_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the TSPI_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- TSPIxTRXE ---*/ + p_obj->p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- TSPIxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (TSPI_TX_DONE_CLR | TSPI_RX_DONE_CLR); + /*--- TSPIxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->CR3 = (TSPI_TX_BUFF_CLR_DONE | TSPI_RX_BUFF_CLR_DONE); + /*--- TSPIxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1), UDRERR(=1), and OVRERR(=1), PERR(=1) */ + p_obj->p_instance->ERR = (TSPI_TRGERR_ERR | TSPI_UNDERRUN_ERR | TSPI_OVERRUN_ERR | TSPI_PARITY_ERR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- TSPIxTRANS ---*/ + /* Write to TRXE(=1). */ + /* Check if the TSPI is already enabled */ + if ((p_obj->p_instance->CR0 & TSPI_ENABLE) != TSPI_ENABLE) { + p_obj->p_instance->CR0 |= TSPI_ENABLE; + } + + /* Enable TSPI Transmission Control */ + p_obj->p_instance->CR1 |= TSPI_TRXE_ENABLE; + + return (result); +} + + +/** + * @} + */ /* End of group TSPI_Exported_functions */ + +/** + * @} + */ /* End of group TSPI */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__TSPI_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_uart.c new file mode 100644 index 00000000000..a4688870388 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/Periph_Driver/src/txzp_uart.c @@ -0,0 +1,1805 @@ +/** + ******************************************************************************* + * @file txzp_uart.c + * @brief This file provides API functions for UART driver. + * @version V1.0.0 + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Includes */ +/*------------------------------------------------------------------------------*/ +#include "txzp_uart_include.h" +#include "txzp_uart.h" + +#if defined(__UART_H) +/** + * @addtogroup Periph_Driver + * @{ + */ + +/** + * @addtogroup UART + * @{ + */ +/*------------------------------------------------------------------------------*/ +/* Configuration */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/** + * @defgroup UART_BourateConfig Bourate Setting Configuration + * @brief Bourate Setting Configuration. + * @{ + */ +#define UART_CFG_GET_BOUDRATE_DISABLE (0) /*!< Disable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE_ENABLE (1) /*!< Enable to get bourate setting. */ +#define UART_CFG_GET_BOUDRATE UART_CFG_GET_BOUDRATE_ENABLE /* Disable/Enable Get Bourate Setting */ + +#define UART_CFG_GET_BOUDRATE_TYPE_SINGLE (0) /*!< When the function finds within error margin, finish calculation. */ +#define UART_CFG_GET_BOUDRATE_TYPE_ALL (1) /*!< The function calculates all patern(calculates minimum error margin). */ +#define UART_CFG_GET_BOUDRATE_TYPE UART_CFG_GET_BOUDRATE_TYPE_ALL + +#define UART_CFG_BOUDRATE_ERROR_RANGE ((uint32_t)3) /*!< Error Margin(%). */ +#define UART_CFG_BOUDRATE_FIXED_POINT_BIT ((uint32_t)6) /*!< Fiexd Point Bit. */ +/** + * @} + */ /* End of group UART_BourateConfig */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Enumerated Type Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_define UART Private Define + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_define */ + + +/*------------------------------------------------------------------------------*/ +/* Structure Definition */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_typedef UART Private Typedef + * @{ + */ + +/* no define */ + +/** + * @} + */ /* End of group UART_Private_typedef */ + + +/*------------------------------------------------------------------------------*/ +/* Private Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup UART_Private_fuctions UART Private Fuctions + * @{ + */ +#ifdef DEBUG +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param); +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param); +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param); +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param); +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param); +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param); +__STATIC_INLINE int32_t check_param_data_length(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param); +__STATIC_INLINE int32_t check_param_err_int(uint32_t param); +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param); +__STATIC_INLINE int32_t check_param_division(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param); +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param); +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param); +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param); +#endif /* #ifdef DEBUG */ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level); +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level); +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64); +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +#ifdef DEBUG +/*--------------------------------------------------*/ +/** + * @brief Check the Noize Fileter's parameter. + * @param param :Noize fileter's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_NoiseFilter"UART_NOISE_FILTER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_noize_filter(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_NOISE_FILTER_NON: + case UART_NOISE_FILTER_2_T0: + case UART_NOISE_FILTER_4_T0: + case UART_NOISE_FILTER_8_T0: + case UART_NOISE_FILTER_2_CLOCK: + case UART_NOISE_FILTER_3_CLOCK: + case UART_NOISE_FILTER_4_CLOCK: + case UART_NOISE_FILTER_5_CLOCK: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the CTS Handshake's parameter. + * @param param :CTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_CTSHandshake"UART_CTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_cts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_CTS_DISABLE: + case UART_CTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the RTS Handshake's parameter. + * @param param :RTS Handshake's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RTSHandshake"UART_RTS_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rts_handshake(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RTS_DISABLE: + case UART_RTS_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Complementation's parameter. + * @param param :Data Complementation's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataComplementation"UART_DATA_COMPLEMENTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_complemention(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_COMPLEMENTION_DISABLE: + case UART_DATA_COMPLEMENTION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Direction's parameter. + * @param param :Data Direction's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataDirection"UART_DATA_DIRECTION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_direction(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_DIRECTION_LSB: + case UART_DATA_DIRECTION_MSB: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Stop Bit's parameter. + * @param param :Stop Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_StopBit"UART_STOP_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_stop_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_STOP_BIT_1: + case UART_STOP_BIT_2: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Bit's parameter. + * @param param :Parity Bit's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityBit"UART_PARITY_BIT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_bit(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_BIT_ODD: + case UART_PARITY_BIT_EVEN: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Parity Enable's parameter. + * @param param :Parity Enable's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ParityEnable"UART_PARITY_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_parity_enable(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PARITY_DISABLE: + case UART_PARITY_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Data Length's parameter. + * @param param :Data Length's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_DataLength"UART_DATA_LENGTH_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_data_length(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DATA_LENGTH_7: + case UART_DATA_LENGTH_8: + case UART_DATA_LENGTH_9: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Fill Level Range's parameter. + * @param param :Tx Fill Level Range's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFillLevelRange"UART_TX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_TX_FILL_RANGE_MIN is 0. ---*/ +#if 0 + if ((UART_TX_FILL_RANGE_MIN <= param) && (param <= UART_TX_FILL_RANGE_MAX)) +#else + if (param <= UART_TX_FILL_RANGE_MAX) +#endif + { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Fill Level's parameter. + * @param param :Rx Fill Level's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFillLevel"UART_RX_FILL_RANGE_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fill_level_range(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RX_FILL_RANGE_MIN <= param) && (param <= UART_RX_FILL_RANGE_MAX)) { + result = UART_PARAM_OK; + } + + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx FIFO Interrpt's parameter. + * @param param :Tx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxFIFOInterrupt"UART_TX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_FIFO_INT_DISABLE: + case UART_TX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Tx Interrpt's parameter. + * @param param :Tx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_TxInterrupt"UART_TX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_TX_INT_DISABLE: + case UART_TX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx FIFO Interrpt's parameter. + * @param param :Rx FIFO Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxFIFOInterrupt"UART_RX_FIFO_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_fifo_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_FIFO_INT_DISABLE: + case UART_RX_FIFO_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Rx Interrpt's parameter. + * @param param :Rx Interrpt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RxInterrupt"UART_RX_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_RX_INT_DISABLE: + case UART_RX_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Error Interrupt's parameter. + * @param param :Error Interrupt's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_ErrorInterrupt"UART_ERR_INT_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_err_int(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_ERR_INT_DISABLE: + case UART_ERR_INT_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Prescaler's parameter. + * @param param :Prescaler's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Prescaler"UART_PLESCALER_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_prescaler(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_PLESCALER_1: + case UART_PLESCALER_2: + case UART_PLESCALER_4: + case UART_PLESCALER_8: + case UART_PLESCALER_16: + case UART_PLESCALER_32: + case UART_PLESCALER_64: + case UART_PLESCALER_128: + case UART_PLESCALER_256: + case UART_PLESCALER_512: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} +/*--------------------------------------------------*/ +/** + * @brief Check the Division's parameter. + * @param param :Division's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_Division"UART_DIVISION_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_division(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + switch (param) { + case UART_DIVISION_DISABLE: + case UART_DIVISION_ENABLE: + result = UART_PARAM_OK; + break; + default: + /* no process */ + break; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range K's parameter. + * @param param :Range K's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeK"UART_RANGE_K_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeK(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + /*--- Now, UART_RANGE_K_MIN is 0. ---*/ +#if 0 + if ((UART_RANGE_K_MIN <= param) && (param <= UART_RANGE_K_MAX)) +#else + if (param <= UART_RANGE_K_MAX) +#endif + { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the Range N's parameter. + * @param param :Range N's parameter + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note Macro definition is @ref UART_RangeN"UART_RANGE_N_xxxx". + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rangeN(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if ((UART_RANGE_N_MIN <= param) && (param <= UART_RANGE_N_MAX)) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for transmit. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_tx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param != 0) { + result = UART_PARAM_OK; + } + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Check the num of buff for receive. + * @param param :Num of buff. + * @retval UART_PARAM_OK :Valid + * @retval UART_PARAM_NG :Invalid + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE int32_t check_param_rx_buff_num(uint32_t param) +{ + int32_t result = UART_PARAM_NG; + + if (param >= 8) { + result = UART_PARAM_OK; + } + + return (result); +} +#endif /* #ifdef DEBUG */ + +/*--------------------------------------------------*/ +/** + * @brief Convert Tx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_tx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result = (level << 12); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Convert Rx FIFO fill level to register. + * @param level :Fill Level. + * @retval Register value. + * @note - + */ +/*--------------------------------------------------*/ +__STATIC_INLINE uint32_t convert_rx_fifo_fill_level_to_reg(uint32_t level) +{ + uint32_t result; + + if (level < 8) { + result = (level << 8); + } else { + result = 0; + } + + return (result); +} + +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) +/*--------------------------------------------------*/ +/** + * @brief Check the within error margin. + * @param boudrate :Boudrate(bps). + * @param clock :Clock(hz). + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param k :K Value. Must be set "UART_RANGE_K_MIN <= k <=UART_RANGE_K_MAX" + * @param n :N Value. Must be set "UART_RANGE_N_MIN <= n <=UART_RANGE_N_MAX" + * @param p_range64 :Error range(after fixed point bit shift). + * @retval TXZ_SUCCESS :Within error margin. + * @retval TXZ_ERROR :Without error margin. + * @note For N+(64-K)/64 division. + */ +/*--------------------------------------------------*/ +static TXZ_Result verification_boudrate64(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uint32_t k, uint32_t n, uint64_t *p_range64) +{ + TXZ_Result result = TXZ_ERROR; + uint64_t boud64 = 0; + uint64_t tx64 = 0; + uint64_t work64 = 0; + + /* phi Tx */ + uint32_t prescaler = (p_clk->prsel >> 4); + + work64 = (uint64_t)((uint64_t)1 << prescaler); + tx64 = (uint64_t)((uint64_t)clock << (UART_CFG_BOUDRATE_FIXED_POINT_BIT + 2)); + tx64 /= work64; + + /* Bourate */ + boud64 = (uint64_t)((uint64_t)boudrate << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + *p_range64 = ((boud64 / 100) * UART_CFG_BOUDRATE_ERROR_RANGE); + /* BourateX */ + work64 = (uint64_t)((uint64_t)n << 6); + work64 = (uint64_t)(work64 + (64 - (uint64_t)k)); + work64 = (tx64 / work64); + if (boud64 >= *p_range64) { + if (((boud64 - *p_range64) <= work64) && (work64 <= (boud64 + *p_range64))) { + if (boud64 < work64) { + *p_range64 = (work64 - boud64); + } else { + *p_range64 = (boud64 - work64); + } + result = TXZ_SUCCESS; + } + } + + return (result); +} +#endif /* #if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + +/** + * @} + */ /* End of group UART_Private_functions */ + + +/*------------------------------------------------------------------------------*/ +/* Public Function */ +/*------------------------------------------------------------------------------*/ +/** + * @addtogroup UART_Exported_functions + * @{ + */ +/*--------------------------------------------------*/ +/** + * @brief Initialize the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_init(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(check_param_prescaler(p_obj->init.clock.prsel)); + assert_param(check_param_division(p_obj->init.boudrate.ken)); + assert_param(check_param_rangeK(p_obj->init.boudrate.brk)); + assert_param(check_param_rangeN(p_obj->init.boudrate.brn)); + assert_param(check_param_tx_int(p_obj->init.inttx)); + assert_param(check_param_rx_int(p_obj->init.intrx)); + assert_param(check_param_err_int(p_obj->init.interr)); + assert_param(check_param_tx_fifo_int(p_obj->init.txfifo.inttx)); + assert_param(check_param_tx_fill_level_range(p_obj->init.txfifo.level)); + assert_param(check_param_rx_fifo_int(p_obj->init.rxfifo.intrx)); + assert_param(check_param_rx_fill_level_range(p_obj->init.rxfifo.level)); + assert_param(check_param_noize_filter(p_obj->init.nf)); + assert_param(check_param_cts_handshake(p_obj->init.ctse)); + assert_param(check_param_rts_handshake(p_obj->init.rtse)); + assert_param(check_param_data_complemention(p_obj->init.iv)); + assert_param(check_param_data_direction(p_obj->init.dir)); + assert_param(check_param_stop_bit(p_obj->init.sblen)); + assert_param(check_param_parity_bit(p_obj->init.even)); + assert_param(check_param_parity_enable(p_obj->init.pe)); + assert_param(check_param_data_length(p_obj->init.sm)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* SW Reset */ + /*------------------------------*/ + /*--- UARTxSWRST ---*/ + /* SW Reset initializes UARTxTRANS, UARTxDR, UARTxSR, UARTxERR. */ + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /* Write to SWRST(=10). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_10; + /* Write to SWRST(=01). */ + p_obj->p_instance->SWRST = UARTxSWRST_SWRST_01; + /* Wait to "SWRSTF = 0". */ + while (((p_obj->p_instance->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + /* no process */ + } + /*------------------------------*/ + /* FIFO Clear */ + /*------------------------------*/ + /*--- UARTxFIFOCLR ---*/ + /* Write to TFCLR(=1), and RFCLR(=1) */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); + /*------------------------------*/ + /* Register Setting */ + /*------------------------------*/ + /*--- UARTxCLK ---*/ + /* Reflecting "p_obj->init.clk" */ + p_obj->p_instance->CLK = (p_obj->init.clock.prsel & UART_UARTxCLK_MASK); + /*--- UARTxBRD ---*/ + /* Reflecting "p_obj->init.brd" */ + /* Be careful, BRK needs to bit shit. */ + { + uint32_t brk = (p_obj->init.boudrate.brk << 16); + p_obj->p_instance->BRD = (p_obj->init.boudrate.ken | brk | p_obj->init.boudrate.brn); + } + /*--- UARTxCR0 ---*/ + /* Reflecting "p_obj->init.cnt0" */ + p_obj->p_instance->CR0 = (p_obj->init.hct | p_obj->init.hcm | + p_obj->init.hcc | p_obj->init.lbc | + p_obj->init.nf | p_obj->init.ctse | + p_obj->init.rtse | p_obj->init.iv | + p_obj->init.dir | p_obj->init.sblen | + p_obj->init.even | p_obj->init.pe | + p_obj->init.sm); + /*--- UARTxCR1 ---*/ + /* Reflecting "p_obj->init.cnt1" */ + /* Fixed: "DMATE=0", "DMARE=0". */ + /* Be careful, "TIL", "RIL" need to bit shit. */ + p_obj->p_instance->CR1 = (convert_tx_fifo_fill_level_to_reg(p_obj->init.txfifo.level) | + convert_rx_fifo_fill_level_to_reg(p_obj->init.rxfifo.level) | + p_obj->init.txfifo.inttx | p_obj->init.inttx | + p_obj->init.rxfifo.intrx | p_obj->init.intrx | + p_obj->init.interr); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Release the UART object. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_deinit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*--- UARTxCR1 ---*/ + p_obj->p_instance->CR1 = 0; + /*--- UARTxCR0 ---*/ + p_obj->p_instance->CR0 = 0; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard transmit. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears transmit's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_transmit(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_TX_STATE_MASK) == UART_TX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxFIFOCLR ---*/ + /* Clear the transmit's FIFO. */ + /* Write to TFCLR(=1). */ + p_obj->p_instance->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR); + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to TRGERR(=1). */ + p_obj->p_instance->ERR = (UARTxERR_TRGERR_W_CLEAR); + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /* Return RXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & UARTxTRANS_RXE_MASK); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Discard receive. + * @param p_obj :UART object. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note This function clears receive's fifo, end flag and error info. + * @attention This function is not available in interrupt. + * @attention Use after interrupt is disabled. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_discard_receive(uart_t *p_obj) +{ + TXZ_Result result = TXZ_SUCCESS; + uint32_t trans = 0; + uint32_t count = 10000000; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transfer */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Read current UARTxTRANS value. */ + trans = p_obj->p_instance->TRANS; + /* Write to BK(=0), TXTRG(=0), TXE(=0), RXE(=0) */ + p_obj->p_instance->TRANS = (UARTxTRANS_BK_STOP | UARTxTRANS_TXTRG_DISABLE | + UARTxTRANS_TXE_DISABLE | UARTxTRANS_RXE_DISABLE); + /*------------------------------*/ + /* Refresh Setting */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Clear the receive's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + while ((p_obj->p_instance->SR & UART_RX_STATE_MASK) == UART_RX_STATE_RUN) { + if (--count == 0) { + break; + } + } + /*--- UARTxERR ---*/ + /* Clear the trigger error flag. */ + /* Write to OVRERR(=1), PERR(=1), and FERR(=1), BERR(=1) */ + p_obj->p_instance->ERR = (UARTxERR_OVRERR_W_CLEAR | UARTxERR_PERR_W_CLEAR | + UARTxERR_FERR_W_CLEAR | UARTxERR_BERR_W_CLEAR); + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /* Return TXE setting to UARTxTRANS */ + p_obj->p_instance->TRANS = (trans & (UARTxTRANS_BK_MASK | UARTxTRANS_TXTRG_MASK | UARTxTRANS_TXE_MASK)); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Transmit data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of transmit data. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_transmitIt(uart_t *p_obj, uart_transmit_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx16.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->tx8.p_data)); + assert_param(check_param_tx_buff_num(p_info->tx8.num)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + p_obj->transmit.rp = 0; + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->transmit.info.tx16.p_data = p_info->tx16.p_data; + p_obj->transmit.info.tx16.num = p_info->tx16.num; + } else { + /* 7/8 bit */ + p_obj->transmit.info.tx8.p_data = p_info->tx8.p_data; + p_obj->transmit.info.tx8.num = p_info->tx8.num; + } + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + { + /*--- UARTxSR ---*/ + /* Read FIFO fill level. */ + /* Read current TLVL. */ + uint32_t tlvl = (p_obj->p_instance->SR & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Empty FIFO Num */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + { + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = ((uint32_t) * (p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + /*------------------------------*/ + /* Enable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_TXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Receive data. Non-Blocking Communication. + * @param p_obj :UART object. + * @param p_info :The information of receive buffer. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note Asynchronous Processing. + * @attention "p_info->rx8(or rx16).num" must be over FIFO max(Refer @ref UART_FifoMax) num. + * @attention This function is not available in interrupt. + */ +/*--------------------------------------------------*/ +TXZ_Result uart_receiveIt(uart_t *p_obj, uart_receive_t *p_info) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_info)); + /* Check the parameter of transmit. */ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx16.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx16.num)); + } else { + /* 7/8 bit */ + assert_param(IS_POINTER_NOT_NULL(p_info->rx8.p_data)); + assert_param(check_param_rx_buff_num(p_info->rx8.num)); + } +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Information Setting */ + /*------------------------------*/ + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + /* 9 bit */ + p_obj->receive.info.rx16.p_data = p_info->rx16.p_data; + p_obj->receive.info.rx16.num = p_info->rx16.num; + } else { + /* 7/8 bit */ + p_obj->receive.info.rx8.p_data = p_info->rx8.p_data; + p_obj->receive.info.rx8.num = p_info->rx8.num; + } + /*------------------------------*/ + /* Enable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=1). */ + /* Bitband Access. */ + enable_UARTxTRANS_RXE(p_obj->p_instance); + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for transmit. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_transmit_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to TXEND(=1), and TXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_TXEND_W_CLEAR | UARTxSR_TXFF_W_CLEAR); + /*------------------------------*/ + /* Transmit Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*---- UARTxSR ---*/ + /* Check the transmit's end flag. */ + if (((status & UARTxSR_TXEND_MASK) == UARTxSR_TXEND_R_END) || + ((status & UARTxSR_TXFF_MASK) == UARTxSR_TXFF_R_REACHED)) { + TXZ_WorkState txDone = TXZ_BUSY; + /* Read FIFO fill level. */ + uint32_t tlvl = (status & UARTxSR_TLVL_MASK); + tlvl >>= 8; + /* FIFO Max = UART_TX_FIFO_MAX */ + if (tlvl > UART_TX_FIFO_MAX) { + tlvl = UART_TX_FIFO_MAX; + } + /* Get the empty num in FIFO. */ + { + uint32_t work = tlvl; + tlvl = (UART_TX_FIFO_MAX - work); + } + if (tlvl == UART_TX_FIFO_MAX) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + default: + if (p_obj->transmit.info.tx8.num <= p_obj->transmit.rp) { + txDone = TXZ_DONE; + } + break; + } + } + if (txDone == TXZ_DONE) { + /*=== Transmit Done!! ===*/ + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_SUCCESS. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_SUCCESS); + } + } else { + /*=== Transmit Continue ===*/ + /*------------------------------*/ + /* Data Setting */ + /*------------------------------*/ + /*--- UARTxDR ---*/ + /* Only the empty number of FIFO is a transmission data set. */ + uint32_t i = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + /* Set data to FIFO. */ + for (i = 0; (i < tlvl) && (loopBreak == TXZ_BUSY); i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + if (p_obj->transmit.info.tx16.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx16.p_data + p_obj->transmit.rp) & UARTxDR_DR_9BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_8: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + case UART_DATA_LENGTH_7: + if (p_obj->transmit.info.tx8.num > p_obj->transmit.rp) { + p_obj->p_instance->DR = (*(p_obj->transmit.info.tx8.p_data + p_obj->transmit.rp) & UARTxDR_DR_8BIT_MASK); + p_obj->transmit.rp += 1; + } else { + loopBreak = TXZ_DONE; + } + break; + default: + /* no process */ + break; + } + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for receive. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_receive_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t status; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Status Registar Control */ + /*------------------------------*/ + /* Read current UARTxSR. */ + status = p_obj->p_instance->SR; + /* Clear the transmit's end flag. */ + /* Write to RXEND(=1), and RXFF(=1). */ + p_obj->p_instance->SR = (UARTxSR_RXEND_W_CLEAR | UARTxSR_RXFF_W_CLEAR); + /*------------------------------*/ + /* Receive Status Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /* Check the receive's end flag. */ + if (((status & UARTxSR_RXEND_MASK) == UARTxSR_RXEND_R_END) || + ((status & UARTxSR_RXFF_MASK) == UARTxSR_RXFF_R_REACHED)) { + /* Read FIFO fill level. */ + uint32_t rlvl = (status & UARTxSR_RLVL_MASK); + /* FIFO Max = UART_RX_FIFO_MAX */ + if (rlvl > UART_RX_FIFO_MAX) { + rlvl = UART_RX_FIFO_MAX; + } + /*------------------------------*/ + /* Data Read */ + /*------------------------------*/ + /* Read FIFO data. */ + if (rlvl != 0) { + uint32_t i; + for (i = 0; i < rlvl; i++) { + switch (p_obj->init.sm) { + case UART_DATA_LENGTH_9: + *(p_obj->receive.info.rx16.p_data + i) = (uint16_t)(p_obj->p_instance->DR & UARTxDR_DR_9BIT_MASK); + break; + case UART_DATA_LENGTH_8: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_8BIT_MASK); + break; + case UART_DATA_LENGTH_7: + *(p_obj->receive.info.rx8.p_data + i) = (uint8_t)(p_obj->p_instance->DR & UARTxDR_DR_7BIT_MASK); + break; + default: + /* no process */ + break; + } + } + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + uart_receive_t param; + + if (p_obj->init.sm == UART_DATA_LENGTH_9) { + param.rx16.p_data = p_obj->receive.info.rx16.p_data; + param.rx16.num = rlvl; + } else { + param.rx8.p_data = p_obj->receive.info.rx8.p_data; + param.rx8.num = rlvl; + } + /* Call the receive handler with TXZ_SUCCESS. */ + p_obj->receive.handler(p_obj->init.id, TXZ_SUCCESS, ¶m); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief IRQ Handler for error. + * @param p_obj :UART object. + * @retval - + * @note - + */ +/*--------------------------------------------------*/ +void uart_error_irq_handler(uart_t *p_obj) +{ + uint32_t trans; + uint32_t error; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Trans Registar */ + /*------------------------------*/ + /* Read current UARTxTRANS */ + trans = p_obj->p_instance->TRANS; + /*------------------------------*/ + /* Error Registar Control */ + /*------------------------------*/ + /* Read current UARTxERR. */ + error = p_obj->p_instance->ERR; + /* Now, no clear the error flag. */ + /*------------------------------*/ + /* Error Check */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Check the transmit error. */ + /* TRGERR */ + if ((error & UARTxERR_TRGERR_MASK) == UARTxERR_TRGERR_R_ERR) { + /*------------------------------*/ + /* Transmit Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_TXE_MASK) == UARTxTRANS_TXE_ENABLE) { + /*------------------------------*/ + /* Disable Transmit */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to TXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_TXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->transmit.handler != UART_NULL) { + /* Call the transmit handler with TXZ_ERROR. */ + p_obj->transmit.handler(p_obj->init.id, TXZ_ERROR); + } + } + } + /* Check the receive error. */ + { + TXZ_Result err = TXZ_SUCCESS; + /* OVRERR */ + if ((error & UARTxERR_OVRERR_MASK) == UARTxERR_OVRERR_R_ERR) { + err = TXZ_ERROR; + } + /* PERR */ + if ((error & UARTxERR_PERR_MASK) == UARTxERR_PERR_R_ERR) { + err = TXZ_ERROR; + } + /* FERR */ + if ((error & UARTxERR_FERR_MASK) == UARTxERR_FERR_R_ERR) { + err = TXZ_ERROR; + } + /* BERR */ + if ((error & UARTxERR_BERR_MASK) == UARTxERR_BERR_R_ERR) { + err = TXZ_ERROR; + } + if (err == TXZ_ERROR) { + /*------------------------------*/ + /* Receive Check */ + /*------------------------------*/ + if ((trans & UARTxTRANS_RXE_MASK) == UARTxTRANS_RXE_ENABLE) { + /*------------------------------*/ + /* Disable Receive */ + /*------------------------------*/ + /*--- UARTxTRANS ---*/ + /* Write to RXE(=0). */ + /* Bitband Access. */ + disable_UARTxTRANS_RXE(p_obj->p_instance); + /*------------------------------*/ + /* Call Handler */ + /*------------------------------*/ + if (p_obj->receive.handler != UART_NULL) { + /* Call the receive handler with TXZ_ERROR. */ + p_obj->receive.handler(p_obj->init.id, TXZ_ERROR, UART_NULL); + } + } + } + } +} + +/*--------------------------------------------------*/ +/** + * @brief Get status. + * @details Status bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31 | SUE | Setting Enable Flag. Use @ref UART_SettingEnable. | + * | 30-16 | - | - | + * | 15 | TXRUN | Transmitting State Flag. Use @ref UART_TxState. | + * | 14 | TXEND | Transmitting Done Flag. Use @ref UART_TxDone. | + * | 13 | TXFF | Reach Transmitting Fill Level Flag. Use @ref UART_TxReachFillLevel. | + * | 12 | - | - | + * | 11-8 | TLVL | Current Transmitting FIFO Level. Use @ref UART_TxFifoLevel | + * | 7 | RXRUN | Receive State Flag. Use @ref UART_RxState. | + * | 6 | RXEND | Receive Done Flag. Use @ref UART_RxDone. | + * | 5 | RXFF | Reach Receive Fill Level Flag. Use @ref UART_RxReachFillLevel | + * | 4 | - | - | + * | 3-0 | RLVL | Current Receive FIFO Level. Use @ref UART_RxFifoLevel | + * + * @param p_obj :UART object. + * @param p_status :Save area for status. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_status(uart_t *p_obj, uint32_t *p_status) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_status)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Status Read */ + /*------------------------------*/ + /*--- UARTxSR ---*/ + /* Read current UARTxSR. */ + *p_status = p_obj->p_instance->SR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get error information. + * @details Error bits. + * | Bit | Bit Symbol | Function | + * | :--- | :--- | :--- | + * | 31-5 | - | - | + * | 4 | TRGERR | Transmitting Trigger Error. Use @ref UART_TriggerErr. | + * | 3 | OVRERR | Overrun Error. Use @ref UART_OverrunErr. | + * | 2 | PERR | Parity Error. Use @ref UART_ParityErr. | + * | 1 | FERR | Framing Error. Use @ref UART_FramingErr. | + * | 0 | BERR | Break Error Flag. Use @ref UART_BreakErr. | + * + * @param p_obj :UART object. + * @param p_error :Save area for error. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Failure. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_error(uart_t *p_obj, uint32_t *p_error) +{ + TXZ_Result result = TXZ_SUCCESS; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the UART_NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_obj)); + assert_param(IS_POINTER_NOT_NULL(p_obj->p_instance)); + assert_param(IS_POINTER_NOT_NULL(p_error)); +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Error Read */ + /*------------------------------*/ + /*--- UARTxERR ---*/ + /* Read current UARTxERR. */ + *p_error = p_obj->p_instance->ERR; + + return (result); +} + +/*--------------------------------------------------*/ +/** + * @brief Get the setting of boudrate. + * @param clock :Clock(hz) "Phi T0" or "Clock Input A" or "Clock Input B". + * @param p_clk :Select Clock Setting. + * @param boudrate :Boudrate(bps). + * @param p_brd :Save area for Division Setting. + * @retval TXZ_SUCCESS :Success. + * @retval TXZ_ERROR :Not support setting. + * @note - + */ +/*--------------------------------------------------*/ +TXZ_Result uart_get_boudrate_setting(uint32_t clock, uart_clock_t *p_clk, uint32_t boudrate, uart_boudrate_t *p_brd) +{ + TXZ_Result result = TXZ_ERROR; +#if (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) + uint64_t tx = 0; + uint64_t work = 0; + uint64_t range64 = 0; + + /*------------------------------*/ + /* Parameter Check */ + /*------------------------------*/ +#ifdef DEBUG + /* Check the NULL of address. */ + assert_param(IS_POINTER_NOT_NULL(p_clk)); + assert_param(IS_POINTER_NOT_NULL(p_brd)); + /* Check the parameter of UARTxCLK. */ +#endif /* #ifdef DEBUG */ + /*------------------------------*/ + /* Calculate Division Setting */ + /*------------------------------*/ + if ((clock > 0) && (boudrate > 0)) { + /*--- phi Tx ---*/ + uint32_t prescaler = (p_clk->prsel >> 4); + + work = (uint64_t)((uint64_t)1 << prescaler); + tx = (uint64_t)((uint64_t)clock << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + tx /= work; + + /*--- N+(64-K)/64 division ---*/ + { + uint8_t k = 0; + TXZ_WorkState loopBreak = TXZ_BUSY; + + work = ((uint64_t)boudrate); + tx /= work; + tx >>= 4; + for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX) && (loopBreak == TXZ_BUSY); k++) { + work = tx + (uint64_t)k; + if (work >= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT)) { + work -= (uint64_t)((uint64_t)1 << UART_CFG_BOUDRATE_FIXED_POINT_BIT); + work >>= UART_CFG_BOUDRATE_FIXED_POINT_BIT; /* Now, omit the figures below the decimal place. */ + if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) { + uint64_t workRange = 0; + + /* Verification */ + if (verification_boudrate64(clock, p_clk, boudrate, (uint32_t)k, (uint32_t)work, &workRange) == TXZ_SUCCESS) { +#if (UART_CFG_GET_BOUDRATE_TYPE == UART_CFG_GET_BOUDRATE_TYPE_ALL) + /* Compare the previous range. */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + range64 = workRange; + } + result = TXZ_SUCCESS; +#else + /* Finish!! */ + if (result == TXZ_SUCCESS) { + if (range64 > workRange) { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + } else { + p_brd->ken = UART_DIVISION_ENABLE; + p_brd->brk = (uint32_t)k; + p_brd->brn = (uint32_t)work; + } + result = TXZ_SUCCESS; + loopBreak = TXZ_DONE; +#endif + } + } + } + } + } + } +#endif /* (UART_CFG_GET_BOUDRATE == UART_CFG_GET_BOUDRATE_ENABLE) */ + + return (result); +} + +/** + * @} + */ /* End of group UART_Exported_functions */ + +/** + * @} + */ /* End of group UART */ + +/** + * @} + */ /* End of group Periph_Driver */ + +#endif /* defined(__UART_H) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PeripheralNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PeripheralNames.h new file mode 100644 index 00000000000..652ec491ab7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PeripheralNames.h @@ -0,0 +1,151 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + SERIAL_0 = 0, + SERIAL_1, + SERIAL_2, + SERIAL_3, + INVALID_SERIAL = (int)NC +} UARTName; + + +typedef enum { + PWM_0 = 0, + PWM_1, + PWM_2, + PWM_3, + PWM_4, + INVALID_PWM = (int)NC +} PWMName; + +typedef enum { + ADC_A0 = 0, + ADC_A1, + ADC_A2, + ADC_A3, + ADC_A4, + ADC_A5, + ADC_A6, + ADC_A7, + ADC_A8, + ADC_A9, + ADC_A10, + ADC_A11, + ADC_A12, + ADC_A13, + ADC_A14, + ADC_A15, + ADC_A16, + ADC_A17, + ADC_A18, + INVALID_ADC = (int)NC +} ADCName; + +typedef enum { + I2C_0 = 0, + I2C_1, + INVALID_I2C = (int)NC +} I2CName; + +typedef enum { + SPI_0 = 0, + SPI_1, + INVALID_SPI = (int)NC +} SPIName; + +typedef enum { + GPIO_IRQ_0 = 0, + GPIO_IRQ_1, + GPIO_IRQ_2, + GPIO_IRQ_3, + GPIO_IRQ_4, + GPIO_IRQ_5, + GPIO_IRQ_6, + GPIO_IRQ_7, + GPIO_IRQ_8, + GPIO_IRQ_9, + GPIO_IRQ_A, + GPIO_IRQ_B, + GPIO_IRQ_C, + GPIO_IRQ_D, + GPIO_IRQ_E, + GPIO_IRQ_F, + GPIO_IRQ_10, + GPIO_IRQ_11, + GPIO_IRQ_12, + GPIO_IRQ_13, + GPIO_IRQ_14, + GPIO_IRQ_15, + INVALID_GPIO_IRQ = (int)NC +} GPIO_IRQName; + +// DAP UART +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif + +#define SERIAL_TX CONSOLE_TX +#define SERIAL_RX CONSOLE_RX + +#define STDIO_UART SERIAL_0 + +// TxD RxD +#define MBED_UART0 PC0, PC1 +#define MBED_UART1 PC4, PC5 +#define MBED_UART2 PU0, PU1 +#define MBED_UART3 PF6, PF7 +#define MBED_UARTUSB CONSOLE_TX, CONSOLE_RX + +// SDA SCK +#define MBED_I2C0 PD3, PD4 + +// MOSI, MISO, SCLK SS +#define MBED_SPI0 PA3, PA2, PA4, PA1 +#define MBED_SPI1 PG5, PG4, PG6, PG1 + +#define MBED_ANALOGIN0 A0 +#define MBED_ANALOGIN1 A1 +#define MBED_ANALOGIN2 A2 +#define MBED_ANALOGIN3 A3 +#define MBED_ANALOGIN4 A4 +#define MBED_ANALOGIN5 A5 + +#define MBED_PWMOUT0 PF4 +#define MBED_PWMOUT2 PU2 +#define MBED_PWMOUT3 PC2 +#define MBED_PWMOUT4 PN1 + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PinNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PinNames.h new file mode 100644 index 00000000000..f3916b221d5 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PinNames.h @@ -0,0 +1,146 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0xFF) +#define PIN_POS(X) ((uint32_t)(X) & 0x7) + +// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction +#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0)) +#define PIN_FUNC(X) (((X) & 0xffff0000) >> 16) +#define PIN_DIR(X) ((X) & 0xffff) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT, + PIN_INOUT +} PinDirection; + +typedef enum { + // TMPM4KN Pin Names + PA0 = 0 << 3, PA1, PA2, PA3, PA4, + PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7, + PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6, PC7, + PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5, + PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7, + PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7, + PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, + PH0 = 7 << 3, PH1, + PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5, + PK0 = 9 << 3, PK1, PK2, PK3, PK4, + PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7, + PM0 = 11 << 3, PM1, PM2, + PN0 = 12 << 3, PN1, PN2, + PU0 = 13 << 3, PU1, PU2, PU3, PU4, PU5, PU6, PU7, + PV0 = 14 << 3, PV1, + + // External data bus Pin Names + D0 = PF7, + D1 = PF6, + D2 = PD4, + D3 = PD5, + D4 = PC6, + D5 = PC7, + D6 = PA0, + D7 = PC3, + D8 = PD0, + D9 = PD1, + D10 = PG1, + D11 = PG5, + D12 = PG4, + D13 = PG6, + D14 = PC0, + D15 = PC1, + + // Analogue in pins + A0 = PM2, + A1 = PM1, + A2 = PM0, + A3 = PL3, + A4 = PL1, + + // DAP_UART + CONSOLE_TX = PC0, + CONSOLE_RX = PC1, + MBEDIF_TXD = CONSOLE_TX, + MBEDIF_RXD = CONSOLE_RX, + + // Push buttons + SW1 = PG3, + SW2 = PG4, + SW3 = PG5, + SW4 = PG6, + + + // TSPI2 + MOSI = D11, + MISO = D12, + SCLK = D13, + CS = D10, + + // SD Shield TSPI2 + SD_SEL = CS, // Chip select + SD_CLK = SCLK, // SPI clock + SD_MISO = MISO, // Master in Salve out + SD_MOSI = MOSI, // Master out Salve in + + // I2C pins + SDA = PD3, + SCL = PD4, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +// LED definitions +#define LED1 PB0 +#define LED2 PB2 +#define LED3 PB4 +#define LED4 PV0 +#define LED5 PV1 +#define LED6 PB6 + +// Standardized button names +#define BUTTON1 SW1 +#define BUTTON2 SW2 +#define BUTTON3 SW3 +#define BUTTON4 SW4 + +//I2C +#define I2C_SDA SDA +#define I2C_SCL SCL + +typedef enum { + PullUp = 0, + PullDown, + PullNone, + OpenDrain, + PullDefault = PullDown +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PortNames.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PortNames.h new file mode 100644 index 00000000000..6cc712c1a80 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/PortNames.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB, + PortC, + PortD, + PortE, + PortF, + PortG, + PortH, + PortJ, + PortK, + PortL, + PortM, + PortN, + PortU, + PortV, +} PortName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/analogin_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/analogin_api.c new file mode 100644 index 00000000000..de8fa0fd85e --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/analogin_api.c @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "analogin_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "txzp_adc_include.h" + +#define ADC_12BIT_RANGE 0xFFF +#define CONVERSION_FLAG 0x4 +#define SINGLE_CONVERSION 0xF + +static const PinMap PinMap_ADC[] = { + {PM2, ADC_A5, PIN_DATA(0, 0)}, + {PM1, ADC_A6, PIN_DATA(0, 0)}, + {PM0, ADC_A7, PIN_DATA(0, 0)}, + {PL7, ADC_A8, PIN_DATA(0, 0)}, + {PL6, ADC_A9, PIN_DATA(0, 0)}, + {PL5, ADC_A13, PIN_DATA(0, 0)}, + {PL3, ADC_A14, PIN_DATA(0, 0)}, + {PL1, ADC_A15, PIN_DATA(0, 0)}, + {PL0, ADC_A16, PIN_DATA(0, 0)}, + {PL2, ADC_A17, PIN_DATA(0, 0)}, + {PL4, ADC_A18, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + // Check that pin belong to ADC module + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + + MBED_ASSERT(obj->adc != (ADCName)NC); + + // Enable ADC clock supply + TSB_CG_FSYSMENB_IPMENB02 = TXZ_ENABLE; + TSB_CG_SPCLKEN_ADCKEN0 = TXZ_ENABLE; + TSB_CG_SPCLKEN_TRCKEN = TXZ_ENABLE; + + // Enable clock for GPIO + if (obj->adc <= ADC_A7) { + // Enable clock for GPIO port M + TSB_CG_FSYSMENA_IPMENA11 = TXZ_ENABLE; + } else if (obj->adc <= ADC_A18) { + // Enable clock for GPIO port L + TSB_CG_FSYSMENA_IPMENA10 = TXZ_ENABLE; + } else { + // Nothing when its NC + } + + // Set pin function as ADC + pinmap_pinout(pin, PinMap_ADC); + + // Initialize + obj->p_adc.p_instance = TSB_ADA; + obj->p_adc.init.id = SINGLE_CONVERSION; + obj->p_adc.init.convert_time = ADC_CONVERT_TIME_0_96_AVDD_4_5; + obj->p_adc.init.rcut = ADC_RCUT_NORMAL; + obj->p_adc.handler = NULL; + obj->pin = pin; + + if (adc_init(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : ADC Initialization"); + } + + // ADC channel setting + obj->param.ain = obj->adc; + + if (adc_channel_setting(&obj->p_adc, obj->param.ain, &obj->param) != TXZ_SUCCESS) { + error("Failed : ADC channel setting"); + } +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t adc_result = 0; + + // Assert that ADC channel is valid + MBED_ASSERT(obj->adc != (ADCName)NC); + + if (adc_start(&obj->p_adc) == TXZ_SUCCESS) { + // adc started + } + + // Wait until AD conversion complete + while ((obj->p_adc.p_instance->ST & CONVERSION_FLAG)) { + // Do nothing + } + + if (adc_channel_get_value(&obj->p_adc, obj->param.ain, &adc_result) != TXZ_SUCCESS) { + error("Failed : To read ADC converted result"); + } + + if (adc_stop(&obj->p_adc) != TXZ_SUCCESS) { + error("Failed : To Stop ADC Conversion"); + } + + return (uint16_t)adc_result; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = 0; + + value = analogin_read_u16(obj); + + return (float)(value * (1.0f / (float)ADC_12BIT_RANGE)); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/crc_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/crc_api.c new file mode 100644 index 00000000000..2ced07a8cd8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/crc_api.c @@ -0,0 +1,80 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "crc_api.h" +#include "device.h" + +#ifdef DEVICE_CRC + +static bool reflect_in; +static bool reflect_out; +static uint32_t final_xor; + +bool hal_crc_is_supported(const crc_mbed_config_t *config) +{ + return (config != NULL); +} + +void hal_crc_compute_partial_start(const crc_mbed_config_t *config) +{ + TSB_CG_FSYSENA_IPENA00 = TXZ_ENABLE; + + // Intial Value as initial_xor + TSB_CRC->CLC = config->initial_xor; + reflect_in = config->reflect_in; + reflect_out = config->reflect_out; + final_xor = config->final_xor; + + // Data width setting CRC data width is 8 bits (--01) + // Form setting CRC form is CRC16 (00--) or CRC32 (11--) + TSB_CRC->TYP = config->width == 16 ? 0x01 : 0x0D; +} + +void hal_crc_compute_partial(const uint8_t *data, const size_t size) +{ + if (data && size) { + uint32_t index = 0U; + bool reflect = reflect_in; + for (index = 0U; index < size; index++) { + unsigned int byte = data[index]; + if (reflect) { + byte = __RBIT(byte) >> 24; + } + TSB_CRC->DIN = byte; + } + } +} + +uint32_t hal_crc_get_result(void) +{ + uint32_t result; + + // Note: Please read [CRCCLC] twice and use the result of the 2nd time + result = TSB_CRC->CLC; + result = TSB_CRC->CLC; + if (reflect_out) { + result = __RBIT(result); + if ((TSB_CRC->TYP & 0x0C) == 0) { + result >>= 16; + } + } + result ^= final_xor; + + return (result); +} +#endif // DEVICE_CRC diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device.h new file mode 100644 index 00000000000..7fd26fc35e5 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device.h @@ -0,0 +1,25 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 32 + +#include +#include "objects.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TMPM4KNA.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TMPM4KNA.h new file mode 100644 index 00000000000..69e34cc37e8 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TMPM4KNA.h @@ -0,0 +1,4157 @@ +/** + ******************************************************************************* + * @file TMPM4KNA.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4KNA' Device Series + * @version V1.0.0.0 + * $Date:: #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +/** @addtogroup TOSHIBA_TXZ_MICROCONTROLLER + * @{ + */ + +/** @addtogroup TMPM4KNA + * @{ + */ + +#ifndef __TMPM4KNA_H__ +#define __TMPM4KNA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/** Interrupt Number Definition */ +typedef enum IRQn { + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** TMPM4KNA Specific Interrupt Numbers *******************************************************************/ + INT00_IRQn = 0, /*!< Interrupt pin 00 */ + INT01_IRQn = 1, /*!< Interrupt pin 01a/00b */ + INT02_IRQn = 2, /*!< Interrupt pin 02a/00b */ + INT03_IRQn = 3, /*!< Interrupt pin 03a/03b */ + INT04_IRQn = 4, /*!< Interrupt pin 04a/04b */ + INT05_IRQn = 5, /*!< Interrupt pin 05a/05b */ + INT06_IRQn = 6, /*!< Interrupt pin 06a/06b */ + INT07_IRQn = 7, /*!< Interrupt pin 07a/07b */ + INT08_IRQn = 8, /*!< Interrupt pin 08a/08b */ + INT09_IRQn = 9, /*!< Interrupt pin 09 */ + INT10_IRQn = 10, /*!< Interrupt pin 10 */ + INT11_IRQn = 11, /*!< Interrupt pin 11a/11b */ + INT12_IRQn = 12, /*!< Interrupt pin 12 */ + INT13_IRQn = 13, /*!< Interrupt pin 13 */ + INT14_IRQn = 14, /*!< Interrupt pin 14a/14b */ + INT15_IRQn = 15, /*!< Interrupt pin 15 */ + INT16_IRQn = 16, /*!< Interrupt pin 16a/16b */ + INT17_IRQn = 17, /*!< Interrupt pin 17a/17b */ + INT18_IRQn = 18, /*!< Interrupt pin 18a/18b */ + INT21_IRQn = 21, /*!< Interrupt pin 21 */ + INTVCN0_IRQn = 22, /*!< A-VE+ ch0 Interrupt */ + INTVCT0_IRQn = 23, /*!< A-VE+ ch0 Task termination interrupt */ + INTEMG0_IRQn = 24, /*!< A-PMD ch0 EMG interrupt */ + INTEMG1_IRQn = 25, /*!< A-PMD ch1 EMG interrupt */ + INTEMG2_IRQn = 26, /*!< A-PMD ch2 EMG interrupt */ + INTOVV0_IRQn = 27, /*!< A-PMD ch0 OVV interrupt */ + INTOVV1_IRQn = 28, /*!< A-PMD ch1 OVV interrupt */ + INTOVV2_IRQn = 29, /*!< A-PMD ch2 OVV interrupt */ + INTPWM0_IRQn = 30, /*!< A-PMD ch0 PWM interrupt */ + INTPWM1_IRQn = 31, /*!< A-PMD ch1 PWM interrupt */ + INTPWM2_IRQn = 32, /*!< A-PMD ch2 PWM interrupt */ + INTENC00_IRQn = 33, /*!< A-ENC32 ch0 Encoder interrupt 0 */ + INTENC01_IRQn = 34, /*!< A-ENC32 ch0 Encoder interrupt 1 */ + INTENC10_IRQn = 35, /*!< A-ENC32 ch1 Encoder interrupt 0 */ + INTENC11_IRQn = 36, /*!< A-ENC32 ch1 Encoder interrupt 1 */ + INTENC20_IRQn = 37, /*!< A-ENC32 ch2 Encoder interrupt 0 */ + INTENC21_IRQn = 38, /*!< A-ENC32 ch2 Encoder interrupt 1 */ + INTADAPDA_IRQn = 39, /*!< ADC unit A PMD trigger program interrupt A */ + INTADAPDB_IRQn = 40, /*!< ADC unit A PMD trigger program interrupt B */ + INTADACP0_IRQn = 41, /*!< ADC unit A Monitor function 0 interrupt */ + INTADACP1_IRQn = 42, /*!< ADC unit A Monitor function 1 interrupt */ + INTADATRG_IRQn = 43, /*!< ADC unit A General purpose trigger program interrupt */ + INTADASGL_IRQn = 44, /*!< ADC unit A Single program interrupt */ + INTADACNT_IRQn = 45, /*!< ADC unit A Continuity program interrupt */ + INTADBPDA_IRQn = 46, /*!< ADC unit B PMD trigger program interrupt A */ + INTADBPDB_IRQn = 47, /*!< ADC unit B PMD trigger program interrupt B */ + INTADBCP0_IRQn = 48, /*!< ADC unit B Monitor function 0 interrupt */ + INTADBCP1_IRQn = 49, /*!< ADC unit B Monitor function 1 interrupt */ + INTADBTRG_IRQn = 50, /*!< ADC unit B General purpose trigger program interrupt */ + INTADBSGL_IRQn = 51, /*!< ADC unit B Single program interrupt */ + INTADBCNT_IRQn = 52, /*!< ADC unit B Continuity program interrupt */ + INTADCPDA_IRQn = 53, /*!< ADC unit C PMD trigger program interrupt A */ + INTADCPDB_IRQn = 54, /*!< ADC unit C PMD trigger program interrupt B */ + INTADCCP0_IRQn = 55, /*!< ADC unit C Monitor function 0 interrupt */ + INTADCCP1_IRQn = 56, /*!< ADC unit C Monitor function 1 interrupt */ + INTADCTRG_IRQn = 57, /*!< ADC unit C General purpose trigger program interrupt */ + INTADCSGL_IRQn = 58, /*!< ADC unit C Single program interrupt */ + INTADCCNT_IRQn = 59, /*!< ADC unit C Continuity program interrupt */ + INTSC0RX_IRQn = 60, /*!< TSPI/UART ch0 Reception interrupt */ + INTSC0TX_IRQn = 61, /*!< TSPI/UART ch0 Transmit interrupt */ + INTSC0ERR_IRQn = 62, /*!< TSPI/UART ch0 Error interrupt */ + INTSC1RX_IRQn = 63, /*!< TSPI/UART ch1 Reception interrupt */ + INTSC1TX_IRQn = 64, /*!< TSPI/UART ch1 Transmit interrupt */ + INTSC1ERR_IRQn = 65, /*!< TSPI/UART ch1 Error interrupt */ + INTSC2RX_IRQn = 66, /*!< UART ch2 Reception interrupt */ + INTSC2TX_IRQn = 67, /*!< UART ch2 Transmit interrupt */ + INTSC2ERR_IRQn = 68, /*!< UART ch2 Error interrupt */ + INTSC3RX_IRQn = 69, /*!< UART ch3 Reception interrupt */ + INTSC3TX_IRQn = 70, /*!< UART ch3 Transmit interrupt */ + INTSC3ERR_IRQn = 71, /*!< UART ch3 Error interrupt */ + INTI2C0NST_IRQn = 72, /*!< I2C ch0 Interrupt / EI2C ch0 Status interrupt */ + INTI2C0ATX_IRQn = 73, /*!< I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt*/ + INTI2C0BRX_IRQn = 74, /*!< I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt*/ + INTI2C0NA_IRQn = 75, /*!< I2C ch0 NACK detection interrupt */ + INTI2C1NST_IRQn = 76, /*!< I2C ch1 Interrupt / EI2C ch1 Status interrupt */ + INTI2C1ATX_IRQn = 77, /*!< I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt*/ + INTI2C1BRX_IRQn = 78, /*!< I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt*/ + INTI2C1NA_IRQn = 79, /*!< I2C ch1 NACK detection interrupt */ + INTT32A00AC_IRQn = 83, /*!< T32A ch0 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A00ACCAP0_IRQn = 84, /*!< T32A ch0 Timer A/C Input capture 0 */ + INTT32A00ACCAP1_IRQn = 85, /*!< T32A ch0 Timer A/C Input capture 1 */ + INTT32A00B_IRQn = 86, /*!< T32A ch0 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A00BCAP0_IRQn = 87, /*!< T32A ch0 Timer B Input capture 0 */ + INTT32A00BCAP1_IRQn = 88, /*!< T32A ch0 Timer B Input capture 1 */ + INTT32A01AC_IRQn = 89, /*!< T32A ch1 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A01ACCAP0_IRQn = 90, /*!< T32A ch1 Timer A/C Input capture 0 */ + INTT32A01ACCAP1_IRQn = 91, /*!< T32A ch1 Timer A/C Input capture 1 */ + INTT32A01B_IRQn = 92, /*!< T32A ch1 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A01BCAP0_IRQn = 93, /*!< T32A ch1 Timer B Input capture 0 */ + INTT32A01BCAP1_IRQn = 94, /*!< T32A ch1 Timer B Input capture 1 */ + INTT32A02AC_IRQn = 95, /*!< T32A ch2 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A02ACCAP0_IRQn = 96, /*!< T32A ch2 Timer A/C Input capture 0 */ + INTT32A02ACCAP1_IRQn = 97, /*!< T32A ch2 Timer A/C Input capture 1 */ + INTT32A02B_IRQn = 98, /*!< T32A ch2 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A02BCAP0_IRQn = 99, /*!< T32A ch2 Timer B Input capture 0 */ + INTT32A02BCAP1_IRQn = 100, /*!< T32A ch2 Timer B Input capture 1 */ + INTT32A03AC_IRQn = 101, /*!< T32A ch3 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A03ACCAP0_IRQn = 102, /*!< T32A ch3 Timer A/C Input capture 0 */ + INTT32A03ACCAP1_IRQn = 103, /*!< T32A ch3 Timer A/C Input capture 1 */ + INTT32A03B_IRQn = 104, /*!< T32A ch3 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A03BCAP0_IRQn = 105, /*!< T32A ch3 Timer B Input capture 0 */ + INTT32A03BCAP1_IRQn = 106, /*!< T32A ch3 Timer B Input capture 1 */ + INTT32A04AC_IRQn = 107, /*!< T32A ch4 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A04ACCAP0_IRQn = 108, /*!< T32A ch4 Timer A/C Input capture 0 */ + INTT32A04ACCAP1_IRQn = 109, /*!< T32A ch4 Timer A/C Input capture 1 */ + INTT32A04B_IRQn = 110, /*!< T32A ch4 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A04BCAP0_IRQn = 111, /*!< T32A ch4 Timer B Input capture 0 */ + INTT32A04BCAP1_IRQn = 112, /*!< T32A ch4 Timer B Input capture 1 */ + INTT32A05AC_IRQn = 113, /*!< T32A ch5 Timer A/C Compare match detection / Over flow / Under flow*/ + INTT32A05ACCAP0_IRQn = 114, /*!< T32A ch5 Timer A/C Input capture 0 */ + INTT32A05ACCAP1_IRQn = 115, /*!< T32A ch5 Timer A/C Input capture 1 */ + INTT32A05B_IRQn = 116, /*!< T32A ch5 Timer B Compare match detection / Over flow / Under flow*/ + INTT32A05BCAP0_IRQn = 117, /*!< T32A ch5 Timer B Input capture 0 */ + INTT32A05BCAP1_IRQn = 118, /*!< T32A ch5 Timer B Input capture 1 */ + INTPARI0_IRQn = 119, /*!< RAMP ch0 Parity error interrupt */ + INTPARI1_IRQn = 120, /*!< RAMP ch1 Parity error interrupt */ + INTDMAATC_IRQn = 121, /*!< DMAC unit A End of transfer (ch0 - 31) */ + INTDMAAERR_IRQn = 122, /*!< DMAC unit A Transfer error */ + INTFLCRDY_IRQn = 123, /*!< Code FLASH Ready interrupt */ + INTFLDRDY_IRQn = 124 /*!< Data FLASH Ready interrupt */ +} IRQn_Type; + +/** Processor and Core Peripheral Section */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_TMPM4KyA.h" /* TMPM4KNA System */ + +/** @addtogroup Device_Peripheral_registers + * @{ + */ + +/** Device Specific Peripheral registers structures */ + +/** + * @brief Interrupt control A Register (IA) + */ +typedef struct { + __IO uint8_t NIC00; /*!< Non Maskable Interrupt Control Register(A) 00*/ +} TSB_IA_TypeDef; + +/** + * @brief Reset Low power Management Register (RLM) + */ +typedef struct { + uint8_t RESERVED0[2]; + __IO uint8_t RSTFLG0; /*!< Reset flag register 0 */ + __IO uint8_t RSTFLG1; /*!< Reset flag register 1 */ +} TSB_RLM_TypeDef; + +/** + * @brief Voltage detection circuit (LVD) + */ +typedef struct { + __IO uint8_t CR; /*!< LVD Control register */ +} TSB_LVD_TypeDef; + +/** + * @brief RAM Parity (RAMP) + */ +typedef struct { + __IO uint32_t CTL; /*!< RAM Parity control register */ + __I uint32_t ST; /*!< RAM Parity status register */ + __O uint32_t CLR; /*!< RAM Parity status clear register */ + __I uint32_t EAD0; /*!< RAM Parity Error address register 0 */ + __I uint32_t EAD1; /*!< RAM Parity Error address register 1 */ +} TSB_RPAR_TypeDef; + +/** + * @brief CRC Calculation Circuit (CRC) + */ +typedef struct { + __IO uint32_t DIN; /*!< CRC input data register */ + uint32_t RESERVED0[4]; + __IO uint32_t TYP; /*!< CRC data type register */ + uint32_t RESERVED1[5]; + __IO uint32_t CLC; /*!< CRC calculation result register */ +} TSB_CRC_TypeDef; + +/** + * @brief Clock Control and Operation Mode (CG) + */ +typedef struct { + __IO uint32_t PROTECT; /*!< Protect Register */ + __IO uint32_t OSCCR; /*!< Oscillation Control Register */ + __IO uint32_t SYSCR; /*!< System Clock Control Register */ + __IO uint32_t STBYCR; /*!< Standby Control Register */ + uint32_t RESERVED0[4]; + __IO uint32_t PLL0SEL; /*!< PLL Selection Register 0 */ + uint32_t RESERVED1[3]; + __IO uint32_t WUPHCR; /*!< High speed OSC Warming-up Register */ + uint32_t RESERVED2[5]; + __IO uint32_t FSYSMENA; /*!< Middle fsys Supply Stop Register A */ + __IO uint32_t FSYSMENB; /*!< Middle fsys Supply Stop Register B */ + __IO uint32_t FSYSENA; /*!< High fsys Supply Stop Register A */ + uint32_t RESERVED3; + __IO uint32_t FCEN; /*!< FC Supply Stop Register */ + __IO uint32_t SPCLKEN; /*!< ADC/TRACE Clock Supply Stop Register */ +} TSB_CG_TypeDef; + +/** + * @brief Interrupt Control B Register (IB) + */ +typedef struct { + uint8_t RESERVED0[16]; + __IO uint8_t NIC00; /*!< Non maskable Interrupt Control Register(B) 00*/ + uint8_t RESERVED1[79]; + __IO uint8_t IMC000; /*!< Interrupt Mode Control Register(B) 000 */ + __IO uint8_t IMC001; /*!< Interrupt Mode Control Register(B) 001 */ + __IO uint8_t IMC002; /*!< Interrupt Mode Control Register(B) 002 */ + __IO uint8_t IMC003; /*!< Interrupt Mode Control Register(B) 003 */ + __IO uint8_t IMC004; /*!< Interrupt Mode Control Register(B) 004 */ + __IO uint8_t IMC005; /*!< Interrupt Mode Control Register(B) 005 */ + __IO uint8_t IMC006; /*!< Interrupt Mode Control Register(B) 006 */ + __IO uint8_t IMC007; /*!< Interrupt Mode Control Register(B) 007 */ + __IO uint8_t IMC008; /*!< Interrupt Mode Control Register(B) 008 */ + __IO uint8_t IMC009; /*!< Interrupt Mode Control Register(B) 009 */ + __IO uint8_t IMC010; /*!< Interrupt Mode Control Register(B) 010 */ + __IO uint8_t IMC011; /*!< Interrupt Mode Control Register(B) 011 */ + __IO uint8_t IMC012; /*!< Interrupt Mode Control Register(B) 012 */ + __IO uint8_t IMC013; /*!< Interrupt Mode Control Register(B) 013 */ + __IO uint8_t IMC014; /*!< Interrupt Mode Control Register(B) 014 */ + __IO uint8_t IMC015; /*!< Interrupt Mode Control Register(B) 015 */ + __IO uint8_t IMC016; /*!< Interrupt Mode Control Register(B) 016 */ + __IO uint8_t IMC017; /*!< Interrupt Mode Control Register(B) 017 */ + __IO uint8_t IMC018; /*!< Interrupt Mode Control Register(B) 018 */ + __IO uint8_t IMC019; /*!< Interrupt Mode Control Register(B) 019 */ + __IO uint8_t IMC020; /*!< Interrupt Mode Control Register(B) 020 */ + __IO uint8_t IMC021; /*!< Interrupt Mode Control Register(B) 021 */ + __IO uint8_t IMC022; /*!< Interrupt Mode Control Register(B) 022 */ + __IO uint8_t IMC023; /*!< Interrupt Mode Control Register(B) 023 */ + __IO uint8_t IMC024; /*!< Interrupt Mode Control Register(B) 024 */ + __IO uint8_t IMC025; /*!< Interrupt Mode Control Register(B) 025 */ + __IO uint8_t IMC026; /*!< Interrupt Mode Control Register(B) 026 */ + __IO uint8_t IMC027; /*!< Interrupt Mode Control Register(B) 027 */ + __IO uint8_t IMC028; /*!< Interrupt Mode Control Register(B) 028 */ + __IO uint8_t IMC029; /*!< Interrupt Mode Control Register(B) 029 */ + __IO uint8_t IMC030; /*!< Interrupt Mode Control Register(B) 030 */ + __IO uint8_t IMC031; /*!< Interrupt Mode Control Register(B) 031 */ + __IO uint8_t IMC032; /*!< Interrupt Mode Control Register(B) 032 */ + __IO uint8_t IMC033; /*!< Interrupt Mode Control Register(B) 033 */ + __IO uint8_t IMC034; /*!< Interrupt Mode Control Register(B) 034 */ + __IO uint8_t IMC035; /*!< Interrupt Mode Control Register(B) 035 */ + __IO uint8_t IMC036; /*!< Interrupt Mode Control Register(B) 036 */ + __IO uint8_t IMC037; /*!< Interrupt Mode Control Register(B) 037 */ + __IO uint8_t IMC038; /*!< Interrupt Mode Control Register(B) 038 */ + __IO uint8_t IMC039; /*!< Interrupt Mode Control Register(B) 039 */ + __IO uint8_t IMC040; /*!< Interrupt Mode Control Register(B) 040 */ + __IO uint8_t IMC041; /*!< Interrupt Mode Control Register(B) 041 */ + __IO uint8_t IMC042; /*!< Interrupt Mode Control Register(B) 042 */ + __IO uint8_t IMC043; /*!< Interrupt Mode Control Register(B) 043 */ + __IO uint8_t IMC044; /*!< Interrupt Mode Control Register(B) 044 */ + __IO uint8_t IMC045; /*!< Interrupt Mode Control Register(B) 045 */ + __IO uint8_t IMC046; /*!< Interrupt Mode Control Register(B) 046 */ + __IO uint8_t IMC047; /*!< Interrupt Mode Control Register(B) 047 */ + __IO uint8_t IMC048; /*!< Interrupt Mode Control Register(B) 048 */ + __IO uint8_t IMC049; /*!< Interrupt Mode Control Register(B) 049 */ + __IO uint8_t IMC050; /*!< Interrupt Mode Control Register(B) 050 */ + __IO uint8_t IMC051; /*!< Interrupt Mode Control Register(B) 051 */ + __IO uint8_t IMC052; /*!< Interrupt Mode Control Register(B) 052 */ + __IO uint8_t IMC053; /*!< Interrupt Mode Control Register(B) 053 */ + __IO uint8_t IMC054; /*!< Interrupt Mode Control Register(B) 054 */ + __IO uint8_t IMC055; /*!< Interrupt Mode Control Register(B) 055 */ + __IO uint8_t IMC056; /*!< Interrupt Mode Control Register(B) 056 */ + __IO uint8_t IMC057; /*!< Interrupt Mode Control Register(B) 057 */ + __IO uint8_t IMC058; /*!< Interrupt Mode Control Register(B) 058 */ + __IO uint8_t IMC059; /*!< Interrupt Mode Control Register(B) 059 */ + __IO uint8_t IMC060; /*!< Interrupt Mode Control Register(B) 060 */ + __IO uint8_t IMC061; /*!< Interrupt Mode Control Register(B) 061 */ + __IO uint8_t IMC062; /*!< Interrupt Mode Control Register(B) 062 */ + __IO uint8_t IMC063; /*!< Interrupt Mode Control Register(B) 063 */ + __IO uint8_t IMC064; /*!< Interrupt Mode Control Register(B) 064 */ + uint8_t RESERVED2[4]; + __IO uint8_t IMC069; /*!< Interrupt Mode Control Register(B) 069 */ +} TSB_IB_TypeDef; + +/** + * @brief Interrupt Monitor Register (IMN) + */ +typedef struct { + __I uint32_t FLGNMI; /*!< NMI Interrupt Monitor Flag */ + uint32_t RESERVED0[2]; + __I uint32_t FLG3; /*!< Interrupt Monitor Flag 3 (096 - 127) */ + __I uint32_t FLG4; /*!< Interrupt Monitor Flag 4 (128 - 159) */ + __I uint32_t FLG5; /*!< Interrupt Monitor Flag 5 (160 - 191) */ +} TSB_IMN_TypeDef; + +/** + * @brief Digital Noise Filter (DNF) + */ +typedef struct { + __IO uint32_t CKCR; /*!< DNF clock Control register */ + __IO uint32_t ENCR; /*!< DNF Enable register */ +} TSB_DNF_TypeDef; + +/** + * @brief Trigger Selection circuit (TSEL) + */ +typedef struct { + __IO uint32_t CR0; /*!< TRGSEL Control register 0 */ + __IO uint32_t CR1; /*!< TRGSEL Control register 1 */ + __IO uint32_t CR2; /*!< TRGSEL Control register 2 */ + __IO uint32_t CR3; /*!< TRGSEL Control register 3 */ + __IO uint32_t CR4; /*!< TRGSEL Control register 4 */ + __IO uint32_t CR5; /*!< TRGSEL Control register 5 */ + __IO uint32_t CR6; /*!< TRGSEL Control register 6 */ + __IO uint32_t CR7; /*!< TRGSEL Control register 7 */ + __IO uint32_t CR8; /*!< TRGSEL Control register 8 */ + __IO uint32_t CR9; /*!< TRGSEL Control register 9 */ + __IO uint32_t CR10; /*!< TRGSEL Control register 10 */ +} TSB_TSEL_TypeDef; + +/** + * @brief Watchdog Timer (SIWD) + */ +typedef struct { + __IO uint32_t PRO; /*!< SIWD Protect Register */ + __IO uint32_t EN; /*!< SIWD Enable Register */ + __O uint32_t CR; /*!< SIWD Control Register */ + __IO uint32_t MOD; /*!< SIWD Mode Register */ + __I uint32_t MONI; /*!< SIWD Count Monitor Register */ + __IO uint32_t OSCCR; /*!< SIWD Oscillator Control Register */ +} TSB_SIWD_TypeDef; + +/** + * @brief Non-Break Debug Interface (NBD) + */ +typedef struct { + __IO uint32_t CR0; /*!< NBD control register 0 */ + __IO uint32_t CR1; /*!< NBD control register 1 */ +} TSB_NBD_TypeDef; + +/** + * @brief Direct Memory Access Controller (DMAC) + */ +typedef struct { + __I uint32_t STATUS; /*!< DMA Status Register */ + __O uint32_t CFG; /*!< DMA Configuration Register */ + __IO uint32_t CTRLBASEPTR; /*!< DMA Control Data Base Pointer Register */ + __I uint32_t ALTCTRLBASEPTR; /*!< DMA Channel Alternate Control Data Base +Pointer Register*/ + uint32_t RESERVED0; + __O uint32_t CHNLSWREQUEST; /*!< DMA Channel Software Request Register */ + __IO uint32_t CHNLUSEBURSTSET; /*!< DMA Channel Useburst Set Register */ + __O uint32_t CHNLUSEBURSTCLR; /*!< DMA Channel Useburst Clear Register */ + __IO uint32_t CHNLREQMASKSET; /*!< DMA Channel Request Mask Set Register */ + __O uint32_t CHNLREQMASKCLR; /*!< DMA Channel Request Mask Clear Register */ + __IO uint32_t CHNLENABLESET; /*!< DMA Channel Enable Set Register */ + __O uint32_t CHNLENABLECLR; /*!< DMA Channel Enable Clear Register */ + __IO uint32_t CHNLPRIALTSET; /*!< DMA Channel Primary-Alternate Set Register */ + __O uint32_t CHNLPRIALTCLR; /*!< DMA Channel Primary-Alternate Clear Register */ + __IO uint32_t CHNLPRIORITYSET; /*!< DMA Channel Priority Set Register */ + __O uint32_t CHNLPRIORITYCLR; /*!< DMA Channel Priority Clear Register */ + uint32_t RESERVED1[3]; + __IO uint32_t ERRCLR; /*!< DMA Bus Error Clear Register */ +} TSB_DMA_TypeDef; + +/** + * @brief 12-bit Analog to Digital Converter(ADC) + */ +typedef struct { + __IO uint32_t CR0; /*!< AD Control Register 0 */ + __IO uint32_t CR1; /*!< AD Control Register 1 */ + __I uint32_t ST; /*!< AD Status Register */ + __IO uint32_t CLK; /*!< AD Conversion Clock Setting Register */ + __IO uint32_t MOD0; /*!< AD Mode Control Register 0 */ + __IO uint32_t MOD1; /*!< AD Mode Control Register 1 */ + __IO uint32_t MOD2; /*!< AD Mode Control Register 2 */ + uint32_t RESERVED0; + __IO uint32_t CMPEN; /*!< AD Monitor function interrupt permission register*/ + __IO uint32_t CMPCR0; /*!< AD Monitor function Setting Register 0 */ + __IO uint32_t CMPCR1; /*!< AD Monitor function Setting Register 1 */ + __IO uint32_t CMP0; /*!< AD Conversion Result Comparison Register 0 */ + __IO uint32_t CMP1; /*!< AD Conversion Result Comparison Register 1 */ + uint32_t RESERVED1[3]; + __IO uint32_t PSEL0; /*!< AD PMD Trigger Program Number Select Register 0*/ + __IO uint32_t PSEL1; /*!< AD PMD Trigger Program Number Select Register 1*/ + __IO uint32_t PSEL2; /*!< AD PMD Trigger Program Number Select Register 2*/ + __IO uint32_t PSEL3; /*!< AD PMD Trigger Program Number Select Register 3*/ + __IO uint32_t PSEL4; /*!< AD PMD Trigger Program Number Select Register 4*/ + __IO uint32_t PSEL5; /*!< AD PMD Trigger Program Number Select Register 5*/ + __IO uint32_t PSEL6; /*!< AD PMD Trigger Program Number Select Register 6*/ + __IO uint32_t PSEL7; /*!< AD PMD Trigger Program Number Select Register 7*/ + __IO uint32_t PSEL8; /*!< AD PMD Trigger Program Number Select Register 8*/ + __IO uint32_t PSEL9; /*!< AD PMD Trigger Program Number Select Register 9*/ + __IO uint32_t PSEL10; /*!< AD PMD Trigger Program Number Select Register 10*/ + __IO uint32_t PSEL11; /*!< AD PMD Trigger Program Number Select Register 11*/ + __IO uint32_t PINTS0; /*!< AD PMD Trigger Interrupt Select Register 0 */ + __IO uint32_t PINTS1; /*!< AD PMD Trigger Interrupt Select Register 1 */ + __IO uint32_t PINTS2; /*!< AD PMD Trigger Interrupt Select Register 2 */ + __IO uint32_t PINTS3; /*!< AD PMD Trigger Interrupt Select Register 3 */ + __IO uint32_t PINTS4; /*!< AD PMD Trigger Interrupt Select Register 4 */ + __IO uint32_t PINTS5; /*!< AD PMD Trigger Interrupt Select Register 5 */ + __IO uint32_t PINTS6; /*!< AD PMD Trigger Interrupt Select Register 6 */ + __IO uint32_t PINTS7; /*!< AD PMD Trigger Interrupt Select Register 7 */ + __IO uint32_t PREGS; /*!< AD PMD Trigger Conversion Result Storage Select Register 1*/ + uint32_t RESERVED2[2]; + __IO uint32_t EXAZSEL; /*!< AD Sampling Time Select Register */ + __IO uint32_t PSET0; /*!< AD PMD Trigger Program Register 0 */ + __IO uint32_t PSET1; /*!< AD PMD Trigger Program Register 1 */ + __IO uint32_t PSET2; /*!< AD PMD Trigger Program Register 2 */ + __IO uint32_t PSET3; /*!< AD PMD Trigger Program Register 3 */ + __IO uint32_t PSET4; /*!< AD PMD Trigger Program Register 4 */ + __IO uint32_t PSET5; /*!< AD PMD Trigger Program Register 5 */ + __IO uint32_t PSET6; /*!< AD PMD Trigger Program Register 6 */ + __IO uint32_t PSET7; /*!< AD PMD Trigger Program Register 7 */ + __IO uint32_t TSET0; /*!< AD General purpose Trigger Program Register 0*/ + __IO uint32_t TSET1; /*!< AD General purpose Trigger Program Register 1*/ + __IO uint32_t TSET2; /*!< AD General purpose Trigger Program Register 2*/ + __IO uint32_t TSET3; /*!< AD General purpose Trigger Program Register 3*/ + __IO uint32_t TSET4; /*!< AD General purpose Trigger Program Register 4*/ + __IO uint32_t TSET5; /*!< AD General purpose Trigger Program Register 5*/ + __IO uint32_t TSET6; /*!< AD General purpose Trigger Program Register 6*/ + __IO uint32_t TSET7; /*!< AD General purpose Trigger Program Register 7*/ + __IO uint32_t TSET8; /*!< AD General purpose Trigger Program Register 8*/ + __IO uint32_t TSET9; /*!< AD General purpose Trigger Program Register 9*/ + __IO uint32_t TSET10; /*!< AD General purpose Trigger Program Register 10*/ + __IO uint32_t TSET11; /*!< AD General purpose Trigger Program Register 11*/ + __IO uint32_t TSET12; /*!< AD General purpose Trigger Program Register 12*/ + __IO uint32_t TSET13; /*!< AD General purpose Trigger Program Register 13*/ + __IO uint32_t TSET14; /*!< AD General purpose Trigger Program Register 14*/ + __IO uint32_t TSET15; /*!< AD General purpose Trigger Program Register 15*/ + __IO uint32_t TSET16; /*!< AD General purpose Trigger Program Register 16*/ + __IO uint32_t TSET17; /*!< AD General purpose Trigger Program Register 17*/ + __IO uint32_t TSET18; /*!< AD General purpose Trigger Program Register 18*/ + __IO uint32_t TSET19; /*!< AD General purpose Trigger Program Register 19*/ + __IO uint32_t TSET20; /*!< AD General purpose Trigger Program Register 20*/ + __IO uint32_t TSET21; /*!< AD General purpose Trigger Program Register 21*/ + __IO uint32_t TSET22; /*!< AD General purpose Trigger Program Register 22*/ + __IO uint32_t TSET23; /*!< AD General purpose Trigger Program Register 23*/ + uint32_t RESERVED3[8]; + __I uint32_t REG0; /*!< AD Conversion Result Register 0 */ + __I uint32_t REG1; /*!< AD Conversion Result Register 1 */ + __I uint32_t REG2; /*!< AD Conversion Result Register 2 */ + __I uint32_t REG3; /*!< AD Conversion Result Register 3 */ + __I uint32_t REG4; /*!< AD Conversion Result Register 4 */ + __I uint32_t REG5; /*!< AD Conversion Result Register 5 */ + __I uint32_t REG6; /*!< AD Conversion Result Register 6 */ + __I uint32_t REG7; /*!< AD Conversion Result Register 7 */ + __I uint32_t REG8; /*!< AD Conversion Result Register 8 */ + __I uint32_t REG9; /*!< AD Conversion Result Register 9 */ + __I uint32_t REG10; /*!< AD Conversion Result Register 10 */ + __I uint32_t REG11; /*!< AD Conversion Result Register 11 */ + __I uint32_t REG12; /*!< AD Conversion Result Register 12 */ + __I uint32_t REG13; /*!< AD Conversion Result Register 13 */ + __I uint32_t REG14; /*!< AD Conversion Result Register 14 */ + __I uint32_t REG15; /*!< AD Conversion Result Register 15 */ + __I uint32_t REG16; /*!< AD Conversion Result Register 16 */ + __I uint32_t REG17; /*!< AD Conversion Result Register 17 */ + __I uint32_t REG18; /*!< AD Conversion Result Register 18 */ + __I uint32_t REG19; /*!< AD Conversion Result Register 19 */ + __I uint32_t REG20; /*!< AD Conversion Result Register 20 */ + __I uint32_t REG21; /*!< AD Conversion Result Register 21 */ + __I uint32_t REG22; /*!< AD Conversion Result Register 22 */ + __I uint32_t REG23; /*!< AD Conversion Result Register 23 */ +} TSB_AD_TypeDef; + +/** + * @brief Gain Op-AMP (AMP) + */ +typedef struct { + __IO uint32_t CTLA; /*!< AMP control register A */ + __IO uint32_t CTLB; /*!< AMP control register B */ + __IO uint32_t CTLC; /*!< AMP control register C */ +} TSB_AMP_TypeDef; + +/** + * @brief 32-bit Timer Event Counter (T32A) + */ +typedef struct { + __IO uint32_t MOD; /*!< T32A Mode Register */ + uint32_t RESERVED0[15]; + __IO uint32_t RUNA; /*!< T32A Run Register A */ + __IO uint32_t CRA; /*!< T32A Control Register A */ + __IO uint32_t CAPCRA; /*!< T32A Capture Control Register A */ + __O uint32_t OUTCRA0; /*!< T32A Output Control Register A0 */ + __IO uint32_t OUTCRA1; /*!< T32A Output Control Register A1 */ + __IO uint32_t STA; /*!< T32A Status Register A */ + __IO uint32_t IMA; /*!< T32A Interrupt Mask Register A */ + __I uint32_t TMRA; /*!< T32A Counter Capture Register A */ + __IO uint32_t RELDA; /*!< T32A Reload Register A */ + __IO uint32_t RGA0; /*!< T32A Timer Register A0 */ + __IO uint32_t RGA1; /*!< T32A Timer Register A1 */ + __I uint32_t CAPA0; /*!< T32A Capture Register A0 */ + __I uint32_t CAPA1; /*!< T32A Capture Register A1 */ + __IO uint32_t DMAA; /*!< T32A DMA Request Enable Register A */ + __I uint32_t CPA0; /*!< T32A Compare Register A0 */ + __I uint32_t CPA1; /*!< T32A Compare Register A1 */ + __IO uint32_t RUNB; /*!< T32A Run Register B */ + __IO uint32_t CRB; /*!< T32A Control Register B */ + __IO uint32_t CAPCRB; /*!< T32A Capture Control Register B */ + __O uint32_t OUTCRB0; /*!< T32A Output Control Register B0 */ + __IO uint32_t OUTCRB1; /*!< T32A Output Control Register B1 */ + __IO uint32_t STB; /*!< T32A Status Register B */ + __IO uint32_t IMB; /*!< T32A Interrupt Mask Register B */ + __I uint32_t TMRB; /*!< T32A Counter Capture Register B */ + __IO uint32_t RELDB; /*!< T32A Reload Register B */ + __IO uint32_t RGB0; /*!< T32A Timer Register B0 */ + __IO uint32_t RGB1; /*!< T32A Timer Register B1 */ + __I uint32_t CAPB0; /*!< T32A Capture Register B0 */ + __I uint32_t CAPB1; /*!< T32A Capture Register B1 */ + __IO uint32_t DMAB; /*!< T32A DMA Request Enable Register B */ + __I uint32_t CPB0; /*!< T32A Compare Register B0 */ + __I uint32_t CPB1; /*!< T32A Compare Register B1 */ + __IO uint32_t RUNC; /*!< T32A Run Register C */ + __IO uint32_t CRC; /*!< T32A Control Register C */ + __IO uint32_t CAPCRC; /*!< T32A Capture Control Register C */ + __O uint32_t OUTCRC0; /*!< T32A Output Control Register C0 */ + __IO uint32_t OUTCRC1; /*!< T32A Output Control Register C1 */ + __IO uint32_t STC; /*!< T32A Status Register C */ + __IO uint32_t IMC; /*!< T32A Interrupt Mask Register C */ + __I uint32_t TMRC; /*!< T32A Counter Capture Register C */ + __IO uint32_t RELDC; /*!< T32A Reload Register C */ + __IO uint32_t RGC0; /*!< T32A Timer Register C0 */ + __IO uint32_t RGC1; /*!< T32A Timer Register C1 */ + __I uint32_t CAPC0; /*!< T32A Capture Register C0 */ + __I uint32_t CAPC1; /*!< T32A Capture Register C1 */ + __IO uint32_t DMAC; /*!< T32A DMA Request Enable Register C */ + __IO uint32_t PLSCR; /*!< T32A Pulse Count Control Register */ + __I uint32_t CPC0; /*!< T32A Compare Register C0 */ + __I uint32_t CPC1; /*!< T32A Compare Register C1 */ +} TSB_T32A_TypeDef; + +/** + * @brief Serial Peripheral Interface (TSPI) + */ +typedef struct { + __IO uint32_t CR0; /*!< TSPI Control Register 0 */ + __IO uint32_t CR1; /*!< TSPI Control Register 1 */ + __IO uint32_t CR2; /*!< TSPI Control Register 2 */ + __IO uint32_t CR3; /*!< TSPI Control Register 3 */ + __IO uint32_t BR; /*!< TSPI Baud Rate Generator Control Register */ + __IO uint32_t FMTR0; /*!< TSPI Format Control Register 0 */ + __IO uint32_t FMTR1; /*!< TSPI Format Control Register 1 */ + __IO uint32_t SECTCR0; /*!< TSPI Sector Mode Control Register 0 */ + __IO uint32_t SECTCR1; /*!< TSPI Sector Mode Control Register 1 */ + uint32_t RESERVED0[55]; + __IO uint32_t DR; /*!< TSPI Data Register */ + uint32_t RESERVED1[63]; + __IO uint32_t SR; /*!< TSPI Status Register */ + __IO uint32_t ERR; /*!< TSPI Parity Error Flag Register */ +} TSB_TSPI_TypeDef; + +/** + * @brief Asynchronous Serial Communication Circuit (UART) + */ +typedef struct { + __IO uint32_t SWRST; /*!< UART Software Reset Register */ + __IO uint32_t CR0; /*!< UART Control Register 0 */ + __IO uint32_t CR1; /*!< UART Control Register 1 */ + __IO uint32_t CLK; /*!< UART Clock Control Register */ + __IO uint32_t BRD; /*!< UART Baud Rate Register */ + __IO uint32_t TRANS; /*!< UART Transfer Enable Register */ + __IO uint32_t DR; /*!< UART Data Register */ + __IO uint32_t SR; /*!< UART Status Register */ + __O uint32_t FIFOCLR; /*!< UART FIFO Clear Register */ + __IO uint32_t ERR; /*!< UART Error Register */ +} TSB_UART_TypeDef; + +#if defined ( __CC_ARM ) /* RealView Compiler */ +#pragma anon_unions +#elif (defined (__ICCARM__)) /* ICC Compiler */ +#pragma language=extended +#endif + +/** + * @brief I2C Interface (I2C) + */ +typedef struct { + __IO uint32_t CR1; /*!< I2C Control Register 1 */ + __IO uint32_t DBR; /*!< Data Buffer Register */ + __IO uint32_t AR; /*!< Bus address Register */ + union { + __O uint32_t CR2; /*!< Control Register 2 */ + __I uint32_t SR; /*!< Status Register */ + }; + __IO uint32_t PRS; /*!< Prescaler clock setting Register */ + __IO uint32_t IE; /*!< Interrupt Enable Register */ + __IO uint32_t ST; /*!< Interrupt Register */ + __IO uint32_t OP; /*!< Optional Function register */ + __I uint32_t PM; /*!< Bus Monitor register */ + __IO uint32_t AR2; /*!< Second Slave address register */ +} TSB_I2C_TypeDef; + +/** + * @brief I2C Interface Version A (EI2C) + */ +typedef struct { + __IO uint32_t ARST; /*!< EI2C Reset Register */ + __IO uint32_t AEN; /*!< EI2C Enable Register */ + __IO uint32_t ACR0; /*!< EI2C Control Register 0 */ + __IO uint32_t ACR1; /*!< EI2C Control Register 1 */ + __IO uint32_t ADBRT; /*!< EI2C Transmit Data Buffer Register */ + __I uint32_t ADBRR; /*!< EI2C Receive Data Buffer Register */ + __I uint32_t ASR0; /*!< EI2C Status Register 0 */ + __IO uint32_t ASR1; /*!< EI2C Status Register 1 */ + __IO uint32_t APRS; /*!< EI2C Prescaler Clock Setting Register */ + __IO uint32_t ASCL; /*!< EI2C SCL Width Setting Register */ + __IO uint32_t AAR1; /*!< EI2C First Slave Address Register */ + __IO uint32_t AAR2; /*!< EI2C Second Slave Address Register */ + __IO uint32_t AIE; /*!< EI2C Interrupt/DMA Setting Register */ + __I uint32_t APM; /*!< EI2C Bus Terminal Monitor Register */ +} TSB_EI2C_TypeDef; + +/** + * @brief Port A + */ +typedef struct { + __IO uint32_t DATA; /*!< Port A Data Register */ + __IO uint32_t CR; /*!< Port A Output Control Register */ + __IO uint32_t FR1; /*!< Port A Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port A Function Register 4 */ + __IO uint32_t FR5; /*!< Port A Function Register 5 */ + __IO uint32_t FR6; /*!< Port A Function Register 6 */ + __IO uint32_t FR7; /*!< Port A Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port A Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port A Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port A Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port A Input Control Register */ +} TSB_PA_TypeDef; + +/** + * @brief Port B + */ +typedef struct { + __IO uint32_t DATA; /*!< Port B Data Register */ + __IO uint32_t CR; /*!< Port B Output Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t FR4; /*!< Port B Function Register 4 */ + __IO uint32_t FR5; /*!< Port B Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port B Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port B Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port B Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port B Input Control Register */ +} TSB_PB_TypeDef; + +/** + * @brief Port C + */ +typedef struct { + __IO uint32_t DATA; /*!< Port C Data Register */ + __IO uint32_t CR; /*!< Port C Output Control Register */ + __IO uint32_t FR1; /*!< Port C Function Register 1 */ + __IO uint32_t FR2; /*!< Port C Function Register 2 */ + __IO uint32_t FR3; /*!< Port C Function Register 3 */ + __IO uint32_t FR4; /*!< Port C Function Register 4 */ + __IO uint32_t FR5; /*!< Port C Function Register 5 */ + __IO uint32_t FR6; /*!< Port C Function Register 6 */ + __IO uint32_t FR7; /*!< Port C Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port C Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port C Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port C Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port C Input Control Register */ +} TSB_PC_TypeDef; + +/** + * @brief Port D + */ +typedef struct { + __IO uint32_t DATA; /*!< Port D Data Register */ + __IO uint32_t CR; /*!< Port D Output Control Register */ + __IO uint32_t FR1; /*!< Port D Function Register 1 */ + __IO uint32_t FR2; /*!< Port D Function Register 2 */ + __IO uint32_t FR3; /*!< Port D Function Register 3 */ + __IO uint32_t FR4; /*!< Port D Function Register 4 */ + __IO uint32_t FR5; /*!< Port D Function Register 5 */ + __IO uint32_t FR6; /*!< Port D Function Register 6 */ + uint32_t RESERVED0[2]; + __IO uint32_t OD; /*!< Port D Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port D Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port D Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port D Input Control Register */ +} TSB_PD_TypeDef; + +/** + * @brief Port E + */ +typedef struct { + __IO uint32_t DATA; /*!< Port E Data Register */ + __IO uint32_t CR; /*!< Port E Output Control Register */ + uint32_t RESERVED0[3]; + __IO uint32_t FR4; /*!< Port E Function Register 4 */ + __IO uint32_t FR5; /*!< Port E Function Register 5 */ + __IO uint32_t FR6; /*!< Port E Function Register 6 */ + __IO uint32_t FR7; /*!< Port E Function Register 7 */ + uint32_t RESERVED1; + __IO uint32_t OD; /*!< Port E Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port E Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port E Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port E Input Control Register */ +} TSB_PE_TypeDef; + +/** + * @brief Port F + */ +typedef struct { + __IO uint32_t DATA; /*!< Port F Data Register */ + __IO uint32_t CR; /*!< Port F Output Control Register */ + __IO uint32_t FR1; /*!< Port F Function Register 1 */ + __IO uint32_t FR2; /*!< Port F Function Register 2 */ + __IO uint32_t FR3; /*!< Port F Function Register 3 */ + __IO uint32_t FR4; /*!< Port F Function Register 4 */ + __IO uint32_t FR5; /*!< Port F Function Register 5 */ + __IO uint32_t FR6; /*!< Port F Function Register 6 */ + __IO uint32_t FR7; /*!< Port F Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port F Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port F Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port F Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port F Input Control Register */ +} TSB_PF_TypeDef; + +/** + * @brief Port G + */ +typedef struct { + __IO uint32_t DATA; /*!< Port G Data Register */ + __IO uint32_t CR; /*!< Port G Output Control Register */ + __IO uint32_t FR1; /*!< Port G Function Register 1 */ + uint32_t RESERVED0[2]; + __IO uint32_t FR4; /*!< Port G Function Register 4 */ + __IO uint32_t FR5; /*!< Port G Function Register 5 */ + uint32_t RESERVED1[3]; + __IO uint32_t OD; /*!< Port G Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port G Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port G Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port G Input Control Register */ +} TSB_PG_TypeDef; + +/** + * @brief Port H + */ +typedef struct { + __IO uint32_t DATA; /*!< Port H Data Register */ + uint32_t RESERVED0[11]; + __IO uint32_t PDN; /*!< Port H Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port H Input Control Register */ +} TSB_PH_TypeDef; + +/** + * @brief Port J + */ +typedef struct { + __IO uint32_t DATA; /*!< Port J Data Register */ + __IO uint32_t CR; /*!< Port J Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port J Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port J Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port J Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port J Input Control Register */ +} TSB_PJ_TypeDef; + +/** + * @brief Port K + */ +typedef struct { + __IO uint32_t DATA; /*!< Port K Data Register */ + __IO uint32_t CR; /*!< Port K Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port K Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port K Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port K Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port K Input Control Register */ +} TSB_PK_TypeDef; + +/** + * @brief Port L + */ +typedef struct { + __IO uint32_t DATA; /*!< Port L Data Register */ + __IO uint32_t CR; /*!< Port L Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port L Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port L Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port L Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port L Input Control Register */ +} TSB_PL_TypeDef; + +/** + * @brief Port M + */ +typedef struct { + __IO uint32_t DATA; /*!< Port M Data Register */ + __IO uint32_t CR; /*!< Port M Output Control Register */ + uint32_t RESERVED0[8]; + __IO uint32_t OD; /*!< Port M Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port M Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port M Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port M Input Control Register */ +} TSB_PM_TypeDef; + +/** + * @brief Port N + */ +typedef struct { + __IO uint32_t DATA; /*!< Port N Data Register */ + __IO uint32_t CR; /*!< Port N Output Control Register */ + __IO uint32_t FR1; /*!< Port N Function Register 1 */ + __IO uint32_t FR2; /*!< Port N Function Register 2 */ + __IO uint32_t FR3; /*!< Port N Function Register 3 */ + __IO uint32_t FR4; /*!< Port N Function Register 4 */ + __IO uint32_t FR5; /*!< Port N Function Register 5 */ + __IO uint32_t FR6; /*!< Port N Function Register 6 */ + __IO uint32_t FR7; /*!< Port N Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port N Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port N Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port N Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port N Input Control Register */ +} TSB_PN_TypeDef; + +/** + * @brief Port U + */ +typedef struct { + __IO uint32_t DATA; /*!< Port U Data Register */ + __IO uint32_t CR; /*!< Port U Output Control Register */ + __IO uint32_t FR1; /*!< Port U Function Register 1 */ + __IO uint32_t FR2; /*!< Port U Function Register 2 */ + __IO uint32_t FR3; /*!< Port U Function Register 3 */ + __IO uint32_t FR4; /*!< Port U Function Register 4 */ + __IO uint32_t FR5; /*!< Port U Function Register 5 */ + __IO uint32_t FR6; /*!< Port U Function Register 6 */ + __IO uint32_t FR7; /*!< Port U Function Register 7 */ + uint32_t RESERVED0; + __IO uint32_t OD; /*!< Port U Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port U Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port U Pull-down Control Register */ + uint32_t RESERVED1; + __IO uint32_t IE; /*!< Port U Input Control Register */ +} TSB_PU_TypeDef; + +/** + * @brief Port V + */ +typedef struct { + __IO uint32_t DATA; /*!< Port V Data Register */ + __IO uint32_t CR; /*!< Port V Output Control Register */ + __IO uint32_t FR1; /*!< Port V Function Register 1 */ + __IO uint32_t FR2; /*!< Port V Function Register 2 */ + uint32_t RESERVED0; + __IO uint32_t FR4; /*!< Port V Function Register 4 */ + uint32_t RESERVED1[4]; + __IO uint32_t OD; /*!< Port V Open Drain Control Register */ + __IO uint32_t PUP; /*!< Port V Pull-up Control Register */ + __IO uint32_t PDN; /*!< Port V Pull-down Control Register */ + uint32_t RESERVED2; + __IO uint32_t IE; /*!< Port V Input Control Register */ +} TSB_PV_TypeDef; + +/** + * @brief Trimming Circuit (TRM) + */ +typedef struct { + __IO uint32_t OSCPRO; /*!< Protection Register */ + __IO uint32_t OSCEN; /*!< TRM Enable Register */ + uint32_t RESERVED0[2]; + __I uint32_t OSCINIT0; /*!< TRM Initial Trimming Value Monitor Register0 */ + __I uint32_t OSCINIT1; /*!< TRM Initial Trimming Value Monitor Register1 */ + __I uint32_t OSCINIT2; /*!< TRM Initial Trimming Value Monitor Register2 */ + uint32_t RESERVED1; + __IO uint32_t OSCSET0; /*!< TRM User Trimming Value Setting Register0 */ + __IO uint32_t OSCSET1; /*!< TRM User Trimming Value Setting Register1 */ + __IO uint32_t OSCSET2; /*!< TRM User Trimming Value Setting Register2 */ +} TSB_TRM_TypeDef; + +/** + * @brief Oscillation Frequency Detector (OFD) + */ +typedef struct { + __IO uint32_t CR1; /*!< OFD Control Register 1 */ + __IO uint32_t CR2; /*!< OFD Control Register 2 */ + __IO uint32_t MN0; /*!< OFD Lower Detection Frequency Setting Register0*/ + __IO uint32_t MN1; /*!< OFD Lower Detection Frequency Setting Register1*/ + __IO uint32_t MX0; /*!< OFD Higher Detection Frequency Setting Register0*/ + __IO uint32_t MX1; /*!< OFD Higher Detection Frequency Setting Register1*/ + __IO uint32_t RST; /*!< OFD Reset Enable Control Register */ + __I uint32_t STAT; /*!< OFD Status Register */ + __IO uint32_t MON; /*!< OFD External high frequency oscillation clock monitor register */ +} TSB_OFD_TypeDef; + +/** + * @brief Advanced Programmable Motor Control Circuit (A-PMD) + */ +typedef struct { + __IO uint32_t MDEN; /*!< PMD Enable Register */ + __IO uint32_t PORTMD; /*!< PMD Port Output Mode Register */ + __IO uint32_t MDCR; /*!< PMD Control Register */ + __I uint32_t CARSTA; /*!< PWM Carrier Status Register */ + __I uint32_t BCARI; /*!< PWM Basic Carrier Register */ + __IO uint32_t RATE; /*!< PWM Frequency Register */ + __IO uint32_t CMPU; /*!< PMD PWM Compare U Register */ + __IO uint32_t CMPV; /*!< PMD PWM Compare V Register */ + __IO uint32_t CMPW; /*!< PMD PWM Compare W Register */ + __IO uint32_t MODESEL; /*!< PMD Mode Select Register */ + __IO uint32_t MDOUT; /*!< PMD Conduction Control Register */ + __IO uint32_t MDPOT; /*!< PMD Output Setting Register */ + __O uint32_t EMGREL; /*!< PMD EMG Release Register */ + __IO uint32_t EMGCR; /*!< PMD EMG Control Register */ + __I uint32_t EMGSTA; /*!< PMD EMG Status Register */ + __IO uint32_t OVVCR; /*!< PMD OVV Control Register */ + __I uint32_t OVVSTA; /*!< PMD OVV Status Register */ + __IO uint32_t DTR; /*!< PMD Dead Time Register */ + __IO uint32_t TRGCMP0; /*!< PMD Trigger Compare Register 0 */ + __IO uint32_t TRGCMP1; /*!< PMD Trigger Compare Register 1 */ + __IO uint32_t TRGCMP2; /*!< PMD Trigger Compare Register 2 */ + __IO uint32_t TRGCMP3; /*!< PMD Trigger Compare Register 3 */ + __IO uint32_t TRGCR; /*!< PMD Trigger Control Register */ + __IO uint32_t TRGMD; /*!< PMD Trigger Output Mode Setting Register */ + __IO uint32_t TRGSEL; /*!< PMD Trigger Output Select Register */ + __IO uint32_t TRGSYNCR; /*!< PMD Trigger Update Timing Setting Register */ + __IO uint32_t VPWMPH; /*!< PMD Phase difference setting of the V-phase PWM*/ + __IO uint32_t WPWMPH; /*!< PMD Phase difference setting of the W-phase PWM*/ + __IO uint32_t MBUFCR; /*!< PMD Update timing of the triple buffer */ + __IO uint32_t SYNCCR; /*!< PMD Synchronization control between the PMD channel*/ + __IO uint32_t DBGOUTCR; /*!< PMD Debug output control */ +} TSB_PMD_TypeDef; + +/** + * @brief Advanced Encoder Input (A-ENC32) + */ +typedef struct { + __IO uint32_t TNCR; /*!< ENC Control Register */ + __IO uint32_t RELOAD; /*!< ENC Reload Compare Register */ + __IO uint32_t INT; /*!< ENC INT Compare Register */ + __I uint32_t CNT; /*!< ENC Counter/Capture Register */ + __IO uint32_t MCMP; /*!< ENC MCMP Compare Register */ + __IO uint32_t RATE; /*!< ENC Phase Count Rate Register */ + __I uint32_t STS; /*!< ENC Status Register */ + __IO uint32_t INPCR; /*!< ENC Input Process Control Register */ + __IO uint32_t SMPDLY; /*!< ENC Sample Delay Register */ + __I uint32_t INPMON; /*!< ENC Input Monitor Register */ + __IO uint32_t CLKCR; /*!< ENC Sample Clock Control Register */ + __IO uint32_t INTCR; /*!< ENC Interrupt Control Register */ + __I uint32_t INTF; /*!< ENC Interrupt Event Flag Register */ +} TSB_EN_TypeDef; + +/** + * @brief Advanced Vector Engine Plus (A-VE+) + */ +typedef struct { + __IO uint32_t EN; /*!< VE enable/disable */ + __O uint32_t CPURUNTRG; /*!< CPU start trigger selection */ + __IO uint32_t TASKAPP; /*!< Task selection */ + __IO uint32_t ACTSCH; /*!< Operation schedule selection */ + __IO uint32_t REPTIME; /*!< Schedule repeat count */ + __IO uint32_t TRGMODE; /*!< Start trigger mode */ + __IO uint32_t ERRINTEN; /*!< Error interrupt enable/disable */ + __O uint32_t COMPEND; /*!< VE forced termination */ + __I uint32_t ERRDET; /*!< Error detection */ + __I uint32_t SCHTASKRUN; /*!< Schedule executing flag/executing task */ + uint32_t RESERVED0; + __IO uint32_t TMPREG0; /*!< Temporary register */ + __IO uint32_t TMPREG1; /*!< Temporary register */ + __IO uint32_t TMPREG2; /*!< Temporary register */ + __IO uint32_t TMPREG3; /*!< Temporary register */ + __IO uint32_t TMPREG4; /*!< Temporary register */ + __IO uint32_t TMPREG5; /*!< Temporary register */ + __IO uint32_t MCTLF; /*!< Status flags */ + __IO uint32_t MODE; /*!< Task control mode */ + __IO uint32_t FMODE; /*!< Flow control */ + __IO uint32_t TPWM; /*!< PWM period rate (PWM period [s] * maximum speed * 2^16) setting*/ + __IO uint32_t OMEGA; /*!< Rotation speed (speed [Hz] / maximum speed * 2^15) setting*/ + __IO uint32_t THETA; /*!< Motor phase (motor phase [deg] / 360 * 2^16) setting*/ + __IO uint32_t IDREF; /*!< d-axis reference value (current [A] / maximum current * 2^15)*/ + __IO uint32_t IQREF; /*!< q-axis reference value (current [A] / maximum current * 2^15)*/ + __IO uint32_t VD; /*!< d-axis voltage (voltage [V] / maximum voltage * 2^31)*/ + __IO uint32_t VQ; /*!< q-axis voltage (voltage [V] / maximum voltage * 2^31)*/ + __IO uint32_t CIDKI; /*!< Integral coefficient for PI control of d-axis*/ + __IO uint32_t CIDKP; /*!< Proportional coefficient for PI control of d-axis*/ + __IO uint32_t CIQKI; /*!< Integral coefficient for PI control of q-axis*/ + __IO uint32_t CIQKP; /*!< Proportional coefficient for PI control of q-axis*/ + __IO uint32_t VDIH; /*!< Upper 32 bits of integral term (VDI ) of d-axis voltage*/ + __IO uint32_t VDILH; /*!< Lower 32 bits of integral term (VDI) of d-axis voltage*/ + __IO uint32_t VQIH; /*!< Upper 32 bits of integral term (VQI) of q-axis voltage*/ + __IO uint32_t VQILH; /*!< Lower 32 bits of integral term (VQI) of q-axis voltage*/ + __IO uint32_t FPWMCHG; /*!< Switching speed (for 2-phase modulation and shift PWM)*/ + __IO uint32_t PWMOFS; /*!< SHIFT2 PWM Offset register */ + __IO uint32_t MINPLS; /*!< Minimum pulse width */ + __IO uint32_t TRGCRC; /*!< Synchronizing trigger correction value */ + __IO uint32_t VDCL; /*!< Cosine value at THETA for output conversion (Q15 data)*/ + __IO uint32_t COS; /*!< Cosine value at THETA for output conversion (Q15 data)*/ + __IO uint32_t SIN; /*!< Sine value at THETA for output conversion (Q15 data)*/ + __IO uint32_t COSM; /*!< Previous cosine value for input processing (Q15 data)*/ + __IO uint32_t SINM; /*!< Previous sine value for input processing (Q15 data)*/ + __IO uint32_t SECTOR; /*!< Sector information (0-11) */ + __IO uint32_t SECTORM; /*!< Previous sector information for input processing (0-11)*/ + __IO uint32_t IAO; /*!< AD conversion result of a-phase zero-current */ + __IO uint32_t IBO; /*!< AD conversion result of b-phase zero-current */ + __IO uint32_t ICO; /*!< AD conversion result of c-phase zero-current */ + __IO uint32_t IAADC; /*!< AD conversion result of a-phase current */ + __IO uint32_t IBADC; /*!< AD conversion result of b-phase current */ + __IO uint32_t ICADC; /*!< AD conversion result of c-phase current */ + __IO uint32_t VDC; /*!< DC supply voltage (voltage [V] / maximum voltage * 2^15)*/ + __IO uint32_t ID; /*!< d-axis current (current [A] / maximum current * 2^31)*/ + __IO uint32_t IQ; /*!< q-axis current (current [A] / maximum current * 2^31)*/ + uint32_t RESERVED1[39]; + __IO uint32_t TADC; /*!< ADC start wait setting */ + __IO uint32_t CMPU; /*!< PMD control: CMPU setting */ + __IO uint32_t CMPV; /*!< PMD control: CMPV setting */ + __IO uint32_t CMPW; /*!< PMD control: CMPW setting */ + __IO uint32_t OUTCR; /*!< PMD control: Output control (MDOUT) */ + __IO uint32_t TRGCMP0; /*!< PMD control: TRGCMP0 setting */ + __IO uint32_t TRGCMP1; /*!< PMD control: TRGCMP1 setting */ + __IO uint32_t TRGSEL; /*!< PMD control: Trigger selection */ + __O uint32_t EMGRS; /*!< PMD control: EMG return (EMGCR[EMGRS]) */ + uint32_t RESERVED2[8]; + __IO uint32_t PIOLIM; /*!< PI controlled output limit value setting */ + __IO uint32_t CIDKG; /*!< PI controlled d-axis coefficient range setting*/ + __IO uint32_t CIQKG; /*!< PI controlled q-axis coefficient range setting*/ + __IO uint32_t VSLIM; /*!< Voltage scalar limits */ + __IO uint32_t VDQ; /*!< Voltage scalar */ + __IO uint32_t DELTA; /*!< Declination angle */ + __IO uint32_t CPHI; /*!< Motor interlinkage magnetic flux */ + __IO uint32_t CLD; /*!< Motor q-axis inductance */ + __IO uint32_t CLQ; /*!< Motor d-axis inductance */ + __IO uint32_t CR; /*!< Motor resistance value */ + __IO uint32_t CPHIG; /*!< Motor magnetic flux range setting */ + __IO uint32_t CLG; /*!< Motor inductance range setting */ + __IO uint32_t CRG; /*!< Motor resistance range setting */ + __IO uint32_t VDE; /*!< Non-interference controlled d-axis voltage */ + __IO uint32_t VQE; /*!< Non-interference controlled q-axis voltage */ + __IO uint32_t DTC; /*!< Dead time compensation */ + __IO uint32_t HYS; /*!< Hysteresis width for current discrimination */ + __IO uint32_t DTCS; /*!< Dead time compensation control / status */ + __IO uint32_t PWMMAX; /*!< PWM upper limit setting */ + __IO uint32_t PWMMIN; /*!< PWM lower limit setting */ + __IO uint32_t THTCLP; /*!< Clipped phase value setting */ + __IO uint32_t HYS2; /*!< The second threshold value for determining the current polarity*/ + __IO uint32_t VALPHA; /*!< ALPHA-phase voltage */ + __IO uint32_t VBETA; /*!< BETA-phase voltage */ + __IO uint32_t VDUTYA; /*!< A-phase duty */ + __IO uint32_t VDUTYB; /*!< B-phase duty */ + __IO uint32_t VDUTYC; /*!< C-phase duty */ + __IO uint32_t IALPHA; /*!< ALPHA-phase current */ + __IO uint32_t IBETA; /*!< BETA-phase current */ + __IO uint32_t IA; /*!< A-phase current */ + __IO uint32_t IB; /*!< B-phase current */ + __IO uint32_t IC; /*!< C-phase current */ + __IO uint32_t VDELTA; /*!< VDQ Declination angle */ + __IO uint32_t VDCRC; /*!< d-axis voltage correction value */ + __IO uint32_t VQCRC; /*!< q-axis voltage correction value */ +} TSB_VE_TypeDef; + +/** + * @brief Flash Memory Interface (FC) + */ +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SBMR; /*!< Flash Security Bit Mask Register */ + __I uint32_t SSR; /*!< Flash Security Status Register */ + __O uint32_t KCR; /*!< Flash Key Code Register */ + uint32_t RESERVED1; + __I uint32_t SR0; /*!< Flash Status Register 0 */ + uint32_t RESERVED2[3]; + __I uint32_t PSR0; /*!< Flash Protect Status Register 0 */ + __I uint32_t PSR1; /*!< Flash Protect Status Register 1 */ + uint32_t RESERVED3[4]; + __I uint32_t PSR6; /*!< Flash Protect Status Register 6 */ + uint32_t RESERVED4; + __IO uint32_t PMR0; /*!< Flash Protect Mask Register 0 */ + __IO uint32_t PMR1; /*!< Flash Protect Mask Register 1 */ + uint32_t RESERVED5[4]; + __IO uint32_t PMR6; /*!< Flash Protect Mask Register 6 */ + uint32_t RESERVED6[37]; + __I uint32_t SR1; /*!< Flash Status Register 1 */ + __I uint32_t SWPSR; /*!< Flash Memory SWAP Status Register */ + uint32_t RESERVED7[14]; + __IO uint32_t AREASEL; /*!< Flash Area Selection Register */ + uint32_t RESERVED8; + __IO uint32_t CR; /*!< Flash Control Register */ + __IO uint32_t STSCLR; /*!< Flash Status Clear Register */ + __IO uint32_t BNKCR; /*!< Flash Bank Change Register */ + __IO uint32_t FCACCR; /*!< Flash Access Control Register */ + __IO uint32_t BUFDISCLR; /*!< Flash Buffer Disable and Clear Register */ +} TSB_FC_TypeDef; + + +/* Memory map */ +#define FLASH_BASE (0x00000000UL) +#define RAM_BASE (0x20000000UL) +#define PERI_BASE (0x40000000UL) + + +#define TSB_IA_BASE (PERI_BASE + 0x003E000UL) +#define TSB_RLM_BASE (PERI_BASE + 0x003E400UL) +#define TSB_LVD_BASE (PERI_BASE + 0x003EC00UL) +#define TSB_RPAR0_BASE (PERI_BASE + 0x0043000UL) +#define TSB_RPAR1_BASE (PERI_BASE + 0x00A3000UL) +#define TSB_CRC_BASE (PERI_BASE + 0x0043100UL) +#define TSB_CG_BASE (PERI_BASE + 0x0083000UL) +#define TSB_IB_BASE (PERI_BASE + 0x0083200UL) +#define TSB_IMN_BASE (PERI_BASE + 0x0083300UL) +#define TSB_DNFA_BASE (PERI_BASE + 0x00A0200UL) +#define TSB_DNFB_BASE (PERI_BASE + 0x00A0300UL) +#define TSB_DNFC_BASE (PERI_BASE + 0x00A0800UL) +#define TSB_TSEL0_BASE (PERI_BASE + 0x00A0400UL) +#define TSB_SIWD0_BASE (PERI_BASE + 0x00A0600UL) +#define TSB_NBD_BASE (PERI_BASE + 0x00A2000UL) +#define TSB_DMAA_BASE (PERI_BASE + 0x00A4000UL) +#define TSB_ADA_BASE (PERI_BASE + 0x00BA000UL) +#define TSB_ADB_BASE (PERI_BASE + 0x00BA400UL) +#define TSB_ADC_BASE (PERI_BASE + 0x00BA800UL) +#define TSB_AMP_BASE (PERI_BASE + 0x00BD000UL) +#define TSB_T32A0_BASE (PERI_BASE + 0x00C1000UL) +#define TSB_T32A1_BASE (PERI_BASE + 0x00C1400UL) +#define TSB_T32A2_BASE (PERI_BASE + 0x00C1800UL) +#define TSB_T32A3_BASE (PERI_BASE + 0x00C1C00UL) +#define TSB_T32A4_BASE (PERI_BASE + 0x00C2000UL) +#define TSB_T32A5_BASE (PERI_BASE + 0x00C2400UL) +#define TSB_TSPI0_BASE (PERI_BASE + 0x00CA000UL) +#define TSB_TSPI1_BASE (PERI_BASE + 0x00CA400UL) +#define TSB_UART0_BASE (PERI_BASE + 0x00CE000UL) +#define TSB_UART1_BASE (PERI_BASE + 0x00CE400UL) +#define TSB_UART2_BASE (PERI_BASE + 0x00CE800UL) +#define TSB_UART3_BASE (PERI_BASE + 0x00CEC00UL) +#define TSB_I2C0_BASE (PERI_BASE + 0x00D1000UL) +#define TSB_I2C1_BASE (PERI_BASE + 0x00D2000UL) +#define TSB_EI2C0_BASE (PERI_BASE + 0x00D8000UL) +#define TSB_EI2C1_BASE (PERI_BASE + 0x00D9000UL) +#define TSB_PA_BASE (PERI_BASE + 0x00E0000UL) +#define TSB_PB_BASE (PERI_BASE + 0x00E0100UL) +#define TSB_PC_BASE (PERI_BASE + 0x00E0200UL) +#define TSB_PD_BASE (PERI_BASE + 0x00E0300UL) +#define TSB_PE_BASE (PERI_BASE + 0x00E0400UL) +#define TSB_PF_BASE (PERI_BASE + 0x00E0500UL) +#define TSB_PG_BASE (PERI_BASE + 0x00E0600UL) +#define TSB_PH_BASE (PERI_BASE + 0x00E0700UL) +#define TSB_PJ_BASE (PERI_BASE + 0x00E0800UL) +#define TSB_PK_BASE (PERI_BASE + 0x00E0900UL) +#define TSB_PL_BASE (PERI_BASE + 0x00E0A00UL) +#define TSB_PM_BASE (PERI_BASE + 0x00E0B00UL) +#define TSB_PN_BASE (PERI_BASE + 0x00E0C00UL) +#define TSB_PU_BASE (PERI_BASE + 0x00E1000UL) +#define TSB_PV_BASE (PERI_BASE + 0x00E1100UL) +#define TSB_TRM_BASE (PERI_BASE + 0x00E3100UL) +#define TSB_OFD_BASE (PERI_BASE + 0x00E4000UL) +#define TSB_PMD0_BASE (PERI_BASE + 0x00E9000UL) +#define TSB_PMD1_BASE (PERI_BASE + 0x00E9400UL) +#define TSB_PMD2_BASE (PERI_BASE + 0x00E9800UL) +#define TSB_EN0_BASE (PERI_BASE + 0x00EA000UL) +#define TSB_EN1_BASE (PERI_BASE + 0x00EA400UL) +#define TSB_EN2_BASE (PERI_BASE + 0x00EA800UL) +#define TSB_VE0_BASE (PERI_BASE + 0x00EB000UL) +#define TSB_FC_BASE (PERI_BASE + 0x1DFF0000UL) + + +/* Peripheral declaration */ +#define TSB_IA (( TSB_IA_TypeDef *) TSB_IA_BASE) +#define TSB_RLM (( TSB_RLM_TypeDef *) TSB_RLM_BASE) +#define TSB_LVD (( TSB_LVD_TypeDef *) TSB_LVD_BASE) +#define TSB_RPAR0 (( TSB_RPAR_TypeDef *) TSB_RPAR0_BASE) +#define TSB_RPAR1 (( TSB_RPAR_TypeDef *) TSB_RPAR1_BASE) +#define TSB_CRC (( TSB_CRC_TypeDef *) TSB_CRC_BASE) +#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE) +#define TSB_IB (( TSB_IB_TypeDef *) TSB_IB_BASE) +#define TSB_IMN (( TSB_IMN_TypeDef *) TSB_IMN_BASE) +#define TSB_DNFA (( TSB_DNF_TypeDef *) TSB_DNFA_BASE) +#define TSB_DNFB (( TSB_DNF_TypeDef *) TSB_DNFB_BASE) +#define TSB_DNFC (( TSB_DNF_TypeDef *) TSB_DNFC_BASE) +#define TSB_TSEL0 (( TSB_TSEL_TypeDef *) TSB_TSEL0_BASE) +#define TSB_SIWD0 (( TSB_SIWD_TypeDef *) TSB_SIWD0_BASE) +#define TSB_NBD (( TSB_NBD_TypeDef *) TSB_NBD_BASE) +#define TSB_DMAA (( TSB_DMA_TypeDef *) TSB_DMAA_BASE) +#define TSB_ADA (( TSB_AD_TypeDef *) TSB_ADA_BASE) +#define TSB_ADB (( TSB_AD_TypeDef *) TSB_ADB_BASE) +#define TSB_ADC (( TSB_AD_TypeDef *) TSB_ADC_BASE) +#define TSB_AMP (( TSB_AMP_TypeDef *) TSB_AMP_BASE) +#define TSB_T32A0 (( TSB_T32A_TypeDef *) TSB_T32A0_BASE) +#define TSB_T32A1 (( TSB_T32A_TypeDef *) TSB_T32A1_BASE) +#define TSB_T32A2 (( TSB_T32A_TypeDef *) TSB_T32A2_BASE) +#define TSB_T32A3 (( TSB_T32A_TypeDef *) TSB_T32A3_BASE) +#define TSB_T32A4 (( TSB_T32A_TypeDef *) TSB_T32A4_BASE) +#define TSB_T32A5 (( TSB_T32A_TypeDef *) TSB_T32A5_BASE) +#define TSB_TSPI0 (( TSB_TSPI_TypeDef *) TSB_TSPI0_BASE) +#define TSB_TSPI1 (( TSB_TSPI_TypeDef *) TSB_TSPI1_BASE) +#define TSB_UART0 (( TSB_UART_TypeDef *) TSB_UART0_BASE) +#define TSB_UART1 (( TSB_UART_TypeDef *) TSB_UART1_BASE) +#define TSB_UART2 (( TSB_UART_TypeDef *) TSB_UART2_BASE) +#define TSB_UART3 (( TSB_UART_TypeDef *) TSB_UART3_BASE) +#define TSB_I2C0 (( TSB_I2C_TypeDef *) TSB_I2C0_BASE) +#define TSB_I2C1 (( TSB_I2C_TypeDef *) TSB_I2C1_BASE) +#define TSB_EI2C0 (( TSB_EI2C_TypeDef *) TSB_EI2C0_BASE) +#define TSB_EI2C1 (( TSB_EI2C_TypeDef *) TSB_EI2C1_BASE) +#define TSB_PA (( TSB_PA_TypeDef *) TSB_PA_BASE) +#define TSB_PB (( TSB_PB_TypeDef *) TSB_PB_BASE) +#define TSB_PC (( TSB_PC_TypeDef *) TSB_PC_BASE) +#define TSB_PD (( TSB_PD_TypeDef *) TSB_PD_BASE) +#define TSB_PE (( TSB_PE_TypeDef *) TSB_PE_BASE) +#define TSB_PF (( TSB_PF_TypeDef *) TSB_PF_BASE) +#define TSB_PG (( TSB_PG_TypeDef *) TSB_PG_BASE) +#define TSB_PH (( TSB_PH_TypeDef *) TSB_PH_BASE) +#define TSB_PJ (( TSB_PJ_TypeDef *) TSB_PJ_BASE) +#define TSB_PK (( TSB_PK_TypeDef *) TSB_PK_BASE) +#define TSB_PL (( TSB_PL_TypeDef *) TSB_PL_BASE) +#define TSB_PM (( TSB_PM_TypeDef *) TSB_PM_BASE) +#define TSB_PN (( TSB_PN_TypeDef *) TSB_PN_BASE) +#define TSB_PU (( TSB_PU_TypeDef *) TSB_PU_BASE) +#define TSB_PV (( TSB_PV_TypeDef *) TSB_PV_BASE) +#define TSB_TRM (( TSB_TRM_TypeDef *) TSB_TRM_BASE) +#define TSB_OFD (( TSB_OFD_TypeDef *) TSB_OFD_BASE) +#define TSB_PMD0 (( TSB_PMD_TypeDef *) TSB_PMD0_BASE) +#define TSB_PMD1 (( TSB_PMD_TypeDef *) TSB_PMD1_BASE) +#define TSB_PMD2 (( TSB_PMD_TypeDef *) TSB_PMD2_BASE) +#define TSB_EN0 (( TSB_EN_TypeDef *) TSB_EN0_BASE) +#define TSB_EN1 (( TSB_EN_TypeDef *) TSB_EN1_BASE) +#define TSB_EN2 (( TSB_EN_TypeDef *) TSB_EN2_BASE) +#define TSB_VE0 (( TSB_VE_TypeDef *) TSB_VE0_BASE) +#define TSB_FC (( TSB_FC_TypeDef *) TSB_FC_BASE) + + +/* Bit-Band for Device Specific Peripheral Registers */ +#define BITBAND_OFFSET (0x02000000UL) +#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET) +#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2)) + + + + + + +/* RAM Parity (RAMP) */ +#define TSB_RPAR0_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR0->CTL,0))) +#define TSB_RPAR0_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR0->CTL,1))) +#define TSB_RPAR0_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR0->ST,0))) +#define TSB_RPAR0_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR0->ST,1))) +#define TSB_RPAR0_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR0->CLR,0))) +#define TSB_RPAR0_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR0->CLR,1))) + +#define TSB_RPAR1_CTL_RPAREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR1->CTL,0))) +#define TSB_RPAR1_CTL_RPARF (*((__IO uint32_t *)BITBAND_PERI(&TSB_RPAR1->CTL,1))) +#define TSB_RPAR1_ST_RPARFG0 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR1->ST,0))) +#define TSB_RPAR1_ST_RPARFG1 (*((__I uint32_t *)BITBAND_PERI(&TSB_RPAR1->ST,1))) +#define TSB_RPAR1_CLR_RPARCLR0 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR1->CLR,0))) +#define TSB_RPAR1_CLR_RPARCLR1 (*((__O uint32_t *)BITBAND_PERI(&TSB_RPAR1->CLR,1))) + + + +/* Clock Control and Operation Mode (CG) */ +#define TSB_CG_OSCCR_IHOSC1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0))) +#define TSB_CG_OSCCR_OSCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8))) +#define TSB_CG_OSCCR_OSCF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9))) +#define TSB_CG_OSCCR_IHOSC1F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16))) +#define TSB_CG_OSCCR_IHOSC2F (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,19))) +#define TSB_CG_PLL0SEL_PLL0ON (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,0))) +#define TSB_CG_PLL0SEL_PLL0SEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,1))) +#define TSB_CG_PLL0SEL_PLL0ST (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->PLL0SEL,2))) +#define TSB_CG_WUPHCR_WUON (*((__O uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,0))) +#define TSB_CG_WUPHCR_WUEF (*((__I uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,1))) +#define TSB_CG_WUPHCR_WUCLK (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->WUPHCR,8))) +#define TSB_CG_FSYSMENA_IPMENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,0))) +#define TSB_CG_FSYSMENA_IPMENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,1))) +#define TSB_CG_FSYSMENA_IPMENA02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,2))) +#define TSB_CG_FSYSMENA_IPMENA03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,3))) +#define TSB_CG_FSYSMENA_IPMENA04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,4))) +#define TSB_CG_FSYSMENA_IPMENA05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,5))) +#define TSB_CG_FSYSMENA_IPMENA06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,6))) +#define TSB_CG_FSYSMENA_IPMENA07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,7))) +#define TSB_CG_FSYSMENA_IPMENA08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,8))) +#define TSB_CG_FSYSMENA_IPMENA09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,9))) +#define TSB_CG_FSYSMENA_IPMENA10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,10))) +#define TSB_CG_FSYSMENA_IPMENA11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,11))) +#define TSB_CG_FSYSMENA_IPMENA12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,12))) +#define TSB_CG_FSYSMENA_IPMENA16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,16))) +#define TSB_CG_FSYSMENA_IPMENA17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,17))) +#define TSB_CG_FSYSMENA_IPMENA19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,19))) +#define TSB_CG_FSYSMENA_IPMENA20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,20))) +#define TSB_CG_FSYSMENA_IPMENA21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,21))) +#define TSB_CG_FSYSMENA_IPMENA22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,22))) +#define TSB_CG_FSYSMENA_IPMENA23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,23))) +#define TSB_CG_FSYSMENA_IPMENA24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,24))) +#define TSB_CG_FSYSMENA_IPMENA25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,25))) +#define TSB_CG_FSYSMENA_IPMENA26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,26))) +#define TSB_CG_FSYSMENA_IPMENA28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,28))) +#define TSB_CG_FSYSMENA_IPMENA29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,29))) +#define TSB_CG_FSYSMENA_IPMENA30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,30))) +#define TSB_CG_FSYSMENA_IPMENA31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENA,31))) +#define TSB_CG_FSYSMENB_IPMENB00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,0))) +#define TSB_CG_FSYSMENB_IPMENB01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,1))) +#define TSB_CG_FSYSMENB_IPMENB02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,2))) +#define TSB_CG_FSYSMENB_IPMENB03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,3))) +#define TSB_CG_FSYSMENB_IPMENB04 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,4))) +#define TSB_CG_FSYSMENB_IPMENB05 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,5))) +#define TSB_CG_FSYSMENB_IPMENB06 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,6))) +#define TSB_CG_FSYSMENB_IPMENB07 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,7))) +#define TSB_CG_FSYSMENB_IPMENB08 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,8))) +#define TSB_CG_FSYSMENB_IPMENB09 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,9))) +#define TSB_CG_FSYSMENB_IPMENB10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,10))) +#define TSB_CG_FSYSMENB_IPMENB11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,11))) +#define TSB_CG_FSYSMENB_IPMENB12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,12))) +#define TSB_CG_FSYSMENB_IPMENB13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,13))) +#define TSB_CG_FSYSMENB_IPMENB14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,14))) +#define TSB_CG_FSYSMENB_IPMENB15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,15))) +#define TSB_CG_FSYSMENB_IPMENB16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,16))) +#define TSB_CG_FSYSMENB_IPMENB17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,17))) +#define TSB_CG_FSYSMENB_IPMENB25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,25))) +#define TSB_CG_FSYSMENB_IPMENB26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,26))) +#define TSB_CG_FSYSMENB_IPMENB29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,29))) +#define TSB_CG_FSYSMENB_IPMENB30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,30))) +#define TSB_CG_FSYSMENB_IPMENB31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMENB,31))) +#define TSB_CG_FSYSENA_IPENA00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,0))) +#define TSB_CG_FSYSENA_IPENA01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSENA,1))) +#define TSB_CG_FCEN_FCIPEN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,23))) +#define TSB_CG_FCEN_FCIPEN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,26))) +#define TSB_CG_FCEN_FCIPEN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,27))) +#define TSB_CG_FCEN_FCIPEN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FCEN,28))) +#define TSB_CG_SPCLKEN_TRCKEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,0))) +#define TSB_CG_SPCLKEN_ADCKEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,16))) +#define TSB_CG_SPCLKEN_ADCKEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,17))) +#define TSB_CG_SPCLKEN_ADCKEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SPCLKEN,18))) + + + +/* Interrupt Monitor Register (IMN) */ +#define TSB_IMN_FLGNMI_INT000FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,0))) +#define TSB_IMN_FLGNMI_INT016FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLGNMI,16))) +#define TSB_IMN_FLG3_INT096FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,0))) +#define TSB_IMN_FLG3_INT097FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,1))) +#define TSB_IMN_FLG3_INT098FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,2))) +#define TSB_IMN_FLG3_INT099FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,3))) +#define TSB_IMN_FLG3_INT100FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,4))) +#define TSB_IMN_FLG3_INT101FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,5))) +#define TSB_IMN_FLG3_INT102FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,6))) +#define TSB_IMN_FLG3_INT103FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,7))) +#define TSB_IMN_FLG3_INT104FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,8))) +#define TSB_IMN_FLG3_INT105FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,9))) +#define TSB_IMN_FLG3_INT106FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,10))) +#define TSB_IMN_FLG3_INT107FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,11))) +#define TSB_IMN_FLG3_INT108FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,12))) +#define TSB_IMN_FLG3_INT109FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,13))) +#define TSB_IMN_FLG3_INT110FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,14))) +#define TSB_IMN_FLG3_INT111FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,15))) +#define TSB_IMN_FLG3_INT112FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,16))) +#define TSB_IMN_FLG3_INT113FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,17))) +#define TSB_IMN_FLG3_INT114FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,18))) +#define TSB_IMN_FLG3_INT115FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,19))) +#define TSB_IMN_FLG3_INT116FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,20))) +#define TSB_IMN_FLG3_INT117FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,21))) +#define TSB_IMN_FLG3_INT118FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,22))) +#define TSB_IMN_FLG3_INT119FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,23))) +#define TSB_IMN_FLG3_INT120FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,24))) +#define TSB_IMN_FLG3_INT121FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,25))) +#define TSB_IMN_FLG3_INT122FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,26))) +#define TSB_IMN_FLG3_INT123FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,27))) +#define TSB_IMN_FLG3_INT124FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,28))) +#define TSB_IMN_FLG3_INT125FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,29))) +#define TSB_IMN_FLG3_INT126FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,30))) +#define TSB_IMN_FLG3_INT127FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG3,31))) +#define TSB_IMN_FLG4_INT128FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,0))) +#define TSB_IMN_FLG4_INT129FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,1))) +#define TSB_IMN_FLG4_INT130FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,2))) +#define TSB_IMN_FLG4_INT131FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,3))) +#define TSB_IMN_FLG4_INT132FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,4))) +#define TSB_IMN_FLG4_INT133FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,5))) +#define TSB_IMN_FLG4_INT134FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,6))) +#define TSB_IMN_FLG4_INT135FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,7))) +#define TSB_IMN_FLG4_INT136FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,8))) +#define TSB_IMN_FLG4_INT137FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,9))) +#define TSB_IMN_FLG4_INT138FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,10))) +#define TSB_IMN_FLG4_INT139FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,11))) +#define TSB_IMN_FLG4_INT140FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,12))) +#define TSB_IMN_FLG4_INT141FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,13))) +#define TSB_IMN_FLG4_INT142FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,14))) +#define TSB_IMN_FLG4_INT143FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,15))) +#define TSB_IMN_FLG4_INT144FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,16))) +#define TSB_IMN_FLG4_INT145FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,17))) +#define TSB_IMN_FLG4_INT146FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,18))) +#define TSB_IMN_FLG4_INT147FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,19))) +#define TSB_IMN_FLG4_INT148FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,20))) +#define TSB_IMN_FLG4_INT149FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,21))) +#define TSB_IMN_FLG4_INT150FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,22))) +#define TSB_IMN_FLG4_INT151FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,23))) +#define TSB_IMN_FLG4_INT152FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,24))) +#define TSB_IMN_FLG4_INT153FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,25))) +#define TSB_IMN_FLG4_INT154FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,26))) +#define TSB_IMN_FLG4_INT155FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,27))) +#define TSB_IMN_FLG4_INT156FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,28))) +#define TSB_IMN_FLG4_INT157FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,29))) +#define TSB_IMN_FLG4_INT158FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,30))) +#define TSB_IMN_FLG4_INT159FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG4,31))) +#define TSB_IMN_FLG5_INT160FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,0))) +#define TSB_IMN_FLG5_INT165FLG (*((__I uint32_t *)BITBAND_PERI(&TSB_IMN->FLG5,5))) + + +/* Digital Noise Filter (DNF) */ +#define TSB_DNFA_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,0))) +#define TSB_DNFA_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,1))) +#define TSB_DNFA_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,2))) +#define TSB_DNFA_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,3))) +#define TSB_DNFA_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,4))) +#define TSB_DNFA_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,5))) +#define TSB_DNFA_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,6))) +#define TSB_DNFA_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,7))) +#define TSB_DNFA_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,8))) +#define TSB_DNFA_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,9))) +#define TSB_DNFA_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,10))) +#define TSB_DNFA_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,11))) +#define TSB_DNFA_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,12))) +#define TSB_DNFA_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,13))) +#define TSB_DNFA_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,14))) +#define TSB_DNFA_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFA->ENCR,15))) + +#define TSB_DNFB_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,0))) +#define TSB_DNFB_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,1))) +#define TSB_DNFB_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,2))) +#define TSB_DNFB_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,3))) +#define TSB_DNFB_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,4))) +#define TSB_DNFB_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,5))) +#define TSB_DNFB_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,6))) +#define TSB_DNFB_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,7))) +#define TSB_DNFB_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,8))) +#define TSB_DNFB_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,9))) +#define TSB_DNFB_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,10))) +#define TSB_DNFB_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,11))) +#define TSB_DNFB_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,12))) +#define TSB_DNFB_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,13))) +#define TSB_DNFB_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,14))) +#define TSB_DNFB_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFB->ENCR,15))) + +#define TSB_DNFC_ENCR_NFEN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,0))) +#define TSB_DNFC_ENCR_NFEN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,1))) +#define TSB_DNFC_ENCR_NFEN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,2))) +#define TSB_DNFC_ENCR_NFEN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,3))) +#define TSB_DNFC_ENCR_NFEN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,4))) +#define TSB_DNFC_ENCR_NFEN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,5))) +#define TSB_DNFC_ENCR_NFEN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,6))) +#define TSB_DNFC_ENCR_NFEN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,7))) +#define TSB_DNFC_ENCR_NFEN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,8))) +#define TSB_DNFC_ENCR_NFEN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,9))) +#define TSB_DNFC_ENCR_NFEN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,10))) +#define TSB_DNFC_ENCR_NFEN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,11))) +#define TSB_DNFC_ENCR_NFEN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,12))) +#define TSB_DNFC_ENCR_NFEN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,13))) +#define TSB_DNFC_ENCR_NFEN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,14))) +#define TSB_DNFC_ENCR_NFEN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_DNFC->ENCR,15))) + + +/* Trigger Selection circuit (TSEL) */ +#define TSB_TSEL0_CR0_EN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,0))) +#define TSB_TSEL0_CR0_OUTSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,1))) +#define TSB_TSEL0_CR0_UPDN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,2))) +#define TSB_TSEL0_CR0_EN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,8))) +#define TSB_TSEL0_CR0_OUTSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,9))) +#define TSB_TSEL0_CR0_UPDN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,10))) +#define TSB_TSEL0_CR0_EN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,16))) +#define TSB_TSEL0_CR0_OUTSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,17))) +#define TSB_TSEL0_CR0_UPDN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,18))) +#define TSB_TSEL0_CR0_EN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,24))) +#define TSB_TSEL0_CR0_OUTSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,25))) +#define TSB_TSEL0_CR0_UPDN3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR0,26))) +#define TSB_TSEL0_CR1_EN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,0))) +#define TSB_TSEL0_CR1_OUTSEL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,1))) +#define TSB_TSEL0_CR1_UPDN4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,2))) +#define TSB_TSEL0_CR1_EN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,8))) +#define TSB_TSEL0_CR1_OUTSEL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,9))) +#define TSB_TSEL0_CR1_UPDN5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,10))) +#define TSB_TSEL0_CR1_EN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,16))) +#define TSB_TSEL0_CR1_OUTSEL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,17))) +#define TSB_TSEL0_CR1_UPDN6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,18))) +#define TSB_TSEL0_CR1_EN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,24))) +#define TSB_TSEL0_CR1_OUTSEL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,25))) +#define TSB_TSEL0_CR1_UPDN7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR1,26))) +#define TSB_TSEL0_CR2_EN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,0))) +#define TSB_TSEL0_CR2_OUTSEL8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,1))) +#define TSB_TSEL0_CR2_UPDN8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,2))) +#define TSB_TSEL0_CR2_EN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,8))) +#define TSB_TSEL0_CR2_OUTSEL9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,9))) +#define TSB_TSEL0_CR2_UPDN9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,10))) +#define TSB_TSEL0_CR2_EN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,16))) +#define TSB_TSEL0_CR2_OUTSEL10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,17))) +#define TSB_TSEL0_CR2_UPDN10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,18))) +#define TSB_TSEL0_CR2_EN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,24))) +#define TSB_TSEL0_CR2_OUTSEL11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,25))) +#define TSB_TSEL0_CR2_UPDN11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR2,26))) +#define TSB_TSEL0_CR3_EN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,0))) +#define TSB_TSEL0_CR3_OUTSEL12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,1))) +#define TSB_TSEL0_CR3_UPDN12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,2))) +#define TSB_TSEL0_CR3_EN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,8))) +#define TSB_TSEL0_CR3_OUTSEL13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,9))) +#define TSB_TSEL0_CR3_UPDN13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,10))) +#define TSB_TSEL0_CR3_EN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,16))) +#define TSB_TSEL0_CR3_OUTSEL14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,17))) +#define TSB_TSEL0_CR3_UPDN14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,18))) +#define TSB_TSEL0_CR3_EN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,24))) +#define TSB_TSEL0_CR3_OUTSEL15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,25))) +#define TSB_TSEL0_CR3_UPDN15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR3,26))) +#define TSB_TSEL0_CR4_EN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,0))) +#define TSB_TSEL0_CR4_OUTSEL16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,1))) +#define TSB_TSEL0_CR4_UPDN16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,2))) +#define TSB_TSEL0_CR4_EN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,8))) +#define TSB_TSEL0_CR4_OUTSEL17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,9))) +#define TSB_TSEL0_CR4_UPDN17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,10))) +#define TSB_TSEL0_CR4_EN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,16))) +#define TSB_TSEL0_CR4_OUTSEL18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,17))) +#define TSB_TSEL0_CR4_UPDN18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,18))) +#define TSB_TSEL0_CR4_EN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,24))) +#define TSB_TSEL0_CR4_OUTSEL19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,25))) +#define TSB_TSEL0_CR4_UPDN19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR4,26))) +#define TSB_TSEL0_CR5_EN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,0))) +#define TSB_TSEL0_CR5_OUTSEL20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,1))) +#define TSB_TSEL0_CR5_UPDN20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,2))) +#define TSB_TSEL0_CR5_EN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,8))) +#define TSB_TSEL0_CR5_OUTSEL21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,9))) +#define TSB_TSEL0_CR5_UPDN21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,10))) +#define TSB_TSEL0_CR5_EN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,16))) +#define TSB_TSEL0_CR5_OUTSEL22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,17))) +#define TSB_TSEL0_CR5_UPDN22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,18))) +#define TSB_TSEL0_CR5_EN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,24))) +#define TSB_TSEL0_CR5_OUTSEL23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,25))) +#define TSB_TSEL0_CR5_UPDN23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR5,26))) +#define TSB_TSEL0_CR6_EN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,0))) +#define TSB_TSEL0_CR6_OUTSEL24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,1))) +#define TSB_TSEL0_CR6_UPDN24 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,2))) +#define TSB_TSEL0_CR6_EN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,8))) +#define TSB_TSEL0_CR6_OUTSEL25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,9))) +#define TSB_TSEL0_CR6_UPDN25 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,10))) +#define TSB_TSEL0_CR6_EN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,16))) +#define TSB_TSEL0_CR6_OUTSEL26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,17))) +#define TSB_TSEL0_CR6_UPDN26 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,18))) +#define TSB_TSEL0_CR6_EN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,24))) +#define TSB_TSEL0_CR6_OUTSEL27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,25))) +#define TSB_TSEL0_CR6_UPDN27 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR6,26))) +#define TSB_TSEL0_CR7_EN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,0))) +#define TSB_TSEL0_CR7_OUTSEL28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,1))) +#define TSB_TSEL0_CR7_UPDN28 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,2))) +#define TSB_TSEL0_CR7_EN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,8))) +#define TSB_TSEL0_CR7_OUTSEL29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,9))) +#define TSB_TSEL0_CR7_UPDN29 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,10))) +#define TSB_TSEL0_CR7_EN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,16))) +#define TSB_TSEL0_CR7_OUTSEL30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,17))) +#define TSB_TSEL0_CR7_UPDN30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,18))) +#define TSB_TSEL0_CR7_EN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,24))) +#define TSB_TSEL0_CR7_OUTSEL31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,25))) +#define TSB_TSEL0_CR7_UPDN31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR7,26))) +#define TSB_TSEL0_CR8_EN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,0))) +#define TSB_TSEL0_CR8_OUTSEL32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,1))) +#define TSB_TSEL0_CR8_UPDN32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,2))) +#define TSB_TSEL0_CR8_EN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,8))) +#define TSB_TSEL0_CR8_OUTSEL33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,9))) +#define TSB_TSEL0_CR8_UPDN33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,10))) +#define TSB_TSEL0_CR8_EN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,16))) +#define TSB_TSEL0_CR8_OUTSEL34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,17))) +#define TSB_TSEL0_CR8_UPDN34 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,18))) +#define TSB_TSEL0_CR8_EN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,24))) +#define TSB_TSEL0_CR8_OUTSEL35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,25))) +#define TSB_TSEL0_CR8_UPDN35 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR8,26))) +#define TSB_TSEL0_CR9_EN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,0))) +#define TSB_TSEL0_CR9_OUTSEL36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,1))) +#define TSB_TSEL0_CR9_UPDN36 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,2))) +#define TSB_TSEL0_CR9_EN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,8))) +#define TSB_TSEL0_CR9_OUTSEL37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,9))) +#define TSB_TSEL0_CR9_UPDN37 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,10))) +#define TSB_TSEL0_CR9_EN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,16))) +#define TSB_TSEL0_CR9_OUTSEL38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,17))) +#define TSB_TSEL0_CR9_UPDN38 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,18))) +#define TSB_TSEL0_CR9_EN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,24))) +#define TSB_TSEL0_CR9_OUTSEL39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,25))) +#define TSB_TSEL0_CR9_UPDN39 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR9,26))) +#define TSB_TSEL0_CR10_EN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,0))) +#define TSB_TSEL0_CR10_OUTSEL40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,1))) +#define TSB_TSEL0_CR10_UPDN40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,2))) +#define TSB_TSEL0_CR10_EN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,8))) +#define TSB_TSEL0_CR10_OUTSEL41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,9))) +#define TSB_TSEL0_CR10_UPDN41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,10))) +#define TSB_TSEL0_CR10_EN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,16))) +#define TSB_TSEL0_CR10_OUTSEL42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,17))) +#define TSB_TSEL0_CR10_UPDN42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSEL0->CR10,18))) + + +/* Watchdog Timer (SIWD) */ +#define TSB_SIWD0_EN_WDTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,0))) +#define TSB_SIWD0_EN_WDTF (*((__I uint32_t *)BITBAND_PERI(&TSB_SIWD0->EN,1))) +#define TSB_SIWD0_MOD_RESCR (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,0))) +#define TSB_SIWD0_MOD_INTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->MOD,1))) +#define TSB_SIWD0_OSCCR_OSCPRO (*((__IO uint32_t *)BITBAND_PERI(&TSB_SIWD0->OSCCR,0))) + + +/* Non-Break Debug Interface (NBD) */ +#define TSB_NBD_CR0_NBDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_NBD->CR0,0))) + + +/* Direct Memory Access Controller (DMAC) */ +#define TSB_DMAA_STATUS_MASTER_ENABLE (*((__I uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0))) +#define TSB_DMAA_CFG_MASTER_ENABLE (*((__O uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0))) +#define TSB_DMAA_ERRCLR_ERR_CLR (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0))) + + +/* 12-bit Analog to Digital Converter(ADC) */ +#define TSB_ADA_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,0))) +#define TSB_ADA_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,1))) +#define TSB_ADA_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR0,7))) +#define TSB_ADA_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,0))) +#define TSB_ADA_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,4))) +#define TSB_ADA_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,5))) +#define TSB_ADA_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CR1,6))) +#define TSB_ADA_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,0))) +#define TSB_ADA_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,1))) +#define TSB_ADA_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,2))) +#define TSB_ADA_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,3))) +#define TSB_ADA_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->ST,7))) +#define TSB_ADA_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,0))) +#define TSB_ADA_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->MOD0,1))) +#define TSB_ADA_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,0))) +#define TSB_ADA_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPEN,1))) +#define TSB_ADA_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,5))) +#define TSB_ADA_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR0,6))) +#define TSB_ADA_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,5))) +#define TSB_ADA_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->CMPCR1,6))) +#define TSB_ADA_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL0,7))) +#define TSB_ADA_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL1,7))) +#define TSB_ADA_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL2,7))) +#define TSB_ADA_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL3,7))) +#define TSB_ADA_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL4,7))) +#define TSB_ADA_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL5,7))) +#define TSB_ADA_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL6,7))) +#define TSB_ADA_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL7,7))) +#define TSB_ADA_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL8,7))) +#define TSB_ADA_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL9,7))) +#define TSB_ADA_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL10,7))) +#define TSB_ADA_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSEL11,7))) +#define TSB_ADA_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,7))) +#define TSB_ADA_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,15))) +#define TSB_ADA_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,23))) +#define TSB_ADA_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET0,31))) +#define TSB_ADA_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,7))) +#define TSB_ADA_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,15))) +#define TSB_ADA_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,23))) +#define TSB_ADA_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET1,31))) +#define TSB_ADA_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,7))) +#define TSB_ADA_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,15))) +#define TSB_ADA_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,23))) +#define TSB_ADA_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET2,31))) +#define TSB_ADA_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,7))) +#define TSB_ADA_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,15))) +#define TSB_ADA_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,23))) +#define TSB_ADA_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET3,31))) +#define TSB_ADA_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,7))) +#define TSB_ADA_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,15))) +#define TSB_ADA_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,23))) +#define TSB_ADA_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET4,31))) +#define TSB_ADA_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,7))) +#define TSB_ADA_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,15))) +#define TSB_ADA_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,23))) +#define TSB_ADA_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET5,31))) +#define TSB_ADA_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,7))) +#define TSB_ADA_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,15))) +#define TSB_ADA_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,23))) +#define TSB_ADA_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET6,31))) +#define TSB_ADA_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,7))) +#define TSB_ADA_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,15))) +#define TSB_ADA_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,23))) +#define TSB_ADA_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->PSET7,31))) +#define TSB_ADA_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET0,7))) +#define TSB_ADA_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET1,7))) +#define TSB_ADA_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET2,7))) +#define TSB_ADA_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET3,7))) +#define TSB_ADA_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET4,7))) +#define TSB_ADA_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET5,7))) +#define TSB_ADA_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET6,7))) +#define TSB_ADA_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET7,7))) +#define TSB_ADA_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET8,7))) +#define TSB_ADA_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET9,7))) +#define TSB_ADA_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET10,7))) +#define TSB_ADA_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET11,7))) +#define TSB_ADA_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET12,7))) +#define TSB_ADA_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET13,7))) +#define TSB_ADA_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET14,7))) +#define TSB_ADA_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET15,7))) +#define TSB_ADA_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET16,7))) +#define TSB_ADA_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET17,7))) +#define TSB_ADA_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET18,7))) +#define TSB_ADA_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET19,7))) +#define TSB_ADA_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET20,7))) +#define TSB_ADA_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET21,7))) +#define TSB_ADA_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET22,7))) +#define TSB_ADA_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADA->TSET23,7))) +#define TSB_ADA_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,0))) +#define TSB_ADA_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,1))) +#define TSB_ADA_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,28))) +#define TSB_ADA_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG0,29))) +#define TSB_ADA_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,0))) +#define TSB_ADA_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,1))) +#define TSB_ADA_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,28))) +#define TSB_ADA_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG1,29))) +#define TSB_ADA_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,0))) +#define TSB_ADA_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,1))) +#define TSB_ADA_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,28))) +#define TSB_ADA_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG2,29))) +#define TSB_ADA_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,0))) +#define TSB_ADA_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,1))) +#define TSB_ADA_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,28))) +#define TSB_ADA_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG3,29))) +#define TSB_ADA_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,0))) +#define TSB_ADA_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,1))) +#define TSB_ADA_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,28))) +#define TSB_ADA_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG4,29))) +#define TSB_ADA_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,0))) +#define TSB_ADA_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,1))) +#define TSB_ADA_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,28))) +#define TSB_ADA_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG5,29))) +#define TSB_ADA_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,0))) +#define TSB_ADA_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,1))) +#define TSB_ADA_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,28))) +#define TSB_ADA_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG6,29))) +#define TSB_ADA_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,0))) +#define TSB_ADA_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,1))) +#define TSB_ADA_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,28))) +#define TSB_ADA_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG7,29))) +#define TSB_ADA_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,0))) +#define TSB_ADA_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,1))) +#define TSB_ADA_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,28))) +#define TSB_ADA_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG8,29))) +#define TSB_ADA_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,0))) +#define TSB_ADA_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,1))) +#define TSB_ADA_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,28))) +#define TSB_ADA_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG9,29))) +#define TSB_ADA_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,0))) +#define TSB_ADA_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,1))) +#define TSB_ADA_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,28))) +#define TSB_ADA_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG10,29))) +#define TSB_ADA_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,0))) +#define TSB_ADA_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,1))) +#define TSB_ADA_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,28))) +#define TSB_ADA_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG11,29))) +#define TSB_ADA_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,0))) +#define TSB_ADA_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,1))) +#define TSB_ADA_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,28))) +#define TSB_ADA_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG12,29))) +#define TSB_ADA_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,0))) +#define TSB_ADA_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,1))) +#define TSB_ADA_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,28))) +#define TSB_ADA_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG13,29))) +#define TSB_ADA_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,0))) +#define TSB_ADA_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,1))) +#define TSB_ADA_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,28))) +#define TSB_ADA_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG14,29))) +#define TSB_ADA_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,0))) +#define TSB_ADA_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,1))) +#define TSB_ADA_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,28))) +#define TSB_ADA_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG15,29))) +#define TSB_ADA_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,0))) +#define TSB_ADA_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,1))) +#define TSB_ADA_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,28))) +#define TSB_ADA_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG16,29))) +#define TSB_ADA_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,0))) +#define TSB_ADA_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,1))) +#define TSB_ADA_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,28))) +#define TSB_ADA_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG17,29))) +#define TSB_ADA_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,0))) +#define TSB_ADA_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,1))) +#define TSB_ADA_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,28))) +#define TSB_ADA_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG18,29))) +#define TSB_ADA_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,0))) +#define TSB_ADA_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,1))) +#define TSB_ADA_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,28))) +#define TSB_ADA_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG19,29))) +#define TSB_ADA_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,0))) +#define TSB_ADA_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,1))) +#define TSB_ADA_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,28))) +#define TSB_ADA_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG20,29))) +#define TSB_ADA_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,0))) +#define TSB_ADA_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,1))) +#define TSB_ADA_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,28))) +#define TSB_ADA_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG21,29))) +#define TSB_ADA_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,0))) +#define TSB_ADA_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,1))) +#define TSB_ADA_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,28))) +#define TSB_ADA_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG22,29))) +#define TSB_ADA_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,0))) +#define TSB_ADA_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,1))) +#define TSB_ADA_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,28))) +#define TSB_ADA_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADA->REG23,29))) + +#define TSB_ADB_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR0,0))) +#define TSB_ADB_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADB->CR0,1))) +#define TSB_ADB_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR0,7))) +#define TSB_ADB_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,0))) +#define TSB_ADB_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,4))) +#define TSB_ADB_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,5))) +#define TSB_ADB_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CR1,6))) +#define TSB_ADB_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,0))) +#define TSB_ADB_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,1))) +#define TSB_ADB_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,2))) +#define TSB_ADB_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,3))) +#define TSB_ADB_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->ST,7))) +#define TSB_ADB_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->MOD0,0))) +#define TSB_ADB_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->MOD0,1))) +#define TSB_ADB_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPEN,0))) +#define TSB_ADB_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPEN,1))) +#define TSB_ADB_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR0,5))) +#define TSB_ADB_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR0,6))) +#define TSB_ADB_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR1,5))) +#define TSB_ADB_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->CMPCR1,6))) +#define TSB_ADB_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL0,7))) +#define TSB_ADB_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL1,7))) +#define TSB_ADB_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL2,7))) +#define TSB_ADB_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL3,7))) +#define TSB_ADB_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL4,7))) +#define TSB_ADB_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL5,7))) +#define TSB_ADB_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL6,7))) +#define TSB_ADB_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL7,7))) +#define TSB_ADB_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL8,7))) +#define TSB_ADB_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL9,7))) +#define TSB_ADB_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL10,7))) +#define TSB_ADB_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSEL11,7))) +#define TSB_ADB_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,7))) +#define TSB_ADB_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,15))) +#define TSB_ADB_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,23))) +#define TSB_ADB_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET0,31))) +#define TSB_ADB_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,7))) +#define TSB_ADB_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,15))) +#define TSB_ADB_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,23))) +#define TSB_ADB_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET1,31))) +#define TSB_ADB_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,7))) +#define TSB_ADB_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,15))) +#define TSB_ADB_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,23))) +#define TSB_ADB_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET2,31))) +#define TSB_ADB_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,7))) +#define TSB_ADB_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,15))) +#define TSB_ADB_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,23))) +#define TSB_ADB_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET3,31))) +#define TSB_ADB_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,7))) +#define TSB_ADB_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,15))) +#define TSB_ADB_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,23))) +#define TSB_ADB_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET4,31))) +#define TSB_ADB_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,7))) +#define TSB_ADB_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,15))) +#define TSB_ADB_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,23))) +#define TSB_ADB_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET5,31))) +#define TSB_ADB_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,7))) +#define TSB_ADB_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,15))) +#define TSB_ADB_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,23))) +#define TSB_ADB_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET6,31))) +#define TSB_ADB_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,7))) +#define TSB_ADB_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,15))) +#define TSB_ADB_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,23))) +#define TSB_ADB_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->PSET7,31))) +#define TSB_ADB_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET0,7))) +#define TSB_ADB_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET1,7))) +#define TSB_ADB_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET2,7))) +#define TSB_ADB_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET3,7))) +#define TSB_ADB_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET4,7))) +#define TSB_ADB_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET5,7))) +#define TSB_ADB_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET6,7))) +#define TSB_ADB_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET7,7))) +#define TSB_ADB_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET8,7))) +#define TSB_ADB_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET9,7))) +#define TSB_ADB_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET10,7))) +#define TSB_ADB_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET11,7))) +#define TSB_ADB_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET12,7))) +#define TSB_ADB_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET13,7))) +#define TSB_ADB_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET14,7))) +#define TSB_ADB_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET15,7))) +#define TSB_ADB_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET16,7))) +#define TSB_ADB_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET17,7))) +#define TSB_ADB_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET18,7))) +#define TSB_ADB_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET19,7))) +#define TSB_ADB_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET20,7))) +#define TSB_ADB_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET21,7))) +#define TSB_ADB_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET22,7))) +#define TSB_ADB_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADB->TSET23,7))) +#define TSB_ADB_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,0))) +#define TSB_ADB_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,1))) +#define TSB_ADB_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,28))) +#define TSB_ADB_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG0,29))) +#define TSB_ADB_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,0))) +#define TSB_ADB_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,1))) +#define TSB_ADB_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,28))) +#define TSB_ADB_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG1,29))) +#define TSB_ADB_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,0))) +#define TSB_ADB_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,1))) +#define TSB_ADB_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,28))) +#define TSB_ADB_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG2,29))) +#define TSB_ADB_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,0))) +#define TSB_ADB_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,1))) +#define TSB_ADB_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,28))) +#define TSB_ADB_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG3,29))) +#define TSB_ADB_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,0))) +#define TSB_ADB_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,1))) +#define TSB_ADB_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,28))) +#define TSB_ADB_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG4,29))) +#define TSB_ADB_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,0))) +#define TSB_ADB_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,1))) +#define TSB_ADB_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,28))) +#define TSB_ADB_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG5,29))) +#define TSB_ADB_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,0))) +#define TSB_ADB_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,1))) +#define TSB_ADB_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,28))) +#define TSB_ADB_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG6,29))) +#define TSB_ADB_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,0))) +#define TSB_ADB_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,1))) +#define TSB_ADB_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,28))) +#define TSB_ADB_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG7,29))) +#define TSB_ADB_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,0))) +#define TSB_ADB_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,1))) +#define TSB_ADB_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,28))) +#define TSB_ADB_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG8,29))) +#define TSB_ADB_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,0))) +#define TSB_ADB_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,1))) +#define TSB_ADB_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,28))) +#define TSB_ADB_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG9,29))) +#define TSB_ADB_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,0))) +#define TSB_ADB_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,1))) +#define TSB_ADB_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,28))) +#define TSB_ADB_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG10,29))) +#define TSB_ADB_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,0))) +#define TSB_ADB_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,1))) +#define TSB_ADB_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,28))) +#define TSB_ADB_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG11,29))) +#define TSB_ADB_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,0))) +#define TSB_ADB_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,1))) +#define TSB_ADB_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,28))) +#define TSB_ADB_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG12,29))) +#define TSB_ADB_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,0))) +#define TSB_ADB_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,1))) +#define TSB_ADB_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,28))) +#define TSB_ADB_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG13,29))) +#define TSB_ADB_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,0))) +#define TSB_ADB_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,1))) +#define TSB_ADB_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,28))) +#define TSB_ADB_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG14,29))) +#define TSB_ADB_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,0))) +#define TSB_ADB_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,1))) +#define TSB_ADB_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,28))) +#define TSB_ADB_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG15,29))) +#define TSB_ADB_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,0))) +#define TSB_ADB_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,1))) +#define TSB_ADB_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,28))) +#define TSB_ADB_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG16,29))) +#define TSB_ADB_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,0))) +#define TSB_ADB_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,1))) +#define TSB_ADB_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,28))) +#define TSB_ADB_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG17,29))) +#define TSB_ADB_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,0))) +#define TSB_ADB_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,1))) +#define TSB_ADB_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,28))) +#define TSB_ADB_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG18,29))) +#define TSB_ADB_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,0))) +#define TSB_ADB_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,1))) +#define TSB_ADB_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,28))) +#define TSB_ADB_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG19,29))) +#define TSB_ADB_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,0))) +#define TSB_ADB_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,1))) +#define TSB_ADB_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,28))) +#define TSB_ADB_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG20,29))) +#define TSB_ADB_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,0))) +#define TSB_ADB_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,1))) +#define TSB_ADB_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,28))) +#define TSB_ADB_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG21,29))) +#define TSB_ADB_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,0))) +#define TSB_ADB_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,1))) +#define TSB_ADB_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,28))) +#define TSB_ADB_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG22,29))) +#define TSB_ADB_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,0))) +#define TSB_ADB_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,1))) +#define TSB_ADB_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,28))) +#define TSB_ADB_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADB->REG23,29))) + +#define TSB_ADC_CR0_CNT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR0,0))) +#define TSB_ADC_CR0_SGL (*((__O uint32_t *)BITBAND_PERI(&TSB_ADC->CR0,1))) +#define TSB_ADC_CR0_ADEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR0,7))) +#define TSB_ADC_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,0))) +#define TSB_ADC_CR1_TRGDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,4))) +#define TSB_ADC_CR1_SGLDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,5))) +#define TSB_ADC_CR1_CNTDMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CR1,6))) +#define TSB_ADC_ST_PMDF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,0))) +#define TSB_ADC_ST_TRGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,1))) +#define TSB_ADC_ST_SNGF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,2))) +#define TSB_ADC_ST_CNTF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,3))) +#define TSB_ADC_ST_ADBF (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->ST,7))) +#define TSB_ADC_MOD0_DACON (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->MOD0,0))) +#define TSB_ADC_MOD0_RCUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->MOD0,1))) +#define TSB_ADC_CMPEN_CMP0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPEN,0))) +#define TSB_ADC_CMPEN_CMP1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPEN,1))) +#define TSB_ADC_CMPCR0_ADBIG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR0,5))) +#define TSB_ADC_CMPCR0_CMPCND0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR0,6))) +#define TSB_ADC_CMPCR1_ADBIG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR1,5))) +#define TSB_ADC_CMPCR1_CMPCND1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->CMPCR1,6))) +#define TSB_ADC_PSEL0_PENS0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL0,7))) +#define TSB_ADC_PSEL1_PENS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL1,7))) +#define TSB_ADC_PSEL2_PENS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL2,7))) +#define TSB_ADC_PSEL3_PENS3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL3,7))) +#define TSB_ADC_PSEL4_PENS4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL4,7))) +#define TSB_ADC_PSEL5_PENS5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL5,7))) +#define TSB_ADC_PSEL6_PENS6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL6,7))) +#define TSB_ADC_PSEL7_PENS7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL7,7))) +#define TSB_ADC_PSEL8_PENS8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL8,7))) +#define TSB_ADC_PSEL9_PENS9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL9,7))) +#define TSB_ADC_PSEL10_PENS10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL10,7))) +#define TSB_ADC_PSEL11_PENS11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSEL11,7))) +#define TSB_ADC_PSET0_ENSP00 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,7))) +#define TSB_ADC_PSET0_ENSP01 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,15))) +#define TSB_ADC_PSET0_ENSP02 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,23))) +#define TSB_ADC_PSET0_ENSP03 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET0,31))) +#define TSB_ADC_PSET1_ENSP10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,7))) +#define TSB_ADC_PSET1_ENSP11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,15))) +#define TSB_ADC_PSET1_ENSP12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,23))) +#define TSB_ADC_PSET1_ENSP13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET1,31))) +#define TSB_ADC_PSET2_ENSP20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,7))) +#define TSB_ADC_PSET2_ENSP21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,15))) +#define TSB_ADC_PSET2_ENSP22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,23))) +#define TSB_ADC_PSET2_ENSP23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET2,31))) +#define TSB_ADC_PSET3_ENSP30 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,7))) +#define TSB_ADC_PSET3_ENSP31 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,15))) +#define TSB_ADC_PSET3_ENSP32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,23))) +#define TSB_ADC_PSET3_ENSP33 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET3,31))) +#define TSB_ADC_PSET4_ENSP40 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,7))) +#define TSB_ADC_PSET4_ENSP41 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,15))) +#define TSB_ADC_PSET4_ENSP42 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,23))) +#define TSB_ADC_PSET4_ENSP43 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET4,31))) +#define TSB_ADC_PSET5_ENSP50 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,7))) +#define TSB_ADC_PSET5_ENSP51 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,15))) +#define TSB_ADC_PSET5_ENSP52 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,23))) +#define TSB_ADC_PSET5_ENSP53 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET5,31))) +#define TSB_ADC_PSET6_ENSP60 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,7))) +#define TSB_ADC_PSET6_ENSP61 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,15))) +#define TSB_ADC_PSET6_ENSP62 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,23))) +#define TSB_ADC_PSET6_ENSP63 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET6,31))) +#define TSB_ADC_PSET7_ENSP70 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,7))) +#define TSB_ADC_PSET7_ENSP71 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,15))) +#define TSB_ADC_PSET7_ENSP72 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,23))) +#define TSB_ADC_PSET7_ENSP73 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->PSET7,31))) +#define TSB_ADC_TSET0_ENINT0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET0,7))) +#define TSB_ADC_TSET1_ENINT1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET1,7))) +#define TSB_ADC_TSET2_ENINT2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET2,7))) +#define TSB_ADC_TSET3_ENINT3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET3,7))) +#define TSB_ADC_TSET4_ENINT4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET4,7))) +#define TSB_ADC_TSET5_ENINT5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET5,7))) +#define TSB_ADC_TSET6_ENINT6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET6,7))) +#define TSB_ADC_TSET7_ENINT7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET7,7))) +#define TSB_ADC_TSET8_ENINT8 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET8,7))) +#define TSB_ADC_TSET9_ENINT9 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET9,7))) +#define TSB_ADC_TSET10_ENINT10 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET10,7))) +#define TSB_ADC_TSET11_ENINT11 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET11,7))) +#define TSB_ADC_TSET12_ENINT12 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET12,7))) +#define TSB_ADC_TSET13_ENINT13 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET13,7))) +#define TSB_ADC_TSET14_ENINT14 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET14,7))) +#define TSB_ADC_TSET15_ENINT15 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET15,7))) +#define TSB_ADC_TSET16_ENINT16 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET16,7))) +#define TSB_ADC_TSET17_ENINT17 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET17,7))) +#define TSB_ADC_TSET18_ENINT18 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET18,7))) +#define TSB_ADC_TSET19_ENINT19 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET19,7))) +#define TSB_ADC_TSET20_ENINT20 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET20,7))) +#define TSB_ADC_TSET21_ENINT21 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET21,7))) +#define TSB_ADC_TSET22_ENINT22 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET22,7))) +#define TSB_ADC_TSET23_ENINT23 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADC->TSET23,7))) +#define TSB_ADC_REG0_ADRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,0))) +#define TSB_ADC_REG0_ADOVRF0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,1))) +#define TSB_ADC_REG0_ADRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,28))) +#define TSB_ADC_REG0_ADOVRF_M0 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG0,29))) +#define TSB_ADC_REG1_ADRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,0))) +#define TSB_ADC_REG1_ADOVRF1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,1))) +#define TSB_ADC_REG1_ADRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,28))) +#define TSB_ADC_REG1_ADOVRF_M1 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG1,29))) +#define TSB_ADC_REG2_ADRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,0))) +#define TSB_ADC_REG2_ADOVRF2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,1))) +#define TSB_ADC_REG2_ADRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,28))) +#define TSB_ADC_REG2_ADOVRF_M2 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG2,29))) +#define TSB_ADC_REG3_ADRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,0))) +#define TSB_ADC_REG3_ADOVRF3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,1))) +#define TSB_ADC_REG3_ADRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,28))) +#define TSB_ADC_REG3_ADOVRF_M3 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG3,29))) +#define TSB_ADC_REG4_ADRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,0))) +#define TSB_ADC_REG4_ADOVRF4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,1))) +#define TSB_ADC_REG4_ADRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,28))) +#define TSB_ADC_REG4_ADOVRF_M4 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG4,29))) +#define TSB_ADC_REG5_ADRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,0))) +#define TSB_ADC_REG5_ADOVRF5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,1))) +#define TSB_ADC_REG5_ADRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,28))) +#define TSB_ADC_REG5_ADOVRF_M5 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG5,29))) +#define TSB_ADC_REG6_ADRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,0))) +#define TSB_ADC_REG6_ADOVRF6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,1))) +#define TSB_ADC_REG6_ADRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,28))) +#define TSB_ADC_REG6_ADOVRF_M6 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG6,29))) +#define TSB_ADC_REG7_ADRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,0))) +#define TSB_ADC_REG7_ADOVRF7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,1))) +#define TSB_ADC_REG7_ADRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,28))) +#define TSB_ADC_REG7_ADOVRF_M7 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG7,29))) +#define TSB_ADC_REG8_ADRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,0))) +#define TSB_ADC_REG8_ADOVRF8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,1))) +#define TSB_ADC_REG8_ADRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,28))) +#define TSB_ADC_REG8_ADOVRF_M8 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG8,29))) +#define TSB_ADC_REG9_ADRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,0))) +#define TSB_ADC_REG9_ADOVRF9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,1))) +#define TSB_ADC_REG9_ADRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,28))) +#define TSB_ADC_REG9_ADOVRF_M9 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG9,29))) +#define TSB_ADC_REG10_ADRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,0))) +#define TSB_ADC_REG10_ADOVRF10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,1))) +#define TSB_ADC_REG10_ADRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,28))) +#define TSB_ADC_REG10_ADOVRF_M10 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG10,29))) +#define TSB_ADC_REG11_ADRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,0))) +#define TSB_ADC_REG11_ADOVRF11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,1))) +#define TSB_ADC_REG11_ADRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,28))) +#define TSB_ADC_REG11_ADOVRF_M11 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG11,29))) +#define TSB_ADC_REG12_ADRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,0))) +#define TSB_ADC_REG12_ADOVRF12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,1))) +#define TSB_ADC_REG12_ADRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,28))) +#define TSB_ADC_REG12_ADOVRF_M12 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG12,29))) +#define TSB_ADC_REG13_ADRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,0))) +#define TSB_ADC_REG13_ADOVRF13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,1))) +#define TSB_ADC_REG13_ADRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,28))) +#define TSB_ADC_REG13_ADOVRF_M13 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG13,29))) +#define TSB_ADC_REG14_ADRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,0))) +#define TSB_ADC_REG14_ADOVRF14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,1))) +#define TSB_ADC_REG14_ADRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,28))) +#define TSB_ADC_REG14_ADOVRF_M14 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG14,29))) +#define TSB_ADC_REG15_ADRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,0))) +#define TSB_ADC_REG15_ADOVRF15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,1))) +#define TSB_ADC_REG15_ADRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,28))) +#define TSB_ADC_REG15_ADOVRF_M15 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG15,29))) +#define TSB_ADC_REG16_ADRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,0))) +#define TSB_ADC_REG16_ADOVRF16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,1))) +#define TSB_ADC_REG16_ADRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,28))) +#define TSB_ADC_REG16_ADOVRF_M16 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG16,29))) +#define TSB_ADC_REG17_ADRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,0))) +#define TSB_ADC_REG17_ADOVRF17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,1))) +#define TSB_ADC_REG17_ADRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,28))) +#define TSB_ADC_REG17_ADOVRF_M17 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG17,29))) +#define TSB_ADC_REG18_ADRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,0))) +#define TSB_ADC_REG18_ADOVRF18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,1))) +#define TSB_ADC_REG18_ADRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,28))) +#define TSB_ADC_REG18_ADOVRF_M18 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG18,29))) +#define TSB_ADC_REG19_ADRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,0))) +#define TSB_ADC_REG19_ADOVRF19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,1))) +#define TSB_ADC_REG19_ADRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,28))) +#define TSB_ADC_REG19_ADOVRF_M19 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG19,29))) +#define TSB_ADC_REG20_ADRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,0))) +#define TSB_ADC_REG20_ADOVRF20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,1))) +#define TSB_ADC_REG20_ADRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,28))) +#define TSB_ADC_REG20_ADOVRF_M20 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG20,29))) +#define TSB_ADC_REG21_ADRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,0))) +#define TSB_ADC_REG21_ADOVRF21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,1))) +#define TSB_ADC_REG21_ADRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,28))) +#define TSB_ADC_REG21_ADOVRF_M21 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG21,29))) +#define TSB_ADC_REG22_ADRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,0))) +#define TSB_ADC_REG22_ADOVRF22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,1))) +#define TSB_ADC_REG22_ADRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,28))) +#define TSB_ADC_REG22_ADOVRF_M22 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG22,29))) +#define TSB_ADC_REG23_ADRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,0))) +#define TSB_ADC_REG23_ADOVRF23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,1))) +#define TSB_ADC_REG23_ADRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,28))) +#define TSB_ADC_REG23_ADOVRF_M23 (*((__I uint32_t *)BITBAND_PERI(&TSB_ADC->REG23,29))) + + +/* Gain Op-AMP (AMP) */ +#define TSB_AMP_CTLA_AMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_AMP->CTLA,0))) +#define TSB_AMP_CTLB_AMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_AMP->CTLB,0))) +#define TSB_AMP_CTLC_AMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_AMP->CTLC,0))) + + +/* 32-bit Timer Event Counter (T32A) */ +#define TSB_T32A0_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,0))) +#define TSB_T32A0_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->MOD,1))) +#define TSB_T32A0_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,0))) +#define TSB_T32A0_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,1))) +#define TSB_T32A0_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,2))) +#define TSB_T32A0_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNA,4))) +#define TSB_T32A0_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRA,20))) +#define TSB_T32A0_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,0))) +#define TSB_T32A0_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,1))) +#define TSB_T32A0_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,2))) +#define TSB_T32A0_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STA,3))) +#define TSB_T32A0_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,0))) +#define TSB_T32A0_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,1))) +#define TSB_T32A0_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,2))) +#define TSB_T32A0_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMA,3))) +#define TSB_T32A0_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,0))) +#define TSB_T32A0_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,1))) +#define TSB_T32A0_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAA,2))) +#define TSB_T32A0_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,0))) +#define TSB_T32A0_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,1))) +#define TSB_T32A0_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,2))) +#define TSB_T32A0_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNB,4))) +#define TSB_T32A0_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRB,20))) +#define TSB_T32A0_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,0))) +#define TSB_T32A0_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,1))) +#define TSB_T32A0_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,2))) +#define TSB_T32A0_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STB,3))) +#define TSB_T32A0_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,0))) +#define TSB_T32A0_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,1))) +#define TSB_T32A0_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,2))) +#define TSB_T32A0_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMB,3))) +#define TSB_T32A0_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,0))) +#define TSB_T32A0_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,1))) +#define TSB_T32A0_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAB,2))) +#define TSB_T32A0_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,0))) +#define TSB_T32A0_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,1))) +#define TSB_T32A0_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,2))) +#define TSB_T32A0_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A0->RUNC,4))) +#define TSB_T32A0_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->CRC,20))) +#define TSB_T32A0_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,0))) +#define TSB_T32A0_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,1))) +#define TSB_T32A0_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,2))) +#define TSB_T32A0_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,3))) +#define TSB_T32A0_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->STC,4))) +#define TSB_T32A0_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,0))) +#define TSB_T32A0_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,1))) +#define TSB_T32A0_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,2))) +#define TSB_T32A0_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,3))) +#define TSB_T32A0_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->IMC,4))) +#define TSB_T32A0_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,0))) +#define TSB_T32A0_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,1))) +#define TSB_T32A0_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->DMAC,2))) +#define TSB_T32A0_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,0))) +#define TSB_T32A0_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A0->PLSCR,1))) + +#define TSB_T32A1_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,0))) +#define TSB_T32A1_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->MOD,1))) +#define TSB_T32A1_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,0))) +#define TSB_T32A1_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,1))) +#define TSB_T32A1_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,2))) +#define TSB_T32A1_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNA,4))) +#define TSB_T32A1_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRA,20))) +#define TSB_T32A1_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,0))) +#define TSB_T32A1_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,1))) +#define TSB_T32A1_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,2))) +#define TSB_T32A1_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STA,3))) +#define TSB_T32A1_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,0))) +#define TSB_T32A1_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,1))) +#define TSB_T32A1_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,2))) +#define TSB_T32A1_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMA,3))) +#define TSB_T32A1_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,0))) +#define TSB_T32A1_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,1))) +#define TSB_T32A1_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAA,2))) +#define TSB_T32A1_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,0))) +#define TSB_T32A1_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,1))) +#define TSB_T32A1_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,2))) +#define TSB_T32A1_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNB,4))) +#define TSB_T32A1_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRB,20))) +#define TSB_T32A1_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,0))) +#define TSB_T32A1_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,1))) +#define TSB_T32A1_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,2))) +#define TSB_T32A1_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STB,3))) +#define TSB_T32A1_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,0))) +#define TSB_T32A1_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,1))) +#define TSB_T32A1_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,2))) +#define TSB_T32A1_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMB,3))) +#define TSB_T32A1_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,0))) +#define TSB_T32A1_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,1))) +#define TSB_T32A1_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAB,2))) +#define TSB_T32A1_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,0))) +#define TSB_T32A1_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,1))) +#define TSB_T32A1_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,2))) +#define TSB_T32A1_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A1->RUNC,4))) +#define TSB_T32A1_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->CRC,20))) +#define TSB_T32A1_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,0))) +#define TSB_T32A1_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,1))) +#define TSB_T32A1_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,2))) +#define TSB_T32A1_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,3))) +#define TSB_T32A1_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->STC,4))) +#define TSB_T32A1_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,0))) +#define TSB_T32A1_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,1))) +#define TSB_T32A1_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,2))) +#define TSB_T32A1_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,3))) +#define TSB_T32A1_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->IMC,4))) +#define TSB_T32A1_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,0))) +#define TSB_T32A1_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,1))) +#define TSB_T32A1_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->DMAC,2))) +#define TSB_T32A1_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,0))) +#define TSB_T32A1_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A1->PLSCR,1))) + +#define TSB_T32A2_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,0))) +#define TSB_T32A2_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->MOD,1))) +#define TSB_T32A2_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,0))) +#define TSB_T32A2_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,1))) +#define TSB_T32A2_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,2))) +#define TSB_T32A2_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNA,4))) +#define TSB_T32A2_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRA,20))) +#define TSB_T32A2_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,0))) +#define TSB_T32A2_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,1))) +#define TSB_T32A2_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,2))) +#define TSB_T32A2_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STA,3))) +#define TSB_T32A2_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,0))) +#define TSB_T32A2_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,1))) +#define TSB_T32A2_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,2))) +#define TSB_T32A2_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMA,3))) +#define TSB_T32A2_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,0))) +#define TSB_T32A2_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,1))) +#define TSB_T32A2_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAA,2))) +#define TSB_T32A2_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,0))) +#define TSB_T32A2_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,1))) +#define TSB_T32A2_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,2))) +#define TSB_T32A2_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNB,4))) +#define TSB_T32A2_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRB,20))) +#define TSB_T32A2_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,0))) +#define TSB_T32A2_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,1))) +#define TSB_T32A2_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,2))) +#define TSB_T32A2_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STB,3))) +#define TSB_T32A2_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,0))) +#define TSB_T32A2_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,1))) +#define TSB_T32A2_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,2))) +#define TSB_T32A2_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMB,3))) +#define TSB_T32A2_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,0))) +#define TSB_T32A2_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,1))) +#define TSB_T32A2_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAB,2))) +#define TSB_T32A2_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,0))) +#define TSB_T32A2_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,1))) +#define TSB_T32A2_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,2))) +#define TSB_T32A2_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A2->RUNC,4))) +#define TSB_T32A2_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->CRC,20))) +#define TSB_T32A2_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,0))) +#define TSB_T32A2_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,1))) +#define TSB_T32A2_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,2))) +#define TSB_T32A2_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,3))) +#define TSB_T32A2_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->STC,4))) +#define TSB_T32A2_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,0))) +#define TSB_T32A2_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,1))) +#define TSB_T32A2_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,2))) +#define TSB_T32A2_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,3))) +#define TSB_T32A2_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->IMC,4))) +#define TSB_T32A2_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,0))) +#define TSB_T32A2_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,1))) +#define TSB_T32A2_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->DMAC,2))) +#define TSB_T32A2_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,0))) +#define TSB_T32A2_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A2->PLSCR,1))) + +#define TSB_T32A3_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,0))) +#define TSB_T32A3_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->MOD,1))) +#define TSB_T32A3_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,0))) +#define TSB_T32A3_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,1))) +#define TSB_T32A3_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,2))) +#define TSB_T32A3_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNA,4))) +#define TSB_T32A3_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRA,20))) +#define TSB_T32A3_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,0))) +#define TSB_T32A3_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,1))) +#define TSB_T32A3_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,2))) +#define TSB_T32A3_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STA,3))) +#define TSB_T32A3_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,0))) +#define TSB_T32A3_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,1))) +#define TSB_T32A3_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,2))) +#define TSB_T32A3_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMA,3))) +#define TSB_T32A3_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,0))) +#define TSB_T32A3_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,1))) +#define TSB_T32A3_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAA,2))) +#define TSB_T32A3_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,0))) +#define TSB_T32A3_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,1))) +#define TSB_T32A3_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,2))) +#define TSB_T32A3_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNB,4))) +#define TSB_T32A3_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRB,20))) +#define TSB_T32A3_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,0))) +#define TSB_T32A3_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,1))) +#define TSB_T32A3_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,2))) +#define TSB_T32A3_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STB,3))) +#define TSB_T32A3_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,0))) +#define TSB_T32A3_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,1))) +#define TSB_T32A3_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,2))) +#define TSB_T32A3_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMB,3))) +#define TSB_T32A3_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,0))) +#define TSB_T32A3_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,1))) +#define TSB_T32A3_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAB,2))) +#define TSB_T32A3_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,0))) +#define TSB_T32A3_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,1))) +#define TSB_T32A3_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,2))) +#define TSB_T32A3_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A3->RUNC,4))) +#define TSB_T32A3_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->CRC,20))) +#define TSB_T32A3_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,0))) +#define TSB_T32A3_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,1))) +#define TSB_T32A3_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,2))) +#define TSB_T32A3_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,3))) +#define TSB_T32A3_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->STC,4))) +#define TSB_T32A3_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,0))) +#define TSB_T32A3_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,1))) +#define TSB_T32A3_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,2))) +#define TSB_T32A3_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,3))) +#define TSB_T32A3_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->IMC,4))) +#define TSB_T32A3_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,0))) +#define TSB_T32A3_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,1))) +#define TSB_T32A3_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->DMAC,2))) +#define TSB_T32A3_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,0))) +#define TSB_T32A3_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A3->PLSCR,1))) + +#define TSB_T32A4_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,0))) +#define TSB_T32A4_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->MOD,1))) +#define TSB_T32A4_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,0))) +#define TSB_T32A4_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,1))) +#define TSB_T32A4_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,2))) +#define TSB_T32A4_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNA,4))) +#define TSB_T32A4_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRA,20))) +#define TSB_T32A4_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,0))) +#define TSB_T32A4_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,1))) +#define TSB_T32A4_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,2))) +#define TSB_T32A4_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STA,3))) +#define TSB_T32A4_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,0))) +#define TSB_T32A4_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,1))) +#define TSB_T32A4_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,2))) +#define TSB_T32A4_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMA,3))) +#define TSB_T32A4_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,0))) +#define TSB_T32A4_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,1))) +#define TSB_T32A4_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAA,2))) +#define TSB_T32A4_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,0))) +#define TSB_T32A4_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,1))) +#define TSB_T32A4_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,2))) +#define TSB_T32A4_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNB,4))) +#define TSB_T32A4_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRB,20))) +#define TSB_T32A4_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,0))) +#define TSB_T32A4_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,1))) +#define TSB_T32A4_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,2))) +#define TSB_T32A4_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STB,3))) +#define TSB_T32A4_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,0))) +#define TSB_T32A4_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,1))) +#define TSB_T32A4_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,2))) +#define TSB_T32A4_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMB,3))) +#define TSB_T32A4_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,0))) +#define TSB_T32A4_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,1))) +#define TSB_T32A4_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAB,2))) +#define TSB_T32A4_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,0))) +#define TSB_T32A4_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,1))) +#define TSB_T32A4_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,2))) +#define TSB_T32A4_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A4->RUNC,4))) +#define TSB_T32A4_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->CRC,20))) +#define TSB_T32A4_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,0))) +#define TSB_T32A4_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,1))) +#define TSB_T32A4_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,2))) +#define TSB_T32A4_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,3))) +#define TSB_T32A4_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->STC,4))) +#define TSB_T32A4_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,0))) +#define TSB_T32A4_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,1))) +#define TSB_T32A4_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,2))) +#define TSB_T32A4_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,3))) +#define TSB_T32A4_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->IMC,4))) +#define TSB_T32A4_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,0))) +#define TSB_T32A4_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,1))) +#define TSB_T32A4_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->DMAC,2))) +#define TSB_T32A4_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,0))) +#define TSB_T32A4_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A4->PLSCR,1))) + +#define TSB_T32A5_MOD_MODE32 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,0))) +#define TSB_T32A5_MOD_HALT (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->MOD,1))) +#define TSB_T32A5_RUNA_RUNA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,0))) +#define TSB_T32A5_RUNA_SFTSTAA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,1))) +#define TSB_T32A5_RUNA_SFTSTPA (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,2))) +#define TSB_T32A5_RUNA_RUNFLGA (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNA,4))) +#define TSB_T32A5_CRA_WBFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRA,20))) +#define TSB_T32A5_STA_INTA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,0))) +#define TSB_T32A5_STA_INTA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,1))) +#define TSB_T32A5_STA_INTOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,2))) +#define TSB_T32A5_STA_INTUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STA,3))) +#define TSB_T32A5_IMA_IMA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,0))) +#define TSB_T32A5_IMA_IMA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,1))) +#define TSB_T32A5_IMA_IMOFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,2))) +#define TSB_T32A5_IMA_IMUFA (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMA,3))) +#define TSB_T32A5_DMAA_DMAENA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,0))) +#define TSB_T32A5_DMAA_DMAENA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,1))) +#define TSB_T32A5_DMAA_DMAENA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAA,2))) +#define TSB_T32A5_RUNB_RUNB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,0))) +#define TSB_T32A5_RUNB_SFTSTAB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,1))) +#define TSB_T32A5_RUNB_SFTSTPB (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,2))) +#define TSB_T32A5_RUNB_RUNFLGB (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNB,4))) +#define TSB_T32A5_CRB_WBFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRB,20))) +#define TSB_T32A5_STB_INTB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,0))) +#define TSB_T32A5_STB_INTB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,1))) +#define TSB_T32A5_STB_INTOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,2))) +#define TSB_T32A5_STB_INTUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STB,3))) +#define TSB_T32A5_IMB_IMB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,0))) +#define TSB_T32A5_IMB_IMB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,1))) +#define TSB_T32A5_IMB_IMOFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,2))) +#define TSB_T32A5_IMB_IMUFB (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMB,3))) +#define TSB_T32A5_DMAB_DMAENB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,0))) +#define TSB_T32A5_DMAB_DMAENB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,1))) +#define TSB_T32A5_DMAB_DMAENB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAB,2))) +#define TSB_T32A5_RUNC_RUNC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,0))) +#define TSB_T32A5_RUNC_SFTSTAC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,1))) +#define TSB_T32A5_RUNC_SFTSTPC (*((__O uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,2))) +#define TSB_T32A5_RUNC_RUNFLGC (*((__I uint32_t *)BITBAND_PERI(&TSB_T32A5->RUNC,4))) +#define TSB_T32A5_CRC_WBFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->CRC,20))) +#define TSB_T32A5_STC_INTC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,0))) +#define TSB_T32A5_STC_INTC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,1))) +#define TSB_T32A5_STC_INTOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,2))) +#define TSB_T32A5_STC_INTUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,3))) +#define TSB_T32A5_STC_INTSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->STC,4))) +#define TSB_T32A5_IMC_IMC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,0))) +#define TSB_T32A5_IMC_IMC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,1))) +#define TSB_T32A5_IMC_IMOFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,2))) +#define TSB_T32A5_IMC_IMUFC (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,3))) +#define TSB_T32A5_IMC_IMSTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->IMC,4))) +#define TSB_T32A5_DMAC_DMAENC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,0))) +#define TSB_T32A5_DMAC_DMAENC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,1))) +#define TSB_T32A5_DMAC_DMAENC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->DMAC,2))) +#define TSB_T32A5_PLSCR_PMODE (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,0))) +#define TSB_T32A5_PLSCR_PDIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_T32A5->PLSCR,1))) + + +/* Serial Peripheral Interface (TSPI) */ +#define TSB_TSPI0_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR0,0))) +#define TSB_TSPI0_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,12))) +#define TSB_TSPI0_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,13))) +#define TSB_TSPI0_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,14))) +#define TSB_TSPI0_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,15))) +#define TSB_TSPI0_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR1,16))) +#define TSB_TSPI0_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,0))) +#define TSB_TSPI0_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,1))) +#define TSB_TSPI0_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,2))) +#define TSB_TSPI0_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,4))) +#define TSB_TSPI0_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,5))) +#define TSB_TSPI0_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,6))) +#define TSB_TSPI0_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,7))) +#define TSB_TSPI0_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR2,21))) +#define TSB_TSPI0_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,0))) +#define TSB_TSPI0_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI0->CR3,1))) +#define TSB_TSPI0_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,14))) +#define TSB_TSPI0_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,15))) +#define TSB_TSPI0_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,16))) +#define TSB_TSPI0_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,17))) +#define TSB_TSPI0_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,18))) +#define TSB_TSPI0_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,19))) +#define TSB_TSPI0_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR0,31))) +#define TSB_TSPI0_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,0))) +#define TSB_TSPI0_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->FMTR1,1))) +#define TSB_TSPI0_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SECTCR0,0))) +#define TSB_TSPI0_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,4))) +#define TSB_TSPI0_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,5))) +#define TSB_TSPI0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,6))) +#define TSB_TSPI0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,7))) +#define TSB_TSPI0_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,20))) +#define TSB_TSPI0_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,21))) +#define TSB_TSPI0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,22))) +#define TSB_TSPI0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,23))) +#define TSB_TSPI0_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI0->SR,31))) +#define TSB_TSPI0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,0))) +#define TSB_TSPI0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,1))) +#define TSB_TSPI0_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,2))) +#define TSB_TSPI0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI0->ERR,3))) + +#define TSB_TSPI1_CR0_TSPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR0,0))) +#define TSB_TSPI1_CR1_MSTR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,12))) +#define TSB_TSPI1_CR1_TSPIMS (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,13))) +#define TSB_TSPI1_CR1_TRXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,14))) +#define TSB_TSPI1_CR1_TRGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,15))) +#define TSB_TSPI1_CR1_INF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR1,16))) +#define TSB_TSPI1_CR2_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,0))) +#define TSB_TSPI1_CR2_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,1))) +#define TSB_TSPI1_CR2_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,2))) +#define TSB_TSPI1_CR2_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,4))) +#define TSB_TSPI1_CR2_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,5))) +#define TSB_TSPI1_CR2_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,6))) +#define TSB_TSPI1_CR2_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,7))) +#define TSB_TSPI1_CR2_TXDEMP (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR2,21))) +#define TSB_TSPI1_CR3_RFFLLCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,0))) +#define TSB_TSPI1_CR3_TFEMPCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_TSPI1->CR3,1))) +#define TSB_TSPI1_FMTR0_CKPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,14))) +#define TSB_TSPI1_FMTR0_CKPHA (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,15))) +#define TSB_TSPI1_FMTR0_CS0POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,16))) +#define TSB_TSPI1_FMTR0_CS1POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,17))) +#define TSB_TSPI1_FMTR0_CS2POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,18))) +#define TSB_TSPI1_FMTR0_CS3POL (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,19))) +#define TSB_TSPI1_FMTR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR0,31))) +#define TSB_TSPI1_FMTR1_VPM (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,0))) +#define TSB_TSPI1_FMTR1_VPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->FMTR1,1))) +#define TSB_TSPI1_SECTCR0_SECT (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SECTCR0,0))) +#define TSB_TSPI1_SR_RFFLL (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,4))) +#define TSB_TSPI1_SR_INTRXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,5))) +#define TSB_TSPI1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,6))) +#define TSB_TSPI1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,7))) +#define TSB_TSPI1_SR_TFEMP (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,20))) +#define TSB_TSPI1_SR_INTTXWF (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,21))) +#define TSB_TSPI1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,22))) +#define TSB_TSPI1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,23))) +#define TSB_TSPI1_SR_TSPISUE (*((__I uint32_t *)BITBAND_PERI(&TSB_TSPI1->SR,31))) +#define TSB_TSPI1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,0))) +#define TSB_TSPI1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,1))) +#define TSB_TSPI1_ERR_UDRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,2))) +#define TSB_TSPI1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_TSPI1->ERR,3))) + + +/* Asynchronous Serial Communication Circuit (UART) */ +#define TSB_UART0_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SWRST,7))) +#define TSB_UART0_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,2))) +#define TSB_UART0_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,3))) +#define TSB_UART0_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,4))) +#define TSB_UART0_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,5))) +#define TSB_UART0_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,6))) +#define TSB_UART0_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,8))) +#define TSB_UART0_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,9))) +#define TSB_UART0_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,10))) +#define TSB_UART0_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,15))) +#define TSB_UART0_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,16))) +#define TSB_UART0_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,17))) +#define TSB_UART0_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR0,18))) +#define TSB_UART0_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,0))) +#define TSB_UART0_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,1))) +#define TSB_UART0_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,2))) +#define TSB_UART0_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,4))) +#define TSB_UART0_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,5))) +#define TSB_UART0_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,6))) +#define TSB_UART0_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR1,7))) +#define TSB_UART0_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->BRD,23))) +#define TSB_UART0_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,0))) +#define TSB_UART0_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,1))) +#define TSB_UART0_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,2))) +#define TSB_UART0_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->TRANS,3))) +#define TSB_UART0_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,16))) +#define TSB_UART0_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,17))) +#define TSB_UART0_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->DR,18))) +#define TSB_UART0_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,5))) +#define TSB_UART0_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,6))) +#define TSB_UART0_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,7))) +#define TSB_UART0_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,13))) +#define TSB_UART0_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->SR,14))) +#define TSB_UART0_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,15))) +#define TSB_UART0_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART0->SR,31))) +#define TSB_UART0_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,0))) +#define TSB_UART0_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART0->FIFOCLR,1))) +#define TSB_UART0_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,0))) +#define TSB_UART0_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,1))) +#define TSB_UART0_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,2))) +#define TSB_UART0_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,3))) +#define TSB_UART0_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->ERR,4))) + +#define TSB_UART1_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SWRST,7))) +#define TSB_UART1_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,2))) +#define TSB_UART1_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,3))) +#define TSB_UART1_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,4))) +#define TSB_UART1_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,5))) +#define TSB_UART1_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,6))) +#define TSB_UART1_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,8))) +#define TSB_UART1_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,9))) +#define TSB_UART1_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,10))) +#define TSB_UART1_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,15))) +#define TSB_UART1_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,16))) +#define TSB_UART1_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,17))) +#define TSB_UART1_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR0,18))) +#define TSB_UART1_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,0))) +#define TSB_UART1_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,1))) +#define TSB_UART1_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,2))) +#define TSB_UART1_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,4))) +#define TSB_UART1_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,5))) +#define TSB_UART1_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,6))) +#define TSB_UART1_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR1,7))) +#define TSB_UART1_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->BRD,23))) +#define TSB_UART1_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,0))) +#define TSB_UART1_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,1))) +#define TSB_UART1_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,2))) +#define TSB_UART1_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->TRANS,3))) +#define TSB_UART1_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,16))) +#define TSB_UART1_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,17))) +#define TSB_UART1_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->DR,18))) +#define TSB_UART1_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,5))) +#define TSB_UART1_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,6))) +#define TSB_UART1_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,7))) +#define TSB_UART1_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,13))) +#define TSB_UART1_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->SR,14))) +#define TSB_UART1_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,15))) +#define TSB_UART1_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART1->SR,31))) +#define TSB_UART1_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,0))) +#define TSB_UART1_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART1->FIFOCLR,1))) +#define TSB_UART1_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,0))) +#define TSB_UART1_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,1))) +#define TSB_UART1_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,2))) +#define TSB_UART1_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,3))) +#define TSB_UART1_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->ERR,4))) + +#define TSB_UART2_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SWRST,7))) +#define TSB_UART2_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,2))) +#define TSB_UART2_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,3))) +#define TSB_UART2_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,4))) +#define TSB_UART2_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,5))) +#define TSB_UART2_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,6))) +#define TSB_UART2_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,8))) +#define TSB_UART2_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,9))) +#define TSB_UART2_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,10))) +#define TSB_UART2_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,15))) +#define TSB_UART2_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,16))) +#define TSB_UART2_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,17))) +#define TSB_UART2_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR0,18))) +#define TSB_UART2_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,0))) +#define TSB_UART2_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,1))) +#define TSB_UART2_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,2))) +#define TSB_UART2_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,4))) +#define TSB_UART2_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,5))) +#define TSB_UART2_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,6))) +#define TSB_UART2_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->CR1,7))) +#define TSB_UART2_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->BRD,23))) +#define TSB_UART2_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,0))) +#define TSB_UART2_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,1))) +#define TSB_UART2_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,2))) +#define TSB_UART2_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->TRANS,3))) +#define TSB_UART2_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,16))) +#define TSB_UART2_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,17))) +#define TSB_UART2_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->DR,18))) +#define TSB_UART2_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,5))) +#define TSB_UART2_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,6))) +#define TSB_UART2_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,7))) +#define TSB_UART2_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,13))) +#define TSB_UART2_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->SR,14))) +#define TSB_UART2_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,15))) +#define TSB_UART2_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART2->SR,31))) +#define TSB_UART2_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,0))) +#define TSB_UART2_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART2->FIFOCLR,1))) +#define TSB_UART2_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,0))) +#define TSB_UART2_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,1))) +#define TSB_UART2_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,2))) +#define TSB_UART2_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,3))) +#define TSB_UART2_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART2->ERR,4))) + +#define TSB_UART3_SWRST_SWRSTF (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SWRST,7))) +#define TSB_UART3_CR0_PE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,2))) +#define TSB_UART3_CR0_EVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,3))) +#define TSB_UART3_CR0_SBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,4))) +#define TSB_UART3_CR0_DIR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,5))) +#define TSB_UART3_CR0_IV (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,6))) +#define TSB_UART3_CR0_WU (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,8))) +#define TSB_UART3_CR0_RTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,9))) +#define TSB_UART3_CR0_CTSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,10))) +#define TSB_UART3_CR0_LPB (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,15))) +#define TSB_UART3_CR0_HBSEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,16))) +#define TSB_UART3_CR0_HBSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,17))) +#define TSB_UART3_CR0_HBSST (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR0,18))) +#define TSB_UART3_CR1_DMARE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,0))) +#define TSB_UART3_CR1_DMATE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,1))) +#define TSB_UART3_CR1_INTERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,2))) +#define TSB_UART3_CR1_INTRXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,4))) +#define TSB_UART3_CR1_INTRXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,5))) +#define TSB_UART3_CR1_INTTXWE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,6))) +#define TSB_UART3_CR1_INTTXFE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->CR1,7))) +#define TSB_UART3_BRD_KEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->BRD,23))) +#define TSB_UART3_TRANS_RXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,0))) +#define TSB_UART3_TRANS_TXE (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,1))) +#define TSB_UART3_TRANS_TXTRG (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,2))) +#define TSB_UART3_TRANS_BK (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->TRANS,3))) +#define TSB_UART3_DR_BERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,16))) +#define TSB_UART3_DR_FERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,17))) +#define TSB_UART3_DR_PERR (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->DR,18))) +#define TSB_UART3_SR_RXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,5))) +#define TSB_UART3_SR_RXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,6))) +#define TSB_UART3_SR_RXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,7))) +#define TSB_UART3_SR_TXFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,13))) +#define TSB_UART3_SR_TXEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->SR,14))) +#define TSB_UART3_SR_TXRUN (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,15))) +#define TSB_UART3_SR_SUE (*((__I uint32_t *)BITBAND_PERI(&TSB_UART3->SR,31))) +#define TSB_UART3_FIFOCLR_RFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,0))) +#define TSB_UART3_FIFOCLR_TFCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_UART3->FIFOCLR,1))) +#define TSB_UART3_ERR_BERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,0))) +#define TSB_UART3_ERR_FERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,1))) +#define TSB_UART3_ERR_PERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,2))) +#define TSB_UART3_ERR_OVRERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,3))) +#define TSB_UART3_ERR_TRGERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART3->ERR,4))) + + +/* I2C Interface (I2C) */ +#define TSB_I2C0_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3))) +#define TSB_I2C0_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4))) +#define TSB_I2C0_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0))) +#define TSB_I2C0_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3))) +#define TSB_I2C0_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4))) +#define TSB_I2C0_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5))) +#define TSB_I2C0_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6))) +#define TSB_I2C0_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7))) +#define TSB_I2C0_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0))) +#define TSB_I2C0_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1))) +#define TSB_I2C0_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2))) +#define TSB_I2C0_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3))) +#define TSB_I2C0_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4))) +#define TSB_I2C0_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5))) +#define TSB_I2C0_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6))) +#define TSB_I2C0_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7))) +#define TSB_I2C0_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0))) +#define TSB_I2C0_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,1))) +#define TSB_I2C0_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,2))) +#define TSB_I2C0_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,3))) +#define TSB_I2C0_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,4))) +#define TSB_I2C0_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,5))) +#define TSB_I2C0_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,6))) +#define TSB_I2C0_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,0))) +#define TSB_I2C0_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,1))) +#define TSB_I2C0_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,2))) +#define TSB_I2C0_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->ST,3))) +#define TSB_I2C0_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,0))) +#define TSB_I2C0_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,1))) +#define TSB_I2C0_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,2))) +#define TSB_I2C0_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,3))) +#define TSB_I2C0_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,4))) +#define TSB_I2C0_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,5))) +#define TSB_I2C0_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,6))) +#define TSB_I2C0_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->OP,7))) +#define TSB_I2C0_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,0))) +#define TSB_I2C0_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C0->PM,1))) +#define TSB_I2C0_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR2,0))) + +#define TSB_I2C1_CR1_NOACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3))) +#define TSB_I2C1_CR1_ACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4))) +#define TSB_I2C1_AR_ALS (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0))) +#define TSB_I2C1_CR2_I2CM (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3))) +#define TSB_I2C1_CR2_PIN (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4))) +#define TSB_I2C1_CR2_BB (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5))) +#define TSB_I2C1_CR2_TRX (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6))) +#define TSB_I2C1_CR2_MST (*((__O uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7))) +#define TSB_I2C1_SR_LRB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0))) +#define TSB_I2C1_SR_AD0 (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1))) +#define TSB_I2C1_SR_AAS (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2))) +#define TSB_I2C1_SR_AL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3))) +#define TSB_I2C1_SR_PIN (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4))) +#define TSB_I2C1_SR_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5))) +#define TSB_I2C1_SR_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6))) +#define TSB_I2C1_SR_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7))) +#define TSB_I2C1_IE_INTI2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0))) +#define TSB_I2C1_IE_INTI2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,1))) +#define TSB_I2C1_IE_INTI2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,2))) +#define TSB_I2C1_IE_INTNACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,3))) +#define TSB_I2C1_IE_DMARI2CRX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,4))) +#define TSB_I2C1_IE_DMARI2CTX (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,5))) +#define TSB_I2C1_IE_SELPINCD (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,6))) +#define TSB_I2C1_ST_I2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,0))) +#define TSB_I2C1_ST_I2CAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,1))) +#define TSB_I2C1_ST_I2CBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,2))) +#define TSB_I2C1_ST_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->ST,3))) +#define TSB_I2C1_OP_MFACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,0))) +#define TSB_I2C1_OP_SREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,1))) +#define TSB_I2C1_OP_GCDI (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,2))) +#define TSB_I2C1_OP_RSTA (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,3))) +#define TSB_I2C1_OP_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,4))) +#define TSB_I2C1_OP_SAST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,5))) +#define TSB_I2C1_OP_SA2ST (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,6))) +#define TSB_I2C1_OP_DISAL (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->OP,7))) +#define TSB_I2C1_PM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,0))) +#define TSB_I2C1_PM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_I2C1->PM,1))) +#define TSB_I2C1_AR2_SA2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR2,0))) + + +/* I2C Interface Version A (EI2C) */ +#define TSB_EI2C0_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AEN,0))) +#define TSB_EI2C0_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,0))) +#define TSB_EI2C0_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,1))) +#define TSB_EI2C0_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,2))) +#define TSB_EI2C0_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,3))) +#define TSB_EI2C0_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,4))) +#define TSB_EI2C0_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,8))) +#define TSB_EI2C0_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR0,11))) +#define TSB_EI2C0_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,0))) +#define TSB_EI2C0_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,1))) +#define TSB_EI2C0_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,2))) +#define TSB_EI2C0_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,3))) +#define TSB_EI2C0_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,4))) +#define TSB_EI2C0_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ACR1,10))) +#define TSB_EI2C0_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,0))) +#define TSB_EI2C0_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,1))) +#define TSB_EI2C0_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,2))) +#define TSB_EI2C0_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR0,3))) +#define TSB_EI2C0_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,0))) +#define TSB_EI2C0_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,1))) +#define TSB_EI2C0_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,2))) +#define TSB_EI2C0_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,3))) +#define TSB_EI2C0_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,4))) +#define TSB_EI2C0_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,5))) +#define TSB_EI2C0_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,6))) +#define TSB_EI2C0_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,7))) +#define TSB_EI2C0_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,8))) +#define TSB_EI2C0_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,9))) +#define TSB_EI2C0_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,10))) +#define TSB_EI2C0_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,11))) +#define TSB_EI2C0_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,12))) +#define TSB_EI2C0_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->ASR1,13))) +#define TSB_EI2C0_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,0))) +#define TSB_EI2C0_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR1,15))) +#define TSB_EI2C0_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,0))) +#define TSB_EI2C0_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AAR2,15))) +#define TSB_EI2C0_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,0))) +#define TSB_EI2C0_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,1))) +#define TSB_EI2C0_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,2))) +#define TSB_EI2C0_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,6))) +#define TSB_EI2C0_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,7))) +#define TSB_EI2C0_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,8))) +#define TSB_EI2C0_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,9))) +#define TSB_EI2C0_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,11))) +#define TSB_EI2C0_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,12))) +#define TSB_EI2C0_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,13))) +#define TSB_EI2C0_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,14))) +#define TSB_EI2C0_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C0->AIE,15))) +#define TSB_EI2C0_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,0))) +#define TSB_EI2C0_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,1))) +#define TSB_EI2C0_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,2))) +#define TSB_EI2C0_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C0->APM,3))) + +#define TSB_EI2C1_AEN_I2CM (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AEN,0))) +#define TSB_EI2C1_ACR0_ALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,0))) +#define TSB_EI2C1_ACR0_GCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,1))) +#define TSB_EI2C1_ACR0_NACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,2))) +#define TSB_EI2C1_ACR0_ESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,3))) +#define TSB_EI2C1_ACR0_ESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,4))) +#define TSB_EI2C1_ACR0_TOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,8))) +#define TSB_EI2C1_ACR0_NFSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR0,11))) +#define TSB_EI2C1_ACR1_ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,0))) +#define TSB_EI2C1_ACR1_RS (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,1))) +#define TSB_EI2C1_ACR1_SP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,2))) +#define TSB_EI2C1_ACR1_ACKSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,3))) +#define TSB_EI2C1_ACR1_ACKWAIT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,4))) +#define TSB_EI2C1_ACR1_OMC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ACR1,10))) +#define TSB_EI2C1_ASR0_ACKF (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,0))) +#define TSB_EI2C1_ASR0_BB (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,1))) +#define TSB_EI2C1_ASR0_TRX (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,2))) +#define TSB_EI2C1_ASR0_MST (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR0,3))) +#define TSB_EI2C1_ASR1_STCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,0))) +#define TSB_EI2C1_ASR1_RSCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,1))) +#define TSB_EI2C1_ASR1_SPCF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,2))) +#define TSB_EI2C1_ASR1_TEND (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,3))) +#define TSB_EI2C1_ASR1_TBE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,4))) +#define TSB_EI2C1_ASR1_RBF (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,5))) +#define TSB_EI2C1_ASR1_NACK (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,6))) +#define TSB_EI2C1_ASR1_AL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,7))) +#define TSB_EI2C1_ASR1_GC (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,8))) +#define TSB_EI2C1_ASR1_AAS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,9))) +#define TSB_EI2C1_ASR1_AAS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,10))) +#define TSB_EI2C1_ASR1_EST (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,11))) +#define TSB_EI2C1_ASR1_ESP (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,12))) +#define TSB_EI2C1_ASR1_TOERR (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->ASR1,13))) +#define TSB_EI2C1_AAR1_SA1E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,0))) +#define TSB_EI2C1_AAR1_SAFS1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR1,15))) +#define TSB_EI2C1_AAR2_SA2E (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,0))) +#define TSB_EI2C1_AAR2_SAFS2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AAR2,15))) +#define TSB_EI2C1_AIE_INTSTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,0))) +#define TSB_EI2C1_AIE_INTRSE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,1))) +#define TSB_EI2C1_AIE_INTSPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,2))) +#define TSB_EI2C1_AIE_INTNACKE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,6))) +#define TSB_EI2C1_AIE_INTALE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,7))) +#define TSB_EI2C1_AIE_INTGCE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,8))) +#define TSB_EI2C1_AIE_INTASE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,9))) +#define TSB_EI2C1_AIE_INTESTE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,11))) +#define TSB_EI2C1_AIE_INTESPE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,12))) +#define TSB_EI2C1_AIE_INTTOE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,13))) +#define TSB_EI2C1_AIE_DMATX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,14))) +#define TSB_EI2C1_AIE_DMARX (*((__IO uint32_t *)BITBAND_PERI(&TSB_EI2C1->AIE,15))) +#define TSB_EI2C1_APM_SCL (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,0))) +#define TSB_EI2C1_APM_SDA (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,1))) +#define TSB_EI2C1_APM_SCLOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,2))) +#define TSB_EI2C1_APM_SDAOUT (*((__I uint32_t *)BITBAND_PERI(&TSB_EI2C1->APM,3))) + + +/* Port A */ +#define TSB_PA_DATA_PA0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0))) +#define TSB_PA_DATA_PA1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1))) +#define TSB_PA_DATA_PA2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2))) +#define TSB_PA_DATA_PA3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3))) +#define TSB_PA_DATA_PA4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4))) +#define TSB_PA_CR_PA0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0))) +#define TSB_PA_CR_PA1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1))) +#define TSB_PA_CR_PA2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2))) +#define TSB_PA_CR_PA3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3))) +#define TSB_PA_CR_PA4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4))) +#define TSB_PA_FR1_PA0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0))) +#define TSB_PA_FR1_PA1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1))) +#define TSB_PA_FR1_PA2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2))) +#define TSB_PA_FR1_PA3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3))) +#define TSB_PA_FR1_PA4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4))) +#define TSB_PA_FR4_PA0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,0))) +#define TSB_PA_FR4_PA1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,1))) +#define TSB_PA_FR4_PA2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,2))) +#define TSB_PA_FR4_PA3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,3))) +#define TSB_PA_FR4_PA4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,4))) +#define TSB_PA_FR5_PA2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,2))) +#define TSB_PA_FR5_PA3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,3))) +#define TSB_PA_FR6_PA2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR6,2))) +#define TSB_PA_FR7_PA2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,2))) +#define TSB_PA_FR7_PA3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,3))) +#define TSB_PA_FR7_PA4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR7,4))) +#define TSB_PA_OD_PA0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0))) +#define TSB_PA_OD_PA1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1))) +#define TSB_PA_OD_PA2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2))) +#define TSB_PA_OD_PA3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3))) +#define TSB_PA_OD_PA4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4))) +#define TSB_PA_PUP_PA0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0))) +#define TSB_PA_PUP_PA1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1))) +#define TSB_PA_PUP_PA2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,2))) +#define TSB_PA_PUP_PA3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3))) +#define TSB_PA_PUP_PA4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4))) +#define TSB_PA_PDN_PA0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,0))) +#define TSB_PA_PDN_PA1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,1))) +#define TSB_PA_PDN_PA2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2))) +#define TSB_PA_PDN_PA3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,3))) +#define TSB_PA_PDN_PA4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,4))) +#define TSB_PA_IE_PA0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0))) +#define TSB_PA_IE_PA1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1))) +#define TSB_PA_IE_PA2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2))) +#define TSB_PA_IE_PA3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3))) +#define TSB_PA_IE_PA4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4))) + + +/* Port B */ +#define TSB_PB_DATA_PB0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0))) +#define TSB_PB_DATA_PB1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1))) +#define TSB_PB_DATA_PB2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2))) +#define TSB_PB_DATA_PB3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3))) +#define TSB_PB_DATA_PB4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4))) +#define TSB_PB_DATA_PB5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5))) +#define TSB_PB_DATA_PB6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6))) +#define TSB_PB_DATA_PB7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7))) +#define TSB_PB_CR_PB0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0))) +#define TSB_PB_CR_PB1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1))) +#define TSB_PB_CR_PB2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2))) +#define TSB_PB_CR_PB3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3))) +#define TSB_PB_CR_PB4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4))) +#define TSB_PB_CR_PB5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5))) +#define TSB_PB_CR_PB6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6))) +#define TSB_PB_CR_PB7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7))) +#define TSB_PB_FR4_PB0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,0))) +#define TSB_PB_FR4_PB1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,1))) +#define TSB_PB_FR4_PB2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2))) +#define TSB_PB_FR4_PB3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3))) +#define TSB_PB_FR4_PB4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,4))) +#define TSB_PB_FR4_PB5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,5))) +#define TSB_PB_FR4_PB6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,6))) +#define TSB_PB_FR4_PB7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,7))) +#define TSB_PB_FR5_PB7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7))) +#define TSB_PB_OD_PB0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0))) +#define TSB_PB_OD_PB1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1))) +#define TSB_PB_OD_PB2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2))) +#define TSB_PB_OD_PB3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3))) +#define TSB_PB_OD_PB4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4))) +#define TSB_PB_OD_PB5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5))) +#define TSB_PB_OD_PB6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6))) +#define TSB_PB_OD_PB7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7))) +#define TSB_PB_PUP_PB0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0))) +#define TSB_PB_PUP_PB1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1))) +#define TSB_PB_PUP_PB2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2))) +#define TSB_PB_PUP_PB3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3))) +#define TSB_PB_PUP_PB4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4))) +#define TSB_PB_PUP_PB5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5))) +#define TSB_PB_PUP_PB6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6))) +#define TSB_PB_PUP_PB7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7))) +#define TSB_PB_PDN_PB0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,0))) +#define TSB_PB_PDN_PB1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,1))) +#define TSB_PB_PDN_PB2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,2))) +#define TSB_PB_PDN_PB3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,3))) +#define TSB_PB_PDN_PB4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,4))) +#define TSB_PB_PDN_PB5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,5))) +#define TSB_PB_PDN_PB6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,6))) +#define TSB_PB_PDN_PB7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PDN,7))) +#define TSB_PB_IE_PB0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0))) +#define TSB_PB_IE_PB1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1))) +#define TSB_PB_IE_PB2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2))) +#define TSB_PB_IE_PB3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3))) +#define TSB_PB_IE_PB4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4))) +#define TSB_PB_IE_PB5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5))) +#define TSB_PB_IE_PB6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,6))) +#define TSB_PB_IE_PB7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7))) + + +/* Port C */ +#define TSB_PC_DATA_PC0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0))) +#define TSB_PC_DATA_PC1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1))) +#define TSB_PC_DATA_PC2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2))) +#define TSB_PC_DATA_PC3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3))) +#define TSB_PC_DATA_PC4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4))) +#define TSB_PC_DATA_PC5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5))) +#define TSB_PC_DATA_PC6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,6))) +#define TSB_PC_DATA_PC7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,7))) +#define TSB_PC_CR_PC0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0))) +#define TSB_PC_CR_PC1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1))) +#define TSB_PC_CR_PC2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2))) +#define TSB_PC_CR_PC3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3))) +#define TSB_PC_CR_PC4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4))) +#define TSB_PC_CR_PC5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5))) +#define TSB_PC_CR_PC6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,6))) +#define TSB_PC_CR_PC7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,7))) +#define TSB_PC_FR1_PC0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,0))) +#define TSB_PC_FR1_PC1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,1))) +#define TSB_PC_FR1_PC4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4))) +#define TSB_PC_FR1_PC5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5))) +#define TSB_PC_FR2_PC0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,0))) +#define TSB_PC_FR2_PC1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,1))) +#define TSB_PC_FR2_PC4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,4))) +#define TSB_PC_FR2_PC5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5))) +#define TSB_PC_FR3_PC0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,0))) +#define TSB_PC_FR3_PC1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,1))) +#define TSB_PC_FR3_PC2F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,2))) +#define TSB_PC_FR3_PC3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,3))) +#define TSB_PC_FR3_PC4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,4))) +#define TSB_PC_FR3_PC5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,5))) +#define TSB_PC_FR3_PC6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,6))) +#define TSB_PC_FR3_PC7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR3,7))) +#define TSB_PC_FR4_PC0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,0))) +#define TSB_PC_FR4_PC1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR4,1))) +#define TSB_PC_FR5_PC0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,0))) +#define TSB_PC_FR5_PC1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,1))) +#define TSB_PC_FR5_PC2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,2))) +#define TSB_PC_FR5_PC3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,3))) +#define TSB_PC_FR5_PC6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,6))) +#define TSB_PC_FR5_PC7F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR5,7))) +#define TSB_PC_FR6_PC0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,0))) +#define TSB_PC_FR6_PC1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,1))) +#define TSB_PC_FR6_PC2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,2))) +#define TSB_PC_FR6_PC6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR6,6))) +#define TSB_PC_FR7_PC2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR7,2))) +#define TSB_PC_FR7_PC3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR7,3))) +#define TSB_PC_OD_PC0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0))) +#define TSB_PC_OD_PC1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1))) +#define TSB_PC_OD_PC2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2))) +#define TSB_PC_OD_PC3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3))) +#define TSB_PC_OD_PC4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4))) +#define TSB_PC_OD_PC5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5))) +#define TSB_PC_OD_PC6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,6))) +#define TSB_PC_OD_PC7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,7))) +#define TSB_PC_PUP_PC0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0))) +#define TSB_PC_PUP_PC1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1))) +#define TSB_PC_PUP_PC2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2))) +#define TSB_PC_PUP_PC3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3))) +#define TSB_PC_PUP_PC4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4))) +#define TSB_PC_PUP_PC5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5))) +#define TSB_PC_PUP_PC6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,6))) +#define TSB_PC_PUP_PC7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,7))) +#define TSB_PC_PDN_PC0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,0))) +#define TSB_PC_PDN_PC1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,1))) +#define TSB_PC_PDN_PC2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,2))) +#define TSB_PC_PDN_PC3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,3))) +#define TSB_PC_PDN_PC4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,4))) +#define TSB_PC_PDN_PC5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,5))) +#define TSB_PC_PDN_PC6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,6))) +#define TSB_PC_PDN_PC7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PDN,7))) +#define TSB_PC_IE_PC0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0))) +#define TSB_PC_IE_PC1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1))) +#define TSB_PC_IE_PC2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2))) +#define TSB_PC_IE_PC3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3))) +#define TSB_PC_IE_PC4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4))) +#define TSB_PC_IE_PC5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5))) +#define TSB_PC_IE_PC6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,6))) +#define TSB_PC_IE_PC7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,7))) + + +/* Port D */ +#define TSB_PD_DATA_PD0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0))) +#define TSB_PD_DATA_PD1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1))) +#define TSB_PD_DATA_PD2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2))) +#define TSB_PD_DATA_PD3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3))) +#define TSB_PD_DATA_PD4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4))) +#define TSB_PD_DATA_PD5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,5))) +#define TSB_PD_CR_PD0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0))) +#define TSB_PD_CR_PD1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1))) +#define TSB_PD_CR_PD2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2))) +#define TSB_PD_CR_PD3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3))) +#define TSB_PD_CR_PD4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4))) +#define TSB_PD_CR_PD5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,5))) +#define TSB_PD_FR1_PD2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2))) +#define TSB_PD_FR1_PD3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3))) +#define TSB_PD_FR2_PD3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,3))) +#define TSB_PD_FR2_PD4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR2,4))) +#define TSB_PD_FR3_PD3F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,3))) +#define TSB_PD_FR3_PD4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR3,4))) +#define TSB_PD_FR4_PD0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,0))) +#define TSB_PD_FR4_PD1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,1))) +#define TSB_PD_FR4_PD2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,2))) +#define TSB_PD_FR4_PD3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,3))) +#define TSB_PD_FR4_PD4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,4))) +#define TSB_PD_FR4_PD5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR4,5))) +#define TSB_PD_FR5_PD2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,2))) +#define TSB_PD_FR5_PD3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR5,3))) +#define TSB_PD_FR6_PD3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,3))) +#define TSB_PD_FR6_PD4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,4))) +#define TSB_PD_FR6_PD5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR6,5))) +#define TSB_PD_OD_PD0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0))) +#define TSB_PD_OD_PD1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1))) +#define TSB_PD_OD_PD2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2))) +#define TSB_PD_OD_PD3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3))) +#define TSB_PD_OD_PD4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4))) +#define TSB_PD_OD_PD5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,5))) +#define TSB_PD_PUP_PD0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0))) +#define TSB_PD_PUP_PD1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1))) +#define TSB_PD_PUP_PD2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2))) +#define TSB_PD_PUP_PD3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3))) +#define TSB_PD_PUP_PD4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4))) +#define TSB_PD_PUP_PD5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,5))) +#define TSB_PD_PDN_PD0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,0))) +#define TSB_PD_PDN_PD1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,1))) +#define TSB_PD_PDN_PD2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,2))) +#define TSB_PD_PDN_PD3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,3))) +#define TSB_PD_PDN_PD4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,4))) +#define TSB_PD_PDN_PD5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PDN,5))) +#define TSB_PD_IE_PD0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0))) +#define TSB_PD_IE_PD1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1))) +#define TSB_PD_IE_PD2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2))) +#define TSB_PD_IE_PD3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3))) +#define TSB_PD_IE_PD4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4))) +#define TSB_PD_IE_PD5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,5))) + + +/* Port E */ +#define TSB_PE_DATA_PE0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0))) +#define TSB_PE_DATA_PE1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1))) +#define TSB_PE_DATA_PE2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2))) +#define TSB_PE_DATA_PE3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3))) +#define TSB_PE_DATA_PE4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4))) +#define TSB_PE_DATA_PE5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5))) +#define TSB_PE_DATA_PE6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6))) +#define TSB_PE_DATA_PE7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7))) +#define TSB_PE_CR_PE0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0))) +#define TSB_PE_CR_PE1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1))) +#define TSB_PE_CR_PE2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2))) +#define TSB_PE_CR_PE3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3))) +#define TSB_PE_CR_PE4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4))) +#define TSB_PE_CR_PE5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5))) +#define TSB_PE_CR_PE6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6))) +#define TSB_PE_CR_PE7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7))) +#define TSB_PE_FR4_PE1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,1))) +#define TSB_PE_FR4_PE2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,2))) +#define TSB_PE_FR4_PE3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3))) +#define TSB_PE_FR4_PE4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4))) +#define TSB_PE_FR4_PE5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,5))) +#define TSB_PE_FR4_PE6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,6))) +#define TSB_PE_FR5_PE1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1))) +#define TSB_PE_FR5_PE2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2))) +#define TSB_PE_FR5_PE3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3))) +#define TSB_PE_FR6_PE0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,0))) +#define TSB_PE_FR6_PE1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,1))) +#define TSB_PE_FR6_PE2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,2))) +#define TSB_PE_FR6_PE3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,3))) +#define TSB_PE_FR6_PE4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,4))) +#define TSB_PE_FR6_PE5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,5))) +#define TSB_PE_FR6_PE6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,6))) +#define TSB_PE_FR6_PE7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR6,7))) +#define TSB_PE_FR7_PE7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR7,7))) +#define TSB_PE_OD_PE0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0))) +#define TSB_PE_OD_PE1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1))) +#define TSB_PE_OD_PE2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2))) +#define TSB_PE_OD_PE3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3))) +#define TSB_PE_OD_PE4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4))) +#define TSB_PE_OD_PE5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5))) +#define TSB_PE_OD_PE6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6))) +#define TSB_PE_OD_PE7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7))) +#define TSB_PE_PUP_PE0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0))) +#define TSB_PE_PUP_PE1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1))) +#define TSB_PE_PUP_PE2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2))) +#define TSB_PE_PUP_PE3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3))) +#define TSB_PE_PUP_PE4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4))) +#define TSB_PE_PUP_PE5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5))) +#define TSB_PE_PUP_PE6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6))) +#define TSB_PE_PUP_PE7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7))) +#define TSB_PE_PDN_PE0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,0))) +#define TSB_PE_PDN_PE1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,1))) +#define TSB_PE_PDN_PE2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,2))) +#define TSB_PE_PDN_PE3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,3))) +#define TSB_PE_PDN_PE4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,4))) +#define TSB_PE_PDN_PE5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,5))) +#define TSB_PE_PDN_PE6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,6))) +#define TSB_PE_PDN_PE7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PDN,7))) +#define TSB_PE_IE_PE0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0))) +#define TSB_PE_IE_PE1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1))) +#define TSB_PE_IE_PE2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2))) +#define TSB_PE_IE_PE3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3))) +#define TSB_PE_IE_PE4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4))) +#define TSB_PE_IE_PE5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5))) +#define TSB_PE_IE_PE6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6))) +#define TSB_PE_IE_PE7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7))) + + +/* Port F */ +#define TSB_PF_DATA_PF0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0))) +#define TSB_PF_DATA_PF1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1))) +#define TSB_PF_DATA_PF2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2))) +#define TSB_PF_DATA_PF3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3))) +#define TSB_PF_DATA_PF4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4))) +#define TSB_PF_DATA_PF5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5))) +#define TSB_PF_DATA_PF6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6))) +#define TSB_PF_DATA_PF7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7))) +#define TSB_PF_CR_PF0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0))) +#define TSB_PF_CR_PF1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1))) +#define TSB_PF_CR_PF2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2))) +#define TSB_PF_CR_PF3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3))) +#define TSB_PF_CR_PF4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4))) +#define TSB_PF_CR_PF5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5))) +#define TSB_PF_CR_PF6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6))) +#define TSB_PF_CR_PF7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7))) +#define TSB_PF_FR1_PF0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0))) +#define TSB_PF_FR1_PF1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1))) +#define TSB_PF_FR1_PF3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3))) +#define TSB_PF_FR1_PF4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4))) +#define TSB_PF_FR1_PF6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6))) +#define TSB_PF_FR1_PF7F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7))) +#define TSB_PF_FR2_PF0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,0))) +#define TSB_PF_FR2_PF1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,1))) +#define TSB_PF_FR2_PF3F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,3))) +#define TSB_PF_FR2_PF4F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,4))) +#define TSB_PF_FR2_PF6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,6))) +#define TSB_PF_FR2_PF7F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR2,7))) +#define TSB_PF_FR3_PF4F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,4))) +#define TSB_PF_FR3_PF5F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,5))) +#define TSB_PF_FR3_PF6F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,6))) +#define TSB_PF_FR3_PF7F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,7))) +#define TSB_PF_FR4_PF0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,0))) +#define TSB_PF_FR4_PF1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,1))) +#define TSB_PF_FR4_PF2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,2))) +#define TSB_PF_FR4_PF3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,3))) +#define TSB_PF_FR4_PF4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,4))) +#define TSB_PF_FR4_PF5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,5))) +#define TSB_PF_FR4_PF6F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,6))) +#define TSB_PF_FR4_PF7F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,7))) +#define TSB_PF_FR5_PF0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,0))) +#define TSB_PF_FR5_PF1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,1))) +#define TSB_PF_FR5_PF2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,2))) +#define TSB_PF_FR5_PF3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,3))) +#define TSB_PF_FR5_PF4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,4))) +#define TSB_PF_FR5_PF5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,5))) +#define TSB_PF_FR6_PF3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,3))) +#define TSB_PF_FR6_PF4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,4))) +#define TSB_PF_FR6_PF5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR6,5))) +#define TSB_PF_FR7_PF0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,0))) +#define TSB_PF_FR7_PF1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,1))) +#define TSB_PF_FR7_PF2F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,2))) +#define TSB_PF_FR7_PF3F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,3))) +#define TSB_PF_FR7_PF4F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,4))) +#define TSB_PF_FR7_PF5F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,5))) +#define TSB_PF_FR7_PF6F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,6))) +#define TSB_PF_FR7_PF7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR7,7))) +#define TSB_PF_OD_PF0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0))) +#define TSB_PF_OD_PF1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1))) +#define TSB_PF_OD_PF2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2))) +#define TSB_PF_OD_PF3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3))) +#define TSB_PF_OD_PF4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4))) +#define TSB_PF_OD_PF5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5))) +#define TSB_PF_OD_PF6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6))) +#define TSB_PF_OD_PF7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7))) +#define TSB_PF_PUP_PF0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0))) +#define TSB_PF_PUP_PF1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1))) +#define TSB_PF_PUP_PF2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2))) +#define TSB_PF_PUP_PF3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3))) +#define TSB_PF_PUP_PF4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4))) +#define TSB_PF_PUP_PF5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5))) +#define TSB_PF_PUP_PF6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6))) +#define TSB_PF_PUP_PF7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7))) +#define TSB_PF_PDN_PF0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,0))) +#define TSB_PF_PDN_PF1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,1))) +#define TSB_PF_PDN_PF2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,2))) +#define TSB_PF_PDN_PF3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,3))) +#define TSB_PF_PDN_PF4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,4))) +#define TSB_PF_PDN_PF5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,5))) +#define TSB_PF_PDN_PF6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,6))) +#define TSB_PF_PDN_PF7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PDN,7))) +#define TSB_PF_IE_PF0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0))) +#define TSB_PF_IE_PF1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1))) +#define TSB_PF_IE_PF2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2))) +#define TSB_PF_IE_PF3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3))) +#define TSB_PF_IE_PF4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4))) +#define TSB_PF_IE_PF5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5))) +#define TSB_PF_IE_PF6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6))) +#define TSB_PF_IE_PF7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7))) + + +/* Port G */ +#define TSB_PG_DATA_PG0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0))) +#define TSB_PG_DATA_PG1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1))) +#define TSB_PG_DATA_PG2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2))) +#define TSB_PG_DATA_PG3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3))) +#define TSB_PG_DATA_PG4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4))) +#define TSB_PG_DATA_PG5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5))) +#define TSB_PG_DATA_PG6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6))) +#define TSB_PG_CR_PG0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0))) +#define TSB_PG_CR_PG1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1))) +#define TSB_PG_CR_PG2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2))) +#define TSB_PG_CR_PG3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3))) +#define TSB_PG_CR_PG4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4))) +#define TSB_PG_CR_PG5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5))) +#define TSB_PG_CR_PG6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6))) +#define TSB_PG_FR1_PG1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1))) +#define TSB_PG_FR1_PG2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2))) +#define TSB_PG_FR1_PG3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3))) +#define TSB_PG_FR1_PG4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4))) +#define TSB_PG_FR1_PG5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,5))) +#define TSB_PG_FR1_PG6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6))) +#define TSB_PG_FR4_PG0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,0))) +#define TSB_PG_FR4_PG1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,1))) +#define TSB_PG_FR4_PG2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2))) +#define TSB_PG_FR4_PG3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3))) +#define TSB_PG_FR4_PG4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,4))) +#define TSB_PG_FR4_PG5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,5))) +#define TSB_PG_FR5_PG0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0))) +#define TSB_PG_FR5_PG1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1))) +#define TSB_PG_FR5_PG2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2))) +#define TSB_PG_OD_PG0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0))) +#define TSB_PG_OD_PG1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1))) +#define TSB_PG_OD_PG2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2))) +#define TSB_PG_OD_PG3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3))) +#define TSB_PG_OD_PG4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4))) +#define TSB_PG_OD_PG5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5))) +#define TSB_PG_OD_PG6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6))) +#define TSB_PG_PUP_PG0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0))) +#define TSB_PG_PUP_PG1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1))) +#define TSB_PG_PUP_PG2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2))) +#define TSB_PG_PUP_PG3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3))) +#define TSB_PG_PUP_PG4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4))) +#define TSB_PG_PUP_PG5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5))) +#define TSB_PG_PUP_PG6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6))) +#define TSB_PG_PDN_PG0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,0))) +#define TSB_PG_PDN_PG1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,1))) +#define TSB_PG_PDN_PG2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,2))) +#define TSB_PG_PDN_PG3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,3))) +#define TSB_PG_PDN_PG4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,4))) +#define TSB_PG_PDN_PG5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,5))) +#define TSB_PG_PDN_PG6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PDN,6))) +#define TSB_PG_IE_PG0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0))) +#define TSB_PG_IE_PG1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1))) +#define TSB_PG_IE_PG2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2))) +#define TSB_PG_IE_PG3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3))) +#define TSB_PG_IE_PG4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4))) +#define TSB_PG_IE_PG5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5))) +#define TSB_PG_IE_PG6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6))) + + +/* Port H */ +#define TSB_PH_DATA_PH0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0))) +#define TSB_PH_DATA_PH1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1))) +#define TSB_PH_PDN_PH0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,0))) +#define TSB_PH_PDN_PH1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PDN,1))) +#define TSB_PH_IE_PH0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0))) +#define TSB_PH_IE_PH1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1))) + + +/* Port J */ +#define TSB_PJ_DATA_PJ0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0))) +#define TSB_PJ_DATA_PJ1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1))) +#define TSB_PJ_DATA_PJ2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2))) +#define TSB_PJ_DATA_PJ3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3))) +#define TSB_PJ_DATA_PJ4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4))) +#define TSB_PJ_DATA_PJ5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5))) +#define TSB_PJ_CR_PJ0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0))) +#define TSB_PJ_CR_PJ1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1))) +#define TSB_PJ_CR_PJ2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2))) +#define TSB_PJ_CR_PJ3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3))) +#define TSB_PJ_CR_PJ4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4))) +#define TSB_PJ_CR_PJ5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5))) +#define TSB_PJ_OD_PJ0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0))) +#define TSB_PJ_OD_PJ1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1))) +#define TSB_PJ_OD_PJ2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2))) +#define TSB_PJ_OD_PJ3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3))) +#define TSB_PJ_OD_PJ4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4))) +#define TSB_PJ_OD_PJ5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5))) +#define TSB_PJ_PUP_PJ0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0))) +#define TSB_PJ_PUP_PJ1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1))) +#define TSB_PJ_PUP_PJ2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2))) +#define TSB_PJ_PUP_PJ3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3))) +#define TSB_PJ_PUP_PJ4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4))) +#define TSB_PJ_PUP_PJ5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5))) +#define TSB_PJ_PDN_PJ0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,0))) +#define TSB_PJ_PDN_PJ1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,1))) +#define TSB_PJ_PDN_PJ2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,2))) +#define TSB_PJ_PDN_PJ3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,3))) +#define TSB_PJ_PDN_PJ4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,4))) +#define TSB_PJ_PDN_PJ5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PDN,5))) +#define TSB_PJ_IE_PJ0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0))) +#define TSB_PJ_IE_PJ1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1))) +#define TSB_PJ_IE_PJ2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2))) +#define TSB_PJ_IE_PJ3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3))) +#define TSB_PJ_IE_PJ4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4))) +#define TSB_PJ_IE_PJ5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5))) + + +/* Port K */ +#define TSB_PK_DATA_PK0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0))) +#define TSB_PK_DATA_PK1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1))) +#define TSB_PK_DATA_PK2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2))) +#define TSB_PK_DATA_PK3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3))) +#define TSB_PK_DATA_PK4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4))) +#define TSB_PK_CR_PK0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0))) +#define TSB_PK_CR_PK1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1))) +#define TSB_PK_CR_PK2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2))) +#define TSB_PK_CR_PK3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3))) +#define TSB_PK_CR_PK4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4))) +#define TSB_PK_OD_PK0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0))) +#define TSB_PK_OD_PK1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1))) +#define TSB_PK_OD_PK2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2))) +#define TSB_PK_OD_PK3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3))) +#define TSB_PK_OD_PK4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4))) +#define TSB_PK_PUP_PK0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0))) +#define TSB_PK_PUP_PK1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1))) +#define TSB_PK_PUP_PK2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2))) +#define TSB_PK_PUP_PK3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3))) +#define TSB_PK_PUP_PK4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4))) +#define TSB_PK_PDN_PK0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,0))) +#define TSB_PK_PDN_PK1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,1))) +#define TSB_PK_PDN_PK2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,2))) +#define TSB_PK_PDN_PK3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,3))) +#define TSB_PK_PDN_PK4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PDN,4))) +#define TSB_PK_IE_PK0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0))) +#define TSB_PK_IE_PK1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1))) +#define TSB_PK_IE_PK2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2))) +#define TSB_PK_IE_PK3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3))) +#define TSB_PK_IE_PK4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4))) + + +/* Port L */ +#define TSB_PL_DATA_PL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0))) +#define TSB_PL_DATA_PL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1))) +#define TSB_PL_DATA_PL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2))) +#define TSB_PL_DATA_PL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3))) +#define TSB_PL_DATA_PL4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,4))) +#define TSB_PL_DATA_PL5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,5))) +#define TSB_PL_DATA_PL6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,6))) +#define TSB_PL_DATA_PL7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,7))) +#define TSB_PL_CR_PL0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0))) +#define TSB_PL_CR_PL1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1))) +#define TSB_PL_CR_PL2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2))) +#define TSB_PL_CR_PL3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3))) +#define TSB_PL_CR_PL4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,4))) +#define TSB_PL_CR_PL5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,5))) +#define TSB_PL_CR_PL6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,6))) +#define TSB_PL_CR_PL7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,7))) +#define TSB_PL_OD_PL0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0))) +#define TSB_PL_OD_PL1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1))) +#define TSB_PL_OD_PL2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2))) +#define TSB_PL_OD_PL3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3))) +#define TSB_PL_OD_PL4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,4))) +#define TSB_PL_OD_PL5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,5))) +#define TSB_PL_OD_PL6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,6))) +#define TSB_PL_OD_PL7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,7))) +#define TSB_PL_PUP_PL0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0))) +#define TSB_PL_PUP_PL1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1))) +#define TSB_PL_PUP_PL2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2))) +#define TSB_PL_PUP_PL3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3))) +#define TSB_PL_PUP_PL4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,4))) +#define TSB_PL_PUP_PL5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,5))) +#define TSB_PL_PUP_PL6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,6))) +#define TSB_PL_PUP_PL7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,7))) +#define TSB_PL_PDN_PL0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,0))) +#define TSB_PL_PDN_PL1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,1))) +#define TSB_PL_PDN_PL2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,2))) +#define TSB_PL_PDN_PL3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,3))) +#define TSB_PL_PDN_PL4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,4))) +#define TSB_PL_PDN_PL5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,5))) +#define TSB_PL_PDN_PL6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,6))) +#define TSB_PL_PDN_PL7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PDN,7))) +#define TSB_PL_IE_PL0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0))) +#define TSB_PL_IE_PL1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1))) +#define TSB_PL_IE_PL2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2))) +#define TSB_PL_IE_PL3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3))) +#define TSB_PL_IE_PL4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,4))) +#define TSB_PL_IE_PL5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,5))) +#define TSB_PL_IE_PL6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,6))) +#define TSB_PL_IE_PL7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,7))) + + +/* Port M */ +#define TSB_PM_DATA_PM0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,0))) +#define TSB_PM_DATA_PM1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,1))) +#define TSB_PM_DATA_PM2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->DATA,2))) +#define TSB_PM_CR_PM0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,0))) +#define TSB_PM_CR_PM1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,1))) +#define TSB_PM_CR_PM2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->CR,2))) +#define TSB_PM_OD_PM0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,0))) +#define TSB_PM_OD_PM1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,1))) +#define TSB_PM_OD_PM2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->OD,2))) +#define TSB_PM_PUP_PM0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,0))) +#define TSB_PM_PUP_PM1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,1))) +#define TSB_PM_PUP_PM2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PUP,2))) +#define TSB_PM_PDN_PM0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,0))) +#define TSB_PM_PDN_PM1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,1))) +#define TSB_PM_PDN_PM2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->PDN,2))) +#define TSB_PM_IE_PM0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,0))) +#define TSB_PM_IE_PM1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,1))) +#define TSB_PM_IE_PM2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PM->IE,2))) + + +/* Port N */ +#define TSB_PN_DATA_PN0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,0))) +#define TSB_PN_DATA_PN1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,1))) +#define TSB_PN_DATA_PN2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->DATA,2))) +#define TSB_PN_CR_PN0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,0))) +#define TSB_PN_CR_PN1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,1))) +#define TSB_PN_CR_PN2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->CR,2))) +#define TSB_PN_FR1_PN0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,0))) +#define TSB_PN_FR1_PN1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,1))) +#define TSB_PN_FR1_PN2F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR1,2))) +#define TSB_PN_FR2_PN0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,0))) +#define TSB_PN_FR2_PN1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR2,1))) +#define TSB_PN_FR3_PN0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,0))) +#define TSB_PN_FR3_PN1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR3,1))) +#define TSB_PN_FR4_PN0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,0))) +#define TSB_PN_FR4_PN1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,1))) +#define TSB_PN_FR4_PN2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR4,2))) +#define TSB_PN_FR5_PN0F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,0))) +#define TSB_PN_FR5_PN1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,1))) +#define TSB_PN_FR5_PN2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR5,2))) +#define TSB_PN_FR6_PN0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR6,0))) +#define TSB_PN_FR6_PN1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR6,1))) +#define TSB_PN_FR6_PN2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR6,2))) +#define TSB_PN_FR7_PN0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR7,0))) +#define TSB_PN_FR7_PN1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->FR7,1))) +#define TSB_PN_OD_PN0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,0))) +#define TSB_PN_OD_PN1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,1))) +#define TSB_PN_OD_PN2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->OD,2))) +#define TSB_PN_PUP_PN0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,0))) +#define TSB_PN_PUP_PN1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,1))) +#define TSB_PN_PUP_PN2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PUP,2))) +#define TSB_PN_PDN_PN0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,0))) +#define TSB_PN_PDN_PN1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,1))) +#define TSB_PN_PDN_PN2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->PDN,2))) +#define TSB_PN_IE_PN0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,0))) +#define TSB_PN_IE_PN1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,1))) +#define TSB_PN_IE_PN2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PN->IE,2))) + + +/* Port U */ +#define TSB_PU_DATA_PU0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,0))) +#define TSB_PU_DATA_PU1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,1))) +#define TSB_PU_DATA_PU2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,2))) +#define TSB_PU_DATA_PU3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,3))) +#define TSB_PU_DATA_PU4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,4))) +#define TSB_PU_DATA_PU5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,5))) +#define TSB_PU_DATA_PU6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,6))) +#define TSB_PU_DATA_PU7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->DATA,7))) +#define TSB_PU_CR_PU0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,0))) +#define TSB_PU_CR_PU1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,1))) +#define TSB_PU_CR_PU2C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,2))) +#define TSB_PU_CR_PU3C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,3))) +#define TSB_PU_CR_PU4C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,4))) +#define TSB_PU_CR_PU5C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,5))) +#define TSB_PU_CR_PU6C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,6))) +#define TSB_PU_CR_PU7C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->CR,7))) +#define TSB_PU_FR1_PU0F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,0))) +#define TSB_PU_FR1_PU1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,1))) +#define TSB_PU_FR1_PU3F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,3))) +#define TSB_PU_FR1_PU4F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,4))) +#define TSB_PU_FR1_PU5F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,5))) +#define TSB_PU_FR1_PU6F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR1,6))) +#define TSB_PU_FR2_PU0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,0))) +#define TSB_PU_FR2_PU1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,1))) +#define TSB_PU_FR2_PU5F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,5))) +#define TSB_PU_FR2_PU6F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR2,6))) +#define TSB_PU_FR3_PU0F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,0))) +#define TSB_PU_FR3_PU1F3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR3,1))) +#define TSB_PU_FR4_PU0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,0))) +#define TSB_PU_FR4_PU1F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,1))) +#define TSB_PU_FR4_PU2F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,2))) +#define TSB_PU_FR4_PU3F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,3))) +#define TSB_PU_FR4_PU4F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,4))) +#define TSB_PU_FR4_PU5F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR4,5))) +#define TSB_PU_FR5_PU1F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,1))) +#define TSB_PU_FR5_PU2F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,2))) +#define TSB_PU_FR5_PU3F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,3))) +#define TSB_PU_FR5_PU4F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,4))) +#define TSB_PU_FR5_PU5F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,5))) +#define TSB_PU_FR5_PU6F5 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR5,6))) +#define TSB_PU_FR6_PU0F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,0))) +#define TSB_PU_FR6_PU1F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,1))) +#define TSB_PU_FR6_PU2F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,2))) +#define TSB_PU_FR6_PU3F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,3))) +#define TSB_PU_FR6_PU4F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,4))) +#define TSB_PU_FR6_PU5F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,5))) +#define TSB_PU_FR6_PU6F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,6))) +#define TSB_PU_FR6_PU7F6 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR6,7))) +#define TSB_PU_FR7_PU0F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,0))) +#define TSB_PU_FR7_PU1F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,1))) +#define TSB_PU_FR7_PU7F7 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->FR7,7))) +#define TSB_PU_OD_PU0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,0))) +#define TSB_PU_OD_PU1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,1))) +#define TSB_PU_OD_PU2OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,2))) +#define TSB_PU_OD_PU3OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,3))) +#define TSB_PU_OD_PU4OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,4))) +#define TSB_PU_OD_PU5OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,5))) +#define TSB_PU_OD_PU6OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,6))) +#define TSB_PU_OD_PU7OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->OD,7))) +#define TSB_PU_PUP_PU0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,0))) +#define TSB_PU_PUP_PU1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,1))) +#define TSB_PU_PUP_PU2UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,2))) +#define TSB_PU_PUP_PU3UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,3))) +#define TSB_PU_PUP_PU4UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,4))) +#define TSB_PU_PUP_PU5UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,5))) +#define TSB_PU_PUP_PU6UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,6))) +#define TSB_PU_PUP_PU7UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PUP,7))) +#define TSB_PU_PDN_PU0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,0))) +#define TSB_PU_PDN_PU1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,1))) +#define TSB_PU_PDN_PU2DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,2))) +#define TSB_PU_PDN_PU3DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,3))) +#define TSB_PU_PDN_PU4DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,4))) +#define TSB_PU_PDN_PU5DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,5))) +#define TSB_PU_PDN_PU6DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,6))) +#define TSB_PU_PDN_PU7DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->PDN,7))) +#define TSB_PU_IE_PU0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,0))) +#define TSB_PU_IE_PU1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,1))) +#define TSB_PU_IE_PU2IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,2))) +#define TSB_PU_IE_PU3IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,3))) +#define TSB_PU_IE_PU4IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,4))) +#define TSB_PU_IE_PU5IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,5))) +#define TSB_PU_IE_PU6IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,6))) +#define TSB_PU_IE_PU7IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PU->IE,7))) + + +/* Port V */ +#define TSB_PV_DATA_PV0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,0))) +#define TSB_PV_DATA_PV1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->DATA,1))) +#define TSB_PV_CR_PV0C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,0))) +#define TSB_PV_CR_PV1C (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->CR,1))) +#define TSB_PV_FR1_PV1F1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR1,1))) +#define TSB_PV_FR2_PV0F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,0))) +#define TSB_PV_FR2_PV1F2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR2,1))) +#define TSB_PV_FR4_PV0F4 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->FR4,0))) +#define TSB_PV_OD_PV0OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,0))) +#define TSB_PV_OD_PV1OD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->OD,1))) +#define TSB_PV_PUP_PV0UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,0))) +#define TSB_PV_PUP_PV1UP (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PUP,1))) +#define TSB_PV_PDN_PV0DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,0))) +#define TSB_PV_PDN_PV1DN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->PDN,1))) +#define TSB_PV_IE_PV0IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,0))) +#define TSB_PV_IE_PV1IE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PV->IE,1))) + + +/* Trimming Circuit (TRM) */ +#define TSB_TRM_OSCEN_TRIMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_TRM->OSCEN,0))) + + +/* Oscillation Frequency Detector (OFD) */ +#define TSB_OFD_RST_OFDRSTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->RST,0))) +#define TSB_OFD_STAT_FRQERR (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,0))) +#define TSB_OFD_STAT_OFDBUSY (*((__I uint32_t *)BITBAND_PERI(&TSB_OFD->STAT,1))) +#define TSB_OFD_MON_OFDMON (*((__IO uint32_t *)BITBAND_PERI(&TSB_OFD->MON,0))) + + +/* Advanced Programmable Motor Control Circuit (A-PMD) */ +#define TSB_PMD0_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDEN,0))) +#define TSB_PMD0_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,3))) +#define TSB_PMD0_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,4))) +#define TSB_PMD0_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,5))) +#define TSB_PMD0_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,6))) +#define TSB_PMD0_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDCR,7))) +#define TSB_PMD0_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,0))) +#define TSB_PMD0_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,1))) +#define TSB_PMD0_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->CARSTA,2))) +#define TSB_PMD0_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,0))) +#define TSB_PMD0_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,1))) +#define TSB_PMD0_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,2))) +#define TSB_PMD0_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,3))) +#define TSB_PMD0_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MODESEL,7))) +#define TSB_PMD0_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,8))) +#define TSB_PMD0_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,9))) +#define TSB_PMD0_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDOUT,10))) +#define TSB_PMD0_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,2))) +#define TSB_PMD0_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->MDPOT,3))) +#define TSB_PMD0_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,0))) +#define TSB_PMD0_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,1))) +#define TSB_PMD0_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,2))) +#define TSB_PMD0_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,5))) +#define TSB_PMD0_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,7))) +#define TSB_PMD0_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,13))) +#define TSB_PMD0_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,14))) +#define TSB_PMD0_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGCR,15))) +#define TSB_PMD0_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,0))) +#define TSB_PMD0_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->EMGSTA,1))) +#define TSB_PMD0_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,0))) +#define TSB_PMD0_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,1))) +#define TSB_PMD0_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,2))) +#define TSB_PMD0_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,5))) +#define TSB_PMD0_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,6))) +#define TSB_PMD0_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,7))) +#define TSB_PMD0_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVCR,15))) +#define TSB_PMD0_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,0))) +#define TSB_PMD0_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD0->OVVSTA,1))) +#define TSB_PMD0_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,3))) +#define TSB_PMD0_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,7))) +#define TSB_PMD0_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,11))) +#define TSB_PMD0_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,15))) +#define TSB_PMD0_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGCR,16))) +#define TSB_PMD0_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,0))) +#define TSB_PMD0_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->TRGMD,1))) +#define TSB_PMD0_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->SYNCCR,0))) +#define TSB_PMD0_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,0))) +#define TSB_PMD0_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,3))) +#define TSB_PMD0_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,4))) +#define TSB_PMD0_DBGOUTCR_IADCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,5))) +#define TSB_PMD0_DBGOUTCR_IADDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,6))) +#define TSB_PMD0_DBGOUTCR_IADEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,7))) +#define TSB_PMD0_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,8))) +#define TSB_PMD0_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,9))) +#define TSB_PMD0_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,10))) +#define TSB_PMD0_DBGOUTCR_IVEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,11))) +#define TSB_PMD0_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,12))) +#define TSB_PMD0_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,16))) +#define TSB_PMD0_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,17))) +#define TSB_PMD0_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,18))) +#define TSB_PMD0_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,19))) +#define TSB_PMD0_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,20))) +#define TSB_PMD0_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,21))) +#define TSB_PMD0_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD0->DBGOUTCR,31))) + +#define TSB_PMD1_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDEN,0))) +#define TSB_PMD1_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,3))) +#define TSB_PMD1_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,4))) +#define TSB_PMD1_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,5))) +#define TSB_PMD1_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,6))) +#define TSB_PMD1_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDCR,7))) +#define TSB_PMD1_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->CARSTA,0))) +#define TSB_PMD1_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->CARSTA,1))) +#define TSB_PMD1_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->CARSTA,2))) +#define TSB_PMD1_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,0))) +#define TSB_PMD1_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,1))) +#define TSB_PMD1_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,2))) +#define TSB_PMD1_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,3))) +#define TSB_PMD1_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MODESEL,7))) +#define TSB_PMD1_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDOUT,8))) +#define TSB_PMD1_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDOUT,9))) +#define TSB_PMD1_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDOUT,10))) +#define TSB_PMD1_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDPOT,2))) +#define TSB_PMD1_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->MDPOT,3))) +#define TSB_PMD1_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,0))) +#define TSB_PMD1_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,1))) +#define TSB_PMD1_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,2))) +#define TSB_PMD1_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,5))) +#define TSB_PMD1_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,7))) +#define TSB_PMD1_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,13))) +#define TSB_PMD1_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,14))) +#define TSB_PMD1_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGCR,15))) +#define TSB_PMD1_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGSTA,0))) +#define TSB_PMD1_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->EMGSTA,1))) +#define TSB_PMD1_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,0))) +#define TSB_PMD1_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,1))) +#define TSB_PMD1_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,2))) +#define TSB_PMD1_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,5))) +#define TSB_PMD1_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,6))) +#define TSB_PMD1_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,7))) +#define TSB_PMD1_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVCR,15))) +#define TSB_PMD1_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVSTA,0))) +#define TSB_PMD1_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD1->OVVSTA,1))) +#define TSB_PMD1_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,3))) +#define TSB_PMD1_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,7))) +#define TSB_PMD1_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,11))) +#define TSB_PMD1_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,15))) +#define TSB_PMD1_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGCR,16))) +#define TSB_PMD1_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGMD,0))) +#define TSB_PMD1_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->TRGMD,1))) +#define TSB_PMD1_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->SYNCCR,0))) +#define TSB_PMD1_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,0))) +#define TSB_PMD1_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,3))) +#define TSB_PMD1_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,4))) +#define TSB_PMD1_DBGOUTCR_IADCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,5))) +#define TSB_PMD1_DBGOUTCR_IADDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,6))) +#define TSB_PMD1_DBGOUTCR_IADEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,7))) +#define TSB_PMD1_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,8))) +#define TSB_PMD1_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,9))) +#define TSB_PMD1_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,10))) +#define TSB_PMD1_DBGOUTCR_IVEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,11))) +#define TSB_PMD1_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,12))) +#define TSB_PMD1_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,16))) +#define TSB_PMD1_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,17))) +#define TSB_PMD1_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,18))) +#define TSB_PMD1_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,19))) +#define TSB_PMD1_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,20))) +#define TSB_PMD1_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,21))) +#define TSB_PMD1_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD1->DBGOUTCR,31))) + +#define TSB_PMD2_MDEN_PWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDEN,0))) +#define TSB_PMD2_MDCR_PINT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,3))) +#define TSB_PMD2_MDCR_DTYMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,4))) +#define TSB_PMD2_MDCR_SYNTMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,5))) +#define TSB_PMD2_MDCR_DCMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,6))) +#define TSB_PMD2_MDCR_DTCREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDCR,7))) +#define TSB_PMD2_CARSTA_PWMUST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->CARSTA,0))) +#define TSB_PMD2_CARSTA_PWMVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->CARSTA,1))) +#define TSB_PMD2_CARSTA_PWMWST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->CARSTA,2))) +#define TSB_PMD2_MODESEL_MDSEL0 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,0))) +#define TSB_PMD2_MODESEL_MDSEL1 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,1))) +#define TSB_PMD2_MODESEL_MDSEL2 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,2))) +#define TSB_PMD2_MODESEL_MDSEL3 (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,3))) +#define TSB_PMD2_MODESEL_DCMPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MODESEL,7))) +#define TSB_PMD2_MDOUT_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDOUT,8))) +#define TSB_PMD2_MDOUT_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDOUT,9))) +#define TSB_PMD2_MDOUT_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDOUT,10))) +#define TSB_PMD2_MDPOT_POLL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDPOT,2))) +#define TSB_PMD2_MDPOT_POLH (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->MDPOT,3))) +#define TSB_PMD2_EMGCR_EMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,0))) +#define TSB_PMD2_EMGCR_EMGRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,1))) +#define TSB_PMD2_EMGCR_EMGISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,2))) +#define TSB_PMD2_EMGCR_INHEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,5))) +#define TSB_PMD2_EMGCR_EMGIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,7))) +#define TSB_PMD2_EMGCR_CPAIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,13))) +#define TSB_PMD2_EMGCR_CPBIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,14))) +#define TSB_PMD2_EMGCR_CPCIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGCR,15))) +#define TSB_PMD2_EMGSTA_EMGST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGSTA,0))) +#define TSB_PMD2_EMGSTA_EMGI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->EMGSTA,1))) +#define TSB_PMD2_OVVCR_OVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,0))) +#define TSB_PMD2_OVVCR_OVVRS (*((__O uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,1))) +#define TSB_PMD2_OVVCR_OVVISEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,2))) +#define TSB_PMD2_OVVCR_ADIN0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,5))) +#define TSB_PMD2_OVVCR_ADIN1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,6))) +#define TSB_PMD2_OVVCR_OVVIPOL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,7))) +#define TSB_PMD2_OVVCR_OVVRSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVCR,15))) +#define TSB_PMD2_OVVSTA_OVVST (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVSTA,0))) +#define TSB_PMD2_OVVSTA_OVVI (*((__I uint32_t *)BITBAND_PERI(&TSB_PMD2->OVVSTA,1))) +#define TSB_PMD2_TRGCR_TRG0BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,3))) +#define TSB_PMD2_TRGCR_TRG1BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,7))) +#define TSB_PMD2_TRGCR_TRG2BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,11))) +#define TSB_PMD2_TRGCR_TRG3BE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,15))) +#define TSB_PMD2_TRGCR_CARSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGCR,16))) +#define TSB_PMD2_TRGMD_EMGTGE (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGMD,0))) +#define TSB_PMD2_TRGMD_TRGOUT (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->TRGMD,1))) +#define TSB_PMD2_SYNCCR_PWMSMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->SYNCCR,0))) +#define TSB_PMD2_DBGOUTCR_DBGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,0))) +#define TSB_PMD2_DBGOUTCR_IADAEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,3))) +#define TSB_PMD2_DBGOUTCR_IADBEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,4))) +#define TSB_PMD2_DBGOUTCR_IADCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,5))) +#define TSB_PMD2_DBGOUTCR_IADDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,6))) +#define TSB_PMD2_DBGOUTCR_IADEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,7))) +#define TSB_PMD2_DBGOUTCR_IPMDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,8))) +#define TSB_PMD2_DBGOUTCR_IEMGEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,9))) +#define TSB_PMD2_DBGOUTCR_IOVVEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,10))) +#define TSB_PMD2_DBGOUTCR_IVEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,11))) +#define TSB_PMD2_DBGOUTCR_IENCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,12))) +#define TSB_PMD2_DBGOUTCR_TRG0EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,16))) +#define TSB_PMD2_DBGOUTCR_TRG1EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,17))) +#define TSB_PMD2_DBGOUTCR_TRG2EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,18))) +#define TSB_PMD2_DBGOUTCR_TRG3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,19))) +#define TSB_PMD2_DBGOUTCR_TRG4EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,20))) +#define TSB_PMD2_DBGOUTCR_TRG5EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,21))) +#define TSB_PMD2_DBGOUTCR_INIFF (*((__IO uint32_t *)BITBAND_PERI(&TSB_PMD2->DBGOUTCR,31))) + + +/* Advanced Encoder Input (A-ENC32) */ +#define TSB_EN0_TNCR_ZEACT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,5))) +#define TSB_EN0_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,6))) +#define TSB_EN0_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,7))) +#define TSB_EN0_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,10))) +#define TSB_EN0_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,11))) +#define TSB_EN0_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,12))) +#define TSB_EN0_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,16))) +#define TSB_EN0_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,21))) +#define TSB_EN0_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,24))) +#define TSB_EN0_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,25))) +#define TSB_EN0_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->TNCR,28))) +#define TSB_EN0_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,0))) +#define TSB_EN0_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,1))) +#define TSB_EN0_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,2))) +#define TSB_EN0_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,12))) +#define TSB_EN0_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,13))) +#define TSB_EN0_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->STS,14))) +#define TSB_EN0_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,0))) +#define TSB_EN0_INPCR_SYNCSPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,1))) +#define TSB_EN0_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,2))) +#define TSB_EN0_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,6))) +#define TSB_EN0_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN0->INPCR,7))) +#define TSB_EN0_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,0))) +#define TSB_EN0_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,1))) +#define TSB_EN0_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,2))) +#define TSB_EN0_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,4))) +#define TSB_EN0_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,5))) +#define TSB_EN0_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INPMON,6))) +#define TSB_EN0_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,0))) +#define TSB_EN0_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,1))) +#define TSB_EN0_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,2))) +#define TSB_EN0_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,3))) +#define TSB_EN0_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,4))) +#define TSB_EN0_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN0->INTCR,5))) +#define TSB_EN0_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,0))) +#define TSB_EN0_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,1))) +#define TSB_EN0_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,2))) +#define TSB_EN0_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,3))) +#define TSB_EN0_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,4))) +#define TSB_EN0_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN0->INTF,5))) + +#define TSB_EN1_TNCR_ZEACT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,5))) +#define TSB_EN1_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,6))) +#define TSB_EN1_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,7))) +#define TSB_EN1_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,10))) +#define TSB_EN1_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,11))) +#define TSB_EN1_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,12))) +#define TSB_EN1_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,16))) +#define TSB_EN1_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,21))) +#define TSB_EN1_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,24))) +#define TSB_EN1_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,25))) +#define TSB_EN1_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->TNCR,28))) +#define TSB_EN1_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,0))) +#define TSB_EN1_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,1))) +#define TSB_EN1_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,2))) +#define TSB_EN1_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,12))) +#define TSB_EN1_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,13))) +#define TSB_EN1_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->STS,14))) +#define TSB_EN1_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,0))) +#define TSB_EN1_INPCR_SYNCSPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,1))) +#define TSB_EN1_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,2))) +#define TSB_EN1_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,6))) +#define TSB_EN1_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN1->INPCR,7))) +#define TSB_EN1_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,0))) +#define TSB_EN1_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,1))) +#define TSB_EN1_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,2))) +#define TSB_EN1_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,4))) +#define TSB_EN1_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,5))) +#define TSB_EN1_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INPMON,6))) +#define TSB_EN1_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,0))) +#define TSB_EN1_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,1))) +#define TSB_EN1_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,2))) +#define TSB_EN1_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,3))) +#define TSB_EN1_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,4))) +#define TSB_EN1_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN1->INTCR,5))) +#define TSB_EN1_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,0))) +#define TSB_EN1_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,1))) +#define TSB_EN1_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,2))) +#define TSB_EN1_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,3))) +#define TSB_EN1_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,4))) +#define TSB_EN1_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN1->INTF,5))) + +#define TSB_EN2_TNCR_ZEACT (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,5))) +#define TSB_EN2_TNCR_ENRUN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,6))) +#define TSB_EN2_TNCR_ZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,7))) +#define TSB_EN2_TNCR_ENCLR (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,10))) +#define TSB_EN2_TNCR_SFTCAP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,11))) +#define TSB_EN2_TNCR_TRGCAPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,12))) +#define TSB_EN2_TNCR_P3EN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,16))) +#define TSB_EN2_TNCR_SDTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,21))) +#define TSB_EN2_TNCR_MCMPMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,24))) +#define TSB_EN2_TNCR_TOVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,25))) +#define TSB_EN2_TNCR_CMPSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->TNCR,28))) +#define TSB_EN2_STS_INERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,0))) +#define TSB_EN2_STS_PDERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,1))) +#define TSB_EN2_STS_SKPDT (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,2))) +#define TSB_EN2_STS_ZDET (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,12))) +#define TSB_EN2_STS_UD (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,13))) +#define TSB_EN2_STS_REVERR (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->STS,14))) +#define TSB_EN2_INPCR_SYNCSPLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,0))) +#define TSB_EN2_INPCR_SYNCSPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,1))) +#define TSB_EN2_INPCR_SYNCNCZEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,2))) +#define TSB_EN2_INPCR_PDSTT (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,6))) +#define TSB_EN2_INPCR_PDSTP (*((__O uint32_t *)BITBAND_PERI(&TSB_EN2->INPCR,7))) +#define TSB_EN2_INPMON_SPLMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,0))) +#define TSB_EN2_INPMON_SPLMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,1))) +#define TSB_EN2_INPMON_SPLMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,2))) +#define TSB_EN2_INPMON_DETMONA (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,4))) +#define TSB_EN2_INPMON_DETMONB (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,5))) +#define TSB_EN2_INPMON_DETMONZ (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INPMON,6))) +#define TSB_EN2_INTCR_TPLSIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,0))) +#define TSB_EN2_INTCR_CAPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,1))) +#define TSB_EN2_INTCR_ERRIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,2))) +#define TSB_EN2_INTCR_CMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,3))) +#define TSB_EN2_INTCR_RLDIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,4))) +#define TSB_EN2_INTCR_MCMPIE (*((__IO uint32_t *)BITBAND_PERI(&TSB_EN2->INTCR,5))) +#define TSB_EN2_INTF_TPLSF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,0))) +#define TSB_EN2_INTF_CAPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,1))) +#define TSB_EN2_INTF_ERRF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,2))) +#define TSB_EN2_INTF_INTCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,3))) +#define TSB_EN2_INTF_RLDCPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,4))) +#define TSB_EN2_INTF_MCMPF (*((__I uint32_t *)BITBAND_PERI(&TSB_EN2->INTF,5))) + + +/* Advanced Vector Engine Plus (A-VE+) */ +#define TSB_VE0_EN_VEEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->EN,0))) +#define TSB_VE0_ERRINTEN_VERREN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->ERRINTEN,0))) +#define TSB_VE0_ERRINTEN_INTTEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->ERRINTEN,2))) +#define TSB_VE0_SCHTASKRUN_VRSCH (*((__I uint32_t *)BITBAND_PERI(&TSB_VE0->SCHTASKRUN,0))) +#define TSB_VE0_MCTLF_LAVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,0))) +#define TSB_VE0_MCTLF_LAVFM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,1))) +#define TSB_VE0_MCTLF_LVTF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,2))) +#define TSB_VE0_MCTLF_PLSLF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,4))) +#define TSB_VE0_MCTLF_PLSLFM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,5))) +#define TSB_VE0_MCTLF_PIDOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,8))) +#define TSB_VE0_MCTLF_PIQOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,9))) +#define TSB_VE0_MCTLF_VSOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,10))) +#define TSB_VE0_MCTLF_PWMOVF (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,11))) +#define TSB_VE0_MCTLF_SFT2ST (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,14))) +#define TSB_VE0_MCTLF_SFT2STM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MCTLF,15))) +#define TSB_VE0_MODE_PVIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,0))) +#define TSB_VE0_MODE_ZIEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,1))) +#define TSB_VE0_MODE_VDCSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,4))) +#define TSB_VE0_MODE_CLPEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,7))) +#define TSB_VE0_MODE_T5ECEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,10))) +#define TSB_VE0_MODE_NICEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,11))) +#define TSB_VE0_MODE_PWMBLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,12))) +#define TSB_VE0_MODE_PWMFLEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,13))) +#define TSB_VE0_MODE_PMDDTCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,14))) +#define TSB_VE0_MODE_IPDEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->MODE,15))) +#define TSB_VE0_FMODE_C2PEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,0))) +#define TSB_VE0_FMODE_SPWMEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,1))) +#define TSB_VE0_FMODE_IDQSEL (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,4))) +#define TSB_VE0_FMODE_IAPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,5))) +#define TSB_VE0_FMODE_IBPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,6))) +#define TSB_VE0_FMODE_ICPLMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,7))) +#define TSB_VE0_FMODE_CRCEN (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,8))) +#define TSB_VE0_FMODE_MREGDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,9))) +#define TSB_VE0_FMODE_PHCVDIS (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,12))) +#define TSB_VE0_FMODE_CCVMD (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->FMODE,13))) +#define TSB_VE0_OUTCR_UPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->OUTCR,6))) +#define TSB_VE0_OUTCR_VPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->OUTCR,7))) +#define TSB_VE0_OUTCR_WPWM (*((__IO uint32_t *)BITBAND_PERI(&TSB_VE0->OUTCR,8))) + +/** @} */ /* End of group Device_Peripheral_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TMPM4KNA_H__ */ + +/** @} */ /* End of group TMPM4KNA */ +/** @} */ /* End of group TOSHIBA_TXZ_MICROCONTROLLER */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/startup_TMPM4KNA.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/startup_TMPM4KNA.S new file mode 100644 index 00000000000..7e9e346e649 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/startup_TMPM4KNA.S @@ -0,0 +1,484 @@ +;/** +; ******************************************************************************* +; * @file startup_TMPM4KNA.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for the +; * TOSHIBA 'TMPM4KNA' Device Series +; * @version V1.0.0.0 +; * $Date:: #$ +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. +; * +; * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 +; ******************************************************************************* +; */ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD INT00_IRQHandler ; 0: Interrupt pin 00 + DCD INT01_IRQHandler ; 1: Interrupt pin 01a/00b + DCD INT02_IRQHandler ; 2: Interrupt pin 02a/00b + DCD INT03_IRQHandler ; 3: Interrupt pin 03a/03b + DCD INT04_IRQHandler ; 4: Interrupt pin 04a/04b + DCD INT05_IRQHandler ; 5: Interrupt pin 05a/05b + DCD INT06_IRQHandler ; 6: Interrupt pin 06a/06b + DCD INT07_IRQHandler ; 7: Interrupt pin 07a/07b + DCD INT08_IRQHandler ; 8: Interrupt pin 08a/08b + DCD INT09_IRQHandler ; 9: Interrupt pin 09 + DCD INT10_IRQHandler ; 10: Interrupt pin 10 + DCD INT11_IRQHandler ; 11: Interrupt pin 11a/11b + DCD INT12_IRQHandler ; 12: Interrupt pin 12 + DCD INT13_IRQHandler ; 13: Interrupt pin 13 + DCD INT14_IRQHandler ; 14: Interrupt pin 14a/14b + DCD INT15_IRQHandler ; 15: Interrupt pin 15 + DCD INT16_IRQHandler ; 16: Interrupt pin 16a/16b + DCD INT17_IRQHandler ; 17: Interrupt pin 17a/17b + DCD INT18_IRQHandler ; 18: Interrupt pin 18a/18b + DCD 0 ; 19: Reserved + DCD 0 ; 20: Reserved + DCD INT21_IRQHandler ; 21: Interrupt pin 21 + DCD INTVCN0_IRQHandler ; 22: A-VE+ ch0 Interrupt + DCD INTVCT0_IRQHandler ; 23: A-VE+ ch0 Task termination interrupt + DCD INTEMG0_IRQHandler ; 24: A-PMD ch0 EMG interrupt + DCD INTEMG1_IRQHandler ; 25: A-PMD ch1 EMG interrupt + DCD INTEMG2_IRQHandler ; 26: A-PMD ch2 EMG interrupt + DCD INTOVV0_IRQHandler ; 27: A-PMD ch0 OVV interrupt + DCD INTOVV1_IRQHandler ; 28: A-PMD ch1 OVV interrupt + DCD INTOVV2_IRQHandler ; 29: A-PMD ch2 OVV interrupt + DCD INTPWM0_IRQHandler ; 30: A-PMD ch0 PWM interrupt + DCD INTPWM1_IRQHandler ; 31: A-PMD ch1 PWM interrupt + DCD INTPWM2_IRQHandler ; 32: A-PMD ch2 PWM interrupt + DCD INTENC00_IRQHandler ; 33: A-ENC32 ch0 Encoder interrupt 0 + DCD INTENC01_IRQHandler ; 34: A-ENC32 ch0 Encoder interrupt 1 + DCD INTENC10_IRQHandler ; 35: A-ENC32 ch1 Encoder interrupt 0 + DCD INTENC11_IRQHandler ; 36: A-ENC32 ch1 Encoder interrupt 1 + DCD INTENC20_IRQHandler ; 37: A-ENC32 ch2 Encoder interrupt 0 + DCD INTENC21_IRQHandler ; 38: A-ENC32 ch2 Encoder interrupt 1 + DCD INTADAPDA_IRQHandler ; 39: ADC unit A PMD trigger program interrupt A + DCD INTADAPDB_IRQHandler ; 40: ADC unit A PMD trigger program interrupt B + DCD INTADACP0_IRQHandler ; 41: ADC unit A Monitor function 0 interrupt + DCD INTADACP1_IRQHandler ; 42: ADC unit A Monitor function 1 interrupt + DCD INTADATRG_IRQHandler ; 43: ADC unit A General purpose trigger program interrupt + DCD INTADASGL_IRQHandler ; 44: ADC unit A Single program interrupt + DCD INTADACNT_IRQHandler ; 45: ADC unit A Continuity program interrupt + DCD INTADBPDA_IRQHandler ; 46: ADC unit B PMD trigger program interrupt A + DCD INTADBPDB_IRQHandler ; 47: ADC unit B PMD trigger program interrupt B + DCD INTADBCP0_IRQHandler ; 48: ADC unit B Monitor function 0 interrupt + DCD INTADBCP1_IRQHandler ; 49: ADC unit B Monitor function 1 interrupt + DCD INTADBTRG_IRQHandler ; 50: ADC unit B General purpose trigger program interrupt + DCD INTADBSGL_IRQHandler ; 51: ADC unit B Single program interrupt + DCD INTADBCNT_IRQHandler ; 52: ADC unit B Continuity program interrupt + DCD INTADCPDA_IRQHandler ; 53: ADC unit C PMD trigger program interrupt A + DCD INTADCPDB_IRQHandler ; 54: ADC unit C PMD trigger program interrupt B + DCD INTADCCP0_IRQHandler ; 55: ADC unit C Monitor function 0 interrupt + DCD INTADCCP1_IRQHandler ; 56: ADC unit C Monitor function 1 interrupt + DCD INTADCTRG_IRQHandler ; 57: ADC unit C General purpose trigger program interrupt + DCD INTADCSGL_IRQHandler ; 58: ADC unit C Single program interrupt + DCD INTADCCNT_IRQHandler ; 59: ADC unit C Continuity program interrupt + DCD INTSC0RX_IRQHandler ; 60: TSPI/UART ch0 Reception interrupt + DCD INTSC0TX_IRQHandler ; 61: TSPI/UART ch0 Transmit interrupt + DCD INTSC0ERR_IRQHandler ; 62: TSPI/UART ch0 Error interrupt + DCD INTSC1RX_IRQHandler ; 63: TSPI/UART ch1 Reception interrupt + DCD INTSC1TX_IRQHandler ; 64: TSPI/UART ch1 Transmit interrupt + DCD INTSC1ERR_IRQHandler ; 65: TSPI/UART ch1 Error interrupt + DCD INTSC2RX_IRQHandler ; 66: UART ch2 Reception interrupt + DCD INTSC2TX_IRQHandler ; 67: UART ch2 Transmit interrupt + DCD INTSC2ERR_IRQHandler ; 68: UART ch2 Error interrupt + DCD INTSC3RX_IRQHandler ; 69: UART ch3 Reception interrupt + DCD INTSC3TX_IRQHandler ; 70: UART ch3 Transmit interrupt + DCD INTSC3ERR_IRQHandler ; 71: UART ch3 Error interrupt + DCD INTI2C0NST_IRQHandler ; 72: I2C ch0 Interrupt / EI2C ch0 Status interrupt + DCD INTI2C0ATX_IRQHandler ; 73: I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt + DCD INTI2C0BRX_IRQHandler ; 74: I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt + DCD INTI2C0NA_IRQHandler ; 75: I2C ch0 NACK detection interrupt + DCD INTI2C1NST_IRQHandler ; 76: I2C ch1 Interrupt / EI2C ch1 Status interrupt + DCD INTI2C1ATX_IRQHandler ; 77: I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt + DCD INTI2C1BRX_IRQHandler ; 78: I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt + DCD INTI2C1NA_IRQHandler ; 79: I2C ch1 NACK detection interrupt + DCD 0 ; 80: Reserved + DCD 0 ; 81: Reserved + DCD 0 ; 82: Reserved + DCD INTT32A00AC_IRQHandler ; 83: T32A ch0 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A00ACCAP0_IRQHandler; 84: T32A ch0 Timer A/C Input capture 0 + DCD INTT32A00ACCAP1_IRQHandler; 85: T32A ch0 Timer A/C Input capture 1 + DCD INTT32A00B_IRQHandler ; 86: T32A ch0 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A00BCAP0_IRQHandler ; 87: T32A ch0 Timer B Input capture 0 + DCD INTT32A00BCAP1_IRQHandler ; 88: T32A ch0 Timer B Input capture 1 + DCD INTT32A01AC_IRQHandler ; 89: T32A ch1 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A01ACCAP0_IRQHandler; 90: T32A ch1 Timer A/C Input capture 0 + DCD INTT32A01ACCAP1_IRQHandler; 91: T32A ch1 Timer A/C Input capture 1 + DCD INTT32A01B_IRQHandler ; 92: T32A ch1 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A01BCAP0_IRQHandler ; 93: T32A ch1 Timer B Input capture 0 + DCD INTT32A01BCAP1_IRQHandler ; 94: T32A ch1 Timer B Input capture 1 + DCD INTT32A02AC_IRQHandler ; 95: T32A ch2 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A02ACCAP0_IRQHandler; 96: T32A ch2 Timer A/C Input capture 0 + DCD INTT32A02ACCAP1_IRQHandler; 97: T32A ch2 Timer A/C Input capture 1 + DCD INTT32A02B_IRQHandler ; 98: T32A ch2 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A02BCAP0_IRQHandler ; 99: T32A ch2 Timer B Input capture 0 + DCD INTT32A02BCAP1_IRQHandler ; 100: T32A ch2 Timer B Input capture 1 + DCD INTT32A03AC_IRQHandler ; 101: T32A ch3 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A03ACCAP0_IRQHandler; 102: T32A ch3 Timer A/C Input capture 0 + DCD INTT32A03ACCAP1_IRQHandler; 103: T32A ch3 Timer A/C Input capture 1 + DCD INTT32A03B_IRQHandler ; 104: T32A ch3 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A03BCAP0_IRQHandler ; 105: T32A ch3 Timer B Input capture 0 + DCD INTT32A03BCAP1_IRQHandler ; 106: T32A ch3 Timer B Input capture 1 + DCD INTT32A04AC_IRQHandler ; 107: T32A ch4 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A04ACCAP0_IRQHandler; 108: T32A ch4 Timer A/C Input capture 0 + DCD INTT32A04ACCAP1_IRQHandler; 109: T32A ch4 Timer A/C Input capture 1 + DCD INTT32A04B_IRQHandler ; 110: T32A ch4 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A04BCAP0_IRQHandler ; 111: T32A ch4 Timer B Input capture 0 + DCD INTT32A04BCAP1_IRQHandler ; 112: T32A ch4 Timer B Input capture 1 + DCD INTT32A05AC_IRQHandler ; 113: T32A ch5 Timer A/C Compare match detection / Over flow / Under flow + DCD INTT32A05ACCAP0_IRQHandler; 114: T32A ch5 Timer A/C Input capture 0 + DCD INTT32A05ACCAP1_IRQHandler; 115: T32A ch5 Timer A/C Input capture 1 + DCD INTT32A05B_IRQHandler ; 116: T32A ch5 Timer B Compare match detection / Over flow / Under flow + DCD INTT32A05BCAP0_IRQHandler ; 117: T32A ch5 Timer B Input capture 0 + DCD INTT32A05BCAP1_IRQHandler ; 118: T32A ch5 Timer B Input capture 1 + DCD INTPARI0_IRQHandler ; 119: RAMP ch0 Parity error interrupt + DCD INTPARI1_IRQHandler ; 120: RAMP ch1 Parity error interrupt + DCD INTDMAATC_IRQHandler ; 121: DMAC unit A End of transfer (ch0 - 31) + DCD INTDMAAERR_IRQHandler ; 122: DMAC unit A Transfer error + DCD INTFLCRDY_IRQHandler ; 123: Code FLASH Ready interrupt + DCD INTFLDRDY_IRQHandler ; 124: Data FLASH Ready interrupt + + + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT INT00_IRQHandler [WEAK] + EXPORT INT01_IRQHandler [WEAK] + EXPORT INT02_IRQHandler [WEAK] + EXPORT INT03_IRQHandler [WEAK] + EXPORT INT04_IRQHandler [WEAK] + EXPORT INT05_IRQHandler [WEAK] + EXPORT INT06_IRQHandler [WEAK] + EXPORT INT07_IRQHandler [WEAK] + EXPORT INT08_IRQHandler [WEAK] + EXPORT INT09_IRQHandler [WEAK] + EXPORT INT10_IRQHandler [WEAK] + EXPORT INT11_IRQHandler [WEAK] + EXPORT INT12_IRQHandler [WEAK] + EXPORT INT13_IRQHandler [WEAK] + EXPORT INT14_IRQHandler [WEAK] + EXPORT INT15_IRQHandler [WEAK] + EXPORT INT16_IRQHandler [WEAK] + EXPORT INT17_IRQHandler [WEAK] + EXPORT INT18_IRQHandler [WEAK] + EXPORT INT21_IRQHandler [WEAK] + EXPORT INTVCN0_IRQHandler [WEAK] + EXPORT INTVCT0_IRQHandler [WEAK] + EXPORT INTEMG0_IRQHandler [WEAK] + EXPORT INTEMG1_IRQHandler [WEAK] + EXPORT INTEMG2_IRQHandler [WEAK] + EXPORT INTOVV0_IRQHandler [WEAK] + EXPORT INTOVV1_IRQHandler [WEAK] + EXPORT INTOVV2_IRQHandler [WEAK] + EXPORT INTPWM0_IRQHandler [WEAK] + EXPORT INTPWM1_IRQHandler [WEAK] + EXPORT INTPWM2_IRQHandler [WEAK] + EXPORT INTENC00_IRQHandler [WEAK] + EXPORT INTENC01_IRQHandler [WEAK] + EXPORT INTENC10_IRQHandler [WEAK] + EXPORT INTENC11_IRQHandler [WEAK] + EXPORT INTENC20_IRQHandler [WEAK] + EXPORT INTENC21_IRQHandler [WEAK] + EXPORT INTADAPDA_IRQHandler [WEAK] + EXPORT INTADAPDB_IRQHandler [WEAK] + EXPORT INTADACP0_IRQHandler [WEAK] + EXPORT INTADACP1_IRQHandler [WEAK] + EXPORT INTADATRG_IRQHandler [WEAK] + EXPORT INTADASGL_IRQHandler [WEAK] + EXPORT INTADACNT_IRQHandler [WEAK] + EXPORT INTADBPDA_IRQHandler [WEAK] + EXPORT INTADBPDB_IRQHandler [WEAK] + EXPORT INTADBCP0_IRQHandler [WEAK] + EXPORT INTADBCP1_IRQHandler [WEAK] + EXPORT INTADBTRG_IRQHandler [WEAK] + EXPORT INTADBSGL_IRQHandler [WEAK] + EXPORT INTADBCNT_IRQHandler [WEAK] + EXPORT INTADCPDA_IRQHandler [WEAK] + EXPORT INTADCPDB_IRQHandler [WEAK] + EXPORT INTADCCP0_IRQHandler [WEAK] + EXPORT INTADCCP1_IRQHandler [WEAK] + EXPORT INTADCTRG_IRQHandler [WEAK] + EXPORT INTADCSGL_IRQHandler [WEAK] + EXPORT INTADCCNT_IRQHandler [WEAK] + EXPORT INTSC0RX_IRQHandler [WEAK] + EXPORT INTSC0TX_IRQHandler [WEAK] + EXPORT INTSC0ERR_IRQHandler [WEAK] + EXPORT INTSC1RX_IRQHandler [WEAK] + EXPORT INTSC1TX_IRQHandler [WEAK] + EXPORT INTSC1ERR_IRQHandler [WEAK] + EXPORT INTSC2RX_IRQHandler [WEAK] + EXPORT INTSC2TX_IRQHandler [WEAK] + EXPORT INTSC2ERR_IRQHandler [WEAK] + EXPORT INTSC3RX_IRQHandler [WEAK] + EXPORT INTSC3TX_IRQHandler [WEAK] + EXPORT INTSC3ERR_IRQHandler [WEAK] + EXPORT INTI2C0NST_IRQHandler [WEAK] + EXPORT INTI2C0ATX_IRQHandler [WEAK] + EXPORT INTI2C0BRX_IRQHandler [WEAK] + EXPORT INTI2C0NA_IRQHandler [WEAK] + EXPORT INTI2C1NST_IRQHandler [WEAK] + EXPORT INTI2C1ATX_IRQHandler [WEAK] + EXPORT INTI2C1BRX_IRQHandler [WEAK] + EXPORT INTI2C1NA_IRQHandler [WEAK] + EXPORT INTT32A00AC_IRQHandler [WEAK] + EXPORT INTT32A00ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A00ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A00B_IRQHandler [WEAK] + EXPORT INTT32A00BCAP0_IRQHandler [WEAK] + EXPORT INTT32A00BCAP1_IRQHandler [WEAK] + EXPORT INTT32A01AC_IRQHandler [WEAK] + EXPORT INTT32A01ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A01ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A01B_IRQHandler [WEAK] + EXPORT INTT32A01BCAP0_IRQHandler [WEAK] + EXPORT INTT32A01BCAP1_IRQHandler [WEAK] + EXPORT INTT32A02AC_IRQHandler [WEAK] + EXPORT INTT32A02ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A02ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A02B_IRQHandler [WEAK] + EXPORT INTT32A02BCAP0_IRQHandler [WEAK] + EXPORT INTT32A02BCAP1_IRQHandler [WEAK] + EXPORT INTT32A03AC_IRQHandler [WEAK] + EXPORT INTT32A03ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A03ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A03B_IRQHandler [WEAK] + EXPORT INTT32A03BCAP0_IRQHandler [WEAK] + EXPORT INTT32A03BCAP1_IRQHandler [WEAK] + EXPORT INTT32A04AC_IRQHandler [WEAK] + EXPORT INTT32A04ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A04ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A04B_IRQHandler [WEAK] + EXPORT INTT32A04BCAP0_IRQHandler [WEAK] + EXPORT INTT32A04BCAP1_IRQHandler [WEAK] + EXPORT INTT32A05AC_IRQHandler [WEAK] + EXPORT INTT32A05ACCAP0_IRQHandler[WEAK] + EXPORT INTT32A05ACCAP1_IRQHandler[WEAK] + EXPORT INTT32A05B_IRQHandler [WEAK] + EXPORT INTT32A05BCAP0_IRQHandler [WEAK] + EXPORT INTT32A05BCAP1_IRQHandler [WEAK] + EXPORT INTPARI0_IRQHandler [WEAK] + EXPORT INTPARI1_IRQHandler [WEAK] + EXPORT INTDMAATC_IRQHandler [WEAK] + EXPORT INTDMAAERR_IRQHandler [WEAK] + EXPORT INTFLCRDY_IRQHandler [WEAK] + EXPORT INTFLDRDY_IRQHandler [WEAK] + +INT00_IRQHandler +INT01_IRQHandler +INT02_IRQHandler +INT03_IRQHandler +INT04_IRQHandler +INT05_IRQHandler +INT06_IRQHandler +INT07_IRQHandler +INT08_IRQHandler +INT09_IRQHandler +INT10_IRQHandler +INT11_IRQHandler +INT12_IRQHandler +INT13_IRQHandler +INT14_IRQHandler +INT15_IRQHandler +INT16_IRQHandler +INT17_IRQHandler +INT18_IRQHandler +INT21_IRQHandler +INTVCN0_IRQHandler +INTVCT0_IRQHandler +INTEMG0_IRQHandler +INTEMG1_IRQHandler +INTEMG2_IRQHandler +INTOVV0_IRQHandler +INTOVV1_IRQHandler +INTOVV2_IRQHandler +INTPWM0_IRQHandler +INTPWM1_IRQHandler +INTPWM2_IRQHandler +INTENC00_IRQHandler +INTENC01_IRQHandler +INTENC10_IRQHandler +INTENC11_IRQHandler +INTENC20_IRQHandler +INTENC21_IRQHandler +INTADAPDA_IRQHandler +INTADAPDB_IRQHandler +INTADACP0_IRQHandler +INTADACP1_IRQHandler +INTADATRG_IRQHandler +INTADASGL_IRQHandler +INTADACNT_IRQHandler +INTADBPDA_IRQHandler +INTADBPDB_IRQHandler +INTADBCP0_IRQHandler +INTADBCP1_IRQHandler +INTADBTRG_IRQHandler +INTADBSGL_IRQHandler +INTADBCNT_IRQHandler +INTADCPDA_IRQHandler +INTADCPDB_IRQHandler +INTADCCP0_IRQHandler +INTADCCP1_IRQHandler +INTADCTRG_IRQHandler +INTADCSGL_IRQHandler +INTADCCNT_IRQHandler +INTSC0RX_IRQHandler +INTSC0TX_IRQHandler +INTSC0ERR_IRQHandler +INTSC1RX_IRQHandler +INTSC1TX_IRQHandler +INTSC1ERR_IRQHandler +INTSC2RX_IRQHandler +INTSC2TX_IRQHandler +INTSC2ERR_IRQHandler +INTSC3RX_IRQHandler +INTSC3TX_IRQHandler +INTSC3ERR_IRQHandler +INTI2C0NST_IRQHandler +INTI2C0ATX_IRQHandler +INTI2C0BRX_IRQHandler +INTI2C0NA_IRQHandler +INTI2C1NST_IRQHandler +INTI2C1ATX_IRQHandler +INTI2C1BRX_IRQHandler +INTI2C1NA_IRQHandler +INTT32A00AC_IRQHandler +INTT32A00ACCAP0_IRQHandler +INTT32A00ACCAP1_IRQHandler +INTT32A00B_IRQHandler +INTT32A00BCAP0_IRQHandler +INTT32A00BCAP1_IRQHandler +INTT32A01AC_IRQHandler +INTT32A01ACCAP0_IRQHandler +INTT32A01ACCAP1_IRQHandler +INTT32A01B_IRQHandler +INTT32A01BCAP0_IRQHandler +INTT32A01BCAP1_IRQHandler +INTT32A02AC_IRQHandler +INTT32A02ACCAP0_IRQHandler +INTT32A02ACCAP1_IRQHandler +INTT32A02B_IRQHandler +INTT32A02BCAP0_IRQHandler +INTT32A02BCAP1_IRQHandler +INTT32A03AC_IRQHandler +INTT32A03ACCAP0_IRQHandler +INTT32A03ACCAP1_IRQHandler +INTT32A03B_IRQHandler +INTT32A03BCAP0_IRQHandler +INTT32A03BCAP1_IRQHandler +INTT32A04AC_IRQHandler +INTT32A04ACCAP0_IRQHandler +INTT32A04ACCAP1_IRQHandler +INTT32A04B_IRQHandler +INTT32A04BCAP0_IRQHandler +INTT32A04BCAP1_IRQHandler +INTT32A05AC_IRQHandler +INTT32A05ACCAP0_IRQHandler +INTT32A05ACCAP1_IRQHandler +INTT32A05B_IRQHandler +INTT32A05BCAP0_IRQHandler +INTT32A05BCAP1_IRQHandler +INTPARI0_IRQHandler +INTPARI1_IRQHandler +INTDMAATC_IRQHandler +INTDMAAERR_IRQHandler +INTFLCRDY_IRQHandler +INTFLDRDY_IRQHandler + + B . + + ENDP + + + ALIGN + END + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct new file mode 100644 index 00000000000..84d7b3a34d4 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_ARM_STD/tmpm4knfyafg.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +/* + * Copyright(C) 2020, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +;; TMPM4KNA scatter file + +;; Vector table starts at 0 +;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model) +;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model) +;; Initial PC == &__main (with LSB set to indicate Thumb) +;; These two values are provided by the library +;; Other vectors must be provided by the user +;; Code starts after the last possible vector +;; Data starts at 0x20000000 +;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries) +;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above) + +;; Compatible with ISSM model + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x00040000 +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +# if defined(MBED_BOOT_STACK_SIZE) +# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +# else +# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +# endif +#endif + +#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE + +; TMPM4KNA: 256 KB FLASH (0x40000) + 24 KB SRAM (0x6000) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region +{ + ER_IROM1 MBED_APP_START MBED_APP_SIZE + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x20000238 (0x6000 - 0x238 - Stack_Size) + { + .ANY (+RW, +ZI) + rda_flash512ud32_b.o(+RO) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000+0x6000 - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (0x20000000+0x6000) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S new file mode 100644 index 00000000000..e8f894d2e04 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/startup_TMPM4KNA.S @@ -0,0 +1,496 @@ +/** + ******************************************************************************* + * @file startup_TMPM4KNA.s + * @brief CMSIS Cortex-M4F Core Device Startup File for the + * TOSHIBA 'TMPM4KNA' Device Series + * @version + * @date + *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 All rights reserved + ******************************************************************************* + */ + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 + +/* +// Stack Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +/* +// Heap Configuration +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +// +*/ + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.if Heap_Size +.space Heap_Size +.endif +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + // External Interrupts + .long INT00_IRQHandler // 0: Interrupt pin 00 + .long INT01_IRQHandler // 1: Interrupt pin 01a/00b + .long INT02_IRQHandler // 2: Interrupt pin 02a/00b + .long INT03_IRQHandler // 3: Interrupt pin 03a/03b + .long INT04_IRQHandler // 4: Interrupt pin 04a/04b + .long INT05_IRQHandler // 5: Interrupt pin 05a/05b + .long INT06_IRQHandler // 6: Interrupt pin 06a/06b + .long INT07_IRQHandler // 7: Interrupt pin 07a/07b + .long INT08_IRQHandler // 8: Interrupt pin 08a/08b + .long INT09_IRQHandler // 9: Interrupt pin 09 + .long INT10_IRQHandler // 10: Interrupt pin 10 + .long INT11_IRQHandler // 11: Interrupt pin 11a/11b + .long INT12_IRQHandler // 12: Interrupt pin 12 + .long INT13_IRQHandler // 13: Interrupt pin 13 + .long INT14_IRQHandler // 14: Interrupt pin 14a/14b + .long INT15_IRQHandler // 15: Interrupt pin 15 + .long INT16_IRQHandler // 16: Interrupt pin 16a/16b + .long INT17_IRQHandler // 17: Interrupt pin 17a/17b + .long INT18_IRQHandler // 18: Interrupt pin 18a/18b + .long 0 // 19: Reserved + .long 0 // 20: Reserved + .long INT21_IRQHandler // 21: Interrupt pin 21 + .long INTVCN0_IRQHandler // 22: A-VE+ ch0 Interrupt + .long INTVCT0_IRQHandler // 23: A-VE+ ch0 Task termination interrupt + .long INTEMG0_IRQHandler // 24: A-PMD ch0 EMG interrupt + .long INTEMG1_IRQHandler // 25: A-PMD ch1 EMG interrupt + .long INTEMG2_IRQHandler // 26: A-PMD ch2 EMG interrupt + .long INTOVV0_IRQHandler // 27: A-PMD ch0 OVV interrupt + .long INTOVV1_IRQHandler // 28: A-PMD ch1 OVV interrupt + .long INTOVV2_IRQHandler // 29: A-PMD ch2 OVV interrupt + .long INTPWM0_IRQHandler // 30: A-PMD ch0 PWM interrupt + .long INTPWM1_IRQHandler // 31: A-PMD ch1 PWM interrupt + .long INTPWM2_IRQHandler // 32: A-PMD ch2 PWM interrupt + .long INTENC00_IRQHandler // 33: A-ENC32 ch0 Encoder interrupt 0 + .long INTENC01_IRQHandler // 34: A-ENC32 ch0 Encoder interrupt 1 + .long INTENC10_IRQHandler // 35: A-ENC32 ch1 Encoder interrupt 0 + .long INTENC11_IRQHandler // 36: A-ENC32 ch1 Encoder interrupt 1 + .long INTENC20_IRQHandler // 37: A-ENC32 ch2 Encoder interrupt 0 + .long INTENC21_IRQHandler // 38: A-ENC32 ch2 Encoder interrupt 1 + .long INTADAPDA_IRQHandler // 39: ADC unit A PMD trigger program interrupt A + .long INTADAPDB_IRQHandler // 40: ADC unit A PMD trigger program interrupt B + .long INTADACP0_IRQHandler // 41: ADC unit A Monitor function 0 interrupt + .long INTADACP1_IRQHandler // 42: ADC unit A Monitor function 1 interrupt + .long INTADATRG_IRQHandler // 43: ADC unit A General purpose trigger program interrupt + .long INTADASGL_IRQHandler // 44: ADC unit A Single program interrupt + .long INTADACNT_IRQHandler // 45: ADC unit A Continuity program interrupt + .long INTADBPDA_IRQHandler // 46: ADC unit B PMD trigger program interrupt A + .long INTADBPDB_IRQHandler // 47: ADC unit B PMD trigger program interrupt B + .long INTADBCP0_IRQHandler // 48: ADC unit B Monitor function 0 interrupt + .long INTADBCP1_IRQHandler // 49: ADC unit B Monitor function 1 interrupt + .long INTADBTRG_IRQHandler // 50: ADC unit B General purpose trigger program interrupt + .long INTADBSGL_IRQHandler // 51: ADC unit B Single program interrupt + .long INTADBCNT_IRQHandler // 52: ADC unit B Continuity program interrupt + .long INTADCPDA_IRQHandler // 53: ADC unit C PMD trigger program interrupt A + .long INTADCPDB_IRQHandler // 54: ADC unit C PMD trigger program interrupt B + .long INTADCCP0_IRQHandler // 55: ADC unit C Monitor function 0 interrupt + .long INTADCCP1_IRQHandler // 56: ADC unit C Monitor function 1 interrupt + .long INTADCTRG_IRQHandler // 57: ADC unit C General purpose trigger program interrupt + .long INTADCSGL_IRQHandler // 58: ADC unit C Single program interrupt + .long INTADCCNT_IRQHandler // 59: ADC unit C Continuity program interrupt + .long INTSC0RX_IRQHandler // 60: TSPI/UART ch0 Reception interrupt + .long INTSC0TX_IRQHandler // 61: TSPI/UART ch0 Transmit interrupt + .long INTSC0ERR_IRQHandler // 62: TSPI/UART ch0 Error interrupt + .long INTSC1RX_IRQHandler // 63: TSPI/UART ch1 Reception interrupt + .long INTSC1TX_IRQHandler // 64: TSPI/UART ch1 Transmit interrupt + .long INTSC1ERR_IRQHandler // 65: TSPI/UART ch1 Error interrupt + .long INTSC2RX_IRQHandler // 66: UART ch2 Reception interrupt + .long INTSC2TX_IRQHandler // 67: UART ch2 Transmit interrupt + .long INTSC2ERR_IRQHandler // 68: UART ch2 Error interrupt + .long INTSC3RX_IRQHandler // 69: UART ch3 Reception interrupt + .long INTSC3TX_IRQHandler // 70: UART ch3 Transmit interrupt + .long INTSC3ERR_IRQHandler // 71: UART ch3 Error interrupt + .long INTI2C0NST_IRQHandler // 72: I2C ch0 Interrupt / EI2C ch0 Status interrupt + .long INTI2C0ATX_IRQHandler // 73: I2C ch0 Arbitration lost detection interrupt / EI2C ch0 Transmission buffer empty interrupt + .long INTI2C0BRX_IRQHandler // 74: I2C ch0 Bus free detection interrupt / EI2C ch0 Reception buffer full interrupt + .long INTI2C0NA_IRQHandler // 75: I2C ch0 NACK detection interrupt + .long INTI2C1NST_IRQHandler // 76: I2C ch1 Interrupt / EI2C ch1 Status interrupt + .long INTI2C1ATX_IRQHandler // 77: I2C ch1 Arbitration lost detection interrupt / EI2C ch1 Transmission buffer empty interrupt + .long INTI2C1BRX_IRQHandler // 78: I2C ch1 Bus free detection interrupt / EI2C ch1 Reception buffer full interrupt + .long INTI2C1NA_IRQHandler // 79: I2C ch1 NACK detection interrupt + .long 0 // 80: Reserved + .long 0 // 81: Reserved + .long 0 // 82: Reserved + .long INTT32A00AC_IRQHandler // 83: T32A ch0 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A00ACCAP0_IRQHandler// 84: T32A ch0 Timer A/C Input capture 0 + .long INTT32A00ACCAP1_IRQHandler// 85: T32A ch0 Timer A/C Input capture 1 + .long INTT32A00B_IRQHandler // 86: T32A ch0 Timer B Compare match detection / Over flow / Under flow + .long INTT32A00BCAP0_IRQHandler // 87: T32A ch0 Timer B Input capture 0 + .long INTT32A00BCAP1_IRQHandler // 88: T32A ch0 Timer B Input capture 1 + .long INTT32A01AC_IRQHandler // 89: T32A ch1 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A01ACCAP0_IRQHandler// 90: T32A ch1 Timer A/C Input capture 0 + .long INTT32A01ACCAP1_IRQHandler// 91: T32A ch1 Timer A/C Input capture 1 + .long INTT32A01B_IRQHandler // 92: T32A ch1 Timer B Compare match detection / Over flow / Under flow + .long INTT32A01BCAP0_IRQHandler // 93: T32A ch1 Timer B Input capture 0 + .long INTT32A01BCAP1_IRQHandler // 94: T32A ch1 Timer B Input capture 1 + .long INTT32A02AC_IRQHandler // 95: T32A ch2 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A02ACCAP0_IRQHandler// 96: T32A ch2 Timer A/C Input capture 0 + .long INTT32A02ACCAP1_IRQHandler// 97: T32A ch2 Timer A/C Input capture 1 + .long INTT32A02B_IRQHandler // 98: T32A ch2 Timer B Compare match detection / Over flow / Under flow + .long INTT32A02BCAP0_IRQHandler // 99: T32A ch2 Timer B Input capture 0 + .long INTT32A02BCAP1_IRQHandler // 100: T32A ch2 Timer B Input capture 1 + .long INTT32A03AC_IRQHandler // 101: T32A ch3 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A03ACCAP0_IRQHandler// 102: T32A ch3 Timer A/C Input capture 0 + .long INTT32A03ACCAP1_IRQHandler// 103: T32A ch3 Timer A/C Input capture 1 + .long INTT32A03B_IRQHandler // 104: T32A ch3 Timer B Compare match detection / Over flow / Under flow + .long INTT32A03BCAP0_IRQHandler // 105: T32A ch3 Timer B Input capture 0 + .long INTT32A03BCAP1_IRQHandler // 106: T32A ch3 Timer B Input capture 1 + .long INTT32A04AC_IRQHandler // 107: T32A ch4 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A04ACCAP0_IRQHandler// 108: T32A ch4 Timer A/C Input capture 0 + .long INTT32A04ACCAP1_IRQHandler// 109: T32A ch4 Timer A/C Input capture 1 + .long INTT32A04B_IRQHandler // 110: T32A ch4 Timer B Compare match detection / Over flow / Under flow + .long INTT32A04BCAP0_IRQHandler // 111: T32A ch4 Timer B Input capture 0 + .long INTT32A04BCAP1_IRQHandler // 112: T32A ch4 Timer B Input capture 1 + .long INTT32A05AC_IRQHandler // 113: T32A ch5 Timer A/C Compare match detection / Over flow / Under flow + .long INTT32A05ACCAP0_IRQHandler// 114: T32A ch5 Timer A/C Input capture 0 + .long INTT32A05ACCAP1_IRQHandler// 115: T32A ch5 Timer A/C Input capture 1 + .long INTT32A05B_IRQHandler // 116: T32A ch5 Timer B Compare match detection / Over flow / Under flow + .long INTT32A05BCAP0_IRQHandler // 117: T32A ch5 Timer B Input capture 0 + .long INTT32A05BCAP1_IRQHandler // 118: T32A ch5 Timer B Input capture 1 + .long INTPARI0_IRQHandler // 119: RAMP ch0 Parity error interrupt + .long INTPARI1_IRQHandler // 120: RAMP ch1 Parity error interrupt + .long INTDMAATC_IRQHandler // 121: DMAC unit A End of transfer (ch0 - 31) + .long INTDMAAERR_IRQHandler // 122: DMAC unit A Transfer error + .long INTFLCRDY_IRQHandler // 123: Code FLASH Ready interrupt + .long INTFLDRDY_IRQHandler // 124: Data FLASH Ready interrupt + + .size __Vectors, . - __Vectors + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler INT00_IRQHandler + def_irq_handler INT01_IRQHandler + def_irq_handler INT02_IRQHandler + def_irq_handler INT03_IRQHandler + def_irq_handler INT04_IRQHandler + def_irq_handler INT05_IRQHandler + def_irq_handler INT06_IRQHandler + def_irq_handler INT07_IRQHandler + def_irq_handler INT08_IRQHandler + def_irq_handler INT09_IRQHandler + def_irq_handler INT10_IRQHandler + def_irq_handler INT11_IRQHandler + def_irq_handler INT12_IRQHandler + def_irq_handler INT13_IRQHandler + def_irq_handler INT14_IRQHandler + def_irq_handler INT15_IRQHandler + def_irq_handler INT16_IRQHandler + def_irq_handler INT17_IRQHandler + def_irq_handler INT18_IRQHandler + def_irq_handler INT21_IRQHandler + def_irq_handler INTVCN0_IRQHandler + def_irq_handler INTVCT0_IRQHandler + def_irq_handler INTEMG0_IRQHandler + def_irq_handler INTEMG1_IRQHandler + def_irq_handler INTEMG2_IRQHandler + def_irq_handler INTOVV0_IRQHandler + def_irq_handler INTOVV1_IRQHandler + def_irq_handler INTOVV2_IRQHandler + def_irq_handler INTPWM0_IRQHandler + def_irq_handler INTPWM1_IRQHandler + def_irq_handler INTPWM2_IRQHandler + def_irq_handler INTENC00_IRQHandler + def_irq_handler INTENC01_IRQHandler + def_irq_handler INTENC10_IRQHandler + def_irq_handler INTENC11_IRQHandler + def_irq_handler INTENC20_IRQHandler + def_irq_handler INTENC21_IRQHandler + def_irq_handler INTADAPDA_IRQHandler + def_irq_handler INTADAPDB_IRQHandler + def_irq_handler INTADACP0_IRQHandler + def_irq_handler INTADACP1_IRQHandler + def_irq_handler INTADATRG_IRQHandler + def_irq_handler INTADASGL_IRQHandler + def_irq_handler INTADACNT_IRQHandler + def_irq_handler INTADBPDA_IRQHandler + def_irq_handler INTADBPDB_IRQHandler + def_irq_handler INTADBCP0_IRQHandler + def_irq_handler INTADBCP1_IRQHandler + def_irq_handler INTADBTRG_IRQHandler + def_irq_handler INTADBSGL_IRQHandler + def_irq_handler INTADBCNT_IRQHandler + def_irq_handler INTADCPDA_IRQHandler + def_irq_handler INTADCPDB_IRQHandler + def_irq_handler INTADCCP0_IRQHandler + def_irq_handler INTADCCP1_IRQHandler + def_irq_handler INTADCTRG_IRQHandler + def_irq_handler INTADCSGL_IRQHandler + def_irq_handler INTADCCNT_IRQHandler + def_irq_handler INTSC0RX_IRQHandler + def_irq_handler INTSC0TX_IRQHandler + def_irq_handler INTSC0ERR_IRQHandler + def_irq_handler INTSC1RX_IRQHandler + def_irq_handler INTSC1TX_IRQHandler + def_irq_handler INTSC1ERR_IRQHandler + def_irq_handler INTSC2RX_IRQHandler + def_irq_handler INTSC2TX_IRQHandler + def_irq_handler INTSC2ERR_IRQHandler + def_irq_handler INTSC3RX_IRQHandler + def_irq_handler INTSC3TX_IRQHandler + def_irq_handler INTSC3ERR_IRQHandler + def_irq_handler INTI2C0NST_IRQHandler + def_irq_handler INTI2C0ATX_IRQHandler + def_irq_handler INTI2C0BRX_IRQHandler + def_irq_handler INTI2C0NA_IRQHandler + def_irq_handler INTI2C1NST_IRQHandler + def_irq_handler INTI2C1ATX_IRQHandler + def_irq_handler INTI2C1BRX_IRQHandler + def_irq_handler INTI2C1NA_IRQHandler + def_irq_handler INTT32A00AC_IRQHandler + def_irq_handler INTT32A00ACCAP0_IRQHandler + def_irq_handler INTT32A00ACCAP1_IRQHandler + def_irq_handler INTT32A00B_IRQHandler + def_irq_handler INTT32A00BCAP0_IRQHandler + def_irq_handler INTT32A00BCAP1_IRQHandler + def_irq_handler INTT32A01AC_IRQHandler + def_irq_handler INTT32A01ACCAP0_IRQHandler + def_irq_handler INTT32A01ACCAP1_IRQHandler + def_irq_handler INTT32A01B_IRQHandler + def_irq_handler INTT32A01BCAP0_IRQHandler + def_irq_handler INTT32A01BCAP1_IRQHandler + def_irq_handler INTT32A02AC_IRQHandler + def_irq_handler INTT32A02ACCAP0_IRQHandler + def_irq_handler INTT32A02ACCAP1_IRQHandler + def_irq_handler INTT32A02B_IRQHandler + def_irq_handler INTT32A02BCAP0_IRQHandler + def_irq_handler INTT32A02BCAP1_IRQHandler + def_irq_handler INTT32A03AC_IRQHandler + def_irq_handler INTT32A03ACCAP0_IRQHandler + def_irq_handler INTT32A03ACCAP1_IRQHandler + def_irq_handler INTT32A03B_IRQHandler + def_irq_handler INTT32A03BCAP0_IRQHandler + def_irq_handler INTT32A03BCAP1_IRQHandler + def_irq_handler INTT32A04AC_IRQHandler + def_irq_handler INTT32A04ACCAP0_IRQHandler + def_irq_handler INTT32A04ACCAP1_IRQHandler + def_irq_handler INTT32A04B_IRQHandler + def_irq_handler INTT32A04BCAP0_IRQHandler + def_irq_handler INTT32A04BCAP1_IRQHandler + def_irq_handler INTT32A05AC_IRQHandler + def_irq_handler INTT32A05ACCAP0_IRQHandler + def_irq_handler INTT32A05ACCAP1_IRQHandler + def_irq_handler INTT32A05B_IRQHandler + def_irq_handler INTT32A05BCAP0_IRQHandler + def_irq_handler INTT32A05BCAP1_IRQHandler + def_irq_handler INTPARI0_IRQHandler + def_irq_handler INTPARI1_IRQHandler + def_irq_handler INTDMAATC_IRQHandler + def_irq_handler INTDMAAERR_IRQHandler + def_irq_handler INTFLCRDY_IRQHandler + def_irq_handler INTFLDRDY_IRQHandler + + .end diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld new file mode 100644 index 00000000000..b7d924e6e0b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/TOOLCHAIN_GCC_ARM/tmpm4knfyafg.ld @@ -0,0 +1,195 @@ +/* + * Copyright(C) 2021, Toshiba Electronic Device Solutions Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* Linker script for Toshiba TMPM4KNA */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 256K +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + /* 8_byte_aligned((125 + 16) vect * 4 bytes) = 8_byte_aligned(0x238) = 0x238 */ + RAM (rwx) : ORIGIN = 0x20000238, LENGTH = (24K - 0x238) +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapBase + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + *(.ram_func*) + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h new file mode 100644 index 00000000000..f31080ae6b7 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis.h @@ -0,0 +1,24 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "TMPM4KNA.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h new file mode 100644 index 00000000000..0c48bbd1051 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + + +#if defined(__ICCARM__) +#pragma section=".intvec" +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec")) +#elif defined(__CC_ARM) +extern uint32_t Load$$LR$$LR_IROM1$$Base[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base) +#elif defined(__GNUC__) +extern uint32_t vectors[]; +#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)vectors) +#else +#error "Flash vector address not set for this toolchain" +#endif + + +#define NVIC_NUM_VECTORS (141) +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c new file mode 100644 index 00000000000..dc1993538bf --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.c @@ -0,0 +1,389 @@ +/** + ******************************************************************************* + * @file system_TMPM4KyA.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the + * TOSHIBA 'TMPM4ky' Device Series + * @version V1.0.0.0 + * $Date:: 2020-09-17 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ******************************************************************************* + */ + +#include "TMPM4KNA.h" + + +/*-------- <<< Start of configuration section >>> ----------------------------*/ + +/* Semi-Independent Watchdog Timer (SIWDT) Configuration */ +#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */ +#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */ +#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */ + +/* Clock Generator (CG) Configuration */ +#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */ + +#define CG_SYSCR_MCKSEL_SET (SYSCR_MCKSEL_Val << 6U) +#define CG_SYSCR_MCKSELGST_Val (SYSCR_MCKSEL_Val << 22U) +#define CG_SYSCR_MCKSELPST_Val (SYSCR_MCKSEL_Val << 30U) + +#define CG_6M_MUL_26_656_FPLL (0x001C1535UL<<8U) /* fPLL = 6MHz * 26.656 */ +#define CG_8M_MUL_20_FPLL (0x00245028UL<<8U) /* fPLL = 8MHz * 20 */ +#define CG_10M_MUL_16_FPLL (0x002E9020UL<<8U) /* fPLL = 10MHz * 16 */ +#define CG_12M_MUL_13_312_FPLL (0x0036DA1AUL<<8U) /* fPLL = 12MHz * 13.312 */ + +#define CG_PLL0SEL_PLL0ON_SET (0x00000001UL) +#define CG_PLL0SEL_PLL0ON_CLEAR (0xFFFFFFFEUL) +#define CG_PLL0SEL_PLL0SEL_SET (0x00000002UL) +#define CG_PLL0SEL_PLL0SEL_CLEAR (0xFFFFFFFDUL) + +#define CG_OSCCR_IHOSC1EN_CLEAR (0xFFFFFFFEUL) +#define CG_OSCCR_EOSCEN_SET (0x00000002UL) +#define CG_OSCCR_OSCSEL_SET (0x00000100UL) + +#define SYSCR_GEAR_Val (0x00000000UL) /* GEAR = fc */ +#define SYSCR_PRCK_Val (0x00000000UL) /* phiT0 = fc */ +#define SYSCR_MCKSEL_Val (0x00000001UL) /* fsysm(phiT0m) = fsysh(phiT0h) / 2 */ + +#define STBYCR_Val (0x00000000UL) + +#define CG_WUPHCR_WUON_START_SET (0x00000001UL) +#define EXT_CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for External HOSC select the IHOSC1 */ + +#if (CLOCK_SETUP) +#define CG_WUPHCR_WUCLK_SET (0x00000100UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_16_FPLL +#else +#define CG_WUPHCR_WUCLK_SET (0x00000000UL) /* WUCLK for Inital/Lockup time */ +#define PLL0SEL_Ready CG_10M_MUL_16_FPLL +#endif + +#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL) +#define PLL0SEL_MASK (0xFFFFFF00UL) + +/*-------- <<< End of configuration section >>> ------------------------------*/ + +/*-------- DEFINES -----------------------------------------------------------*/ +/* Define clocks */ +#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ +#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ +#define IOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ + +#define EOSC_6M (6000000UL) +#define EOSC_8M (8000000UL) +#define EOSC_10M (10000000UL) +#define EOSC_12M (12000000UL) +#define IOSC_10M (10000000UL) +#define EXTALH EOSC_10M /* External high-speed oscillator freq */ +#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */ +#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */ +#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */ +#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */ +#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */ +#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */ +#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */ +#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */ +#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */ +#define EOSC_6M_DIV2_PLLON (160000000UL) /* 6.00MHz * 53.3125 / 2 */ +#define EOSC_8M_DIV2_PLLON (160000000UL) /* 8.00MHz * 40.0000 / 2 */ +#define EOSC_10M_DIV2_PLLON (160000000UL) /* 10.00MHz * 32.0000 / 2 */ +#define EOSC_12M_DIV2_PLLON (160000000UL) /* 12.00MHz * 26.6250 / 2 */ + +/* Configure Warm-up time */ +#define HZ_1M (1000000UL) +#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */ +#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */ +#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */ + +#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR = (warm-up time(us) * IXTALH - 16) / 16 */ +#if (CLOCK_SETUP) +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#else +#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U)) +#endif +/* Determine core clock frequency according to settings */ +/* System clock is high-speed clock*/ +#if (CLOCK_SETUP) +#define CORE_TALH (EXTALH) +#else +#define CORE_TALH (IXTALH) +#endif + +#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */ +#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_26_656_FPLL)) +#define __CORE_CLK EOSC_6M_DIV2_PLLON /* output clock is 159.938MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 6MHz */ +#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_20_FPLL)) +#define __CORE_CLK EOSC_8M_DIV2_PLLON /* output clock is 160MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 8MHz */ +#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) +#define __CORE_CLK EOSC_10M_DIV2_PLLON /* output clock is 160MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 10MHz */ +#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) +#define __CORE_CLK EOSC_12M_DIV2_PLLON /* output clock is 159.75MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */ +#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) +#define __CORE_CLK IOSC_10M_DIV2_PLLON /* output clock is 160MHz */ +#else /* fc -> reserved */ +#define __CORE_CLK (0U) +#endif /* End input is 12MHz */ +#else /* input clock not known */ +#define __CORE_CLK (0U) +#error "Core Oscillator Frequency invalid!" +#endif /* End switch input clock */ +#else /* If PLL not used */ +#define __CORE_CLK (CORE_TALH) +#endif + +#if ((SYSCR_GEAR_Val & 7U) == 0U) /* Gear -> fc */ +#define __CORE_SYS (__CORE_CLK) +#elif ((SYSCR_GEAR_Val & 7U) == 1U) /* Gear -> fc/2 */ +#define __CORE_SYS (__CORE_CLK / 2U) +#elif ((SYSCR_GEAR_Val & 7U) == 2U) /* Gear -> fc/4 */ +#define __CORE_SYS (__CORE_CLK / 4U ) +#elif ((SYSCR_GEAR_Val & 7U) == 3U) /* Gear -> fc/8 */ +#define __CORE_SYS (__CORE_CLK / 8U) +#elif ((SYSCR_GEAR_Val & 7U) == 4U) /* Gear -> fc/16 */ +#define __CORE_SYS (__CORE_CLK / 16U) +#else /* Gear -> reserved */ +#define __CORE_SYS (0U) +#endif + + +/* Clock Variable definitions */ +uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */ + +/*------------------------------------------------------------------------------*/ +/* Macro Function */ +/*------------------------------------------------------------------------------*/ +/** + * @defgroup Flash_Private_define Flash Private Define + * @{ + */ +#define FC_KCR_KEYCODE (0xA74A9D23UL) /*!< The specific code that writes the FCKCR register. */ +#define FC_BRANK_VALUE (uint32_t)(0xFFFFFFFFUL) /*!< Brank value */ +#define FC_MAX_PAGES (uint8_t)(0x80) /*!< Maxmum pages */ +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ +#define FC_MAX_AREAS (uint8_t)(0x1) /*!< Maxmum areas */ +#define FC_MAX_DATA_PAGES (uint8_t)(0x21) /*!< Maxmum pages */ +#define FC_MAX_DATA_BLOCKS (uint8_t)(0x8) /*!< Maxmum blocks */ +#define FC_CMD_ADDRESS_MASK (uint32_t)(0xFFFF0000UL) /*!< Upper address mask of the upper address */ +#define FC_CMD_BC1_ADDR (0x00000550UL) /*!< The lower address of the first bus cycle when uses commans */ +#define FC_CMD_BC2_ADDR (0x00000AA0UL) /*!< The lower address of the second bus cycle when uses commans */ +#define FC_BANK_USER_INFO (0x00000007UL) /*!< Bank Change User Information Area */ +#define FC_BANK_CODE_FLASH (0x00000000UL) /*!< Bank Change Code Flash */ +#define FC_BUFFER_DISABLE (0x00000007UL) /*!< Flash Buffer Disable nad Clear */ +#define FC_BUFFER_ENABLE (0x00000000UL) /*!< Flash Buffer Enable */ + +#define FC_ACCR_FDLC_4 (0x00000300UL) /*!< Data Flash read clock 4clock */ +#define FC_ACCR_FDLC_5 (0x00000400UL) /*!< Data Flash read clock 5clock */ +#define FC_ACCR_FDLC_6 (0x00000500UL) /*!< Data Flash read clock 6clock */ +#define FC_ACCR_FCLC_1 (0x00000000UL) /*!< Code Flash read clock 1clock */ +#define FC_ACCR_FCLC_2 (0x00000001UL) /*!< Code Flash read clock 2clock */ +#define FC_ACCR_FCLC_3 (0x00000002UL) /*!< Code Flash read clock 3clock */ +#define FC_ACCR_FCLC_4 (0x00000003UL) /*!< Code Flash read clock 4clock */ +#define FC_ACCR_FCLC_5 (0x00000004UL) /*!< Code Flash read clock 5clock */ +#define FC_ACCR_FCLC_6 (0x00000005UL) /*!< Code Flash read clock 6clock */ +#define SYSCORECLOCK_80M (80000000UL) /*!< 80MHz */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Update SystemCoreClock according register values. + */ +void SystemCoreClockUpdate(void) +{ + /* Get Core Clock Frequency */ + + uint32_t CoreClock = 0U; + uint32_t CoreClockInput = 0U; + uint32_t regval = 0U; + uint32_t oscsel = 0U; + uint32_t pll0sel = 0U; + uint32_t pll0on = 0U; + /* Determine clock frequency according to clock register values */ + /* System clock is high-speed clock */ + regval = TSB_CG->OSCCR; + oscsel = regval & CG_OSCCR_OSCSEL_SET; + if (oscsel) { /* If system clock is External high-speed oscillator freq */ + CoreClock = EXTALH; + } else { /* If system clock is Internal high-speed oscillator freq */ + CoreClock = IXTALH; + } + regval = TSB_CG->PLL0SEL; + pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET; + pll0on = regval & CG_PLL0SEL_PLL0ON_SET; + if (pll0sel && pll0on) { /* If PLL enabled */ + if (CoreClock == EOSC_6M) { /* If input is 6MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_26_656_FPLL) { + CoreClockInput = EOSC_6M_DIV2_PLLON; /* output clock is 159.938MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_8M) { /* If input is 8MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_20_FPLL) { + CoreClockInput = EOSC_8M_DIV2_PLLON; /* output clock is 160MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_10M) { /* If input is 10MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_16_FPLL) { + CoreClockInput = EOSC_10M_DIV2_PLLON; /* output clock is 160MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else if (CoreClock == EOSC_12M) { /* If input is 12MHz */ + if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_13_312_FPLL) { + CoreClockInput = EOSC_12M_DIV2_PLLON; /* output clock is 159.75MHz */ + } else { + CoreClockInput = 0U; /* fc -> reserved */ + } + } else { + CoreClockInput = 0U; + } + } else { /* If PLL not used */ + CoreClockInput = CoreClock; + } + + switch (TSB_CG->SYSCR & 7U) { + case 0U: /* Gear -> fc */ + SystemCoreClock = CoreClockInput; + break; + case 1U: /* Gear -> fc/2 */ + SystemCoreClock = CoreClockInput / 2U; + break; + case 2U: /* Gear -> fc/4 */ + SystemCoreClock = CoreClockInput / 4U; + break; + case 3U: /* Gear -> fc/8 */ + if (CoreClockInput >= EOSC_8M) { + SystemCoreClock = CoreClockInput / 8U; + } else { + SystemCoreClock = 0U; + } + break; + case 4U: /* Gear -> fc/16 */ + if (CoreClockInput >= EOSC_12M) { + SystemCoreClock = CoreClockInput / 16U; + } else { + SystemCoreClock = 0U; + } + break; + case 5U: + case 6U: + case 7U: + SystemCoreClock = 0U; + break; + default: + SystemCoreClock = 0U; + break; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit(void) +{ +#if (SIWD_SETUP) /* Watchdog Setup */ + /* SIWD Disable */ + TSB_SIWD0->EN = SIWDEN_Val; + TSB_SIWD0->CR = SIWDCR_Val; +#else + /* SIWD Enable (Setting after a Reset) */ +#endif + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* FPU setting */ + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + +#if (CLOCK_SETUP) /* Clock(external) Setup */ + TSB_CG->SYSCR = (SYSCR_GEAR_Val | (SYSCR_PRCK_Val << 8)); /* set */ + + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET); + TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET; + TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET; + while (!TSB_CG_OSCCR_OSCF) { + ; + } /* Confirm CGOSCCR="1" */ + TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ; +#else + /* Internal HOSC Enable (Setting after a Reset) */ +#endif + + /* PLL Setup */ + TSB_CG->SYSCR = (SYSCR_GEAR_Val | CG_SYSCR_MCKSEL_SET); /* set */ + while ((TSB_CG->SYSCR & (CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val)) + != ((CG_SYSCR_MCKSELGST_Val | CG_SYSCR_MCKSELPST_Val))) { + ; + } + + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */ + TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR; + TSB_CG->PLL0SEL = PLL0SEL_Ready; + TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Warm-up */ + + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET); + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */ + TSB_CG->STBYCR = STBYCR_Val; + TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET); + while (TSB_CG_WUPHCR_WUEF) { + ; + } /* Lockup */ + TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET; + while (!TSB_CG_PLL0SEL_PLL0ST) { + ; + } /*Confirm CGPLL0SEL = "1" */ + +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.h new file mode 100644 index 00000000000..56987ea3298 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/device/system_TMPM4KyA.h @@ -0,0 +1,65 @@ +/** + ***************************************************************************** + * @file system_TMPM4KyA.h + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the + * TOSHIBA 'TMPM4KyA' Device Series + * @version V1.0.0.0 + * $Date:: 2020-09-09 14:33:28 #$ + * + * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT. + * + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ***************************************************************************** + */ + +#include + +#ifndef __SYSTEM_TMPM4KYA_H +#define __SYSTEM_TMPM4KYA_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/flash_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/flash_api.c new file mode 100644 index 00000000000..a2edf53b058 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/flash_api.c @@ -0,0 +1,172 @@ +/* mbed Microcontroller Library + * Copyright(C) TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "flash_api.h" +#include "mbed_critical.h" +#include "flash.h" + +#define PROGRAM_WRITE_MAX (16U) // Page program could be written 16 bytes/4 words once +#define SECTOR_SIZE (0x8000) // 32KB each sectors or block +#define FLASH_CHIP_SIZE (0x00040000) // Flash chip size is 2048 KByte +#define MASK_CHIP_ID_FROM_ADD (0x00FFFFFFUL) +#define FC_MAX_BLOCKS (uint8_t)(0x16) /*!< Maxmum blocks */ + +#define SUCCESS (0U) +#define FAIL (-1) +// IHOSC1EN +#define CGOSCCR_IHOSC1EN_MASK ((uint32_t)0x00000001) // IHOSC1EN :Mask +#define CGOSCCR_IHOSC1EN_RW_DISABLE ((uint32_t)0x00000000) // IHOSC1EN :[R/W] :Disable +#define CGOSCCR_IHOSC1EN_RW_ENABLE ((uint32_t)0x00000001) // IHOSC1EN :[R/W] :Enable + +static void internal_hosc_enable(void); +static int16_t flash_get_block_no(const flash_t *obj, uint32_t address); + +static uint32_t flash_block_address[FC_MAX_BLOCKS] = { + (0x5E000000UL), /*!< CODE FLASH Block0 */ + (0x5E008000UL), /*!< CODE FLASH Block1 */ + (0x5E010000UL), /*!< CODE FLASH Block2 */ + (0x5E018000UL), /*!< CODE FLASH Block3 */ + (0x5E020000UL), /*!< CODE FLASH Block4 */ + (0x5E028000UL), /*!< CODE FLASH Block5 */ + (0x5E030000UL), /*!< CODE FLASH Block6 */ + (0x5E038000UL), /*!< CODE FLASH Block7 */ + (0x5E040000UL), /*!< CODE FLASH Block8 */ + (0x5E048000UL), /*!< CODE FLASH Block9 */ + (0x5E050000UL), /*!< CODE FLASH Block10 */ + (0x5E058000UL), /*!< CODE FLASH Block11 */ + (0x5E060000UL), /*!< CODE FLASH Block12 */ + (0x5E068000UL), /*!< CODE FLASH Block13 */ + (0x5E070000UL), /*!< CODE FLASH Block14 */ + (0x5E078000UL) /*!< CODE FLASH Block15 */ +}; + + +int32_t flash_init(flash_t *obj) +{ + obj->flash_inited = 0; + obj->flash_inited = 1; + internal_hosc_enable(); // Internal HOSC enable + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + obj->flash_inited = 0; + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + int status = FAIL; + int16_t block_no; + + if (obj->flash_inited == 0) { + flash_init(obj); + } + + // We need to prevent flash accesses during erase operation + core_util_critical_section_enter(); + + block_no = flash_get_block_no(obj, address); + if (block_no == FAIL) { + return status; + } else { + //Continue + } + + if (TXZ_SUCCESS == fc_erase_block_code_flash(block_no, 1)) { + status = SUCCESS; + } else { + // Do nothing + } + + core_util_critical_section_exit(); + + return status; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + int status = SUCCESS; + + address &= MASK_CHIP_ID_FROM_ADD; + + // We need to prevent flash accesses during program operation + core_util_critical_section_enter(); + + if (TXZ_SUCCESS == fc_write_code_flash((uint32_t *)data, (uint32_t *)address, size)) { + // Do nothing + } else { + status = FAIL; + } + + core_util_critical_section_exit(); + + return status; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) { + return SECTOR_SIZE; + } else { + // Do nothing + } + + return MBED_FLASH_INVALID_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return PROGRAM_WRITE_MAX; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return FC_CODE_FLASH_ADDRESS_TOP; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FLASH_CHIP_SIZE; +} + +static void internal_hosc_enable(void) +{ + uint32_t work; + work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK); + TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE); +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + +static int16_t flash_get_block_no(const flash_t *obj, uint32_t address) +{ + (void)obj; + for (int i = 0 ; i < FC_MAX_BLOCKS; i++) { + if (flash_block_address[i] == address) { + return i; + } + } + return FAIL; + +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_api.c new file mode 100644 index 00000000000..6ffe26e5bdb --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_api.c @@ -0,0 +1,126 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "txzp_gpio.h" + +#define GPIO_DATA PIN_DATA(0, 2) +#define ALT_FUNC_GPIO 0 + +_gpio_t gpio_port_add = { + .p_pa_instance = TSB_PA, + .p_pb_instance = TSB_PB, + .p_pc_instance = TSB_PC, + .p_pd_instance = TSB_PD, + .p_pe_instance = TSB_PE, + .p_pf_instance = TSB_PF, + .p_pg_instance = TSB_PG, + .p_ph_instance = TSB_PH, + .p_pj_instance = TSB_PJ, + .p_pk_instance = TSB_PK, + .p_pl_instance = TSB_PL, + .p_pm_instance = TSB_PM, + .p_pn_instance = TSB_PN, + .p_pu_instance = TSB_PU, + .p_pv_instance = TSB_PV +}; + +uint32_t gpio_set(PinName pin) +{ + // Check that pin is valid + MBED_ASSERT(pin != (PinName)NC); + + // Set pin function as GPIO pin + pin_function(pin, GPIO_DATA); + + // Return pin mask + return (1 << (pin & 0x07)); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + // Store above pin mask, pin name into GPIO object + obj->pin = pin; + if (pin == (PinName)NC) { + return; + } + obj->pin_num = PIN_POS(pin); + obj->mask = gpio_set(pin); + obj->port = (PortName) PIN_PORT(pin); + // Enable clock for particular port + if (obj->port <= 12) { + TSB_CG->FSYSMENA |= (1 << (obj->port)); + } else { + TSB_CG->FSYSMENA |= (1 << (obj->port + 3)); + } +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + // Set pin mode + pin_mode(obj->pin, mode); +} + +// Set gpio object pin direction +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + // Set direction + switch (direction) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, + (gpio_gr_t)obj->port, + (gpio_num_t)obj->pin_num, + (uint32_t)ALT_FUNC_GPIO, + GPIO_PIN_INOUT); + break; + default: + break; + } +} + +void gpio_write(gpio_t *obj, int value) +{ + // Write gpio object pin data + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, value); +} + +int gpio_read(gpio_t *obj) +{ + // Read gpio object pin data + gpio_pinstate_t val = GPIO_PIN_SET; // To initialize local variable + gpio_read_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, &val); + return val; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_irq_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_irq_api.c new file mode 100644 index 00000000000..702a7e59591 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_irq_api.c @@ -0,0 +1,335 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_irq_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "mbed_critical.h" +#include "txzp_gpio.h" + +#define CHANNEL_NUM (22) +#define DISABLE (0) +#define ENABLE (1) +#define CLR_INT_FLAG (0xC0) + +const PinMap PinMap_GPIO_IRQ[] = { + {PA2, GPIO_IRQ_0, PIN_DATA(0, 0)}, + {PA4, GPIO_IRQ_1, PIN_DATA(0, 0)}, + {PC3, GPIO_IRQ_3, PIN_DATA(0, 0)}, + {PE3, GPIO_IRQ_4, PIN_DATA(0, 0)}, + {PE5, GPIO_IRQ_5, PIN_DATA(0, 0)}, + {PU1, GPIO_IRQ_7, PIN_DATA(0, 0)}, + {PU3, GPIO_IRQ_8, PIN_DATA(0, 0)}, + {PU6, GPIO_IRQ_9, PIN_DATA(0, 0)}, + {PC2, GPIO_IRQ_A, PIN_DATA(0, 0)}, + {PE4, GPIO_IRQ_B, PIN_DATA(0, 0)}, + {PU0, GPIO_IRQ_C, PIN_DATA(0, 0)}, + {PU5, GPIO_IRQ_D, PIN_DATA(0, 0)}, + {PA1, GPIO_IRQ_F, PIN_DATA(0, 0)}, + {PN1, GPIO_IRQ_10, PIN_DATA(0, 0)}, + {PD1, GPIO_IRQ_11, PIN_DATA(0, 0)}, + {PD5, GPIO_IRQ_12, PIN_DATA(0, 0)}, + {PG3, GPIO_IRQ_15, PIN_DATA(0, 0)}, + {NC, NC, 0} +}; + + +extern _gpio_t gpio_port_add; +static uintptr_t channel_contexts[CHANNEL_NUM] = {0}; +static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL}; +static CG_INTActiveState CurrentState; + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc, CG_INTActiveState, uint8_t); +static void INT_IRQHandler(PinName, uint32_t); + +void INT00_IRQHandler(void) +{ + INT_IRQHandler(PA2, 0); +} + +void INT01_IRQHandler(void) +{ + INT_IRQHandler(PA4, 1); +} + +void INT03_IRQHandler(void) +{ + INT_IRQHandler(PC3, 3); +} + +void INT04_IRQHandler(void) +{ + INT_IRQHandler(PE3, 4); +} + +void INT05_IRQHandler(void) +{ + INT_IRQHandler(PE5, 5); +} + +void INT07_IRQHandler(void) +{ + INT_IRQHandler(PU1, 7); +} + +void INT08_IRQHandler(void) +{ + INT_IRQHandler(PU3, 8); +} + +void INT09_IRQHandler(void) +{ + INT_IRQHandler(PU6, 9); +} + +void INT10_IRQHandler(void) +{ + INT_IRQHandler(PC2, 10); +} + +void INT11_IRQHandler(void) +{ + INT_IRQHandler(PE4, 11); +} + +void INT12_IRQHandler(void) +{ + INT_IRQHandler(PU0, 12); +} + +void INT13_IRQHandler(void) +{ + INT_IRQHandler(PU5, 13); +} + +void INT15_IRQHandler(void) +{ + INT_IRQHandler(PA1, 15); +} + +void INT16_IRQHandler(void) +{ + INT_IRQHandler(PN1, 16); +} + +void INT17_IRQHandler(void) +{ + INT_IRQHandler(PD1, 17); +} + +void INT18_IRQHandler(void) +{ + INT_IRQHandler(PD5, 18); +} + +void INT21_IRQHandler(void) +{ + INT_IRQHandler(PG3, 21); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uintptr_t context) +{ + // Get gpio interrupt ID + obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ); + core_util_critical_section_enter(); + // Get GPIO port and pin num + obj->port = (PortName)PIN_PORT(pin); + obj->pin_num = PIN_POS(pin); + // Set pin level as LOW + gpio_write_bit(&gpio_port_add, obj->port, obj->pin_num, GPIO_Mode_DATA, 0); + // Enable gpio interrupt function + pinmap_pinout(pin, PinMap_GPIO_IRQ); + // Get GPIO irq source + obj->irq_src = (CG_INTSrc)obj->irq_id; + // Save irq handler + hal_irq_handler[obj->irq_src] = handler; + // Save irq id + channel_contexts[obj->irq_src] = context; + // Initialize interrupt event as both edges detection + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + core_util_critical_section_exit(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + // Clear gpio_irq + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Reset interrupt handler + hal_irq_handler[obj->irq_src] = NULL; + // Reset interrupt id + channel_contexts[obj->irq_src] = 0; + + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + // Disable GPIO interrupt on obj + gpio_irq_disable(obj); + + if (enable) { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else { + error("Not supported event\n"); + } + } else { + // Get gpio interrupt event + if (event == IRQ_RISE) { + if ((obj->event == CG_INT_ACTIVE_STATE_RISING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_FALLING; + } + } else if (event == IRQ_FALL) { + if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) || + (obj->event == CG_INT_ACTIVE_STATE_INVALID)) { + obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES; + } else { + obj->event = CG_INT_ACTIVE_STATE_RISING; + } + } else { + error("Not supported event\n"); + } + } + + CurrentState = obj->event; + if (obj->event != CG_INT_ACTIVE_STATE_INVALID) { + // Set interrupt event and enable INTx clear + CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE); + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 0); + } else { + gpio_write_bit(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)obj->pin_num, GPIO_Mode_DATA, 1); + } + + // Clear interrupt request + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + // Enable GPIO interrupt on obj + gpio_irq_enable(obj); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + // Clear and Enable gpio_irq object + NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id); + NVIC_EnableIRQ((IRQn_Type)obj->irq_id); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + // Disable gpio_irq object + NVIC_DisableIRQ((IRQn_Type)obj->irq_id); +} + +static void INT_IRQHandler(PinName pin, uint32_t index) +{ + PortName port; + uint8_t pin_num; + gpio_pinstate_t data = GPIO_PIN_RESET; + pin_num = PIN_POS(pin); + port = (PortName)PIN_PORT(pin); + + // Clear interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, DISABLE); + // Get pin value + gpio_read_bit(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)pin_num, GPIO_Mode_DATA, &data); + + switch (data) { + // Falling edge detection + case 0: + hal_irq_handler[index](channel_contexts[index], IRQ_FALL); + break; + // Rising edge detection + case 1: + hal_irq_handler[index](channel_contexts[index], IRQ_RISE); + break; + default: + break; + } + + // Clear gpio pending interrupt + NVIC_ClearPendingIRQ((IRQn_Type)(CG_INT_SRC_0 + index)); + // Enable interrupt request + CG_SetSTBYReleaseINTSrc((CG_INTSrc)(CG_INT_SRC_0 + index), CurrentState, ENABLE); +} + +static void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource, CG_INTActiveState ActiveState, uint8_t NewState) +{ + uint8_t *ptr = NULL; + if (INTSource == 0) { + ptr = (uint8_t *)(&(TSB_IB->IMC033)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 8) { + ptr = ((uint8_t *)(&(TSB_IB->IMC034)) + ((INTSource - 1) * 2)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 10) { + ptr = ((uint8_t *)(&(TSB_IB->IMC050)) + ((INTSource - 9))); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 11) { + ptr = (uint8_t *)(&(TSB_IB->IMC052)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 13) { + ptr = ((uint8_t *)(&(TSB_IB->IMC054)) + ((INTSource - 12))); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 14) { + ptr = (uint8_t *)(&(TSB_IB->IMC056)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 15) { + ptr = (uint8_t *)(&(TSB_IB->IMC058)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource <= 18) { + ptr = ((uint8_t *)(&(TSB_IB->IMC059)) + ((INTSource - 16) * 2)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } else if (INTSource == 21) { + ptr = (uint8_t *)(&(TSB_IB->IMC069)); + *ptr = CLR_INT_FLAG; + *ptr = (ActiveState | NewState); + } + { + uint8_t regval = *ptr; + (void)regval; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_object.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_object.h new file mode 100644 index 00000000000..1d3816cd7a2 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/gpio_object.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "txzp_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t pin_num; + uint32_t mask; + PinName pin; + PortName port; +} gpio_t; + +typedef enum { + CG_INT_SRC_0 = 0U, + CG_INT_SRC_1, + CG_INT_SRC_2, + CG_INT_SRC_3, + CG_INT_SRC_4, + CG_INT_SRC_5, + CG_INT_SRC_6, + CG_INT_SRC_7, + CG_INT_SRC_8, + CG_INT_SRC_9, + CG_INT_SRC_A, + CG_INT_SRC_B, + CG_INT_SRC_C, + CG_INT_SRC_D, + CG_INT_SRC_E, + CG_INT_SRC_F, + CG_INT_SRC_10, + CG_INT_SRC_11, + CG_INT_SRC_12, + CG_INT_SRC_13, + CG_INT_SRC_14, + CG_INT_SRC_15 +} CG_INTSrc; + +typedef enum { + CG_INT_ACTIVE_STATE_L = 0x00U, + CG_INT_ACTIVE_STATE_H = 0x02U, + CG_INT_ACTIVE_STATE_FALLING = 0x04U, + CG_INT_ACTIVE_STATE_RISING = 0x06U, + CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x08U, + CG_INT_ACTIVE_STATE_INVALID = 0x0AU +} CG_INTActiveState; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName)NC); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/i2c_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/i2c_api.c new file mode 100644 index 00000000000..b1e503538b9 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/i2c_api.c @@ -0,0 +1,193 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include "i2c_api.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "txzp_i2c_api.h" + +#define MAX_I2C_FREQ 400000 + +static const PinMap PinMap_I2C_SDA[] = { + {PD3, I2C_1, PIN_DATA(2, 2)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {PD4, I2C_1, PIN_DATA(2, 2)}, + {NC, NC, 0} +}; + +// Initialize the I2C peripheral. It sets the default parameters for I2C +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + MBED_ASSERT(obj != NULL); + + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl); + + MBED_ASSERT((int)i2c_name != NC); + + switch (i2c_name) { + case I2C_1: + TSB_CG_FSYSMENA_IPMENA26 = TXZ_ENABLE; // Enable clock for I2C_1 + TSB_CG_FSYSMENA_IPMENA03 = TXZ_ENABLE; // Enable clock for GPIO D + obj->my_i2c.i2c.p_instance = TSB_I2C1; + obj->my_i2c.info.irqn = INTI2C1NST_IRQn; + break; + default: + error("I2C is not available"); + break; + } + + + pinmap_pinout(sda, PinMap_I2C_SDA); + pin_mode(sda, OpenDrain); + pin_mode(sda, PullUp); + + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(scl, OpenDrain); + pin_mode(scl, PullUp); + + i2c_reset(obj); + i2c_frequency(obj, 100000); + I2C_init(&obj->my_i2c.i2c); +} + +// Configure the I2C frequency +void i2c_frequency(i2c_t *obj, int hz) +{ + if (hz <= MAX_I2C_FREQ) { + i2c_frequency_t(&obj->my_i2c, hz); + } else { + error("Failed : Max I2C frequency is 400000"); + } +} + +int i2c_start(i2c_t *obj) +{ + i2c_start_t(&obj->my_i2c); + return TXZ_SUCCESS; +} + +int i2c_stop(i2c_t *obj) +{ + i2c_stop_t(&obj->my_i2c); + return TXZ_SUCCESS; +} + +void i2c_reset(i2c_t *obj) +{ + // Software reset + i2c_reset_t(&obj->my_i2c); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + int32_t count = 0; + + count = i2c_read_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + int32_t count = 0; + + count = i2c_write_t(&obj->my_i2c, address, (uint8_t *)data, length, stop); + + return count; +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + int32_t data = 0; + + data = i2c_byte_read_t(&obj->my_i2c, last); + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + int32_t result = 0; + + result = i2c_byte_write_t(&obj->my_i2c, data); + + return result; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + i2c_slave_mode_t(&obj->my_i2c, enable_slave); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + i2c_slave_address_t(&obj->my_i2c, address); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int32_t result = 0; + + result = i2c_slave_receive_t(&obj->my_i2c); + + return result; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + int32_t count = 0; + + count = i2c_slave_read_t(&obj->my_i2c, (uint8_t *)data, length); + + return count; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + int32_t count = 0; + + count = i2c_slave_write_t(&obj->my_i2c, (uint8_t *)data, length); + + return count; +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/objects.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/objects.h new file mode 100644 index 00000000000..e8e13768940 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/objects.h @@ -0,0 +1,110 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "PortNames.h" +#include "PeripheralNames.h" +#include "gpio_object.h" +#include "txzp_gpio.h" +#include "txzp_uart.h" +#include "txzp_tspi.h" +#include "txzp_t32a.h" +#include "txzp_cg.h" +#include "txzp_driver_def.h" +#include "txzp_adc.h" +#include "txzp_i2c_api.h" +#include "txzp_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct port_s { + uint32_t mask; + PortName port; +}; + + +struct serial_s { + uint32_t index; + uint32_t mode; + TSB_UART_TypeDef *UARTx; + uart_boudrate_t boud_obj; +}; + +struct pwmout_s { + uint32_t divisor; + uint32_t type; + uint32_t trailing_timing; + uint32_t leading_timing; + float period; + t32a_t p_t32a; + PinName pin; +}; + +struct spi_s { + uint8_t bits; + tspi_t p_obj; + SPIName module; + PinName clk_pin; + PinName ssel_pin; + IRQn_Type rxirqn; + IRQn_Type txirqn; + IRQn_Type errirqn; +#ifdef DEVICE_SPI_ASYNCH + uint32_t event_mask; + uint8_t state; +#endif +}; + +struct gpio_irq_s { + PortName port; + uint8_t pin_num; + uint32_t irq_id; + CG_INTSrc irq_src; + CG_INTActiveState event; +}; + +struct analogin_s { + adc_t p_adc; + PinName pin; + ADCName adc; + adc_channel_setting_t param; +}; + +struct i2c_s { + int address; + uint32_t index; + _i2c_t my_i2c; +}; + +struct flash_s { + int flash_inited; +}; + +#include "gpio_object.h" + +#define HAL_CRC_IS_SUPPORTED(polynomial, width) (((width) == 16 && (polynomial) == 0x1021) || \ + ((width) == 32 && (polynomial) == 0x04C11DB7)) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pinmap.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pinmap.c new file mode 100644 index 00000000000..a48eeb9d856 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pinmap.c @@ -0,0 +1,106 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "txzp_gpio.h" + +#define PIN_FUNC_MAX 7 + +extern _gpio_t gpio_port_add; + + +void pin_function(PinName pin, int function) +{ + uint32_t port = 0; + uint8_t bit = 0; + uint8_t func = 0; + uint8_t dir = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Calculate pin function and pin direction + func = PIN_FUNC(function); + dir = PIN_DIR(function); + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Find function is in range or not + if (func <= PIN_FUNC_MAX) { + // Set pin function and direction if direction is in range + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)port, (gpio_num_t)bit, (uint32_t)func, GPIO_PIN_INOUT); + break; + default: + break; + } + } else { + // Do nothing + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + uint32_t port = 0; + uint8_t bit = 0; + + // Assert that pin is valid + MBED_ASSERT(pin != NC); + + // Check if function is in range + if (mode > OpenDrain) { + return; + } + + // Calculate port and pin position + port = PIN_PORT(pin); + bit = PIN_POS(pin); + + // Set pin mode + switch (mode) { + case PullNone: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PUP, GPIO_PIN_RESET); + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PDN, GPIO_PIN_RESET); + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_OD, GPIO_PIN_RESET); + + break; + case PullUp: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PUP, GPIO_PIN_SET); + break; + case PullDown: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_PDN, GPIO_PIN_SET); + break; + case OpenDrain: + gpio_write_bit(&gpio_port_add, port, (uint32_t) bit, GPIO_Mode_OD, GPIO_PIN_SET); + break; + default: + break; + } +} + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/port_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/port_api.c new file mode 100644 index 00000000000..dca3b31a1f1 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/port_api.c @@ -0,0 +1,145 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "txzp_gpio.h" +#include "pinmap.h" + +#define PORT_PIN_NUM (8) +#define ALT_FUNC_GPIO (0) + +extern _gpio_t gpio_port_add; +typedef struct port_s port_t; +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num); + +PinName port_pin(PortName port, int pin_n) +{ + PinName pin = NC; + pin = (PinName)((port << 3) | pin_n); + return pin; +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(port <= PortV); + + // Store port and port mask for future use + obj->port = port; + obj->mask = mask; + + // Enable the clock for particular port + _gpio_init(&gpio_port_add, obj->port); + + // Set port function and port direction + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_function(port_pin(obj->port, i), dir); + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Set mode for masked pins + for (i = 0; i < PORT_PIN_NUM; i++) { + // If the pin is used + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint8_t i = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + for (i = 0; i < PORT_PIN_NUM; i++) { + // Set direction for masked pins + if (obj->mask & (1 << i)) { + gpio_pin_dir(obj, dir, i); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data to write to masked pins + data = (port_data & ~obj->mask) | (value & obj->mask); + + // Write data to masked pins of the port + gpio_write_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, data); +} + +int port_read(port_t *obj) +{ + uint32_t port_data = 0; + uint32_t data = 0; + + // Assert that port is valid + MBED_ASSERT(obj->port <= PortV); + + // Get current data of port + gpio_read_mode(&gpio_port_add, obj->port, GPIO_Mode_DATA, &port_data); + + // Calculate data of masked pins + data = port_data & obj->mask; + + return data; +} + +static void gpio_pin_dir(port_t *obj, PinDirection dir, uint32_t pin_num) +{ + switch (dir) { + case PIN_INPUT: + // Set pin input + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INPUT); + break; + case PIN_OUTPUT: + // Set pin output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_OUTPUT); + break; + case PIN_INOUT: + // Set pin both input and output + gpio_func(&gpio_port_add, (gpio_gr_t)obj->port, (gpio_num_t)pin_num, (uint32_t)ALT_FUNC_GPIO, GPIO_PIN_INOUT); + break; + default: + // error("Invalid direction\n"); + break; + } +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pwmout_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pwmout_api.c new file mode 100644 index 00000000000..a83bd9be192 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/pwmout_api.c @@ -0,0 +1,191 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pwmout_api.h" +#include "PeripheralNames.h" +#include "pinmap.h" + +#define DUTY_CYCLE_INIT_VALUE 1 +#define CALCULATE_RGC1_VAL 2.4 + +static const PinMap PinMap_PWM[] = { + {PF4, PWM_0, PIN_DATA(5, 1)}, + {PU2, PWM_1, PIN_DATA(5, 1)}, + {PC2, PWM_2, PIN_DATA(6, 1)}, + {PN1, PWM_3, PIN_DATA(5, 1)}, + {NC, NC, 0} +}; + +void pwmout_init(pwmout_t *obj, PinName pin) +{ + // Determine the pwm channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + + // Assert input is valid + MBED_ASSERT(pwm != (PWMName)NC); + + switch (pwm) { + case PWM_0: + obj->p_t32a.p_instance = TSB_T32A1; + // Clock enable of T32A ch01 + TSB_CG_FSYSMENA_IPMENA29 = TXZ_ENABLE; + break; + case PWM_1: + obj->p_t32a.p_instance = TSB_T32A2; + // Clock enable of T32A ch02 + TSB_CG_FSYSMENA_IPMENA30 = TXZ_ENABLE; + break; + case PWM_2: + obj->p_t32a.p_instance = TSB_T32A3; + // Clock enable of T32A ch03 + TSB_CG_FSYSMENA_IPMENA31 = TXZ_ENABLE; + break; + case PWM_3: + obj->p_t32a.p_instance = TSB_T32A5; + // Clock enable of T32A ch05 + TSB_CG_FSYSMENB_IPMENB01 = TXZ_ENABLE; + break; + default: + obj->p_t32a.p_instance = NULL; + break; + } + + if (obj->p_t32a.p_instance == NULL) { + return; + } + + // Enable clock for GPIO port. + if (pwm == PWM_1) { + TSB_CG->FSYSMENA |= (TXZ_ENABLE << (PIN_PORT(pin) + 3)); + } else { + TSB_CG->FSYSMENA |= (TXZ_ENABLE << (PIN_PORT(pin))); + } + + // Set pin function as PWM + pinmap_pinout(pin, PinMap_PWM); + + // Default to 20ms, 0% duty cycle + // Assign same init value to trailing and leading timing duty cycle is zero. + pwmout_period_ms(obj, 20); +} + +void pwmout_free(pwmout_t *obj) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + obj->trailing_timing = TXZ_DISABLE; + obj->leading_timing = TXZ_DISABLE; + obj->p_t32a.p_instance = NULL; +} + +void pwmout_write(pwmout_t *obj, float value) +{ + // Stop PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + + if (value <= 0.0f) { + value = TXZ_DISABLE; + } else if (value >= 1.0f) { + value = TXZ_ENABLE; + } + + // Store the new leading_timing value + obj->leading_timing = obj->trailing_timing - (obj->trailing_timing * value); + + // Setting T32A_RGA0 register + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + + // Start PWM + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +float pwmout_read(pwmout_t *obj) +{ + float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing; + return duty_cycle; +} + +void pwmout_period(pwmout_t *obj, float seconds) +{ + pwmout_period_us(obj, (int)(seconds * 1000000.0f)); +} + +void pwmout_period_ms(pwmout_t *obj, int ms) +{ + pwmout_period_us(obj, (ms * 1000)); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t *obj, int us) +{ + uint32_t prscl = 0; + float duty_cycle = 0; + float seconds = (float)((us) / 1000000.0f); + + obj->period = seconds; + // Restore the duty-cycle + duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing); + prscl = T32A_PRSCLx_32; + + obj->trailing_timing = (us * CALCULATE_RGC1_VAL); + obj->leading_timing = ((obj->trailing_timing) - (obj->trailing_timing * duty_cycle)); + + obj->p_t32a.p_instance->MOD = T32A_MODE_32; + obj->p_t32a.p_instance->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); + obj->p_t32a.p_instance->CRC = (prscl | T32A_RELOAD_TREGx); + obj->p_t32a.p_instance->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ | + T32A_IMx1_MASK_REQ | T32A_IMx0_MASK_REQ); + obj->p_t32a.p_instance->RGC0 = obj->leading_timing; + obj->p_t32a.p_instance->RGC1 = obj->trailing_timing; + obj->p_t32a.p_instance->OUTCRC0 = T32A_OCR_DISABLE; + obj->p_t32a.p_instance->OUTCRC1 = (T32A_OCRCMPx1_CLR | T32A_OCRCMPx0_SET); + obj->p_t32a.p_instance->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->trailing_timing; +} + +void pwmout_pulsewidth(pwmout_t *obj, float seconds) +{ + pwmout_pulsewidth_us(obj, (seconds * 1000000.0f)); +} + +void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) +{ + pwmout_pulsewidth_us(obj, (ms * 1000)); +} + +void pwmout_pulsewidth_us(pwmout_t *obj, int us) +{ + float seconds = 0; + float value = 0; + + seconds = (float)(us / 1000000.0f); + value = (((seconds / obj->period) * 100.0f) / 100.0f); + pwmout_write(obj, value); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->trailing_timing - obj->leading_timing; +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/reset_reason_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/reset_reason_api.c new file mode 100644 index 00000000000..9786d3ca91a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/reset_reason_api.c @@ -0,0 +1,114 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2020 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "device.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "pinmap.h" +#include "reset_reason_api.h" + +#define CLEAR_FLAGS (0) +//reset reason flag bit positions +#define PORSTF_FLAG (1<<0) +#define PINRSTF_FLAG (1<<3) +#define LVDRSTF_FLAG (1<<5) + +#define SYSRSTF_FLAG (1<<0) +#define LOCKRSTF_FLAG (1<<1) +#define WDTRSTF_FLAG (1<<2) +#define OFDRSTF_FLAG (1<<3) + + +reset_reason_t hal_reset_reason_get(void) +{ + reset_reason_t reason = RESET_REASON_UNKNOWN; + + //check if its power on reset, as it clears other flags to 0 or undefined state. + if (TSB_RLM->RSTFLG0 & PORSTF_FLAG) { + //set PINRSTF_FLAG and LVDRSTF_FLAG flags to 0 as they may be in undefined state after POR + TSB_RLM->RSTFLG0 &= ~(PINRSTF_FLAG | LVDRSTF_FLAG); + reason = RESET_REASON_POWER_ON; + } else { + //multiple reset reasons might occur if flags are not cleared in previous reset + //hence check all flags. + + if (TSB_RLM->RSTFLG0 & PINRSTF_FLAG) { + reason = RESET_REASON_PIN_RESET; + } + + if (TSB_RLM->RSTFLG0 & LVDRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_BROWN_OUT : RESET_REASON_MULTIPLE; + } + + // check 2nd reset reason register + + if (TSB_RLM->RSTFLG1 & SYSRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_SOFTWARE : RESET_REASON_MULTIPLE; + } + + if (TSB_RLM->RSTFLG1 & LOCKRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_LOCKUP : RESET_REASON_MULTIPLE; + } + + if (TSB_RLM->RSTFLG1 & WDTRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_WATCHDOG : RESET_REASON_MULTIPLE; + } + + if (TSB_RLM->RSTFLG1 & OFDRSTF_FLAG) { + reason = (reason == RESET_REASON_UNKNOWN) ? RESET_REASON_PLATFORM : RESET_REASON_MULTIPLE; + } + } + + return reason; +} + +void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap) +{ + cap->reasons = 1 << RESET_REASON_UNKNOWN; + cap->reasons |= 1 << RESET_REASON_POWER_ON; + cap->reasons |= 1 << RESET_REASON_PIN_RESET; + cap->reasons |= 1 << RESET_REASON_BROWN_OUT; + cap->reasons |= 1 << RESET_REASON_SOFTWARE; + cap->reasons |= 1 << RESET_REASON_LOCKUP; + cap->reasons |= 1 << RESET_REASON_WATCHDOG; + cap->reasons |= 1 << RESET_REASON_PLATFORM; + cap->reasons |= 1 << RESET_REASON_MULTIPLE; +} + +uint32_t hal_reset_reason_get_raw(void) +{ + uint32_t reason_raw = 0; + //check if its power on reset, as it clears other flags to 0 or undefined state. + if (TSB_RLM->RSTFLG0 & PORSTF_FLAG) { + //set PINRSTF_FLAG and LVDRSTF_FLAG flags to 0 as they may be in undefined state after POR + TSB_RLM->RSTFLG0 &= ~(PINRSTF_FLAG | LVDRSTF_FLAG); + } + + //concatenating RSTFLG1 and RSTFLG0 register contents + reason_raw = ((TSB_RLM->RSTFLG1) << 8) | TSB_RLM->RSTFLG0 ; + return reason_raw; +} + + + +void hal_reset_reason_clear(void) +{ + //clear both reset reason registers RSTFLG1 and RSTFLG0 + TSB_RLM->RSTFLG0 = CLEAR_FLAGS; + TSB_RLM->RSTFLG1 = CLEAR_FLAGS; +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/serial_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/serial_api.c new file mode 100644 index 00000000000..e4dde27d13a --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/serial_api.c @@ -0,0 +1,363 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_error.h" +#include "serial_api.h" +#include "pinmap.h" +#include "txzp_cg.h" +#include "uart_spi_interrupts.h" + +#define UART_NUM 4 +#define UART_ENABLE_RX ((uint32_t)0x00000001) +#define UART_ENABLE_TX ((uint32_t)0x00000002) +#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002) +#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001) +#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080) +#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080) +#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002) +#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001) +#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100) +#define BAUDRATE_DEFAULT (9600) +#define CLR_REGISTER (0x00) + + +serial_t stdio_uart; +int stdio_uart_inited = 0; +static uintptr_t serial_irq_contexts[UART_NUM] = {0}; +static void uart_swreset(TSB_UART_TypeDef *UARTx); +static uart_irq_handler irq_handler; +void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event); + + +static const PinMap PinMap_UART_TX[] = { + {PC0, SERIAL_0, PIN_DATA(1, 1)}, + {PC4, SERIAL_1, PIN_DATA(1, 1)}, + {PU0, SERIAL_2, PIN_DATA(1, 1)}, + {PF6, SERIAL_3, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {PC1, SERIAL_0, PIN_DATA(1, 0)}, + {PC5, SERIAL_1, PIN_DATA(1, 0)}, + {PU1, SERIAL_2, PIN_DATA(1, 0)}, + {PF7, SERIAL_3, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + int is_stdio_uart = 0; + obj->mode = 0; + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal = {0}; + + UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); + UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); + UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx); + + MBED_ASSERT((int)uart_name != NC); + obj->index = uart_name; + + switch (uart_name) { + case SERIAL_0: + obj->UARTx = TSB_UART0; + // Enable clock for UART0 and Port N + TSB_CG_FSYSMENA_IPMENA21 = TXZ_ENABLE;//for uart + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + break; + case SERIAL_1: + obj->UARTx = TSB_UART1; + // Enable clock for UART1 and Port C + TSB_CG_FSYSMENA_IPMENA22 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA02 = TXZ_ENABLE; + break; + case SERIAL_2: + obj->UARTx = TSB_UART2; + // Enable clock for UART2 and Port U + TSB_CG_FSYSMENA_IPMENA23 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA16 = TXZ_ENABLE; + break; + case SERIAL_3: + obj->UARTx = TSB_UART3; + // Enable clock for UART3 and Port F + TSB_CG_FSYSMENA_IPMENA24 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA05 = TXZ_ENABLE; + break; + default: + break; + } +// Set alternate function + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC && rx != NC) { + obj->mode = UART_ENABLE_RX | UART_ENABLE_TX; + } else { + if (tx != NC) { + obj->mode = UART_ENABLE_TX; + } else { + if (rx != NC) { + obj->mode = UART_ENABLE_RX; + } + } + } + // Software reset + uart_swreset(obj->UARTx); + + obj->UARTx->CR0 |= (1U); // Data lengh 8 bit No parity one stop bit + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, BAUDRATE_DEFAULT, &obj->boud_obj); + + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn));// buad rate register(ken is from 23 but not shifted??) + obj->UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR); // Clear FIFO + obj->UARTx->TRANS |= obj->mode; // Enable TX RX block. + obj->UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL); + + is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0); + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } + +} + +void serial_free(serial_t *obj) +{ + obj->UARTx->TRANS = CLR_REGISTER; + obj->UARTx->CR0 = CLR_REGISTER; + obj->UARTx->CR1 = CLR_REGISTER; + obj->UARTx = CLR_REGISTER; + uart_swreset(obj->UARTx); + obj->index = (uint32_t)NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + cg_t paramCG; + paramCG.p_instance = TSB_CG; + uart_clock_t prescal; + prescal.prsel = UART_PLESCALER_1; + uart_get_boudrate_setting(cg_get_mphyt0(¶mCG), &prescal, baudrate, &obj->boud_obj); + obj->UARTx->BRD = CLR_REGISTER; // Clear BRD register + obj->UARTx->BRD |= ((obj->boud_obj.ken) | (obj->boud_obj.brk << 16) | (obj->boud_obj.brn)); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + uint32_t parity_check = 0; + uint32_t data_length = 0; + uint32_t tmp = 0; + uint32_t sblen = 0; + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven)); + MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits + + parity_check = ((parity == ParityOdd) ? 1 : ((parity == ParityEven) ? 3 : 0)); + data_length = (data_bits == 8 ? 1 : ((data_bits == 7) ? 0 : 2)); + sblen = (stop_bits == 1) ? 0 : 1; // 0: 1 stop bits, 1: 2 stop bits + tmp = ((sblen << 4) | (parity_check << 2) | data_length); + obj->UARTx->CR0 = tmp; +} + + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uintptr_t context) +{ + irq_handler = handler; + serial_irq_contexts[obj->index] = context; +} + + +void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event) +{ + irq_handler(serial_irq_contexts[uart_name], event); +} + + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type irq_n = (IRQn_Type)0; + + if (enable) { + obj->UARTx->CR1 |= ((irq == RxIrq) ? UART_RX_INT_ENABLE : UART_TX_INT_ENABLE); + } else { + obj->UARTx->CR1 &= ((irq == RxIrq) ? (~(UART_RX_INT_ENABLE)) : (~(UART_TX_INT_ENABLE))); + } + + switch (obj->index) { + case SERIAL_0: + if (irq == RxIrq) { + irq_n = INTSC0RX_IRQn; + } else { + irq_n = INTSC0TX_IRQn; + } + break; + case SERIAL_1: + if (irq == RxIrq) { + irq_n = INTSC1RX_IRQn; + } else { + irq_n = INTSC1TX_IRQn; + } + break; + case SERIAL_2: + if (irq == RxIrq) { + irq_n = INTSC2RX_IRQn; + } else { + irq_n = INTSC2TX_IRQn; + } + break; + case SERIAL_3: + if (irq == RxIrq) { + irq_n = INTSC3RX_IRQn; + } else { + irq_n = INTSC3TX_IRQn; + } + break; + + default: + break; + } + + //NVIC_ClearPendingIRQ(irq_n); + uart_spi_clear_pending_irq(irq_n); + + if (enable) { + //NVIC_EnableIRQ(irq_n); + uart_spi_enable_irq(irq_n, UART_PERIPH); + } else { + //NVIC_DisableIRQ(irq_n); + uart_spi_disable_irq(irq_n, UART_PERIPH); + } +} + + +int serial_getc(serial_t *obj) +{ + int data = 0; + + while (!serial_readable(obj)) { // Wait until Rx buffer is full + // Do nothing + } + + // Read Data Register + data = (obj->UARTx->DR & 0xFFU); + obj->UARTx->SR |= (1U << 6); // Clear RXEND flag + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)) { + // Do nothing + } + + // Write Data Register + obj->UARTx->DR = (c & 0xFF); + + while ((obj->UARTx->SR & (1U << 14)) == 0) { + // Do nothing + } + + obj->UARTx->SR |= (1U << 14); // Clear TXEND flag +} + + +int serial_readable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x000F) != 0) { + ret = 1; + } + + return ret; +} + +int serial_writable(serial_t *obj) +{ + int ret = 0; + + if ((obj->UARTx->SR & 0x8000) == 0) { + ret = 1; + } + + return ret; +} + +// Pause transmission +void serial_break_set(serial_t *obj) +{ + obj->UARTx->TRANS |= 0x08; +} + +// Switch to normal transmission +void serial_break_clear(serial_t *obj) +{ + obj->UARTx->TRANS &= ~(0x08); +} + +static void uart_swreset(TSB_UART_TypeDef *UARTx) +{ + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + + UARTx->SWRST = UARTxSWRST_SWRST_10; + UARTx->SWRST = UARTxSWRST_SWRST_01; + + while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) { + // No process + } + +} +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_CTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_RTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_RTS; +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/sleep.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/sleep.c new file mode 100644 index 00000000000..c62b062d808 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/sleep.c @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" + +// Number of warm-up cycle in EHOSC = (warming up time (s) / clock period (s)) - 16 +#define CG_WUODR_EXT_5MS ((uint16_t)0xC340) +// Number of warm-up cycle in IHOSC = ((warming up time (s) – 63.3(μs) / clock period (s)) - 41 +#define CG_WUODR_INT_67_4us ((uint16_t)0x0000) +#define CG_STBY_MODE_IDLE 0x0 +#define CG_STBY_MODE_STOP1 0x1 +#define EXTERNEL_OSC_MASK 0xFFFFFFF1 +#define SIWDT_DISABLE 0xB1 +#define WUPT_LOWER_MASK 0x000F +#define WUPT_UPPER_MASK 0xFFF0 + +static void external_hosc_enable(void); + +void hal_sleep(void) +{ + // Set low power consumption mode IDLE + TSB_CG->STBYCR = CG_STBY_MODE_IDLE; + + // Enter idle mode + __DSB(); + __WFI(); +} + +void hal_deepsleep(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + uint32_t tmp = 0; + + TSB_CG_FSYSMENB_IPMENB31 = TXZ_ENABLE; + + TSB_SIWD0->EN = TXZ_DISABLE; + TSB_SIWD0->CR = SIWDT_DISABLE; + + + while ((TSB_FC->SR0 & TXZ_DONE) != TXZ_DONE) { + // Flash wait + } + + while (TSB_CG_WUPHCR_WUEF) { + // Wait for end of Warming-up for IHOSC1 + } + + TSB_CG_WUPHCR_WUCLK = TXZ_DISABLE; + wupt_lower = ((CG_WUODR_INT_67_4us & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_INT_67_4us & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + TSB_CG->STBYCR = CG_STBY_MODE_STOP1; + TSB_CG_PLL0SEL_PLL0SEL = TXZ_DISABLE; + + + while (TSB_CG_PLL0SEL_PLL0ST) { + // Wait for PLL status of fsys until off state(fosc=0) + } + + // Stop PLL of fsys + TSB_CG_PLL0SEL_PLL0ON = TXZ_DISABLE; + TSB_CG_OSCCR_IHOSC1EN = TXZ_ENABLE; + TSB_CG_OSCCR_OSCSEL = TXZ_DISABLE; + + while (TSB_CG_OSCCR_OSCF) { + // Wait for fosc status until IHOSC1 = 0 + } + + tmp = TSB_CG->OSCCR; + tmp &= EXTERNEL_OSC_MASK; + TSB_CG->OSCCR = tmp; + + + // Enter stop1 mode + __DSB(); + __WFI(); + + // Switch over from IHOSC to EHOSC + // After coming out off sleep mode, Restore the clock setting to EHOSC. + external_hosc_enable(); +} + +static void external_hosc_enable(void) +{ + uint32_t wupt_lower = 0; + uint32_t wupt_upper = 0; + + // Enable high-speed oscillator + TSB_CG->OSCCR |= (TXZ_ENABLE << 1); + + // Select internal(fIHOSC) as warm-up clock + wupt_lower = ((CG_WUODR_EXT_5MS & WUPT_LOWER_MASK) << 16U); + wupt_upper = ((CG_WUODR_EXT_5MS & WUPT_UPPER_MASK) << 16U); + TSB_CG->WUPHCR |= (wupt_lower | wupt_upper); + + // Start warm-up + TSB_CG->WUPHCR |= TXZ_ENABLE; + + // Wait until EHOSC become stable + while ((TSB_CG->WUPHCR & 0x0002)) { + // Do nothing + } + + // Set fosc source + TSB_CG->OSCCR |= (1 << 8); + + // Wait for to become "1" + while (!((TSB_CG->OSCCR & 0x200) >> 9)) { + // Do nothing + } + + // Stop IHOSC + TSB_CG->OSCCR &= ~TXZ_ENABLE; +} diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/spi_api.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/spi_api.c new file mode 100644 index 00000000000..d0a7220fa68 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/spi_api.c @@ -0,0 +1,356 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "spi_api.h" +#include "mbed_error.h" +#include "txzp_tspi.h" +#include "pinmap.h" + +#define TIMEOUT (5000) + +static const PinMap PinMap_SPI_MOSI[] = { + {PA3, SPI_0, PIN_DATA(1, 1)}, + {PG5, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {PA2, SPI_0, PIN_DATA(1, 0)}, + {PG4, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SCLK[] = { + {PA4, SPI_0, PIN_DATA(1, 1)}, + {PG6, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SCLK[] = { + {PA4, SPI_0, PIN_DATA(1, 0)}, + {PG6, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {PA1, SPI_0, PIN_DATA(1, 1)}, + {PG1, SPI_1, PIN_DATA(1, 1)}, + {NC, NC, 0} +}; + +static const PinMap PinMap_SPI_SLAVE_SSEL[] = { + {PA0, SPI_0, PIN_DATA(1, 0)}, + {PG3, SPI_1, PIN_DATA(1, 0)}, + {NC, NC, 0} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Check pin parameters + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + obj->module = (SPIName)pinmap_merge(spi_mosi, spi_miso); + + MBED_ASSERT((int)obj->module != NC); + + obj->clk_pin = sclk; + obj->ssel_pin = ssel; + + // Identify SPI module to use + switch ((int)obj->module) { + case SPI_0: + obj->p_obj.p_instance = TSB_TSPI0; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA00 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA19 = TXZ_ENABLE; + break; + case SPI_1: + obj->p_obj.p_instance = TSB_TSPI1; + // Enable clock for particular Port and SPI + TSB_CG_FSYSMENA_IPMENA06 = TXZ_ENABLE; + TSB_CG_FSYSMENA_IPMENA20 = TXZ_ENABLE; + break; + default: + obj->p_obj.p_instance = NULL; + obj->module = (SPIName)NC; + error("Cannot found SPI module corresponding with input pins."); + break; + } + + // Pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + + // Default configurations 8 bit, 1Mhz frequency + // Control 1 configurations + obj->p_obj.init.id = (uint32_t)obj->module; + obj->p_obj.init.cnt1.inf = TSPI_INF_DISABLE; // Infinite Transfer Control disabled + obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled + obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication + obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode + obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // Master mode operation + obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive) + obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_CONTINUE; // Transfer single frame at a time continously + + // Control 2 configurations + obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI; + obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // When slave underruns TxD fixed to low + obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_FSYS_FSCK_16; + obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // Transmit FIFO Level + obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // Receive FIFO Level + obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE; + obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE; + obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE; + obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE; + obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE; + obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE; + obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE; + + // Control 3 configurations + obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // Transmit buffer clear + obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // Receive buffer clear + + // Baudrate settings - 1 Mhz default + obj->p_obj.init.brd.brck = TSPI_BR_CLOCK_4; + obj->p_obj.init.brd.brs = TSPI_BR_DIVIDER_10; + + // Format Control 0 settings + obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first + obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8; + obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0; + + // Special control on polarity of signal and generation timing + obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE; + obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE; + obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE; + obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE; + + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1; + obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1; + obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1; + + // Format Control 1 settings tspi_fmtr1_t + obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE; + obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD; + + obj->p_obj.init.sectcr0.sect = TSPI_SECTCR0_SECT_FRAME_MODE; + + obj->bits = (uint8_t)TSPI_DATA_LENGTH_8; + + // Initialize SPI + tspi_init(&obj->p_obj); +} + +void spi_free(spi_t *obj) +{ + tspi_deinit(&obj->p_obj); + obj->module = (SPIName)NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode + MBED_ASSERT((bits >= 8) && (bits <= 32)); + + obj->bits = bits; + obj->p_obj.init.fmr0.fl = (bits << 24); + + if (slave) { + pinmap_pinout(obj->clk_pin, PinMap_SPI_SLAVE_SCLK); + pinmap_pinout(obj->ssel_pin, PinMap_SPI_SLAVE_SSEL); + obj->p_obj.init.cnt1.mstr = TSPI_SLAVE_OPERATION; // Slave mode operation + } else { + pinmap_pinout(obj->clk_pin, PinMap_SPI_SCLK); + pinmap_pinout(obj->ssel_pin, PinMap_SPI_SSEL); + obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPERATION; // Master mode operation + } + + if ((mode >> 1) & 0x1) { + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI; + } else { + obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW; + } + + if (mode & 0x1) { + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE; + } else { + obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE; + } + + tspi_init(&obj->p_obj); +} + +void spi_frequency(spi_t *obj, int hz) +{ + SystemCoreClockUpdate(); + uint8_t brs = 0; + uint8_t brck = 0; + uint16_t prsck = 1; + uint64_t fscl = 0; + uint64_t tmp_fscl = 0; + uint64_t fx = 0; + uint64_t tmpvar = SystemCoreClock / 2; + + for (prsck = 1; prsck <= 512; prsck *= 2) { + fx = ((uint64_t)tmpvar / prsck); + for (brs = 1; brs <= 16; brs++) { + fscl = fx / brs; + if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) { + tmp_fscl = fscl; + obj->p_obj.init.brd.brck = (brck << 4); + if (brs == 16) { + obj->p_obj.init.brd.brs = 0; + } else { + obj->p_obj.init.brd.brs = brs; + } + } + } + brck ++; + } + + tspi_init(&obj->p_obj); +} + +int spi_master_write(spi_t *obj, int value) +{ + uint8_t ret_value = 0; + + tspi_transmit_t send_obj; + tspi_receive_t rec_obj; + + // Transmit data + send_obj.tx8.p_data = (uint8_t *)&value; + send_obj.tx8.num = 1; + tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT); + + // Read received data + rec_obj.rx8.p_data = &ret_value; + rec_obj.rx8.num = 1; + tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT); + + return ret_value; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) +{ + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_slave_receive(spi_t *obj) +{ + if ((obj->p_obj.p_instance->SR & 0x0F) != 0) { + return 1; + } + + return 0; +} + +int spi_slave_read(spi_t *obj) +{ + + uint8_t ret_value = 0; + + ret_value = obj->p_obj.p_instance->DR & 0xFF; + obj->p_obj.p_instance->CR1 &= TSPI_TRXE_DISABLE_MASK; + + return ret_value; +} + +void spi_slave_write(spi_t *obj, int value) +{ + if ((obj->p_obj.p_instance->CR1 & TSPI_TX_ONLY) != TSPI_TX_ONLY) { //Enable TX if not Enabled + obj->p_obj.p_instance->CR1 |= TSPI_TX_ONLY; + } + + obj->p_obj.p_instance->DR = (uint8_t)(value * 0xFF); + + obj->p_obj.p_instance->CR1 |= TSPI_TRXE_ENABLE; + +} + +int spi_busy(spi_t *obj) +{ + int ret = 1; + uint32_t status = 0; + + tspi_get_status(&obj->p_obj, &status); + + if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) { + ret = 0; + } + + return ret; +} + + +uint8_t spi_get_module(spi_t *obj) +{ + return (uint8_t)(obj->module); +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SLAVE_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SLAVE_SSEL; +} + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.c new file mode 100644 index 00000000000..ee0640cec87 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.c @@ -0,0 +1,281 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" +#include "uart_spi_interrupts.h" + +//The UART and TSPI in M4KNA target have shared irq lines. For this reason we have to maintain shared irq handlers. +// Also enable/disable of these shared IRQ lines from NVIC need to be controlled carefully to avoid loss of interrupt when +// any one peripheral disables/enables interrupt. For this reason IRQ related code is seperated from peripheral driver apis and +// maintained separately in this source file. + +#define CHANNEL_COUNT (4) + +extern void invoke_serial_irq_handler(UARTName uart_name, SerialIrq event); +typedef struct { + int ch0_tx_uart: 1; + int ch0_tx_spi: 1; + int ch0_rx_uart: 1; + int ch0_rx_spi: 1; + + int ch1_tx_uart: 1; + int ch1_tx_spi: 1; + int ch1_rx_uart: 1; + int ch1_rx_spi: 1; + + int ch2_tx_uart: 1; + int ch2_tx_spi: 1; + int ch2_rx_uart: 1; + int ch2_rx_spi: 1; + + int ch3_tx_uart: 1; + int ch3_tx_spi: 1; + int ch3_rx_uart: 1; + int ch3_rx_spi: 1; +} shared_nvic_irq_status; + +shared_nvic_irq_status shared_irqs; + +// IRQ Handlers shared by both SPI and UART + +void INTSC0RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_0, RxIrq); +} + +void INTSC0TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_0, TxIrq); +} + +void INTSC1RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_1, RxIrq); +} + +void INTSC1TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_1, TxIrq); +} + +void INTSC2RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_2, RxIrq); +} + +void INTSC2TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_2, TxIrq); +} + +void INTSC3RX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_3, RxIrq); +} + +void INTSC3TX_IRQHandler(void) +{ + invoke_serial_irq_handler(SERIAL_3, TxIrq); +} + + + +void uart_spi_clear_pending_irq(IRQn_Type irq) +{ + if (NVIC_GetEnableIRQ(irq) == 0) { + NVIC_ClearPendingIRQ(irq); + } +} + + + +void uart_spi_enable_irq(IRQn_Type irq, int uart_spi_device) +{ + if (NVIC_GetEnableIRQ(irq) == 0) { + NVIC_EnableIRQ(irq); + } + + switch (irq) { + case INTSC0RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch0_rx_spi = TXZ_ENABLE; + } + break; + case INTSC0TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch0_tx_spi = TXZ_ENABLE; + } + break; + case INTSC1RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch1_rx_spi = TXZ_ENABLE; + } + break; + case INTSC1TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch1_tx_spi = TXZ_ENABLE; + } + break; + case INTSC2RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch2_rx_spi = TXZ_ENABLE; + } + break; + case INTSC2TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch2_tx_spi = TXZ_ENABLE; + } + break; + case INTSC3RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_rx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch3_rx_spi = TXZ_ENABLE; + } + break; + case INTSC3TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_tx_uart = TXZ_ENABLE; + } else { + shared_irqs.ch3_tx_spi = TXZ_ENABLE; + } + break; + + default: + break; + + } +} + + + + +void uart_spi_disable_irq(IRQn_Type irq, int uart_spi_device) +{ + int disable_flag = 0; + + switch (irq) { + case INTSC0RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch0_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch0_rx_uart || shared_irqs.ch0_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC0TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch0_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch0_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch0_tx_uart || shared_irqs.ch0_tx_spi)) { + disable_flag = 1; + } + break; + case INTSC1RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch1_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch1_rx_uart || shared_irqs.ch1_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC1TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch1_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch1_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch1_tx_uart || shared_irqs.ch1_tx_spi)) { + disable_flag = 1; + } + break; + case INTSC2RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch2_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch2_rx_uart || shared_irqs.ch2_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC2TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch2_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch2_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch2_tx_uart || shared_irqs.ch2_tx_spi)) { + disable_flag = 1; + } + break; + case INTSC3RX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_rx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch3_rx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch3_rx_uart || shared_irqs.ch3_rx_spi)) { + disable_flag = 1; + } + break; + case INTSC3TX_IRQn: + if (uart_spi_device == UART_PERIPH) { + shared_irqs.ch3_tx_uart = TXZ_DISABLE; + } else { + shared_irqs.ch3_tx_spi = TXZ_DISABLE; + } + + if (!(shared_irqs.ch3_tx_uart || shared_irqs.ch3_tx_spi)) { + disable_flag = 1; + } + break; + + default: + break; + } + + if (disable_flag) { + NVIC_DisableIRQ(irq); + } +} + + diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h new file mode 100644 index 00000000000..51962b6c594 --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/uart_spi_interrupts.h @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ +#define TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ + +#define SPI_PEPIRH (0) +#define UART_PERIPH (1) + +void uart_spi_clear_pending_irq(IRQn_Type irq); +void uart_spi_enable_irq(IRQn_Type irq, int uart_spi_device); +void uart_spi_disable_irq(IRQn_Type irq, int uart_spi_device); + + +#endif /* TARGETS_TARGET_TOSHIBA_TARGET_TMPM4KNA_UART_SPI_INTERRUPTS_H_ */ diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c new file mode 100644 index 00000000000..52478673b5b --- /dev/null +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM4KN/us_ticker.c @@ -0,0 +1,98 @@ +/* mbed Microcontroller Library + * Copyright(C) Toshiba Electronic Device Solutions Corporation 2021 + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "txzp_t32a.h" +#include "TMPM4KNA.h" + + +static uint8_t us_ticker_inited = 0; // Is ticker initialized yet? + + +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + 2500000, + 32 + }; + return &info; +} +// Initialize us_ticker +void us_ticker_init(void) +{ + if (us_ticker_inited) { + us_ticker_disable_interrupt(); + return; + } + us_ticker_inited = 1; + TSB_CG_FSYSMENA_IPMENA28 = TXZ_ENABLE; + + // Configure Timer T32A0 + TSB_T32A0->MOD = T32A_MODE_32; + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->CRC = T32A_PRSCLx_32; + TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); + + NVIC_SetVector(INTT32A00AC_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(INTT32A00AC_IRQn); +} + +uint32_t us_ticker_read(void) +{ + uint32_t ret_val = 0; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + ret_val = (TSB_T32A0->TMRC); + return ret_val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + NVIC_DisableIRQ(INTT32A00AC_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP); + TSB_T32A0->RGC1 = timestamp ; + NVIC_EnableIRQ(INTT32A00AC_IRQn); + TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); +} + +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(INTT32A00AC_IRQn); + NVIC_EnableIRQ(INTT32A00AC_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + NVIC_ClearPendingIRQ(INTT32A00AC_IRQn); + NVIC_DisableIRQ(INTT32A00AC_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + NVIC_ClearPendingIRQ(INTT32A00AC_IRQn); +} + +void us_ticker_free(void) +{ + TSB_T32A0->RUNC = T32A_RUN_DISABLE; + NVIC_ClearPendingIRQ(INTT32A00AC_IRQn); + NVIC_DisableIRQ(INTT32A00AC_IRQn); + TSB_CG_FSYSMENA_IPMENA28 = TXZ_DISABLE; +} diff --git a/targets/TARGET_TOSHIBA/mbed_rtx.h b/targets/TARGET_TOSHIBA/mbed_rtx.h index 2110efe8dea..3c62f5be8d7 100644 --- a/targets/TARGET_TOSHIBA/mbed_rtx.h +++ b/targets/TARGET_TOSHIBA/mbed_rtx.h @@ -36,4 +36,12 @@ #endif +#if defined(TARGET_TMPM4KN) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20006000UL) +#endif + +#endif + #endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index e66c4c73d7e..79b7e2119fd 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1718,6 +1718,9 @@ "detect_code": [ "0747" ], + "device_has_add": [ + "USBDEVICE" + ], "device_name": "STM32F303ZETx" }, "MCU_STM32F334x8": { @@ -1798,6 +1801,7 @@ ], "device_has_add": [ "ANALOGOUT", + "CAN", "TRNG" ] }, @@ -1816,6 +1820,7 @@ "EMAC" ], "device_has_remove": [ + "CAN", "LPTICKER", "SERIAL_FC" ], @@ -2380,6 +2385,27 @@ "MPU" ] }, + "NUCLEO_F722ZE": { + "inherits": [ + "MCU_STM32F7" + ], + "extra_labels_add": [ + "STM32F722xE" + ], + "macros_add": [ + "STM32F722xx" + ], + "device_has_add": [ + "USBDEVICE" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "0812" + ], + "device_name": "STM32F722ZETx" + }, "DISCO_F746NG": { "inherits": [ "MCU_STM32F7" @@ -2568,6 +2594,10 @@ "flash_dual_bank": { "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1", "value": "0" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_HS" } }, "detect_code": [ @@ -2624,6 +2654,7 @@ "MBED_TICKLESS" ], "overrides": { + "lpuart_clock_source": "USE_LPUART_CLK_HSI", "lpticker_delay_ticks": 0 }, "device_has_add": [ @@ -2632,7 +2663,7 @@ "MPU" ] }, - "MCU_STM32G031xx": { + "MCU_STM32G030x8": { "inherits": [ "MCU_STM32G0" ], @@ -2644,7 +2675,29 @@ "bare-metal" ], "extra_labels_add": [ - "STM32G031xx" + "STM32G030x8" + ], + "macros_add": [ + "STM32G030xx" + ], + "overrides": { + "lpticker_delay_ticks": 1, + "lpticker_lptim": "0" + } + }, + "MCU_STM32G031x8": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "overrides": { + "boot-stack-size": "0x400" + }, + "supported_application_profiles": [ + "bare-metal" + ], + "extra_labels_add": [ + "STM32G031x8" ], "macros_add": [ "STM32G031xx" @@ -2652,20 +2705,102 @@ }, "NUCLEO_G031K8": { "inherits": [ - "MCU_STM32G031xx" + "MCU_STM32G031x8" ], "detect_code": [ "0852" ], "device_name": "STM32G031K8Tx" }, - "MCU_STM32G070xx": { + "MCU_STM32G041x8": { "inherits": [ "MCU_STM32G0" ], "public": false, + "overrides": { + "boot-stack-size": "0x400" + }, + "supported_application_profiles": [ + "bare-metal" + ], "extra_labels_add": [ - "STM32G070xx" + "STM32G041x8" + ], + "macros_add": [ + "STM32G041xx" + ] + }, + "MCU_STM32G050x8": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "overrides": { + "boot-stack-size": "0x400" + }, + "supported_application_profiles": [ + "bare-metal" + ], + "extra_labels_add": [ + "STM32G050x8" + ], + "macros_add": [ + "STM32G050xx" + ], + "overrides": { + "lpticker_delay_ticks": 1, + "lpticker_lptim": "0" + } + }, + "MCU_STM32G051x8": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "overrides": { + "boot-stack-size": "0x400" + }, + "supported_application_profiles": [ + "bare-metal" + ], + "extra_labels_add": [ + "STM32G051x8" + ], + "macros_add": [ + "STM32G051xx" + ], + "device_has_add": [ + "ANALOGOUT" + ] + }, + "MCU_STM32G061x8": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "overrides": { + "boot-stack-size": "0x400" + }, + "supported_application_profiles": [ + "bare-metal" + ], + "extra_labels_add": [ + "STM32G061x8" + ], + "macros_add": [ + "STM32G061xx" + ], + "device_has_add": [ + "ANALOGOUT" + ] + }, + "MCU_STM32G070xB": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "extra_labels_add": [ + "STM32G070xB" ], "macros_add": [ "STM32G070xx" @@ -2679,13 +2814,13 @@ "lpticker_lptim": "0" } }, - "MCU_STM32G071xx": { + "MCU_STM32G071xB": { "inherits": [ "MCU_STM32G0" ], "public": false, "extra_labels_add": [ - "STM32G071xx" + "STM32G071xB" ], "macros_add": [ "STM32G071xx" @@ -2696,23 +2831,89 @@ }, "NUCLEO_G071RB": { "inherits": [ - "MCU_STM32G071xx" + "MCU_STM32G071xB" ], "supported_form_factors": [ "ARDUINO_UNO" ], - "config": { - "hse_value": { - "help": "HSE default value is 25MHz in HAL", - "value": "8000000", - "macro_name": "HSE_VALUE" - } - }, "detect_code": [ "0221" ], "device_name": "STM32G071RBTx" }, + "MCU_STM32G081xB": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "extra_labels_add": [ + "STM32G081xB" + ], + "macros_add": [ + "STM32G081xx" + ], + "device_has_add": [ + "ANALOGOUT" + ] + }, + "MCU_STM32G0B0xE": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "extra_labels_add": [ + "STM32G0B0xE" + ], + "macros_add": [ + "STM32G0B0xx" + ], + "overrides": { + "lpticker_delay_ticks": 1, + "lpticker_lptim": "0" + } + }, + "MCU_STM32G0B1xE": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "extra_labels_add": [ + "STM32G0B1xE" + ], + "macros_add": [ + "STM32G0B1xx" + ], + "device_has_add": [ + "ANALOGOUT" + ] + }, + "NUCLEO_G0B1RE": { + "inherits": [ + "MCU_STM32G0B1xE" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "0872" + ], + "device_name": "STM32G0B1RETx" + }, + "MCU_STM32G0C1xE": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "extra_labels_add": [ + "STM32G0C1xE" + ], + "macros_add": [ + "STM32G0C1xx" + ], + "device_has_add": [ + "ANALOGOUT" + ] + }, "MCU_STM32G4": { "inherits": [ "MCU_STM32" @@ -2967,16 +3168,72 @@ "MPU" ] }, - "MCU_STM32H743xI": { + "MCU_STM32H723xG": { "inherits": [ "MCU_STM32H7" ], "public": false, "core": "Cortex-M7FD", "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x200000", + "mbed_rom_size": "0x100000", "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x80000", + "mbed_ram_size": "0x50000", + "extra_labels_add": [ + "STM32H723xG" + ], + "macros_add": [ + "STM32H723xx" + ], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY" + } + }, + "MCU_STM32H725xE": { + "inherits": [ + "MCU_STM32H7" + ], + "public": false, + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size": "0x80000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x50000", + "extra_labels_add": [ + "STM32H725xE" + ], + "macros_add": [ + "STM32H725xx" + ], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY" + } + }, + "MCU_STM32H735xG": { + "inherits": [ + "MCU_STM32H7" + ], + "public": false, + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size": "0x100000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x50000", + "extra_labels_add": [ + "STM32H735xG" + ], + "macros_add": [ + "STM32H735xx" + ], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY" + } + }, + "MCU_STM32H743xI": { + "inherits": [ + "MCU_STM32H7" + ], + "public": false, + "core": "Cortex-M7FD", "extra_labels_add": [ "STM32H743xI" ], @@ -3250,12 +3507,52 @@ "MPU" ] }, + "MCU_STM32H750xB": { + "inherits": [ + "MCU_STM32H7" + ], + "public": false, + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size": "0x20000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x80000", + "extra_labels_add": [ + "STM32H750xB" + ], + "macros_add": [ + "STM32H750xx" + ], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY" + } + }, + "MCU_STM32H753xI": { + "inherits": [ + "MCU_STM32H7" + ], + "public": false, + "core": "Cortex-M7FD", + "extra_labels_add": [ + "STM32H753xI" + ], + "macros_add": [ + "STM32H753xx" + ], + "overrides": { + "system_power_supply": "PWR_LDO_SUPPLY" + } + }, "MCU_STM32H7A3xIQ": { "inherits": [ "MCU_STM32H7" ], "public": false, "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size": "0x200000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x100000", "extra_labels_add": [ "STM32H7A3xIQ" ], @@ -3284,6 +3581,26 @@ "0860" ] }, + "MCU_STM32H7B3xIQ": { + "inherits": [ + "MCU_STM32H7" + ], + "public": false, + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size": "0x200000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x100000", + "extra_labels_add": [ + "STM32H7B3xIQ" + ], + "macros_add": [ + "STM32H7B3xxQ" + ], + "overrides": { + "system_power_supply": "PWR_DIRECT_SMPS_SUPPLY" + } + }, "MCU_STM32L0": { "inherits": [ "MCU_STM32" @@ -3466,6 +3783,33 @@ "MPU" ] }, + "MCU_STM32L151xB": { + "inherits": [ + "MCU_STM32L1" + ], + "public": false, + "extra_labels_add": [ + "STM32L151xB" + ], + "device_has_remove": [ + "LPTICKER" + ], + "macros_add": [ + "STM32L151xB" + ] + }, + "MCU_STM32L151xBA": { + "inherits": [ + "MCU_STM32L1" + ], + "public": false, + "extra_labels_add": [ + "STM32L151xBA" + ], + "macros_add": [ + "STM32L151xBA" + ] + }, "MCU_STM32L151xC": { "inherits": [ "MCU_STM32L1" @@ -3606,6 +3950,23 @@ "TRNG" ] }, + "MCU_STM32L412xB": { + "inherits": [ + "MCU_STM32L4" + ], + "public": false, + "c_lib": "small", + "extra_labels_add": [ + "STM32L412xB" + ], + "macros_add": [ + "STM32L412xx" + ], + "device_has_remove": [ + "ANALOGOUT", + "CAN" + ] + }, "MCU_STM32L432xC": { "inherits": [ "MCU_STM32L4" @@ -3761,7 +4122,8 @@ ], "extra_labels_add": [ "CORDIO", - "MX25R6435F" + "MX25R6435F", + "M24SR" ], "supported_form_factors": [ "ARDUINO_UNO" @@ -3975,6 +4337,21 @@ ], "device_name": "STM32L496VGTx" }, + "MCU_STM32L4P5xG": { + "inherits": [ + "MCU_STM32L4" + ], + "public": false, + "components_add": [ + "FLASHIAP" + ], + "extra_labels_add": [ + "STM32L4P5xG" + ], + "macros_add": [ + "STM32L4P5xx" + ] + }, "MCU_STM32L4R5xI": { "inherits": [ "MCU_STM32L4" @@ -4147,6 +4524,7 @@ }, "device_has_add": [ "ANALOGOUT", + "CAN", "CRC", "FLASH", "MPU", @@ -4262,6 +4640,7 @@ }, "device_has_add": [ "ANALOGOUT", + "CAN", "CRC", "FLASH", "MPU", @@ -4315,6 +4694,20 @@ "ARDUINO_UNO" ], "device_name": "STM32U585AIIx", + "extra_labels_add": [ + "MX25LM51245G" + ], + "components_add": [ + "OSPIF" + ], + "device_has_add": [ + "QSPI", + "OSPI" + ], + "components_add": ["EMW3080B"], + "overrides": { + "network-default-interface-type": "WIFI" + }, "detect_code": [ "887" ] @@ -5723,6 +6116,86 @@ ] } }, + "MAX32660": { + "inherits": [ + "Target" + ], + "public": false, + "core": "Cortex-M4F", + "macros": [ + "__SYSTEM_HFX=96000000", + "TARGET=MAX32660", + "TARGET_REV=0x4131", + "MBED_MPU_CUSTOM" + ], + "extra_labels": [ + "Maxim", + "MAX32660" + ], + "supported_toolchains": [ + "GCC_ARM", + "ARM" + ], + "device_has": [ + "SERIAL", + "SERIAL_FC", + "STDIO_MESSAGES", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "USTICKER", + "LPTICKER", + "INTERRUPTIN", + "SPI", + "I2C", + "RTC", + "SLEEP", + "WATCHDOG", + "FLASH" + ], + "supported_application_profiles" : ["full", "bare-metal"], + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ] + } + }, + "MAX32660EVSYS": { + "inherits": [ + "MAX32660" + ], + "macros_add": [ + "OPEN_DRAIN_LEDS" + ], + "device_has_remove": [ + "LPTICKER" + ], + "extra_labels_add": [ + "MAX32660EVSYS" + ], + "config": { + "stdio_uart": { + "help": "default STDIO port is defined in PeripheralNames.h file, but it can be overridden, default UART_1", + "value": null + }, + "stdio_uart_tx": { + "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden, default P0_10", + "value": null + }, + "stdio_uart_rx": { + "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden, default P0_11", + "value": null + } + }, + "detect_code": [ + "0421" + ] + }, "EFM32": { "inherits": [ "Target" @@ -8306,7 +8779,8 @@ "FLASH", "MPU", "WATCHDOG", - "USBDEVICE" + "USBDEVICE", + "CAN" ], "components_add": [ "FLASHIAP" @@ -8535,5 +9009,46 @@ "__build_tools_metadata__": { "version": "1", "public": false + }, + "TMPM4KN": { + "inherits": ["Target"], + "core": "Cortex-M4F", + "is_disk_virtual": true, + "extra_labels": ["TOSHIBA"], + "macros": ["__TMPM4KN__"], + "supported_toolchains": ["GCC_ARM","ARMC6"], + "device_has": [ + "ANALOGIN", + "INTERRUPTIN", + "CRC", + "I2C", + "I2CSLAVE", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "RESET_REASON", + "SERIAL", + "SLEEP", + "SPI", + "SPISLAVE", + "USTICKER", + "STDIO_MESSAGES", + "MPU", + "FLASH" + ], + "device_name": "TMPM4KNFYAFG", + "detect_code": ["7020"], + "release_versions": ["5"], + "bootloader_supported": true, + "supported_application_profiles" : ["full"], + "supported_c_libs": { + "arm": [ + "std" + ], + "gcc_arm": [ + "std" + ] + } } } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index a3841553c72..ae55d0e6c48 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -419113,100 +419113,212 @@ ], "sub_family": "STM32G041", "vendor": "STMicroelectronics:13" - }, - "STM32G070CBTx": { + }, + "STM32G050K8Tx": { "algorithms": [ { - "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", - "ram_size": null, - "ram_start": null, - "size": 131072, + "default": true, + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "ram_size": null, + "ram_start": null, + "size": 65536, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32G0xx_OTP.FLM", - "ram_size": null, - "ram_start": null, - "size": 1024, - "start": 536834048 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32G0x0_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 12, - "start": 536836096 } - ], - "family": "STM32G0 Series", + ], + "family": "STM32G0 Series", "from_pack": { - "pack": "STM32G0xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "1.2.0" - }, + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.3.0" + }, "memories": { "IRAM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 36864, - "start": 536870912, + }, + "default": true, + "size": 18432, + "start": 536870912, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, - "size": 131072, - "start": 134217728, + }, + "default": true, + "size": 65536, + "start": 134217728, "startup": true } - }, - "name": "STM32G070CBTx", + }, + "name": "STM32G050K8Tx", "processor": { "Symmetric": { - "core": "CortexM0Plus", - "fpu": "None", - "mpu": "Present", + "core": "CortexM0Plus", + "fpu": "None", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ - 134217728, + 134217728, 2048 - ], + ] + ], + "sub_family": "STM32G050", + "vendor": "STMicroelectronics:13" + }, + "STM32G051K8Tx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "ram_size": null, + "ram_start": null, + "size": 65536, + "start": 134217728 + } + ], + "family": "STM32G0 Series", + "from_pack": { + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.3.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 18432, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 65536, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G051K8Tx", + "processor": { + "Symmetric": { + "core": "CortexM0Plus", + "fpu": "None", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ [ - 536834048, - 1024 - ], + 134217728, + 2048 + ] + ], + "sub_family": "STM32G051", + "vendor": "STMicroelectronics:13" + }, + "STM32G061K8Tx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "ram_size": null, + "ram_start": null, + "size": 65536, + "start": 134217728 + } + ], + "family": "STM32G0 Series", + "from_pack": { + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.3.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 18432, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 65536, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G061K8Tx", + "processor": { + "Symmetric": { + "core": "CortexM0Plus", + "fpu": "None", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ [ - 536836096, - 12 + 134217728, + 2048 ] - ], - "sub_family": "STM32G070", + ], + "sub_family": "STM32G061", "vendor": "STMicroelectronics:13" - }, - "STM32G070KBTx": { + }, + "STM32G070CBTx": { "algorithms": [ { "default": true, @@ -419272,7 +419384,7 @@ "startup": true } }, - "name": "STM32G070KBTx", + "name": "STM32G070CBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419298,7 +419410,7 @@ "sub_family": "STM32G070", "vendor": "STMicroelectronics:13" }, - "STM32G070RBTx": { + "STM32G070KBTx": { "algorithms": [ { "default": true, @@ -419364,7 +419476,7 @@ "startup": true } }, - "name": "STM32G070RBTx", + "name": "STM32G070KBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419390,14 +419502,14 @@ "sub_family": "STM32G070", "vendor": "STMicroelectronics:13" }, - "STM32G071C6Tx": { + "STM32G070RBTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", "ram_size": null, "ram_start": null, - "size": 32768, + "size": 131072, "start": 134217728 }, { @@ -419410,10 +419522,10 @@ }, { "default": false, - "file_name": "CMSIS/Flash/STM32G0x1_OPT.FLM", + "file_name": "CMSIS/Flash/STM32G0x0_OPT.FLM", "ram_size": null, "ram_start": null, - "size": 32, + "size": 12, "start": 536836096 } ], @@ -419451,12 +419563,12 @@ "write": false }, "default": true, - "size": 32768, + "size": 131072, "start": 134217728, "startup": true } }, - "name": "STM32G071C6Tx", + "name": "STM32G070RBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419476,13 +419588,13 @@ ], [ 536836096, - 32 + 12 ] ], - "sub_family": "STM32G071", + "sub_family": "STM32G070", "vendor": "STMicroelectronics:13" }, - "STM32G071C6Ux": { + "STM32G071C6Tx": { "algorithms": [ { "default": true, @@ -419548,7 +419660,7 @@ "startup": true } }, - "name": "STM32G071C6Ux", + "name": "STM32G071C6Tx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419574,14 +419686,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071C8Tx": { + "STM32G071C6Ux": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", "ram_size": null, "ram_start": null, - "size": 65536, + "size": 32768, "start": 134217728 }, { @@ -419635,12 +419747,12 @@ "write": false }, "default": true, - "size": 65536, + "size": 32768, "start": 134217728, "startup": true } }, - "name": "STM32G071C8Tx", + "name": "STM32G071C6Ux", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419666,7 +419778,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071C8Ux": { + "STM32G071C8Tx": { "algorithms": [ { "default": true, @@ -419732,7 +419844,7 @@ "startup": true } }, - "name": "STM32G071C8Ux", + "name": "STM32G071C8Tx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419758,14 +419870,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071CBTx": { + "STM32G071C8Ux": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", "ram_size": null, "ram_start": null, - "size": 131072, + "size": 65536, "start": 134217728 }, { @@ -419819,12 +419931,12 @@ "write": false }, "default": true, - "size": 131072, + "size": 65536, "start": 134217728, "startup": true } }, - "name": "STM32G071CBTx", + "name": "STM32G071C8Ux", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419850,7 +419962,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071CBUx": { + "STM32G071CBTx": { "algorithms": [ { "default": true, @@ -419916,7 +420028,7 @@ "startup": true } }, - "name": "STM32G071CBUx", + "name": "STM32G071CBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -419942,7 +420054,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071EBYx": { + "STM32G071CBUx": { "algorithms": [ { "default": true, @@ -420008,7 +420120,7 @@ "startup": true } }, - "name": "STM32G071EBYx", + "name": "STM32G071CBUx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420034,14 +420146,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071G6Ux": { + "STM32G071EBYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", "ram_size": null, "ram_start": null, - "size": 32768, + "size": 131072, "start": 134217728 }, { @@ -420095,12 +420207,12 @@ "write": false }, "default": true, - "size": 32768, + "size": 131072, "start": 134217728, "startup": true } }, - "name": "STM32G071G6Ux", + "name": "STM32G071EBYx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420126,14 +420238,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071G8Ux": { + "STM32G071G6Ux": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", "ram_size": null, "ram_start": null, - "size": 65536, + "size": 32768, "start": 134217728 }, { @@ -420187,12 +420299,12 @@ "write": false }, "default": true, - "size": 65536, + "size": 32768, "start": 134217728, "startup": true } }, - "name": "STM32G071G8Ux", + "name": "STM32G071G6Ux", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420218,7 +420330,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071G8UxN": { + "STM32G071G8Ux": { "algorithms": [ { "default": true, @@ -420284,7 +420396,7 @@ "startup": true } }, - "name": "STM32G071G8UxN", + "name": "STM32G071G8Ux", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420310,14 +420422,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071GBUx": { + "STM32G071G8UxN": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", "ram_size": null, "ram_start": null, - "size": 131072, + "size": 65536, "start": 134217728 }, { @@ -420371,12 +420483,12 @@ "write": false }, "default": true, - "size": 131072, + "size": 65536, "start": 134217728, "startup": true } }, - "name": "STM32G071GBUx", + "name": "STM32G071G8UxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420402,7 +420514,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071GBUxN": { + "STM32G071GBUx": { "algorithms": [ { "default": true, @@ -420468,7 +420580,7 @@ "startup": true } }, - "name": "STM32G071GBUxN", + "name": "STM32G071GBUx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420494,14 +420606,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071K6Tx": { + "STM32G071GBUxN": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", "ram_size": null, "ram_start": null, - "size": 32768, + "size": 131072, "start": 134217728 }, { @@ -420555,12 +420667,12 @@ "write": false }, "default": true, - "size": 32768, + "size": 131072, "start": 134217728, "startup": true } }, - "name": "STM32G071K6Tx", + "name": "STM32G071GBUxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420586,7 +420698,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071K6Ux": { + "STM32G071K6Tx": { "algorithms": [ { "default": true, @@ -420652,7 +420764,7 @@ "startup": true } }, - "name": "STM32G071K6Ux", + "name": "STM32G071K6Tx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420678,14 +420790,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071K8Tx": { + "STM32G071K6Ux": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", "ram_size": null, "ram_start": null, - "size": 65536, + "size": 32768, "start": 134217728 }, { @@ -420739,12 +420851,12 @@ "write": false }, "default": true, - "size": 65536, + "size": 32768, "start": 134217728, "startup": true } }, - "name": "STM32G071K8Tx", + "name": "STM32G071K6Ux", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420770,7 +420882,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071K8TxN": { + "STM32G071K8Tx": { "algorithms": [ { "default": true, @@ -420836,7 +420948,7 @@ "startup": true } }, - "name": "STM32G071K8TxN", + "name": "STM32G071K8Tx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420862,7 +420974,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071K8Ux": { + "STM32G071K8TxN": { "algorithms": [ { "default": true, @@ -420928,7 +421040,7 @@ "startup": true } }, - "name": "STM32G071K8Ux", + "name": "STM32G071K8TxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -420954,7 +421066,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071K8UxN": { + "STM32G071K8Ux": { "algorithms": [ { "default": true, @@ -421020,7 +421132,7 @@ "startup": true } }, - "name": "STM32G071K8UxN", + "name": "STM32G071K8Ux", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421046,14 +421158,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071KBTx": { + "STM32G071K8UxN": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", "ram_size": null, "ram_start": null, - "size": 131072, + "size": 65536, "start": 134217728 }, { @@ -421107,12 +421219,12 @@ "write": false }, "default": true, - "size": 131072, + "size": 65536, "start": 134217728, "startup": true } }, - "name": "STM32G071KBTx", + "name": "STM32G071K8UxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421138,7 +421250,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071KBTxN": { + "STM32G071KBTx": { "algorithms": [ { "default": true, @@ -421204,7 +421316,7 @@ "startup": true } }, - "name": "STM32G071KBTxN", + "name": "STM32G071KBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421230,7 +421342,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071KBUx": { + "STM32G071KBTxN": { "algorithms": [ { "default": true, @@ -421296,7 +421408,7 @@ "startup": true } }, - "name": "STM32G071KBUx", + "name": "STM32G071KBTxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421322,7 +421434,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071KBUxN": { + "STM32G071KBUx": { "algorithms": [ { "default": true, @@ -421388,7 +421500,7 @@ "startup": true } }, - "name": "STM32G071KBUxN", + "name": "STM32G071KBUx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421414,14 +421526,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071R6Tx": { + "STM32G071KBUxN": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", "ram_size": null, "ram_start": null, - "size": 32768, + "size": 131072, "start": 134217728 }, { @@ -421475,12 +421587,12 @@ "write": false }, "default": true, - "size": 32768, + "size": 131072, "start": 134217728, "startup": true } }, - "name": "STM32G071R6Tx", + "name": "STM32G071KBUxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421506,14 +421618,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071R8Tx": { + "STM32G071R6Tx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_32.FLM", "ram_size": null, "ram_start": null, - "size": 65536, + "size": 32768, "start": 134217728 }, { @@ -421567,12 +421679,12 @@ "write": false }, "default": true, - "size": 65536, + "size": 32768, "start": 134217728, "startup": true } }, - "name": "STM32G071R8Tx", + "name": "STM32G071R6Tx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421598,14 +421710,14 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071RBIx": { + "STM32G071R8Tx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_64.FLM", "ram_size": null, "ram_start": null, - "size": 131072, + "size": 65536, "start": 134217728 }, { @@ -421659,12 +421771,12 @@ "write": false }, "default": true, - "size": 131072, + "size": 65536, "start": 134217728, "startup": true } }, - "name": "STM32G071RBIx", + "name": "STM32G071R8Tx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421690,7 +421802,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G071RBTx": { + "STM32G071RBIx": { "algorithms": [ { "default": true, @@ -421756,7 +421868,7 @@ "startup": true } }, - "name": "STM32G071RBTx", + "name": "STM32G071RBIx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421782,99 +421894,7 @@ "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G081CBTx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", - "ram_size": null, - "ram_start": null, - "size": 131072, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32G0xx_OTP.FLM", - "ram_size": null, - "ram_start": null, - "size": 1024, - "start": 536834048 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32G0x1_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 32, - "start": 536836096 - } - ], - "family": "STM32G0 Series", - "from_pack": { - "pack": "STM32G0xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "1.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 36864, - "start": 536870912, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 131072, - "start": 134217728, - "startup": true - } - }, - "name": "STM32G081CBTx", - "processor": { - "Symmetric": { - "core": "CortexM0Plus", - "fpu": "None", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ], - [ - 536834048, - 1024 - ], - [ - 536836096, - 32 - ] - ], - "sub_family": "STM32G081", - "vendor": "STMicroelectronics:13" - }, - "STM32G081CBUx": { + "STM32G071RBTx": { "algorithms": [ { "default": true, @@ -421940,7 +421960,7 @@ "startup": true } }, - "name": "STM32G081CBUx", + "name": "STM32G071RBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -421963,10 +421983,10 @@ 32 ] ], - "sub_family": "STM32G081", + "sub_family": "STM32G071", "vendor": "STMicroelectronics:13" }, - "STM32G081EBYx": { + "STM32G081CBTx": { "algorithms": [ { "default": true, @@ -422032,7 +422052,7 @@ "startup": true } }, - "name": "STM32G081EBYx", + "name": "STM32G081CBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422058,7 +422078,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081GBUx": { + "STM32G081CBUx": { "algorithms": [ { "default": true, @@ -422124,7 +422144,7 @@ "startup": true } }, - "name": "STM32G081GBUx", + "name": "STM32G081CBUx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422150,7 +422170,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081GBUxN": { + "STM32G081EBYx": { "algorithms": [ { "default": true, @@ -422216,7 +422236,7 @@ "startup": true } }, - "name": "STM32G081GBUxN", + "name": "STM32G081EBYx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422242,7 +422262,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081KBTx": { + "STM32G081GBUx": { "algorithms": [ { "default": true, @@ -422308,7 +422328,7 @@ "startup": true } }, - "name": "STM32G081KBTx", + "name": "STM32G081GBUx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422334,7 +422354,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081KBTxN": { + "STM32G081GBUxN": { "algorithms": [ { "default": true, @@ -422400,7 +422420,7 @@ "startup": true } }, - "name": "STM32G081KBTxN", + "name": "STM32G081GBUxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422426,7 +422446,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081KBUx": { + "STM32G081KBTx": { "algorithms": [ { "default": true, @@ -422492,7 +422512,7 @@ "startup": true } }, - "name": "STM32G081KBUx", + "name": "STM32G081KBTx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422518,7 +422538,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081KBUxN": { + "STM32G081KBTxN": { "algorithms": [ { "default": true, @@ -422584,7 +422604,7 @@ "startup": true } }, - "name": "STM32G081KBUxN", + "name": "STM32G081KBTxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422610,7 +422630,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081RBIx": { + "STM32G081KBUx": { "algorithms": [ { "default": true, @@ -422676,7 +422696,7 @@ "startup": true } }, - "name": "STM32G081RBIx", + "name": "STM32G081KBUx", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422702,7 +422722,7 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G081RBTx": { + "STM32G081KBUxN": { "algorithms": [ { "default": true, @@ -422768,7 +422788,7 @@ "startup": true } }, - "name": "STM32G081RBTx", + "name": "STM32G081KBUxN", "processor": { "Symmetric": { "core": "CortexM0Plus", @@ -422794,28 +422814,44 @@ "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G431C6Tx": { + "STM32G081RBIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G4xx_32.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", "ram_size": null, "ram_start": null, - "size": 32768, + "size": 131072, "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32G0xx_OTP.FLM", + "ram_size": null, + "ram_start": null, + "size": 1024, + "start": 536834048 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32G0x1_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 32, + "start": 536836096 } ], - "family": "STM32G4 Series", + "family": "STM32G0 Series", "from_pack": { - "pack": "STM32G4xx_DFP", - "url": "http://www.keil.com/pack", + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", "vendor": "Keil", - "version": "1.1.0" + "version": "1.2.0" }, "memories": { "IRAM1": { "access": { - "execute": false, + "execute": true, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -422824,7 +422860,7 @@ "write": true }, "default": true, - "size": 32768, + "size": 36864, "start": 536870912, "startup": false }, @@ -422839,16 +422875,16 @@ "write": false }, "default": true, - "size": 32768, + "size": 131072, "start": 134217728, "startup": true } }, - "name": "STM32G431C6Tx", + "name": "STM32G081RBIx", "processor": { "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", + "core": "CortexM0Plus", + "fpu": "None", "mpu": "Present", "units": 1 } @@ -422857,33 +422893,57 @@ [ 134217728, 2048 + ], + [ + 536834048, + 1024 + ], + [ + 536836096, + 32 ] ], - "sub_family": "STM32G431", + "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" }, - "STM32G431C6Ux": { + "STM32G081RBTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G4xx_32.FLM", + "file_name": "CMSIS/Flash/STM32G0xx_128.FLM", "ram_size": null, "ram_start": null, - "size": 32768, + "size": 131072, "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32G0xx_OTP.FLM", + "ram_size": null, + "ram_start": null, + "size": 1024, + "start": 536834048 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32G0x1_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 32, + "start": 536836096 } ], - "family": "STM32G4 Series", + "family": "STM32G0 Series", "from_pack": { - "pack": "STM32G4xx_DFP", - "url": "http://www.keil.com/pack", + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", "vendor": "Keil", - "version": "1.1.0" + "version": "1.2.0" }, "memories": { "IRAM1": { "access": { - "execute": false, + "execute": true, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -422892,7 +422952,7 @@ "write": true }, "default": true, - "size": 32768, + "size": 36864, "start": 536870912, "startup": false }, @@ -422907,16 +422967,16 @@ "write": false }, "default": true, - "size": 32768, + "size": 131072, "start": 134217728, "startup": true } }, - "name": "STM32G431C6Ux", + "name": "STM32G081RBTx", "processor": { "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", + "core": "CortexM0Plus", + "fpu": "None", "mpu": "Present", "units": 1 } @@ -422925,19 +422985,367 @@ [ 134217728, 2048 + ], + [ + 536834048, + 1024 + ], + [ + 536836096, + 32 ] ], - "sub_family": "STM32G431", + "sub_family": "STM32G081", "vendor": "STMicroelectronics:13" - }, - "STM32G431C8Tx": { + }, + "STM32G0B0RETx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G0Bx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + } + ], + "family": "STM32G0 Series", + "from_pack": { + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.3.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 147456, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G0B0RETx", + "processor": { + "Symmetric": { + "core": "CortexM0Plus", + "fpu": "None", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G0B0", + "vendor": "STMicroelectronics:13" + }, + "STM32G0B1RETx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G0Bx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + } + ], + "family": "STM32G0 Series", + "from_pack": { + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.3.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 147456, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G0B1RETx", + "processor": { + "Symmetric": { + "core": "CortexM0Plus", + "fpu": "None", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G0B1", + "vendor": "STMicroelectronics:13" + }, + "STM32G0C1RETx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G0Bx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + } + ], + "family": "STM32G0 Series", + "from_pack": { + "pack": "STM32G0xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.3.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 147456, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G0C1RETx", + "processor": { + "Symmetric": { + "core": "CortexM0Plus", + "fpu": "None", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G0C1", + "vendor": "STMicroelectronics:13" + }, + "STM32G431C6Tx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32G4xx_64.FLM", + "file_name": "CMSIS/Flash/STM32G4xx_32.FLM", "ram_size": null, "ram_start": null, - "size": 65536, + "size": 32768, + "start": 134217728 + } + ], + "family": "STM32G4 Series", + "from_pack": { + "pack": "STM32G4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "1.1.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 32768, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 32768, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G431C6Tx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G431", + "vendor": "STMicroelectronics:13" + }, + "STM32G431C6Ux": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G4xx_32.FLM", + "ram_size": null, + "ram_start": null, + "size": 32768, + "start": 134217728 + } + ], + "family": "STM32G4 Series", + "from_pack": { + "pack": "STM32G4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "1.1.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 32768, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 32768, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G431C6Ux", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G431", + "vendor": "STMicroelectronics:13" + }, + "STM32G431C8Tx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32G4xx_64.FLM", + "ram_size": null, + "ram_start": null, + "size": 65536, "start": 134217728 } ], @@ -431290,6 +431698,142 @@ "sub_family": "STM32G484", "vendor": "STMicroelectronics:13" }, + "STM32G491RETx": { + "algorithms": [ + { + "default": false, + "file_name": "CMSIS/Flash/STM32G4xx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + } + ], + "family": "STM32G4 Series", + "from_pack": { + "pack": "STM32G4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "1.4.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 114688, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G491RETx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G491", + "vendor": "STMicroelectronics:13" + }, + "STM32G4A1RETx": { + "algorithms": [ + { + "default": false, + "file_name": "CMSIS/Flash/STM32G4xx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + } + ], + "family": "STM32G4 Series", + "from_pack": { + "pack": "STM32G4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "1.4.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 114688, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32G4A1RETx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32G4A1", + "vendor": "STMicroelectronics:13" + }, "STM32GBK1CB": { "algorithms": [ { @@ -431357,572 +431901,347 @@ ], "sub_family": "STM32GBK1", "vendor": "STMicroelectronics:13" - }, - "STM32H742AGIx": { + }, + "STM32H723ZGTx": { "algorithms": [ { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 536870912, - "size": 2097152, + "default": true, + "file_name": "CMSIS/Flash/STM32H72x-73x_1024.FLM", + "ram_size": 131072, + "ram_start": 536870912, + "size": 1048576, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } - ], - "family": "STM32H7 Series", + ], + "family": "STM32H7 Series", "from_pack": { - "pack": "STM32H7xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "2.3.1" - }, + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.7.0" + }, "memories": { "IRAM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 131072, - "start": 536870912, + }, + "default": true, + "size": 131072, + "start": 536870912, "startup": false - }, + }, "IRAM2": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 356352, - "start": 603979776, + }, + "default": true, + "size": 327680, + "start": 603979776, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, + }, + "default": true, + "size": 1048576, + "start": 134217728, "startup": true - }, + }, "RAM_D2": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 32768, - "start": 805306368, - "startup": false - }, - "RAM_D2S2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 16384, - "start": 805437440, + }, + "default": true, + "size": 32768, + "start": 805306368, "startup": false - }, + }, "RAM_D3": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 65536, - "start": 939524096, + }, + "default": true, + "size": 16384, + "start": 939524096, "startup": false } - }, - "name": "STM32H742AGIx", + }, + "name": "STM32H723ZGTx", "processor": { "Symmetric": { - "core": "CortexM7", - "fpu": "DoublePrecision", - "mpu": "Present", + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ - 134217728, - 131072 - ], - [ - 1610612736, - 131072 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 131072 - ], - [ - 2415919104, + 134217728, 131072 ] - ], - "sub_family": "STM32H742", + ], + "sub_family": "STM32H723", "vendor": "STMicroelectronics:13" - }, - "STM32H742AIIx": { + }, + "STM32H725AEIx": { "algorithms": [ { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 536870912, - "size": 2097152, + "default": true, + "file_name": "CMSIS/Flash/STM32H72x-73x_1024.FLM", + "ram_size": 131072, + "ram_start": 536870912, + "size": 524288, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } - ], - "family": "STM32H7 Series", + ], + "family": "STM32H7 Series", "from_pack": { - "pack": "STM32H7xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "2.3.1" - }, + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.7.0" + }, "memories": { "IRAM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 131072, - "start": 536870912, + }, + "default": true, + "size": 131072, + "start": 536870912, "startup": false - }, + }, "IRAM2": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 356352, - "start": 603979776, + }, + "default": true, + "size": 131072, + "start": 603979776, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, - "size": 2097152, - "start": 134217728, + }, + "default": true, + "size": 524288, + "start": 134217728, "startup": true - }, + }, "RAM_D2": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 32768, - "start": 805306368, - "startup": false - }, - "RAM_D2S2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 16384, - "start": 805437440, + }, + "default": true, + "size": 16384, + "start": 805306368, "startup": false - }, + }, "RAM_D3": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 65536, - "start": 939524096, + }, + "default": true, + "size": 16384, + "start": 805322752, "startup": false } - }, - "name": "STM32H742AIIx", + }, + "name": "STM32H725AEIx", "processor": { "Symmetric": { - "core": "CortexM7", - "fpu": "DoublePrecision", - "mpu": "Present", + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ - 134217728, - 131072 - ], - [ - 1610612736, - 131072 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 131072 - ], - [ - 2415919104, + 134217728, 131072 ] - ], - "sub_family": "STM32H742", + ], + "sub_family": "STM32H725", "vendor": "STMicroelectronics:13" - }, - "STM32H742BGTx": { + }, + "STM32H735IGTx": { "algorithms": [ { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 536870912, - "size": 2097152, + "default": true, + "file_name": "CMSIS/Flash/STM32H72x-73x_1024.FLM", + "ram_size": 131072, + "ram_start": 536870912, + "size": 1048576, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } - ], - "family": "STM32H7 Series", + ], + "family": "STM32H7 Series", "from_pack": { - "pack": "STM32H7xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "2.3.1" - }, + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.7.0" + }, "memories": { "IRAM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 131072, - "start": 536870912, + }, + "default": true, + "size": 131072, + "start": 536870912, "startup": false - }, + }, "IRAM2": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 356352, - "start": 603979776, + }, + "default": true, + "size": 131072, + "start": 603979776, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, + }, + "default": true, + "size": 1048576, + "start": 134217728, "startup": true - }, + }, "RAM_D2": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 32768, - "start": 805306368, - "startup": false - }, - "RAM_D2S2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 16384, - "start": 805437440, + }, + "default": true, + "size": 16384, + "start": 805306368, "startup": false - }, + }, "RAM_D3": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 65536, - "start": 939524096, + }, + "default": true, + "size": 16384, + "start": 805322752, "startup": false } - }, - "name": "STM32H742BGTx", + }, + "name": "STM32H735IGTx", "processor": { "Symmetric": { - "core": "CortexM7", - "fpu": "DoublePrecision", - "mpu": "Present", + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ - 134217728, - 131072 - ], - [ - 1610612736, - 131072 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 131072 - ], - [ - 2415919104, + 134217728, 131072 ] - ], - "sub_family": "STM32H742", + ], + "sub_family": "STM32H735", "vendor": "STMicroelectronics:13" - }, - "STM32H742BITx": { + }, + "STM32H742AGIx": { "algorithms": [ { "default": true, @@ -432022,7 +432341,7 @@ "write": false }, "default": true, - "size": 2097152, + "size": 1048576, "start": 134217728, "startup": true }, @@ -432072,7 +432391,7 @@ "startup": false } }, - "name": "STM32H742BITx", + "name": "STM32H742AGIx", "processor": { "Symmetric": { "core": "CortexM7", @@ -432110,7 +432429,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742IGKx": { + "STM32H742AIIx": { "algorithms": [ { "default": true, @@ -432210,7 +432529,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -432260,7 +432579,7 @@ "startup": false } }, - "name": "STM32H742IGKx", + "name": "STM32H742AIIx", "processor": { "Symmetric": { "core": "CortexM7", @@ -432298,7 +432617,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742IGTx": { + "STM32H742BGTx": { "algorithms": [ { "default": true, @@ -432448,7 +432767,7 @@ "startup": false } }, - "name": "STM32H742IGTx", + "name": "STM32H742BGTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -432486,7 +432805,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742IIKx": { + "STM32H742BITx": { "algorithms": [ { "default": true, @@ -432636,7 +432955,7 @@ "startup": false } }, - "name": "STM32H742IIKx", + "name": "STM32H742BITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -432674,7 +432993,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742IITx": { + "STM32H742IGKx": { "algorithms": [ { "default": true, @@ -432774,7 +433093,7 @@ "write": false }, "default": true, - "size": 2097152, + "size": 1048576, "start": 134217728, "startup": true }, @@ -432824,7 +433143,7 @@ "startup": false } }, - "name": "STM32H742IITx", + "name": "STM32H742IGKx", "processor": { "Symmetric": { "core": "CortexM7", @@ -432862,7 +433181,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742VGHx": { + "STM32H742IGTx": { "algorithms": [ { "default": true, @@ -433012,7 +433331,7 @@ "startup": false } }, - "name": "STM32H742VGHx", + "name": "STM32H742IGTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -433050,7 +433369,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742VGTx": { + "STM32H742IIKx": { "algorithms": [ { "default": true, @@ -433150,7 +433469,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -433200,7 +433519,7 @@ "startup": false } }, - "name": "STM32H742VGTx", + "name": "STM32H742IIKx", "processor": { "Symmetric": { "core": "CortexM7", @@ -433238,7 +433557,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742VIHx": { + "STM32H742IITx": { "algorithms": [ { "default": true, @@ -433388,7 +433707,7 @@ "startup": false } }, - "name": "STM32H742VIHx", + "name": "STM32H742IITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -433426,7 +433745,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742VITx": { + "STM32H742VGHx": { "algorithms": [ { "default": true, @@ -433526,7 +433845,7 @@ "write": false }, "default": true, - "size": 2097152, + "size": 1048576, "start": 134217728, "startup": true }, @@ -433576,7 +433895,7 @@ "startup": false } }, - "name": "STM32H742VITx", + "name": "STM32H742VGHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -433614,7 +433933,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742XGHx": { + "STM32H742VGTx": { "algorithms": [ { "default": true, @@ -433764,7 +434083,7 @@ "startup": false } }, - "name": "STM32H742XGHx", + "name": "STM32H742VGTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -433802,7 +434121,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742XIHx": { + "STM32H742VIHx": { "algorithms": [ { "default": true, @@ -433952,7 +434271,7 @@ "startup": false } }, - "name": "STM32H742XIHx", + "name": "STM32H742VIHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -433990,7 +434309,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742ZGTx": { + "STM32H742VITx": { "algorithms": [ { "default": true, @@ -434090,7 +434409,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -434140,7 +434459,7 @@ "startup": false } }, - "name": "STM32H742ZGTx", + "name": "STM32H742VITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -434178,7 +434497,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H742ZITx": { + "STM32H742XGHx": { "algorithms": [ { "default": true, @@ -434278,7 +434597,7 @@ "write": false }, "default": true, - "size": 2097152, + "size": 1048576, "start": 134217728, "startup": true }, @@ -434328,7 +434647,7 @@ "startup": false } }, - "name": "STM32H742ZITx", + "name": "STM32H742XGHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -434366,7 +434685,7 @@ "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H743AGIx": { + "STM32H742XIHx": { "algorithms": [ { "default": true, @@ -434451,7 +434770,7 @@ "write": true }, "default": true, - "size": 524288, + "size": 356352, "start": 603979776, "startup": false }, @@ -434466,7 +434785,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -434481,10 +434800,25 @@ "write": true }, "default": true, - "size": 294912, + "size": 32768, "start": 805306368, "startup": false }, + "RAM_D2S2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 16384, + "start": 805437440, + "startup": false + }, "RAM_D3": { "access": { "execute": true, @@ -434501,7 +434835,7 @@ "startup": false } }, - "name": "STM32H743AGIx", + "name": "STM32H742XIHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -434536,10 +434870,10 @@ 131072 ] ], - "sub_family": "STM32H743", + "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H743AIIx": { + "STM32H742ZGTx": { "algorithms": [ { "default": true, @@ -434624,7 +434958,7 @@ "write": true }, "default": true, - "size": 524288, + "size": 356352, "start": 603979776, "startup": false }, @@ -434643,7 +434977,7 @@ "start": 134217728, "startup": true }, - "IROM2": { + "RAM_D2": { "access": { "execute": true, "non_secure": false, @@ -434651,14 +434985,14 @@ "peripheral": false, "read": true, "secure": false, - "write": false + "write": true }, "default": true, - "size": 1048576, - "start": 135266304, - "startup": true + "size": 32768, + "start": 805306368, + "startup": false }, - "RAM_D2": { + "RAM_D2S2": { "access": { "execute": true, "non_secure": false, @@ -434669,8 +435003,8 @@ "write": true }, "default": true, - "size": 294912, - "start": 805306368, + "size": 16384, + "start": 805437440, "startup": false }, "RAM_D3": { @@ -434689,7 +435023,7 @@ "startup": false } }, - "name": "STM32H743AIIx", + "name": "STM32H742ZGTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -434724,10 +435058,10 @@ 131072 ] ], - "sub_family": "STM32H743", + "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H743BGTx": { + "STM32H742ZITx": { "algorithms": [ { "default": true, @@ -434812,7 +435146,7 @@ "write": true }, "default": true, - "size": 524288, + "size": 356352, "start": 603979776, "startup": false }, @@ -434827,7 +435161,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -434842,10 +435176,25 @@ "write": true }, "default": true, - "size": 294912, + "size": 32768, "start": 805306368, "startup": false }, + "RAM_D2S2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 16384, + "start": 805437440, + "startup": false + }, "RAM_D3": { "access": { "execute": true, @@ -434862,7 +435211,7 @@ "startup": false } }, - "name": "STM32H743BGTx", + "name": "STM32H742ZITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -434897,10 +435246,10 @@ 131072 ] ], - "sub_family": "STM32H743", + "sub_family": "STM32H742", "vendor": "STMicroelectronics:13" }, - "STM32H743BITx": { + "STM32H743AGIx": { "algorithms": [ { "default": true, @@ -435004,7 +435353,125 @@ "start": 134217728, "startup": true }, - "IROM2": { + "RAM_D2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 294912, + "start": 805306368, + "startup": false + }, + "RAM_D3": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 65536, + "start": 939524096, + "startup": false + } + }, + "name": "STM32H743AGIx", + "processor": { + "Symmetric": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 131072 + ], + [ + 1610612736, + 131072 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 131072 + ], + [ + 2415919104, + 131072 + ] + ], + "sub_family": "STM32H743", + "vendor": "STMicroelectronics:13" + }, + "STM32H743AIIx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.3.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 524288, + "start": 603979776, + "startup": false + }, + "IROM1": { "access": { "execute": true, "non_secure": false, @@ -435015,8 +435482,8 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, + "size": 2097152, + "start": 134217728, "startup": true }, "RAM_D2": { @@ -435050,7 +435517,7 @@ "startup": false } }, - "name": "STM32H743BITx", + "name": "STM32H743AIIx", "processor": { "Symmetric": { "core": "CortexM7", @@ -435088,7 +435555,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743IGKx": { + "STM32H743BGTx": { "algorithms": [ { "default": true, @@ -435223,7 +435690,7 @@ "startup": false } }, - "name": "STM32H743IGKx", + "name": "STM32H743BGTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -435261,7 +435728,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743IGTx": { + "STM32H743BITx": { "algorithms": [ { "default": true, @@ -435270,46 +435737,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -435361,7 +435788,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -435396,7 +435823,7 @@ "startup": false } }, - "name": "STM32H743IGTx", + "name": "STM32H743BITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -435434,7 +435861,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743IIKx": { + "STM32H743IGKx": { "algorithms": [ { "default": true, @@ -435538,21 +435965,6 @@ "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -435584,7 +435996,7 @@ "startup": false } }, - "name": "STM32H743IIKx", + "name": "STM32H743IGKx", "processor": { "Symmetric": { "core": "CortexM7", @@ -435622,7 +436034,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743IITx": { + "STM32H743IGTx": { "algorithms": [ { "default": true, @@ -435726,7 +436138,125 @@ "start": 134217728, "startup": true }, - "IROM2": { + "RAM_D2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 294912, + "start": 805306368, + "startup": false + }, + "RAM_D3": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 65536, + "start": 939524096, + "startup": false + } + }, + "name": "STM32H743IGTx", + "processor": { + "Symmetric": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 131072 + ], + [ + 1610612736, + 131072 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 131072 + ], + [ + 2415919104, + 131072 + ] + ], + "sub_family": "STM32H743", + "vendor": "STMicroelectronics:13" + }, + "STM32H743IIKx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.3.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 524288, + "start": 603979776, + "startup": false + }, + "IROM1": { "access": { "execute": true, "non_secure": false, @@ -435737,8 +436267,8 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, + "size": 2097152, + "start": 134217728, "startup": true }, "RAM_D2": { @@ -435772,7 +436302,7 @@ "startup": false } }, - "name": "STM32H743IITx", + "name": "STM32H743IIKx", "processor": { "Symmetric": { "core": "CortexM7", @@ -435810,7 +436340,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743VGHx": { + "STM32H743IITx": { "algorithms": [ { "default": true, @@ -435819,46 +436349,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -435910,7 +436400,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, @@ -435945,7 +436435,7 @@ "startup": false } }, - "name": "STM32H743VGHx", + "name": "STM32H743IITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -435983,7 +436473,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743VGTx": { + "STM32H743VGHx": { "algorithms": [ { "default": true, @@ -436118,7 +436608,7 @@ "startup": false } }, - "name": "STM32H743VGTx", + "name": "STM32H743VGHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -436156,7 +436646,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743VIHx": { + "STM32H743VGTx": { "algorithms": [ { "default": true, @@ -436260,21 +436750,6 @@ "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -436306,7 +436781,7 @@ "startup": false } }, - "name": "STM32H743VIHx", + "name": "STM32H743VGTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -436344,7 +436819,7 @@ "sub_family": "STM32H743", "vendor": "STMicroelectronics:13" }, - "STM32H743VITx": { + "STM32H743VIHx": { "algorithms": [ { "default": true, @@ -436353,46 +436828,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -436444,11 +436879,129 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { + "RAM_D2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 294912, + "start": 805306368, + "startup": false + }, + "RAM_D3": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 65536, + "start": 939524096, + "startup": false + } + }, + "name": "STM32H743VIHx", + "processor": { + "Symmetric": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 131072 + ], + [ + 1610612736, + 131072 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 131072 + ], + [ + 2415919104, + 131072 + ] + ], + "sub_family": "STM32H743", + "vendor": "STMicroelectronics:13" + }, + "STM32H743VITx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.3.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 524288, + "start": 603979776, + "startup": false + }, + "IROM1": { "access": { "execute": true, "non_secure": false, @@ -436459,8 +437012,8 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, + "size": 2097152, + "start": 134217728, "startup": true }, "RAM_D2": { @@ -436714,46 +437267,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -436805,25 +437318,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -437075,46 +437573,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -437166,25 +437624,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -437337,6 +437780,89 @@ "sub_family": "STM32H7A3", "vendor": "STMicroelectronics:13" }, + "STM32H7B3ZITxQ": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.8.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 1048576, + "start": 603979776, + "startup": false + }, + "IRAM2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 2097152, + "start": 134217728, + "startup": true + } + }, + "name": "STM32H7B3ZITxQ", + "processor": { + "Symmetric": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 131072 + ] + ], + "sub_family": "STM32H7B3", + "vendor": "STMicroelectronics:13" + }, "STM32H745BGTx": { "algorithms": [ { @@ -439759,185 +440285,7 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, - "RAM_D3": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 65536, - "start": 939524096, - "startup": false - } - }, - "name": "STM32H747BITx", - "processor": { - "Asymmetric": { - "CM4": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - }, - "CM7": { - "core": "CortexM7", - "fpu": "DoublePrecision", - "mpu": "Present", - "units": 1 - } - } - }, - "sectors": [ - [ - 134217728, - 131072 - ], - [ - 134217728, - 131072 - ], - [ - 1610612736, - 131072 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 65536 - ], - [ - 2415919104, - 131072 - ], - [ - 2415919104, - 131072 - ] - ], - "sub_family": "STM32H747", - "vendor": "STMicroelectronics:13" - }, - "STM32H747IGTx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 536870912, - "size": 2097152, - "start": 134217728 - }, - { - "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 268435456, - "size": 2097152, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 - } - ], - "family": "STM32H7 Series", - "from_pack": { - "pack": "STM32H7xx_DFP", - "url": "https://www.keil.com/pack/", - "vendor": "Keil", - "version": "2.3.1" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 294912, - "start": 268435456, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 524288, - "start": 603979776, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 524288, + "size": 1048576, "start": 135266304, "startup": true }, @@ -439957,7 +440305,7 @@ "startup": false } }, - "name": "STM32H747IGTx", + "name": "STM32H747BITx", "processor": { "Asymmetric": { "CM4": { @@ -440007,7 +440355,7 @@ "sub_family": "STM32H747", "vendor": "STMicroelectronics:13" }, - "STM32H747IITx": { + "STM32H747IGTx": { "algorithms": [ { "default": true, @@ -440115,7 +440463,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 135266304, "startup": true }, @@ -440135,7 +440483,7 @@ "startup": false } }, - "name": "STM32H747IITx", + "name": "STM32H747IGTx", "processor": { "Asymmetric": { "CM4": { @@ -440185,7 +440533,7 @@ "sub_family": "STM32H747", "vendor": "STMicroelectronics:13" }, - "STM32H747XGHx": { + "STM32H747IITx": { "algorithms": [ { "default": true, @@ -440293,7 +440641,7 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 135266304, "startup": true }, @@ -440313,7 +440661,7 @@ "startup": false } }, - "name": "STM32H747XGHx", + "name": "STM32H747IITx", "processor": { "Asymmetric": { "CM4": { @@ -440363,7 +440711,7 @@ "sub_family": "STM32H747", "vendor": "STMicroelectronics:13" }, - "STM32H747XIHx": { + "STM32H747XGHx": { "algorithms": [ { "default": true, @@ -440471,7 +440819,7 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 135266304, "startup": true }, @@ -440491,7 +440839,7 @@ "startup": false } }, - "name": "STM32H747XIHx:CM7", + "name": "STM32H747XGHx", "processor": { "Asymmetric": { "CM4": { @@ -440541,7 +440889,7 @@ "sub_family": "STM32H747", "vendor": "STMicroelectronics:13" }, - "STM32H747ZIYx": { + "STM32H747XIHx": { "algorithms": [ { "default": true, @@ -440669,7 +441017,7 @@ "startup": false } }, - "name": "STM32H747ZIYx", + "name": "STM32H747XIHx:CM7", "processor": { "Asymmetric": { "CM4": { @@ -440719,14 +441067,22 @@ "sub_family": "STM32H747", "vendor": "STMicroelectronics:13" }, - "STM32H750IBKx": { + "STM32H747ZIYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32H7x_128k.FLM", - "ram_size": null, - "ram_start": null, - "size": 131072, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + }, + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 268435456, + "size": 2097152, "start": 134217728 }, { @@ -440780,7 +441136,7 @@ "memories": { "IRAM1": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -440789,13 +441145,13 @@ "write": true }, "default": true, - "size": 131072, - "start": 536870912, + "size": 294912, + "start": 268435456, "startup": false }, "IRAM2": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -440819,28 +441175,13 @@ "write": false }, "default": true, - "size": 131072, - "start": 134217728, + "size": 1048576, + "start": 135266304, "startup": true }, - "RAM_D2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 294912, - "start": 805306368, - "startup": false - }, "RAM_D3": { "access": { - "execute": true, + "execute": false, "non_secure": false, "non_secure_callable": false, "peripheral": false, @@ -440854,16 +441195,28 @@ "startup": false } }, - "name": "STM32H750IBKx", + "name": "STM32H747ZIYx", "processor": { - "Symmetric": { - "core": "CortexM7", - "fpu": "DoublePrecision", - "mpu": "Present", - "units": 1 + "Asymmetric": { + "CM4": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + }, + "CM7": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } } }, "sectors": [ + [ + 134217728, + 131072 + ], [ 134217728, 131072 @@ -440889,10 +441242,10 @@ 131072 ] ], - "sub_family": "STM32H750", + "sub_family": "STM32H747", "vendor": "STMicroelectronics:13" }, - "STM32H750VBTx": { + "STM32H750IBKx": { "algorithms": [ { "default": true, @@ -441027,7 +441380,7 @@ "startup": false } }, - "name": "STM32H750VBTx", + "name": "STM32H750IBKx", "processor": { "Symmetric": { "core": "CortexM7", @@ -441065,7 +441418,7 @@ "sub_family": "STM32H750", "vendor": "STMicroelectronics:13" }, - "STM32H750XBHx": { + "STM32H750VBTx": { "algorithms": [ { "default": true, @@ -441200,7 +441553,7 @@ "startup": false } }, - "name": "STM32H750XBHx", + "name": "STM32H750VBTx", "processor": { "Symmetric": { "core": "CortexM7", @@ -441238,14 +441591,14 @@ "sub_family": "STM32H750", "vendor": "STMicroelectronics:13" }, - "STM32H753AIIx": { + "STM32H750XBHx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", - "ram_size": 32768, - "ram_start": 536870912, - "size": 2097152, + "file_name": "CMSIS/Flash/STM32H7x_128k.FLM", + "ram_size": null, + "ram_start": null, + "size": 131072, "start": 134217728 }, { @@ -441338,25 +441691,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 131072, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -441388,7 +441726,7 @@ "startup": false } }, - "name": "STM32H753AIIx", + "name": "STM32H750XBHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -441423,10 +441761,10 @@ 131072 ] ], - "sub_family": "STM32H753", + "sub_family": "STM32H750", "vendor": "STMicroelectronics:13" }, - "STM32H753BITx": { + "STM32H753AIIx": { "algorithms": [ { "default": true, @@ -441435,46 +441773,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -441526,25 +441824,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -441576,7 +441859,7 @@ "startup": false } }, - "name": "STM32H753BITx", + "name": "STM32H753AIIx", "processor": { "Symmetric": { "core": "CortexM7", @@ -441614,7 +441897,7 @@ "sub_family": "STM32H753", "vendor": "STMicroelectronics:13" }, - "STM32H753IIKx": { + "STM32H753BITx": { "algorithms": [ { "default": true, @@ -441623,46 +441906,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -441714,25 +441957,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -441764,7 +441992,7 @@ "startup": false } }, - "name": "STM32H753IIKx", + "name": "STM32H753BITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -441802,7 +442030,7 @@ "sub_family": "STM32H753", "vendor": "STMicroelectronics:13" }, - "STM32H753IITx": { + "STM32H753IIKx": { "algorithms": [ { "default": true, @@ -441811,46 +442039,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -441902,25 +442090,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -441952,7 +442125,7 @@ "startup": false } }, - "name": "STM32H753IITx", + "name": "STM32H753IIKx", "processor": { "Symmetric": { "core": "CortexM7", @@ -441990,7 +442163,7 @@ "sub_family": "STM32H753", "vendor": "STMicroelectronics:13" }, - "STM32H753VIHx": { + "STM32H753IITx": { "algorithms": [ { "default": true, @@ -441999,46 +442172,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -442090,25 +442223,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -442140,7 +442258,7 @@ "startup": false } }, - "name": "STM32H753VIHx", + "name": "STM32H753IITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -442178,7 +442296,7 @@ "sub_family": "STM32H753", "vendor": "STMicroelectronics:13" }, - "STM32H753VITx": { + "STM32H753VIHx": { "algorithms": [ { "default": true, @@ -442187,46 +442305,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -442278,25 +442356,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -442328,7 +442391,7 @@ "startup": false } }, - "name": "STM32H753VITx", + "name": "STM32H753VIHx", "processor": { "Symmetric": { "core": "CortexM7", @@ -442366,7 +442429,7 @@ "sub_family": "STM32H753", "vendor": "STMicroelectronics:13" }, - "STM32H753XIHx": { + "STM32H753VITx": { "algorithms": [ { "default": true, @@ -442375,46 +442438,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -442466,25 +442489,10 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 135266304, - "startup": true - }, "RAM_D2": { "access": { "execute": true, @@ -442516,7 +442524,7 @@ "startup": false } }, - "name": "STM32H753XIHx", + "name": "STM32H753VITx", "processor": { "Symmetric": { "core": "CortexM7", @@ -442554,7 +442562,7 @@ "sub_family": "STM32H753", "vendor": "STMicroelectronics:13" }, - "STM32H753ZITx": { + "STM32H753XIHx": { "algorithms": [ { "default": true, @@ -442563,46 +442571,6 @@ "ram_start": 536870912, "size": 2097152, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 67108864, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H7xx_MT25TL01G_DUAL.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H750B-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/MT25TL01G_STM32H745I-DISCO.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 134217728, - "start": 2415919104 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32H743I-eval_FMC.FLM", - "ram_size": 65524, - "ram_start": 536870912, - "size": 16777216, - "start": 1610612736 } ], "family": "STM32H7 Series", @@ -442654,11 +442622,129 @@ "write": false }, "default": true, - "size": 1048576, + "size": 2097152, "start": 134217728, "startup": true }, - "IROM2": { + "RAM_D2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 294912, + "start": 805306368, + "startup": false + }, + "RAM_D3": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 65536, + "start": 939524096, + "startup": false + } + }, + "name": "STM32H753XIHx", + "processor": { + "Symmetric": { + "core": "CortexM7", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 131072 + ], + [ + 1610612736, + 131072 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 65536 + ], + [ + 2415919104, + 131072 + ], + [ + 2415919104, + 131072 + ] + ], + "sub_family": "STM32H753", + "vendor": "STMicroelectronics:13" + }, + "STM32H753ZITx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32H7x_2048.FLM", + "ram_size": 32768, + "ram_start": 536870912, + "size": 2097152, + "start": 134217728 + } + ], + "family": "STM32H7 Series", + "from_pack": { + "pack": "STM32H7xx_DFP", + "url": "https://www.keil.com/pack/", + "vendor": "Keil", + "version": "2.3.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 524288, + "start": 603979776, + "startup": false + }, + "IROM1": { "access": { "execute": true, "non_secure": false, @@ -442669,8 +442755,8 @@ "write": false }, "default": true, - "size": 1048576, - "start": 135266304, + "size": 2097152, + "start": 134217728, "startup": true }, "RAM_D2": { @@ -465658,6 +465744,57 @@ "sub_family": "STM32L162", "vendor": "STMicroelectronics:13" }, + "STM32L412KBTx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_128.FLM", + "ram_size": null, + "ram_start": null, + "size": 131072, + "start": 134217728 + } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.6.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 40960, + "start": 536870912, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 131072, + "start": 134217728, + "startup": true + } + } + }, "STM32L431CBTx": { "algorithms": [ { @@ -470190,7 +470327,98 @@ "startup": true } }, - "name": "STM32L451VCIx", + "name": "STM32L451VCIx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L451", + "vendor": "STMicroelectronics:13" + }, + "STM32L451VCTx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "ram_size": null, + "ram_start": null, + "size": 262144, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 32768, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 262144, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L451VCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470208,14 +470436,14 @@ "sub_family": "STM32L451", "vendor": "STMicroelectronics:13" }, - "STM32L451VCTx": { + "STM32L451VEIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 524288, "start": 134217728 }, { @@ -470276,12 +470504,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L451VCTx", + "name": "STM32L451VEIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470299,7 +470527,7 @@ "sub_family": "STM32L451", "vendor": "STMicroelectronics:13" }, - "STM32L451VEIx": { + "STM32L451VETx": { "algorithms": [ { "default": true, @@ -470317,6 +470545,97 @@ "size": 20, "start": 536836096 } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 32768, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L451VETx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L451", + "vendor": "STMicroelectronics:13" + }, + "STM32L452CCUx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "ram_size": null, + "ram_start": null, + "size": 262144, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } ], "family": "STM32L4 Series", "from_pack": { @@ -470367,12 +470686,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L451VEIx", + "name": "STM32L452CCUx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470387,10 +470706,10 @@ 2048 ] ], - "sub_family": "STM32L451", + "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L451VETx": { + "STM32L452CEUx": { "algorithms": [ { "default": true, @@ -470408,95 +470727,95 @@ "size": 20, "start": 536836096 } - ], + ], "family": "STM32L4 Series", "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", "version": "2.2.0" - }, + }, "memories": { "IRAM1": { "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 131072, - "start": 536870912, + }, + "default": true, + "size": 131072, + "start": 536870912, "startup": false - }, + }, "IRAM2": { "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, + }, + "default": false, + "size": 32768, + "start": 268435456, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, - "size": 524288, - "start": 134217728, + }, + "default": true, + "size": 524288, + "start": 134217728, "startup": true } - }, - "name": "STM32L451VETx", + }, + "name": "STM32L452CEUx", "processor": { "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ 134217728, 2048 ] ], - "sub_family": "STM32L451", + "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" - }, - "STM32L452CCUx": { + }, + "STM32L452RCIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", - "ram_size": null, - "ram_start": null, - "size": 262144, + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "ram_size": null, + "ram_start": null, + "size": 262144, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", "ram_size": null, "ram_start": null, - "size": 20, + "size": 20, "start": 536836096 } ], @@ -470549,12 +470868,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L452CCUx", + "name": "STM32L452RCIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470572,14 +470891,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452CEUx": { + "STM32L452RCTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 262144, "start": 134217728 }, { @@ -470640,12 +470959,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L452CEUx", + "name": "STM32L452RCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470663,14 +470982,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452RCIx": { + "STM32L452RCYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 262144, "start": 134217728 }, { @@ -470731,12 +471050,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L452RCIx", + "name": "STM32L452RCYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470754,14 +471073,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452RCTx": { + "STM32L452REIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 524288, "start": 134217728 }, { @@ -470822,12 +471141,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L452RCTx", + "name": "STM32L452REIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470845,14 +471164,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452RCYx": { + "STM32L452RETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 524288, "start": 134217728 }, { @@ -470913,12 +471232,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L452RCYx", + "name": "STM32L452RETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -470936,7 +471255,7 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452REIx": { + "STM32L452REYx": { "algorithms": [ { "default": true, @@ -471009,7 +471328,7 @@ "startup": true } }, - "name": "STM32L452REIx", + "name": "STM32L452REYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471027,14 +471346,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452RETx": { + "STM32L452VCIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 262144, "start": 134217728 }, { @@ -471095,12 +471414,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L452RETx", + "name": "STM32L452VCIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471118,14 +471437,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452REYx": { + "STM32L452VCTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 262144, "start": 134217728 }, { @@ -471186,12 +471505,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L452REYx", + "name": "STM32L452VCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471209,14 +471528,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452VCIx": { + "STM32L452VEIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 524288, "start": 134217728 }, { @@ -471277,12 +471596,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L452VCIx", + "name": "STM32L452VEIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471300,14 +471619,14 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452VCTx": { + "STM32L452VETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 524288, "start": 134217728 }, { @@ -471368,12 +471687,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L452VCTx", + "name": "STM32L452VETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471391,7 +471710,7 @@ "sub_family": "STM32L452", "vendor": "STMicroelectronics:13" }, - "STM32L452VEIx": { + "STM32L462CEUx": { "algorithms": [ { "default": true, @@ -471403,7 +471722,7 @@ }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -471429,7 +471748,7 @@ "write": true }, "default": true, - "size": 131072, + "size": 131072, "start": 536870912, "startup": false }, @@ -471464,7 +471783,7 @@ "startup": true } }, - "name": "STM32L452VEIx", + "name": "STM32L462CEUx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471479,22 +471798,22 @@ 2048 ] ], - "sub_family": "STM32L452", + "sub_family": "STM32L462", "vendor": "STMicroelectronics:13" }, - "STM32L452VETx": { + "STM32L462REIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 524288, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -471520,7 +471839,7 @@ "write": true }, "default": true, - "size": 131072, + "size": 131072, "start": 536870912, "startup": false }, @@ -471550,12 +471869,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L452VETx", + "name": "STM32L462REIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471570,10 +471889,10 @@ 2048 ] ], - "sub_family": "STM32L452", + "sub_family": "STM32L462", "vendor": "STMicroelectronics:13" }, - "STM32L462CEUx": { + "STM32L462RETx": { "algorithms": [ { "default": true, @@ -471646,7 +471965,7 @@ "startup": true } }, - "name": "STM32L462CEUx", + "name": "STM32L462RETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471664,7 +471983,189 @@ "sub_family": "STM32L462", "vendor": "STMicroelectronics:13" }, - "STM32L462REIx": { + "STM32L462REYx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 32768, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L462REYx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L462", + "vendor": "STMicroelectronics:13" + }, + "STM32L462VEIx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 32768, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L462VEIx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L462", + "vendor": "STMicroelectronics:13" + }, + "STM32L462VETx": { "algorithms": [ { "default": true, @@ -471737,7 +472238,7 @@ "startup": true } }, - "name": "STM32L462REIx", + "name": "STM32L462VETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471755,7 +472256,7 @@ "sub_family": "STM32L462", "vendor": "STMicroelectronics:13" }, - "STM32L462RETx": { + "STM32L471JEYx": { "algorithms": [ { "default": true, @@ -471767,7 +472268,7 @@ }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -471793,7 +472294,7 @@ "write": true }, "default": true, - "size": 131072, + "size": 98304, "start": 536870912, "startup": false }, @@ -471828,7 +472329,7 @@ "startup": true } }, - "name": "STM32L462RETx", + "name": "STM32L471JEYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471843,22 +472344,22 @@ 2048 ] ], - "sub_family": "STM32L462", + "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L462REYx": { + "STM32L471JGYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -471884,7 +472385,7 @@ "write": true }, "default": true, - "size": 131072, + "size": 98304, "start": 536870912, "startup": false }, @@ -471914,12 +472415,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L462REYx", + "name": "STM32L471JGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -471934,10 +472435,10 @@ 2048 ] ], - "sub_family": "STM32L462", + "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L462VEIx": { + "STM32L471QEIx": { "algorithms": [ { "default": true, @@ -471949,7 +472450,7 @@ }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -471975,7 +472476,7 @@ "write": true }, "default": true, - "size": 131072, + "size": 98304, "start": 536870912, "startup": false }, @@ -472010,7 +472511,7 @@ "startup": true } }, - "name": "STM32L462VEIx", + "name": "STM32L471QEIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472025,22 +472526,22 @@ 2048 ] ], - "sub_family": "STM32L462", + "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L462VETx": { + "STM32L471QGIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_SB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -472066,7 +472567,7 @@ "write": true }, "default": true, - "size": 131072, + "size": 98304, "start": 536870912, "startup": false }, @@ -472096,12 +472597,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L462VETx", + "name": "STM32L471QGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472116,17 +472617,17 @@ 2048 ] ], - "sub_family": "STM32L462", + "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471JEYx": { + "STM32L471RCTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 262144, "start": 134217728 }, { @@ -472187,12 +472688,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L471JEYx", + "name": "STM32L471RCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472210,14 +472711,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471JGYx": { + "STM32L471RCYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 262144, "start": 134217728 }, { @@ -472278,12 +472779,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L471JGYx", + "name": "STM32L471RCYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472301,14 +472802,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471QEIx": { + "STM32L471RETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 524288, "start": 134217728 }, { @@ -472369,12 +472870,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L471QEIx", + "name": "STM32L471RETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472392,14 +472893,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471QGIx": { + "STM32L471RGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 1048576, "start": 134217728 }, { @@ -472460,12 +472961,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L471QGIx", + "name": "STM32L471RGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472483,14 +472984,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471RCTx": { + "STM32L471RGYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 1048576, "start": 134217728 }, { @@ -472551,12 +473052,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L471RCTx", + "name": "STM32L471RGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472574,7 +473075,7 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471RCYx": { + "STM32L471VCTx": { "algorithms": [ { "default": true, @@ -472647,7 +473148,7 @@ "startup": true } }, - "name": "STM32L471RCYx", + "name": "STM32L471VCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472665,7 +473166,7 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471RETx": { + "STM32L471VETx": { "algorithms": [ { "default": true, @@ -472738,7 +473239,7 @@ "startup": true } }, - "name": "STM32L471RETx", + "name": "STM32L471VETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472756,7 +473257,7 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471RGTx": { + "STM32L471VGTx": { "algorithms": [ { "default": true, @@ -472829,98 +473330,7 @@ "startup": true } }, - "name": "STM32L471RGTx", - "processor": { - "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ] - ], - "sub_family": "STM32L471", - "vendor": "STMicroelectronics:13" - }, - "STM32L471RGYx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, - "size": 1048576, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 - } - ], - "family": "STM32L4 Series", - "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", - "version": "2.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 98304, - "start": 536870912, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, - "startup": true - } - }, - "name": "STM32L471RGYx", + "name": "STM32L471VGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -472938,14 +473348,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471VCTx": { + "STM32L471ZETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 524288, "start": 134217728 }, { @@ -473006,12 +473416,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L471VCTx", + "name": "STM32L471ZETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473029,14 +473439,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471VETx": { + "STM32L471ZGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { @@ -473097,12 +473507,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L471VETx", + "name": "STM32L471ZGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473120,14 +473530,14 @@ "sub_family": "STM32L471", "vendor": "STMicroelectronics:13" }, - "STM32L471VGTx": { + "STM32L475JEYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 524288, "start": 134217728 }, { @@ -473188,12 +473598,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L471VGTx", + "name": "STM32L475JEYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473208,17 +473618,17 @@ 2048 ] ], - "sub_family": "STM32L471", + "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L471ZETx": { + "STM32L475JGYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { @@ -473279,12 +473689,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L471ZETx", + "name": "STM32L475JGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473299,17 +473709,17 @@ 2048 ] ], - "sub_family": "STM32L471", + "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L471ZGTx": { + "STM32L475QEIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 524288, "start": 134217728 }, { @@ -473370,12 +473780,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L471ZGTx", + "name": "STM32L475QEIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473390,17 +473800,17 @@ 2048 ] ], - "sub_family": "STM32L471", + "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475JEYx": { + "STM32L475QGIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { @@ -473411,6 +473821,97 @@ "size": 20, "start": 536836096 } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 98304, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 32768, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 1048576, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L475QGIx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L475", + "vendor": "STMicroelectronics:13" + }, + "STM32L475RCTx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "ram_size": null, + "ram_start": null, + "size": 262144, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } ], "family": "STM32L4 Series", "from_pack": { @@ -473461,12 +473962,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L475JEYx", + "name": "STM32L475RCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473484,14 +473985,14 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475JGYx": { + "STM32L475RETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 524288, "start": 134217728 }, { @@ -473552,12 +474053,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L475JGYx", + "name": "STM32L475RETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473575,14 +474076,14 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475QEIx": { + "STM32L475RGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { @@ -473643,12 +474144,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L475QEIx", + "name": "STM32L475RGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473666,14 +474167,14 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475QGIx": { + "STM32L475VCTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 262144, "start": 134217728 }, { @@ -473684,70 +474185,70 @@ "size": 20, "start": 536836096 } - ], + ], "family": "STM32L4 Series", "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", "version": "2.2.0" - }, + }, "memories": { "IRAM1": { "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 98304, - "start": 536870912, + }, + "default": true, + "size": 98304, + "start": 536870912, "startup": false - }, + }, "IRAM2": { "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, + }, + "default": false, + "size": 32768, + "start": 268435456, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, + }, + "default": true, + "size": 262144, + "start": 134217728, "startup": true } - }, - "name": "STM32L475QGIx", + }, + "name": "STM32L475VCTx", "processor": { "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ 134217728, @@ -473756,23 +474257,23 @@ ], "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" - }, - "STM32L475RCTx": { + }, + "STM32L475VETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", - "ram_size": null, - "ram_start": null, - "size": 262144, + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "ram_size": null, + "ram_start": null, + "size": 524288, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, - "size": 20, + "size": 20, "start": 536836096 } ], @@ -473825,12 +474326,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L475RCTx", + "name": "STM32L475VETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473848,14 +474349,14 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475RETx": { + "STM32L475VGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { @@ -473916,12 +474417,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L475RETx", + "name": "STM32L475VGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -473939,14 +474440,14 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475RGTx": { + "STM32L475ZETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 524288, "start": 134217728 }, { @@ -474007,12 +474508,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L475RGTx", + "name": "STM32L475ZETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474030,14 +474531,14 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475VCTx": { + "STM32L475ZGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 1048576, "start": 134217728 }, { @@ -474098,12 +474599,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L475VCTx", + "name": "STM32L475ZGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474121,7 +474622,7 @@ "sub_family": "STM32L475", "vendor": "STMicroelectronics:13" }, - "STM32L475VETx": { + "STM32L476JEYx": { "algorithms": [ { "default": true, @@ -474189,194 +474690,12 @@ "write": false }, "default": true, - "size": 524288, - "start": 134217728, - "startup": true - } - }, - "name": "STM32L475VETx", - "processor": { - "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ] - ], - "sub_family": "STM32L475", - "vendor": "STMicroelectronics:13" - }, - "STM32L475VGTx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, - "size": 1048576, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 - } - ], - "family": "STM32L4 Series", - "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", - "version": "2.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 98304, - "start": 536870912, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, - "startup": true - } - }, - "name": "STM32L475VGTx", - "processor": { - "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ] - ], - "sub_family": "STM32L475", - "vendor": "STMicroelectronics:13" - }, - "STM32L475ZETx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", - "ram_size": null, - "ram_start": null, - "size": 524288, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 - } - ], - "family": "STM32L4 Series", - "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", - "version": "2.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 98304, - "start": 536870912, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 524288, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L475ZETx", + "name": "STM32L476JEYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474391,17 +474710,17 @@ 2048 ] ], - "sub_family": "STM32L475", + "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L475ZGTx": { + "STM32L476JGYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 1048576, "start": 134217728 }, { @@ -474462,12 +474781,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L475ZGTx", + "name": "STM32L476JGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474482,10 +474801,10 @@ 2048 ] ], - "sub_family": "STM32L475", + "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476JEYx": { + "STM32L476MEYx": { "algorithms": [ { "default": true, @@ -474558,7 +474877,7 @@ "startup": true } }, - "name": "STM32L476JEYx", + "name": "STM32L476MEYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474576,7 +474895,7 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476JGYx": { + "STM32L476MGYx": { "algorithms": [ { "default": true, @@ -474649,7 +474968,7 @@ "startup": true } }, - "name": "STM32L476JGYx", + "name": "STM32L476MGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474667,14 +474986,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476MEYx": { + "STM32L476QEIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 524288, "start": 134217728 }, { @@ -474735,12 +475054,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L476MEYx", + "name": "STM32L476QEIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474758,14 +475077,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476MGYx": { + "STM32L476QGIx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 1048576, "start": 134217728 }, { @@ -474826,12 +475145,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L476MGYx", + "name": "STM32L476QGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474849,14 +475168,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476QEIx": { + "STM32L476RCTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 262144, "start": 134217728 }, { @@ -474917,12 +475236,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L476QEIx", + "name": "STM32L476RCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -474940,14 +475259,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476QGIx": { + "STM32L476RETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 524288, "start": 134217728 }, { @@ -475008,12 +475327,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L476QGIx", + "name": "STM32L476RETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475031,14 +475350,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476RCTx": { + "STM32L476RGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 1048576, "start": 134217728 }, { @@ -475099,12 +475418,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L476RCTx", + "name": "STM32L476RGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475122,14 +475441,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476RETx": { + "STM32L476VCTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 262144, "start": 134217728 }, { @@ -475190,12 +475509,12 @@ "write": false }, "default": true, - "size": 524288, + "size": 262144, "start": 134217728, "startup": true } }, - "name": "STM32L476RETx", + "name": "STM32L476VCTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475213,14 +475532,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476RGTx": { + "STM32L476VETx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 524288, "start": 134217728 }, { @@ -475281,12 +475600,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 524288, "start": 134217728, "startup": true } }, - "name": "STM32L476RGTx", + "name": "STM32L476VETx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475304,14 +475623,14 @@ "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476VCTx": { + "STM32L476VGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_256.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 262144, + "size": 1048576, "start": 134217728 }, { @@ -475372,12 +475691,12 @@ "write": false }, "default": true, - "size": 262144, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L476VCTx", + "name": "STM32L476VGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475388,14 +475707,14 @@ }, "sectors": [ [ - 134217728, + 134217728, 2048 ] - ], + ], "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476VETx": { + "STM32L476ZETx": { "algorithms": [ { "default": true, @@ -475413,70 +475732,70 @@ "size": 20, "start": 536836096 } - ], + ], "family": "STM32L4 Series", "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", "version": "2.2.0" - }, + }, "memories": { "IRAM1": { "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": true, - "size": 98304, - "start": 536870912, + }, + "default": true, + "size": 98304, + "start": 536870912, "startup": false - }, + }, "IRAM2": { "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, + }, + "default": false, + "size": 32768, + "start": 268435456, "startup": false - }, + }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, "write": false - }, - "default": true, + }, + "default": true, "size": 524288, - "start": 134217728, + "start": 134217728, "startup": true } - }, - "name": "STM32L476VETx", + }, + "name": "STM32L476ZETx", "processor": { "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ 134217728, @@ -475485,23 +475804,23 @@ ], "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" - }, - "STM32L476VGTx": { + }, + "STM32L476ZGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, - "size": 1048576, + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "ram_size": null, + "ram_start": null, + "size": 1048576, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, - "size": 20, + "size": 20, "start": 536836096 } ], @@ -475559,7 +475878,7 @@ "startup": true } }, - "name": "STM32L476VGTx", + "name": "STM32L476ZGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475570,21 +475889,21 @@ }, "sectors": [ [ - 134217728, + 134217728, 2048 ] - ], + ], "sub_family": "STM32L476", "vendor": "STMicroelectronics:13" }, - "STM32L476ZETx": { + "STM32L485JCYx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_512.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 524288, + "size": 1048576, "start": 134217728 }, { @@ -475595,97 +475914,6 @@ "size": 20, "start": 536836096 } - ], - "family": "STM32L4 Series", - "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", - "version": "2.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 98304, - "start": 536870912, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": false, - "size": 32768, - "start": 268435456, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 524288, - "start": 134217728, - "startup": true - } - }, - "name": "STM32L476ZETx", - "processor": { - "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ] - ], - "sub_family": "STM32L476", - "vendor": "STMicroelectronics:13" - }, - "STM32L476ZGTx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, - "size": 1048576, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 - } ], "family": "STM32L4 Series", "from_pack": { @@ -475741,7 +475969,7 @@ "startup": true } }, - "name": "STM32L476ZGTx", + "name": "STM32L485JCYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475756,10 +475984,10 @@ 2048 ] ], - "sub_family": "STM32L476", + "sub_family": "STM32L485", "vendor": "STMicroelectronics:13" }, - "STM32L485JCYx": { + "STM32L486JGYx": { "algorithms": [ { "default": true, @@ -475797,7 +476025,7 @@ "write": true }, "default": true, - "size": 98304, + "size": 98304, "start": 536870912, "startup": false }, @@ -475812,7 +476040,7 @@ "write": true }, "default": false, - "size": 32768, + "size": 32768, "start": 268435456, "startup": false }, @@ -475832,7 +476060,7 @@ "startup": true } }, - "name": "STM32L485JCYx", + "name": "STM32L486JGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475847,10 +476075,10 @@ 2048 ] ], - "sub_family": "STM32L485", + "sub_family": "STM32L486", "vendor": "STMicroelectronics:13" }, - "STM32L486JGYx": { + "STM32L486QGIx": { "algorithms": [ { "default": true, @@ -475923,7 +476151,7 @@ "startup": true } }, - "name": "STM32L486JGYx", + "name": "STM32L486QGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -475941,7 +476169,7 @@ "sub_family": "STM32L486", "vendor": "STMicroelectronics:13" }, - "STM32L486QGIx": { + "STM32L486RGTx": { "algorithms": [ { "default": true, @@ -476014,7 +476242,7 @@ "startup": true } }, - "name": "STM32L486QGIx", + "name": "STM32L486RGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476032,7 +476260,7 @@ "sub_family": "STM32L486", "vendor": "STMicroelectronics:13" }, - "STM32L486RGTx": { + "STM32L486VGTx": { "algorithms": [ { "default": true, @@ -476105,7 +476333,7 @@ "startup": true } }, - "name": "STM32L486RGTx", + "name": "STM32L486VGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476123,7 +476351,7 @@ "sub_family": "STM32L486", "vendor": "STMicroelectronics:13" }, - "STM32L486VGTx": { + "STM32L486ZGTx": { "algorithms": [ { "default": true, @@ -476196,7 +476424,7 @@ "startup": true } }, - "name": "STM32L486VGTx", + "name": "STM32L486ZGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476214,7 +476442,7 @@ "sub_family": "STM32L486", "vendor": "STMicroelectronics:13" }, - "STM32L486ZGTx": { + "STM32L496AGIx": { "algorithms": [ { "default": true, @@ -476252,7 +476480,7 @@ "write": true }, "default": true, - "size": 98304, + "size": 262144, "start": 536870912, "startup": false }, @@ -476267,7 +476495,7 @@ "write": true }, "default": false, - "size": 32768, + "size": 65536, "start": 268435456, "startup": false }, @@ -476287,7 +476515,7 @@ "startup": true } }, - "name": "STM32L486ZGTx", + "name": "STM32L496AGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476298,14 +476526,14 @@ }, "sectors": [ [ - 134217728, + 134217728, 2048 ] - ], - "sub_family": "STM32L486", + ], + "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496AGIx": { + "STM32L496QGIx": { "algorithms": [ { "default": true, @@ -476378,7 +476606,7 @@ "startup": true } }, - "name": "STM32L496AGIx", + "name": "STM32L496QGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476389,14 +476617,14 @@ }, "sectors": [ [ - 134217728, + 134217728, 2048 ] - ], + ], "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496QGIx": { + "STM32L496RGTx": { "algorithms": [ { "default": true, @@ -476469,7 +476697,7 @@ "startup": true } }, - "name": "STM32L496QGIx", + "name": "STM32L496RGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476487,7 +476715,7 @@ "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496RGTx": { + "STM32L496VGTx": { "algorithms": [ { "default": true, @@ -476560,7 +476788,7 @@ "startup": true } }, - "name": "STM32L496RGTx", + "name": "STM32L496VGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476578,7 +476806,7 @@ "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496VGTx": { + "STM32L496VGYx": { "algorithms": [ { "default": true, @@ -476651,7 +476879,7 @@ "startup": true } }, - "name": "STM32L496VGTx", + "name": "STM32L496VGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476669,7 +476897,7 @@ "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496VGYx": { + "STM32L496ZGTx": { "algorithms": [ { "default": true, @@ -476742,7 +476970,7 @@ "startup": true } }, - "name": "STM32L496VGYx", + "name": "STM32L496ZGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476760,7 +476988,7 @@ "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496ZGTx": { + "STM32L496ZGYx": { "algorithms": [ { "default": true, @@ -476833,7 +477061,7 @@ "startup": true } }, - "name": "STM32L496ZGTx", + "name": "STM32L496ZGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476851,7 +477079,7 @@ "sub_family": "STM32L496", "vendor": "STMicroelectronics:13" }, - "STM32L496ZGYx": { + "STM32L4A6AGIx": { "algorithms": [ { "default": true, @@ -476924,7 +477152,7 @@ "startup": true } }, - "name": "STM32L496ZGYx", + "name": "STM32L4A6AGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -476939,10 +477167,10 @@ 2048 ] ], - "sub_family": "STM32L496", + "sub_family": "STM32L4A6", "vendor": "STMicroelectronics:13" }, - "STM32L4A6AGIx": { + "STM32L4A6QGIx": { "algorithms": [ { "default": true, @@ -477015,7 +477243,7 @@ "startup": true } }, - "name": "STM32L4A6AGIx", + "name": "STM32L4A6QGIx", "processor": { "Symmetric": { "core": "CortexM4", @@ -477033,19 +477261,19 @@ "sub_family": "STM32L4A6", "vendor": "STMicroelectronics:13" }, - "STM32L4A6QGIx": { + "STM32L4A6RGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", "ram_size": null, "ram_start": null, - "size": 1048576, + "size": 1048576, "start": 134217728 }, { "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", "ram_size": null, "ram_start": null, "size": 20, @@ -477071,11 +477299,87 @@ "write": true }, "default": true, - "size": 262144, + "size": 262144, "start": 536870912, "startup": false }, "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 65536, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 1048576, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L4A6RGTx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L4A6", + "vendor": "STMicroelectronics:13" + }, + "STM32L4A6VGTx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "ram_size": null, + "ram_start": null, + "size": 1048576, + "start": 134217728 + }, + { + "default": false, + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { "access": { "execute": false, "non_secure": false, @@ -477085,11 +477389,117 @@ "secure": false, "write": true }, + "default": true, + "size": 262144, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 65536, + "start": 268435456, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 1048576, + "start": 134217728, + "startup": true + } + }, + "name": "STM32L4A6VGTx", + "processor": { + "Symmetric": { + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 134217728, + 2048 + ] + ], + "sub_family": "STM32L4A6", + "vendor": "STMicroelectronics:13" + }, + "STM32L4A6VGYx": { + "algorithms": [ + { + "default": true, + "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", + "ram_size": null, + "ram_start": null, + "size": 1048576, + "start": 134217728 + }, + { "default": false, - "size": 65536, - "start": 268435456, + "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", + "ram_size": null, + "ram_start": null, + "size": 20, + "start": 536836096 + } + ], + "family": "STM32L4 Series", + "from_pack": { + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", + "version": "2.2.0" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 262144, + "start": 536870912, "startup": false }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 65536, + "start": 268435456, + "startup": false + }, "IROM1": { "access": { "execute": true, @@ -477101,12 +477511,12 @@ "write": false }, "default": true, - "size": 1048576, + "size": 1048576, "start": 134217728, "startup": true } }, - "name": "STM32L4A6QGIx", + "name": "STM32L4A6VGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -477124,7 +477534,7 @@ "sub_family": "STM32L4A6", "vendor": "STMicroelectronics:13" }, - "STM32L4A6RGTx": { + "STM32L4A6ZGTx": { "algorithms": [ { "default": true, @@ -477197,7 +477607,7 @@ "startup": true } }, - "name": "STM32L4A6RGTx", + "name": "STM32L4A6ZGTx", "processor": { "Symmetric": { "core": "CortexM4", @@ -477215,7 +477625,7 @@ "sub_family": "STM32L4A6", "vendor": "STMicroelectronics:13" }, - "STM32L4A6VGTx": { + "STM32L4A6ZGYx": { "algorithms": [ { "default": true, @@ -477288,7 +477698,7 @@ "startup": true } }, - "name": "STM32L4A6VGTx", + "name": "STM32L4A6ZGYx", "processor": { "Symmetric": { "core": "CortexM4", @@ -477306,140 +477716,26 @@ "sub_family": "STM32L4A6", "vendor": "STMicroelectronics:13" }, - "STM32L4A6VGYx": { + "STM32L4P5ZGTx": { "algorithms": [ { "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, + "file_name": "CMSIS/Flash/STM32L4P5xx_1M.FLM", + "ram_size": null, + "ram_start": null, "size": 1048576, "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 } - ], - "family": "STM32L4 Series", - "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", - "version": "2.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 262144, - "start": 536870912, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": false, - "size": 65536, - "start": 268435456, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, - "startup": true - } - }, - "name": "STM32L4A6VGYx", - "processor": { - "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ] ], - "sub_family": "STM32L4A6", - "vendor": "STMicroelectronics:13" - }, - "STM32L4A6ZGTx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, - "size": 1048576, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 - } - ], "family": "STM32L4 Series", "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", + "pack": "STM32L4xx_DFP", + "url": "http://www.keil.com/pack", + "vendor": "Keil", "version": "2.2.0" - }, + }, "memories": { "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 262144, - "start": 536870912, - "startup": false - }, - "IRAM2": { "access": { "execute": false, "non_secure": false, @@ -477449,136 +477745,45 @@ "secure": false, "write": true }, - "default": false, - "size": 65536, - "start": 268435456, + "default": true, + "size": 327680, + "start": 536870912, "startup": false }, "IROM1": { "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": false - }, - "default": true, - "size": 1048576, - "start": 134217728, - "startup": true - } - }, - "name": "STM32L4A6ZGTx", - "processor": { - "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", - "units": 1 - } - }, - "sectors": [ - [ - 134217728, - 2048 - ] - ], - "sub_family": "STM32L4A6", - "vendor": "STMicroelectronics:13" - }, - "STM32L4A6ZGYx": { - "algorithms": [ - { - "default": true, - "file_name": "CMSIS/Flash/STM32L4xx_1024.FLM", - "ram_size": null, - "ram_start": null, - "size": 1048576, - "start": 134217728 - }, - { - "default": false, - "file_name": "CMSIS/Flash/STM32L4xx_DB_OPT.FLM", - "ram_size": null, - "ram_start": null, - "size": 20, - "start": 536836096 - } - ], - "family": "STM32L4 Series", - "from_pack": { - "pack": "STM32L4xx_DFP", - "url": "http://www.keil.com/pack", - "vendor": "Keil", - "version": "2.2.0" - }, - "memories": { - "IRAM1": { - "access": { - "execute": false, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, - "write": true - }, - "default": true, - "size": 262144, - "start": 536870912, - "startup": false - }, - "IRAM2": { - "access": { - "execute": false, + "execute": true, "non_secure": false, "non_secure_callable": false, "peripheral": false, "read": true, "secure": false, - "write": true - }, - "default": false, - "size": 65536, - "start": 268435456, - "startup": false - }, - "IROM1": { - "access": { - "execute": true, - "non_secure": false, - "non_secure_callable": false, - "peripheral": false, - "read": true, - "secure": false, "write": false - }, - "default": true, + }, + "default": true, "size": 1048576, - "start": 134217728, + "start": 134217728, "startup": true } - }, - "name": "STM32L4A6ZGYx", + }, + "name": "STM32L4P5ZGTx", "processor": { "Symmetric": { - "core": "CortexM4", - "fpu": "SinglePrecision", - "mpu": "Present", + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present", "units": 1 } - }, + }, "sectors": [ [ 134217728, - 2048 + 4096 ] ], - "sub_family": "STM32L4A6", + "sub_family": "STM32L4P5", "vendor": "STMicroelectronics:13" - }, + }, "STM32L4R5AIIx": { "algorithms": [ { @@ -504138,7 +504343,83 @@ ], "sub_family": "M4K(1)", "vendor": "Toshiba:92" - }, + }, + "TMPM4KNFYAFG": { + "name": "TMPM4KNFYAFG", + "memories": { + "IROM1": { + "access": { + "read": true, + "write": false, + "execute": true, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 0, + "size": 262144, + "startup": true, + "default": true + }, + "IRAM1": { + "access": { + "read": true, + "write": true, + "execute": false, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 536870912, + "size": 24576, + "startup": false, + "default": true + } + }, + "algorithms": [ + { + "file_name": "Flash/TMPM4Kx_code_256.FLM", + "start": 0, + "size": 262144, + "default": true, + "ram_start": 536870912, + "ram_size": 8192 + }, + { + "file_name": "Flash/TMPM4Kx_data_32.FLM", + "start": 805306368, + "size": 32768, + "default": true, + "ram_start": 536870912, + "ram_size": 8192 + } + ], + "processor": { + "Symmetric": { + "units": 1, + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present" + } + }, + "from_pack": { + "vendor": "Toshiba", + "pack": "TXZ4Aplus-M4K2_DFP", + "version": "1.0.0", + "url": "https://toshiba.semicon-storage.com/content/dam/toshiba-ss/shared/docs/product/micro/device-family-Pack/" + }, + "sectors": [ + [ + 0, + 32768 + ] + ], + "vendor": "Toshiba:92", + "family": "TXZ4A+ Series", + "sub_family": "M4K(2)" + }, "XMC1100-Q024x0008": { "algorithms": [ { diff --git a/tools/cmake/app.cmake b/tools/cmake/app.cmake index 9f62df8204b..e82a25a5b88 100644 --- a/tools/cmake/app.cmake +++ b/tools/cmake/app.cmake @@ -61,3 +61,6 @@ else() message(STATUS "Missing Python dependencies (python3, intelhex, prettytable) so the memory map cannot be printed") endif() +# load mbed_create_distro +include(${CMAKE_CURRENT_LIST_DIR}/create_distro.cmake) + diff --git a/tools/cmake/create_distro.cmake b/tools/cmake/create_distro.cmake new file mode 100644 index 00000000000..2e518014f7d --- /dev/null +++ b/tools/cmake/create_distro.cmake @@ -0,0 +1,70 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# This script provides mbed_create_distro(), a function that lets you compile multiple +# apps that use Mbed OS without waiting for Mbed OS to build multiple times. + +# You can use it like this: +# mbed_create_distro(mbed_for_my_app mbed-os mbed-storage-kvstore mbed-storage-filesystem) +# +# add_executable(myapp1 MyApp1.cpp) +# target_link_libraries(myapp1 PRIVATE mbed_for_my_app) +# mbed_set_post_build(myapp1) +# +# add_executable(myapp2 MyApp2.cpp) +# target_link_libraries(myapp2 PRIVATE mbed_for_my_app) +# mbed_set_post_build(myapp2) +# +# Both myapp1 and myapp2 will act like they were linked to mbed-os, mbed-storage-kvstore, +# and mbed-storage-filesystem. Note that if you actually did target_link_libraries(myapp1 PRIVATE mbed-os +# mbed-storage-kvstore mbed-storage-filesystem), it would compile a new version of the Mbed OS source +# files for each target. However, using mbed_create_distro(), Mbed OS will only be compiled once. + +# Append the value of PROPERTY from SOURCE to the value of PROPERTY on DESTINATION +function(copy_append_property PROPERTY SOURCE DESTINATION) + get_property(PROP_IS_DEFINED TARGET ${SOURCE} PROPERTY ${PROPERTY} SET) + if(PROP_IS_DEFINED) + get_property(PROP_VALUE TARGET ${SOURCE} PROPERTY ${PROPERTY}) + set_property(TARGET ${DESTINATION} APPEND PROPERTY ${PROPERTY} "${PROP_VALUE}") + endif() +endfunction(copy_append_property) + +# Create a "distribution" of Mbed OS containing the base Mbed and certain modules. +# This distribution only needs to be compiled once and can be referenced in an arbitrary amount of targets. +function(mbed_create_distro NAME) # ARGN: modules... + add_library(${NAME} OBJECT) + mbed_configure_app_target(${NAME}) + + # First link as private dependencies + target_link_libraries(${NAME} PRIVATE ${ARGN}) + + # Now copy include dirs, compile defs, and compile options (but NOT interface source files) over + # to the distribution target so they will be passed into things that link to it. + # To do this, we need to recursively traverse the tree of dependencies. + set(REMAINING_MODULES ${ARGN}) + set(COMPLETED_MODULES ${ARGN}) + while(NOT "${REMAINING_MODULES}" STREQUAL "") + + list(GET REMAINING_MODULES 0 CURR_MODULE) + + copy_append_property(INTERFACE_COMPILE_DEFINITIONS ${CURR_MODULE} ${NAME}) + copy_append_property(INTERFACE_COMPILE_OPTIONS ${CURR_MODULE} ${NAME}) + copy_append_property(INTERFACE_INCLUDE_DIRECTORIES ${CURR_MODULE} ${NAME}) + copy_append_property(INTERFACE_LINK_OPTIONS ${CURR_MODULE} ${NAME}) + + list(REMOVE_AT REMAINING_MODULES 0) + list(APPEND COMPLETED_MODULES ${CURR_MODULE}) + + # find sub-modules of this module + get_property(SUBMODULES TARGET ${CURR_MODULE} PROPERTY INTERFACE_LINK_LIBRARIES) + foreach(SUBMODULE ${SUBMODULES}) + if(NOT "${SUBMODULE}" MATCHES "::@") # remove CMake internal CMAKE_DIRECTORY_ID_SEP markers + if(NOT ${SUBMODULE} IN_LIST COMPLETED_MODULES) + list(APPEND REMAINING_MODULES ${SUBMODULE}) + endif() + endif() + endforeach() + + endwhile() + +endfunction(mbed_create_distro) \ No newline at end of file diff --git a/tools/cmake/mbed_set_linker_script.cmake b/tools/cmake/mbed_set_linker_script.cmake index 390de139854..3a29b0873aa 100644 --- a/tools/cmake/mbed_set_linker_script.cmake +++ b/tools/cmake/mbed_set_linker_script.cmake @@ -3,6 +3,7 @@ # # Preprocesses and sets the linker script for an Mbed target. +# Called once for each MCU target in the build system. # function(mbed_set_linker_script input_target raw_linker_script_path) set(LINKER_SCRIPT_PATH ${CMAKE_CURRENT_BINARY_DIR}/${input_target}.link_script.ld) diff --git a/tools/cmake/mbed_set_post_build.cmake b/tools/cmake/mbed_set_post_build.cmake index ac9b2795143..f381d0a4dcf 100644 --- a/tools/cmake/mbed_set_post_build.cmake +++ b/tools/cmake/mbed_set_post_build.cmake @@ -58,8 +58,6 @@ function(mbed_generate_map_file target) COMMAND ${Python3_EXECUTABLE} ${mbed-os_SOURCE_DIR}/tools/memap.py -t ${MBED_TOOLCHAIN} ${CMAKE_CURRENT_BINARY_DIR}/${target}${CMAKE_EXECUTABLE_SUFFIX}.map WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT - "Displaying memory map for ${target}" ) endfunction() @@ -87,6 +85,18 @@ function(mbed_set_post_build target) # The mapfile name includes the top-level target name and the # executable suffix for all toolchains as CMake hardcodes the name of the # diagnostic output file for some toolchains. + + # copy mapfile .map to .map.old for ram/rom statistics diff in memap.py + if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/${target}${CMAKE_EXECUTABLE_SUFFIX}.map) + add_custom_command( + TARGET + ${target} + PRE_BUILD + COMMAND + ${CMAKE_COMMAND} -E rename "${CMAKE_CURRENT_BINARY_DIR}/${target}${CMAKE_EXECUTABLE_SUFFIX}.map" "${CMAKE_CURRENT_BINARY_DIR}/${target}${CMAKE_EXECUTABLE_SUFFIX}.map.old" + ) + endif() + mbed_configure_memory_map(${target} "${CMAKE_CURRENT_BINARY_DIR}/${target}${CMAKE_EXECUTABLE_SUFFIX}.map") mbed_validate_application_profile(${target}) mbed_generate_bin_hex(${target}) diff --git a/tools/memap.py b/tools/memap.py index 2a0a90a596b..42f3a5ad944 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -247,7 +247,7 @@ def parse_mapfile(self, file_desc): class _ArmccParser(_Parser): RE = re.compile( r'^\s+0x(\w{8})\s+0x(\w{8})\s+(\w+)\s+(\w+)\s+(\d+)\s+[*]?.+\s+(.+)$') - RE_OBJECT = re.compile(r'(.+\.(l|ar))\((.+\.o(bj)?)\)') + RE_OBJECT = re.compile(r'(.+\.(l|a|ar))\((.+\.o(bj)?)\)') OBJECT_EXTENSIONS = (".o", ".obj") def parse_object_name(self, line): diff --git a/tools/targets/NU_M2354.py b/tools/targets/NU_M2354.py index a6894a18145..bc691134870 100644 --- a/tools/targets/NU_M2354.py +++ b/tools/targets/NU_M2354.py @@ -27,7 +27,6 @@ SCRIPT_DIR = dirname(abspath(__file__)) MBED_OS_ROOT = abspath(path_join(SCRIPT_DIR, os.pardir, os.pardir)) -SECURE_ROOT = path_join(MBED_OS_ROOT, 'targets', 'TARGET_NUVOTON', 'TARGET_M2354', 'TARGET_TFM', 'TARGET_NU_M2354', 'COMPONENT_TFM_S_FW') def m2354_tfm_bin(t_self, non_secure_image, secure_bin): @@ -37,6 +36,8 @@ def m2354_tfm_bin(t_self, non_secure_image, secure_bin): secure_bin = abspath(secure_bin) non_secure_image = abspath(non_secure_image) + SECURE_ROOT = dirname(secure_bin) + build_dir = dirname(non_secure_image) tempdir = path_join(build_dir, 'temp') if not isdir(tempdir):