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Pull requests: riscv-collab/riscv-openocd

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Pull requests list

Add support for batch read/write handling for targets without abstractauto
#1314 opened Nov 12, 2025 by nadime15 • Draft
5
Update riscv_reg_impl.h to add warning before the assert.
#1313 opened Nov 8, 2025 by Biancaa-R Loading…
4
riscv: add batch.c and batch.h for skip-rti-nop sequence handling
#1312 opened Nov 7, 2025 by Biancaa-R Loading…
6
Fix: Memory leak in riscv_openocd_step_impl()
#1303 opened Oct 27, 2025 by Biancaa-R Loading…
7
Allign tcl/target/gd32vf103.cfg with the mainline
#1302 opened Oct 27, 2025 by en-sc Loading…
6
necessary tests for progbufsize | Skip CSR read if insufficient progbuf in RISC-V targets
#1300 opened Oct 26, 2025 by Biancaa-R Loading…
14
target/riscv: fix ub during instruction decode
#1299 opened Oct 15, 2025 by aap-sc Loading…
1
target/riscv: fix potential UB reported by ubsan in ac cache lookup
#1297 opened Oct 8, 2025 by aap-sc Loading…
fix error detection during trigger removal
#1296 opened Oct 7, 2025 by aap-sc Loading…
1
Merge up to 88b9bd396d5a1f83c49fa1b28745fd7feaca2b2e from upstream
#1290 opened Sep 12, 2025 by en-sc Loading…
2
Breakpoint size auto selection
#1288 opened Sep 8, 2025 by AlexandraKulyatskaya Loading…
target/riscv: hard reset DTM if dmistat is busy
#1287 opened Sep 4, 2025 by lz-bro Loading…
6
Apply XVC patch from openocd main to riscv
#1283 opened Aug 17, 2025 by stridge-tnp • Draft
3
target/riscv: access registers via reg->type
#1269 opened Jun 20, 2025 by en-sc Loading…
5
target/riscv: warn about truncating register values
#1268 opened Jun 20, 2025 by en-sc Loading…
2
target/riscv: Fix some timeout check order
#1265 opened Jun 13, 2025 by lz-bro Loading…
4
target/riscv: extend trigger controls
#1261 opened May 28, 2025 by lz-bro Loading…
32
riscv_openocd_poll(): fix premature termination of algorithms under SMP
#1259 opened May 19, 2025 by Wren6991 Loading…
3
target/riscv: fix riscv_mmu behaviour
#1256 opened May 14, 2025 by fk-sc Loading…
20
Add dcsr cetrig control
#1255 opened May 13, 2025 by lz-bro Loading…
43
target/riscv: Adjust to upstream coding style
#1254 opened May 6, 2025 by berolinux Loading…
1
target/riscv: Regenerate debug_defines.{c,h} from current riscv-debug…
#1253 opened May 6, 2025 by berolinux Loading…
5
target/riscv: active dm before get nextdm
#1252 opened May 6, 2025 by lz-bro Loading…
32
target/riscv: Add support for external triggers
#1243 opened Mar 31, 2025 by lz-bro Loading…
52
target/riscv: add is_virtual parameter to memory access method
#1241 opened Mar 18, 2025 by fk-sc Loading…
12
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