Missing `unsafe`s in both x86 and riscv64 implementations.

In both the x86 and riscv64 implementations the constructors are not marked as `unsafe` despite taking an arbitrary port address and later writing to it. A user of the crate could incredibly easily cause an illegal write by passing an invalid address.

### x86

https://github.com/rust-embedded/qemu-exit/blob/d157a2aae6940ff0fb876935097ce8ef48d0974f/src/x86.rs#L36

https://github.com/rust-embedded/qemu-exit/blob/d157a2aae6940ff0fb876935097ce8ef48d0974f/src/x86.rs#L25-L30

### riscv64

https://github.com/rust-embedded/qemu-exit/blob/d157a2aae6940ff0fb876935097ce8ef48d0974f/src/riscv64.rs#L29

https://github.com/rust-embedded/qemu-exit/blob/d157a2aae6940ff0fb876935097ce8ef48d0974f/src/riscv64.rs#L44-L47

	asm!(
	"out dx, eax",
	in("dx") io_base,
	in("eax") code,
	options(nomem, nostack)
	);

	asm!(
	"sw {0}, 0({1})",
	in(reg)code_new, in(reg)self.addr
	);

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Missing `unsafe`s in both x86 and riscv64 implementations. #35

x86

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Missing unsafes in both x86 and riscv64 implementations. #35

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x86

riscv64

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Missing `unsafe`s in both x86 and riscv64 implementations. #35