Skip to content
#

hierarchical-hardware-design

Star

Here is 1 public repository matching this topic...

SazzadSowmik / HiVeGen-Pipeline-Reproduction

Star 0

Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).

llvm verilog systemverilog hardware-designs hdl verilog-hdl hierachical verilog-code hierachical-structure llm-based hivegen hierarchical-hardware-design demo-paper-implementation paper-demo hivegen-demo
  • Updated Nov 8, 2025
  • SystemVerilog

Improve this page

Add a description, image, and links to the hierarchical-hardware-design topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the hierarchical-hardware-design topic, visit your repo's landing page and select "manage topics."

Learn more