A powerful multi-format file parsing, data cleaning, and AI annotation toolkit.
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Oct 30, 2025 - Python
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llm-based
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Apr 10, 2025 - Python
Reproduction of the HiVeGen (Hierarchical LLM-based Verilog Generation) pipeline from the paper "HiVeGen – Hierarchical LLM-based Verilog Generation for Scalable Chip Design" (arXiv:2412.05393).
llvm verilog systemverilog hardware-designs hdl verilog-hdl hierachical verilog-code hierachical-structure llm-based hivegen hierarchical-hardware-design demo-paper-implementation paper-demo hivegen-demo
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Oct 31, 2025 - Python
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